opcodes/ppc-dis.c

   1 /* ppc-dis.c -- Disassemble PowerPC instructions
   2    Copyright (C) 1994-2019 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #include "sysdep.h"
  23 #include <stdio.h>
  24 #include "disassemble.h"
  25 #include "elf-bfd.h"
  26 #include "elf/ppc.h"
  27 #include "opintl.h"
  28 #include "opcode/ppc.h"
  29 #include "libiberty.h"
  30
  31 /* This file provides several disassembler functions, all of which use
  32    the disassembler interface defined in dis-asm.h.  Several functions
  33    are provided because this file handles disassembly for the PowerPC
  34    in both big and little endian mode and also for the POWER (RS/6000)
  35    chip.  */
  36 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
  37                                ppc_cpu_t);
  38
  39 struct dis_private
  40 {
  41   /* Stash the result of parsing disassembler_options here.  */
  42   ppc_cpu_t dialect;
  43 } private;
  44
  45 #define POWERPC_DIALECT(INFO) \
  46   (((struct dis_private *) ((INFO)->private_data))->dialect)
  47
  48 struct ppc_mopt {
  49   /* Option string, without -m or -M prefix.  */
  50   const char *opt;
  51   /* CPU option flags.  */
  52   ppc_cpu_t cpu;
  53   /* Flags that should stay on, even when combined with another cpu
  54      option.  This should only be used for generic options like
  55      "-many" or "-maltivec" where it is reasonable to add some
  56      capability to another cpu selection.  The added flags are sticky
  57      so that, for example, "-many -me500" and "-me500 -many" result in
  58      the same assembler or disassembler behaviour.  Do not use
  59      "sticky" for specific cpus, as this will prevent that cpu's flags
  60      from overriding the defaults set in powerpc_init_dialect or a
  61      prior -m option.  */
  62   ppc_cpu_t sticky;
  63 };
  64
  65 struct ppc_mopt ppc_opts[] = {
  66   { "403",     PPC_OPCODE_PPC | PPC_OPCODE_403,
  67     0 },
  68   { "405",     PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
  69     0 },
  70   { "440",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  71                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  72     0 },
  73   { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  74                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  75     0 },
  76   { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_476
  77                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
  78     0 },
  79   { "601",     PPC_OPCODE_PPC | PPC_OPCODE_601,
  80     0 },
  81   { "603",     PPC_OPCODE_PPC,
  82     0 },
  83   { "604",     PPC_OPCODE_PPC,
  84     0 },
  85   { "620",     PPC_OPCODE_PPC | PPC_OPCODE_64,
  86     0 },
  87   { "7400",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  88     0 },
  89   { "7410",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  90     0 },
  91   { "7450",    PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
  92     0 },
  93   { "7455",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  94     0 },
  95   { "750cl",   PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
  96     , 0 },
  97   { "gekko",   PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
  98     , 0 },
  99   { "broadway", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
 100     , 0 },
 101   { "821",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 102     0 },
 103   { "850",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 104     0 },
 105   { "860",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 106     0 },
 107   { "a2",      (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
 108                 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
 109                 | PPC_OPCODE_A2),
 110     0 },
 111   { "altivec", PPC_OPCODE_PPC,
 112     PPC_OPCODE_ALTIVEC },
 113   { "any",     PPC_OPCODE_PPC,
 114     PPC_OPCODE_ANY },
 115   { "booke",   PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
 116     0 },
 117   { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
 118     0 },
 119   { "cell",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 120                 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
 121     0 },
 122   { "com",     PPC_OPCODE_COMMON,
 123     0 },
 124   { "e200z4",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
 125                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 126                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 127                 | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4
 128                 | PPC_OPCODE_EFS2 | PPC_OPCODE_LSP),
 129     0 },
 130   { "e300",    PPC_OPCODE_PPC | PPC_OPCODE_E300,
 131     0 },
 132   { "e500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 133                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 134                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 135                 | PPC_OPCODE_E500),
 136     0 },
 137   { "e500mc",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 138                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 139                 | PPC_OPCODE_E500MC),
 140     0 },
 141   { "e500mc64",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 142                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 143                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
 144                 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 145     0 },
 146   { "e5500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 147                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 148                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 149                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 150     0 },
 151   { "e6500",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 152                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 153                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
 154                 | PPC_OPCODE_E6500 | PPC_OPCODE_TMR | PPC_OPCODE_POWER4
 155                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 156     0 },
 157   { "e500x2",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 158                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 159                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 160                 | PPC_OPCODE_E500),
 161     0 },
 162   { "efs",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
 163     0 },
 164   { "efs2",    PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2,
 165     0 },
 166   { "power4",  PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
 167     0 },
 168   { "power5",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 169                 | PPC_OPCODE_POWER5),
 170     0 },
 171   { "power6",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 172                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 173     0 },
 174   { "power7",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 175                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 176                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 177     0 },
 178   { "power8",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 179                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 180                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
 181                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 182     0 },
 183   { "power9",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 184                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 185                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 186                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 187     0 },
 188   { "future",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 189                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 190                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 191                 | PPC_OPCODE_POWERXX | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 192     0 },
 193   { "ppc",     PPC_OPCODE_PPC,
 194     0 },
 195   { "ppc32",   PPC_OPCODE_PPC,
 196     0 },
 197   { "32",      PPC_OPCODE_PPC,
 198     0 },
 199   { "ppc64",   PPC_OPCODE_PPC | PPC_OPCODE_64,
 200     0 },
 201   { "64",      PPC_OPCODE_PPC | PPC_OPCODE_64,
 202     0 },
 203   { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
 204     0 },
 205   { "ppcps",   PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
 206     0 },
 207   { "pwr",     PPC_OPCODE_POWER,
 208     0 },
 209   { "pwr2",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
 210     0 },
 211   { "pwr4",    PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
 212     0 },
 213   { "pwr5",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 214                 | PPC_OPCODE_POWER5),
 215     0 },
 216   { "pwr5x",   (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 217                 | PPC_OPCODE_POWER5),
 218     0 },
 219   { "pwr6",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 220                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 221     0 },
 222   { "pwr7",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 223                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 224                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 225     0 },
 226   { "pwr8",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 227                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 228                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
 229                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 230     0 },
 231   { "pwr9",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 232                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 233                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 234                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 235     0 },
 236   { "pwrx",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
 237     0 },
 238   { "raw",     PPC_OPCODE_PPC,
 239     PPC_OPCODE_RAW },
 240   { "spe",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
 241     PPC_OPCODE_SPE },
 242   { "spe2",     PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE,
 243     PPC_OPCODE_SPE2 },
 244   { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
 245                 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
 246     0 },
 247   { "vle",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
 248                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 249                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 250                 | PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),
 251     PPC_OPCODE_VLE },
 252   { "vsx",     PPC_OPCODE_PPC,
 253     PPC_OPCODE_VSX },
 254 };
 255
 256 /* Switch between Booke and VLE dialects for interlinked dumps.  */
 257 static ppc_cpu_t
 258 get_powerpc_dialect (struct disassemble_info *info)
 259 {
 260   ppc_cpu_t dialect = 0;
 261
 262   dialect = POWERPC_DIALECT (info);
 263
 264   /* Disassemble according to the section headers flags for VLE-mode.  */
 265   if (dialect & PPC_OPCODE_VLE
 266       && info->section != NULL && info->section->owner != NULL
 267       && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
 268       && elf_object_id (info->section->owner) == PPC32_ELF_DATA
 269       && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
 270     return dialect;
 271   else
 272     return dialect & ~ PPC_OPCODE_VLE;
 273 }
 274
 275 /* Handle -m and -M options that set cpu type, and .machine arg.  */
 276
 277 ppc_cpu_t
 278 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
 279 {
 280   unsigned int i;
 281
 282   for (i = 0; i < ARRAY_SIZE (ppc_opts); i++)
 283     if (disassembler_options_cmp (ppc_opts[i].opt, arg) == 0)
 284       {
 285         if (ppc_opts[i].sticky)
 286           {
 287             *sticky |= ppc_opts[i].sticky;
 288             if ((ppc_cpu & ~*sticky) != 0)
 289               break;
 290           }
 291         ppc_cpu = ppc_opts[i].cpu;
 292         break;
 293       }
 294   if (i >= ARRAY_SIZE (ppc_opts))
 295     return 0;
 296
 297   ppc_cpu |= *sticky;
 298   return ppc_cpu;
 299 }
 300
 301 /* Determine which set of machines to disassemble for.  */
 302
 303 static void
 304 powerpc_init_dialect (struct disassemble_info *info)
 305 {
 306   ppc_cpu_t dialect = 0;
 307   ppc_cpu_t sticky = 0;
 308   struct dis_private *priv = calloc (sizeof (*priv), 1);
 309
 310   if (priv == NULL)
 311     priv = &private;
 312
 313   switch (info->mach)
 314     {
 315     case bfd_mach_ppc_403:
 316     case bfd_mach_ppc_403gc:
 317       dialect = ppc_parse_cpu (dialect, &sticky, "403");
 318       break;
 319     case bfd_mach_ppc_405:
 320       dialect = ppc_parse_cpu (dialect, &sticky, "405");
 321       break;
 322     case bfd_mach_ppc_601:
 323       dialect = ppc_parse_cpu (dialect, &sticky, "601");
 324       break;
 325     case bfd_mach_ppc_750:
 326       dialect = ppc_parse_cpu (dialect, &sticky, "750cl");
 327       break;
 328     case bfd_mach_ppc_a35:
 329     case bfd_mach_ppc_rs64ii:
 330     case bfd_mach_ppc_rs64iii:
 331       dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
 332       break;
 333     case bfd_mach_ppc_e500:
 334       dialect = ppc_parse_cpu (dialect, &sticky, "e500");
 335       break;
 336     case bfd_mach_ppc_e500mc:
 337       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
 338       break;
 339     case bfd_mach_ppc_e500mc64:
 340       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
 341       break;
 342     case bfd_mach_ppc_e5500:
 343       dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
 344       break;
 345     case bfd_mach_ppc_e6500:
 346       dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
 347       break;
 348     case bfd_mach_ppc_titan:
 349       dialect = ppc_parse_cpu (dialect, &sticky, "titan");
 350       break;
 351     case bfd_mach_ppc_vle:
 352       dialect = ppc_parse_cpu (dialect, &sticky, "vle");
 353       break;
 354     default:
 355       if (info->arch == bfd_arch_powerpc)
 356         dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY;
 357       else
 358         dialect = ppc_parse_cpu (dialect, &sticky, "pwr");
 359       break;
 360     }
 361
 362   const char *opt;
 363   FOR_EACH_DISASSEMBLER_OPTION (opt, info->disassembler_options)
 364     {
 365       ppc_cpu_t new_cpu = 0;
 366
 367       if (disassembler_options_cmp (opt, "32") == 0)
 368         dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
 369       else if (disassembler_options_cmp (opt, "64") == 0)
 370         dialect |= PPC_OPCODE_64;
 371       else if ((new_cpu = ppc_parse_cpu (dialect, &sticky, opt)) != 0)
 372         dialect = new_cpu;
 373       else
 374         /* xgettext: c-format */
 375         opcodes_error_handler (_("warning: ignoring unknown -M%s option"), opt);
 376     }
 377
 378   info->private_data = priv;
 379   POWERPC_DIALECT(info) = dialect;
 380 }
 381
 382 #define PPC_OPCD_SEGS (1 + PPC_OP (-1))
 383 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS + 1];
 384 #define PREFIX_OPCD_SEGS (1 + PPC_PREFIX_SEG (-1))
 385 static unsigned short prefix_opcd_indices[PREFIX_OPCD_SEGS + 1];
 386 #define VLE_OPCD_SEGS (1 + VLE_OP_TO_SEG (VLE_OP (-1, 0xffff)))
 387 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS + 1];
 388 #define SPE2_OPCD_SEGS (1 + SPE2_XOP_TO_SEG (SPE2_XOP (-1)))
 389 static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS + 1];
 390
 391 /* Calculate opcode table indices to speed up disassembly,
 392    and init dialect.  */
 393
 394 void
 395 disassemble_init_powerpc (struct disassemble_info *info)
 396 {
 397   if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
 398     {
 399       unsigned seg, idx, op;
 400
 401       /* PPC opcodes */
 402       for (seg = 0, idx = 0; seg <= PPC_OPCD_SEGS; seg++)
 403         {
 404           powerpc_opcd_indices[seg] = idx;
 405           for (; idx < powerpc_num_opcodes; idx++)
 406             if (seg < PPC_OP (powerpc_opcodes[idx].opcode))
 407               break;
 408         }
 409
 410       /* 64-bit prefix opcodes */
 411       for (seg = 0, idx = 0; seg <= PREFIX_OPCD_SEGS; seg++)
 412         {
 413           prefix_opcd_indices[seg] = idx;
 414           for (; idx < prefix_num_opcodes; idx++)
 415             if (seg < PPC_PREFIX_SEG (prefix_opcodes[idx].opcode))
 416               break;
 417         }
 418
 419       /* VLE opcodes */
 420       for (seg = 0, idx = 0; seg <= VLE_OPCD_SEGS; seg++)
 421         {
 422           vle_opcd_indices[seg] = idx;
 423           for (; idx < vle_num_opcodes; idx++)
 424             {
 425               op = VLE_OP (vle_opcodes[idx].opcode, vle_opcodes[idx].mask);
 426               if (seg < VLE_OP_TO_SEG (op))
 427                 break;
 428             }
 429         }
 430
 431       /* SPE2 opcodes */
 432       for (seg = 0, idx = 0; seg <= SPE2_OPCD_SEGS; seg++)
 433         {
 434           spe2_opcd_indices[seg] = idx;
 435           for (; idx < spe2_num_opcodes; idx++)
 436             {
 437               op = SPE2_XOP (spe2_opcodes[idx].opcode);
 438               if (seg < SPE2_XOP_TO_SEG (op))
 439                 break;
 440             }
 441         }
 442     }
 443
 444   powerpc_init_dialect (info);
 445 }
 446
 447 /* Print a big endian PowerPC instruction.  */
 448
 449 int
 450 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 451 {
 452   return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
 453 }
 454
 455 /* Print a little endian PowerPC instruction.  */
 456
 457 int
 458 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 459 {
 460   return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
 461 }
 462
 463 /* Extract the operand value from the PowerPC or POWER instruction.  */
 464
 465 static int64_t
 466 operand_value_powerpc (const struct powerpc_operand *operand,
 467                        uint64_t insn, ppc_cpu_t dialect)
 468 {
 469   int64_t value;
 470   int invalid = 0;
 471   /* Extract the value from the instruction.  */
 472   if (operand->extract)
 473     value = (*operand->extract) (insn, dialect, &invalid);
 474   else
 475     {
 476       if (operand->shift >= 0)
 477         value = (insn >> operand->shift) & operand->bitm;
 478       else
 479         value = (insn << -operand->shift) & operand->bitm;
 480       if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
 481         {
 482           /* BITM is always some number of zeros followed by some
 483              number of ones, followed by some number of zeros.  */
 484           uint64_t top = operand->bitm;
 485           /* top & -top gives the rightmost 1 bit, so this
 486              fills in any trailing zeros.  */
 487           top |= (top & -top) - 1;
 488           top &= ~(top >> 1);
 489           value = (value ^ top) - top;
 490         }
 491     }
 492
 493   return value;
 494 }
 495
 496 /* Determine whether the optional operand(s) should be printed.  */
 497
 498 static bfd_boolean
 499 skip_optional_operands (const unsigned char *opindex,
 500                         uint64_t insn, ppc_cpu_t dialect)
 501 {
 502   const struct powerpc_operand *operand;
 503   int num_optional;
 504
 505   for (num_optional = 0; *opindex != 0; opindex++)
 506     {
 507       operand = &powerpc_operands[*opindex];
 508       if ((operand->flags & PPC_OPERAND_NEXT) != 0)
 509         return FALSE;
 510       if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
 511         {
 512           /* Negative count is used as a flag to extract function.  */
 513           --num_optional;
 514           if (operand_value_powerpc (operand, insn, dialect)
 515               != ppc_optional_operand_value (operand, insn, dialect,
 516                                              num_optional))
 517             return FALSE;
 518         }
 519     }
 520
 521   return TRUE;
 522 }
 523
 524 /* Find a match for INSN in the opcode table, given machine DIALECT.  */
 525
 526 static const struct powerpc_opcode *
 527 lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
 528 {
 529   const struct powerpc_opcode *opcode, *opcode_end, *last;
 530   unsigned long op;
 531
 532   /* Get the major opcode of the instruction.  */
 533   op = PPC_OP (insn);
 534
 535   /* Find the first match in the opcode table for this major opcode.  */
 536   opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
 537   last = NULL;
 538   for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
 539        opcode < opcode_end;
 540        ++opcode)
 541     {
 542       const unsigned char *opindex;
 543       const struct powerpc_operand *operand;
 544       int invalid;
 545
 546       if ((insn & opcode->mask) != opcode->opcode
 547           || ((dialect & PPC_OPCODE_ANY) == 0
 548               && ((opcode->flags & dialect) == 0
 549                   || (opcode->deprecated & dialect) != 0)))
 550         continue;
 551
 552       /* Check validity of operands.  */
 553       invalid = 0;
 554       for (opindex = opcode->operands; *opindex != 0; opindex++)
 555         {
 556           operand = powerpc_operands + *opindex;
 557           if (operand->extract)
 558             (*operand->extract) (insn, dialect, &invalid);
 559         }
 560       if (invalid)
 561         continue;
 562
 563       if ((dialect & PPC_OPCODE_RAW) == 0)
 564         return opcode;
 565
 566       /* The raw machine insn is one that is not a specialization.  */
 567       if (last == NULL
 568           || (last->mask & ~opcode->mask) != 0)
 569         last = opcode;
 570     }
 571
 572   return last;
 573 }
 574
 575 /* Find a match for INSN in the PREFIX opcode table.  */
 576
 577 static const struct powerpc_opcode *
 578 lookup_prefix (uint64_t insn, ppc_cpu_t dialect)
 579 {
 580   const struct powerpc_opcode *opcode, *opcode_end, *last;
 581   unsigned long seg;
 582
 583   /* Get the opcode segment of the instruction.  */
 584   seg = PPC_PREFIX_SEG (insn);
 585
 586   /* Find the first match in the opcode table for this major opcode.  */
 587   opcode_end = prefix_opcodes + prefix_opcd_indices[seg + 1];
 588   last = NULL;
 589   for (opcode = prefix_opcodes + prefix_opcd_indices[seg];
 590        opcode < opcode_end;
 591        ++opcode)
 592     {
 593       const unsigned char *opindex;
 594       const struct powerpc_operand *operand;
 595       int invalid;
 596
 597       if ((insn & opcode->mask) != opcode->opcode
 598           || ((dialect & PPC_OPCODE_ANY) == 0
 599               && ((opcode->flags & dialect) == 0
 600                   || (opcode->deprecated & dialect) != 0)))
 601         continue;
 602
 603       /* Check validity of operands.  */
 604       invalid = 0;
 605       for (opindex = opcode->operands; *opindex != 0; opindex++)
 606         {
 607           operand = powerpc_operands + *opindex;
 608           if (operand->extract)
 609             (*operand->extract) (insn, dialect, &invalid);
 610         }
 611       if (invalid)
 612         continue;
 613
 614       if ((dialect & PPC_OPCODE_RAW) == 0)
 615         return opcode;
 616
 617       /* The raw machine insn is one that is not a specialization.  */
 618       if (last == NULL
 619           || (last->mask & ~opcode->mask) != 0)
 620         last = opcode;
 621     }
 622
 623   return last;
 624 }
 625
 626 /* Find a match for INSN in the VLE opcode table.  */
 627
 628 static const struct powerpc_opcode *
 629 lookup_vle (uint64_t insn)
 630 {
 631   const struct powerpc_opcode *opcode;
 632   const struct powerpc_opcode *opcode_end;
 633   unsigned op, seg;
 634
 635   op = PPC_OP (insn);
 636   if (op >= 0x20 && op <= 0x37)
 637     {
 638       /* This insn has a 4-bit opcode.  */
 639       op &= 0x3c;
 640     }
 641   seg = VLE_OP_TO_SEG (op);
 642
 643   /* Find the first match in the opcode table for this major opcode.  */
 644   opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
 645   for (opcode = vle_opcodes + vle_opcd_indices[seg];
 646        opcode < opcode_end;
 647        ++opcode)
 648     {
 649       uint64_t table_opcd = opcode->opcode;
 650       uint64_t table_mask = opcode->mask;
 651       bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
 652       uint64_t insn2;
 653       const unsigned char *opindex;
 654       const struct powerpc_operand *operand;
 655       int invalid;
 656
 657       insn2 = insn;
 658       if (table_op_is_short)
 659         insn2 >>= 16;
 660       if ((insn2 & table_mask) != table_opcd)
 661         continue;
 662
 663       /* Check validity of operands.  */
 664       invalid = 0;
 665       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 666         {
 667           operand = powerpc_operands + *opindex;
 668           if (operand->extract)
 669             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 670         }
 671       if (invalid)
 672         continue;
 673
 674       return opcode;
 675     }
 676
 677   return NULL;
 678 }
 679
 680 /* Find a match for INSN in the SPE2 opcode table.  */
 681
 682 static const struct powerpc_opcode *
 683 lookup_spe2 (uint64_t insn)
 684 {
 685   const struct powerpc_opcode *opcode, *opcode_end;
 686   unsigned op, xop, seg;
 687
 688   op = PPC_OP (insn);
 689   if (op != 0x4)
 690     {
 691       /* This is not SPE2 insn.
 692        * All SPE2 instructions have OP=4 and differs by XOP  */
 693       return NULL;
 694     }
 695   xop = SPE2_XOP (insn);
 696   seg = SPE2_XOP_TO_SEG (xop);
 697
 698   /* Find the first match in the opcode table for this major opcode.  */
 699   opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1];
 700   for (opcode = spe2_opcodes + spe2_opcd_indices[seg];
 701        opcode < opcode_end;
 702        ++opcode)
 703     {
 704       uint64_t table_opcd = opcode->opcode;
 705       uint64_t table_mask = opcode->mask;
 706       uint64_t insn2;
 707       const unsigned char *opindex;
 708       const struct powerpc_operand *operand;
 709       int invalid;
 710
 711       insn2 = insn;
 712       if ((insn2 & table_mask) != table_opcd)
 713         continue;
 714
 715       /* Check validity of operands.  */
 716       invalid = 0;
 717       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 718         {
 719           operand = powerpc_operands + *opindex;
 720           if (operand->extract)
 721             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 722         }
 723       if (invalid)
 724         continue;
 725
 726       return opcode;
 727     }
 728
 729   return NULL;
 730 }
 731
 732 /* Print a PowerPC or POWER instruction.  */
 733
 734 static int
 735 print_insn_powerpc (bfd_vma memaddr,
 736                     struct disassemble_info *info,
 737                     int bigendian,
 738                     ppc_cpu_t dialect)
 739 {
 740   bfd_byte buffer[4];
 741   int status;
 742   uint64_t insn;
 743   const struct powerpc_opcode *opcode;
 744   int insn_length = 4;  /* Assume we have a normal 4-byte instruction.  */
 745
 746   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
 747
 748   /* The final instruction may be a 2-byte VLE insn.  */
 749   if (status != 0 && (dialect & PPC_OPCODE_VLE) != 0)
 750     {
 751       /* Clear buffer so unused bytes will not have garbage in them.  */
 752       buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
 753       status = (*info->read_memory_func) (memaddr, buffer, 2, info);
 754     }
 755
 756   if (status != 0)
 757     {
 758       (*info->memory_error_func) (status, memaddr, info);
 759       return -1;
 760     }
 761
 762   if (bigendian)
 763     insn = bfd_getb32 (buffer);
 764   else
 765     insn = bfd_getl32 (buffer);
 766
 767   /* Get the major opcode of the insn.  */
 768   opcode = NULL;
 769   if ((dialect & PPC_OPCODE_POWERXX) != 0
 770       && PPC_OP (insn) == 0x1)
 771     {
 772       uint64_t temp_insn, suffix;
 773       status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
 774       if (status == 0)
 775         {
 776           if (bigendian)
 777             suffix = bfd_getb32 (buffer);
 778           else
 779             suffix = bfd_getl32 (buffer);
 780           temp_insn = (insn << 32) | suffix;
 781           opcode = lookup_prefix (temp_insn, dialect & ~PPC_OPCODE_ANY);
 782           if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
 783             opcode = lookup_prefix (temp_insn, dialect);
 784           if (opcode != NULL)
 785             {
 786               insn = temp_insn;
 787               insn_length = 8;
 788               if ((info->flags & WIDE_OUTPUT) != 0)
 789                 info->bytes_per_line = 8;
 790             }
 791         }
 792     }
 793   if (opcode == NULL && (dialect & PPC_OPCODE_VLE) != 0)
 794     {
 795       opcode = lookup_vle (insn);
 796       if (opcode != NULL && PPC_OP_SE_VLE (opcode->mask))
 797         {
 798           /* The operands will be fetched out of the 16-bit instruction.  */
 799           insn >>= 16;
 800           insn_length = 2;
 801         }
 802     }
 803   if (opcode == NULL && (dialect & PPC_OPCODE_SPE2) != 0)
 804     opcode = lookup_spe2 (insn);
 805   if (opcode == NULL)
 806     opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY);
 807   if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
 808     opcode = lookup_powerpc (insn, dialect);
 809
 810   if (opcode != NULL)
 811     {
 812       const unsigned char *opindex;
 813       const struct powerpc_operand *operand;
 814       enum {
 815         need_comma = 0,
 816         need_1space = 1,
 817         need_2spaces = 2,
 818         need_3spaces = 3,
 819         need_4spaces = 4,
 820         need_5spaces = 5,
 821         need_6spaces = 6,
 822         need_7spaces = 7,
 823         need_paren
 824       } op_separator;
 825       bfd_boolean skip_optional;
 826       int spaces;
 827
 828       (*info->fprintf_func) (info->stream, "%s", opcode->name);
 829       /* gdb fprintf_func doesn't return count printed.  */
 830       spaces = 8 - strlen (opcode->name);
 831       if (spaces <= 0)
 832         spaces = 1;
 833
 834       /* Now extract and print the operands.  */
 835       op_separator = spaces;
 836       skip_optional = FALSE;
 837       for (opindex = opcode->operands; *opindex != 0; opindex++)
 838         {
 839           int64_t value;
 840
 841           operand = powerpc_operands + *opindex;
 842
 843           /* If all of the optional operands past this one have their
 844              default value, then don't print any of them.  Except in
 845              raw mode, print them all.  */
 846           if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
 847               && (dialect & PPC_OPCODE_RAW) == 0)
 848             {
 849               if (!skip_optional)
 850                 skip_optional = skip_optional_operands (opindex, insn, dialect);
 851               if (skip_optional)
 852                 continue;
 853             }
 854
 855           value = operand_value_powerpc (operand, insn, dialect);
 856
 857           if (op_separator == need_comma)
 858             (*info->fprintf_func) (info->stream, ",");
 859           else if (op_separator == need_paren)
 860             (*info->fprintf_func) (info->stream, "(");
 861           else
 862             (*info->fprintf_func) (info->stream, "%*s", op_separator, " ");
 863
 864           /* Print the operand as directed by the flags.  */
 865           if ((operand->flags & PPC_OPERAND_GPR) != 0
 866               || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
 867             (*info->fprintf_func) (info->stream, "r%" PRId64, value);
 868           else if ((operand->flags & PPC_OPERAND_FPR) != 0)
 869             (*info->fprintf_func) (info->stream, "f%" PRId64, value);
 870           else if ((operand->flags & PPC_OPERAND_VR) != 0)
 871             (*info->fprintf_func) (info->stream, "v%" PRId64, value);
 872           else if ((operand->flags & PPC_OPERAND_VSR) != 0)
 873             (*info->fprintf_func) (info->stream, "vs%" PRId64, value);
 874           else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
 875             (*info->print_address_func) (memaddr + value, info);
 876           else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
 877             (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
 878           else if ((operand->flags & PPC_OPERAND_FSL) != 0)
 879             (*info->fprintf_func) (info->stream, "fsl%" PRId64, value);
 880           else if ((operand->flags & PPC_OPERAND_FCR) != 0)
 881             (*info->fprintf_func) (info->stream, "fcr%" PRId64, value);
 882           else if ((operand->flags & PPC_OPERAND_UDI) != 0)
 883             (*info->fprintf_func) (info->stream, "%" PRId64, value);
 884           else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
 885                    && (operand->flags & PPC_OPERAND_CR_BIT) == 0
 886                    && (((dialect & PPC_OPCODE_PPC) != 0)
 887                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 888             (*info->fprintf_func) (info->stream, "cr%" PRId64, value);
 889           else if ((operand->flags & PPC_OPERAND_CR_BIT) != 0
 890                    && (operand->flags & PPC_OPERAND_CR_REG) == 0
 891                    && (((dialect & PPC_OPCODE_PPC) != 0)
 892                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 893             {
 894               static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
 895               int cr;
 896               int cc;
 897
 898               cr = value >> 2;
 899               if (cr != 0)
 900                 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
 901               cc = value & 3;
 902               (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
 903             }
 904           else
 905             (*info->fprintf_func) (info->stream, "%" PRId64, value);
 906
 907           if (op_separator == need_paren)
 908             (*info->fprintf_func) (info->stream, ")");
 909
 910           op_separator = need_comma;
 911           if ((operand->flags & PPC_OPERAND_PARENS) != 0)
 912             op_separator = need_paren;
 913         }
 914
 915       /* We have found and printed an instruction.  */
 916       return insn_length;
 917     }
 918
 919   /* We could not find a match.  */
 920   (*info->fprintf_func) (info->stream, ".long 0x%" PRIx64, insn);
 921
 922   return 4;
 923 }
 924
 925 const disasm_options_and_args_t *
 926 disassembler_options_powerpc (void)
 927 {
 928   static disasm_options_and_args_t *opts_and_args;
 929
 930   if (opts_and_args == NULL)
 931     {
 932       size_t i, num_options = ARRAY_SIZE (ppc_opts);
 933       disasm_options_t *opts;
 934
 935       opts_and_args = XNEW (disasm_options_and_args_t);
 936       opts_and_args->args = NULL;
 937
 938       opts = &opts_and_args->options;
 939       opts->name = XNEWVEC (const char *, num_options + 1);
 940       opts->description = NULL;
 941       opts->arg = NULL;
 942       for (i = 0; i < num_options; i++)
 943         opts->name[i] = ppc_opts[i].opt;
 944       /* The array we return must be NULL terminated.  */
 945       opts->name[i] = NULL;
 946     }
 947
 948   return opts_and_args;
 949 }
 950
 951 void
 952 print_ppc_disassembler_options (FILE *stream)
 953 {
 954   unsigned int i, col;
 955
 956   fprintf (stream, _("\n\
 957 The following PPC specific disassembler options are supported for use with\n\
 958 the -M switch:\n"));
 959
 960   for (col = 0, i = 0; i < ARRAY_SIZE (ppc_opts); i++)
 961     {
 962       col += fprintf (stream, " %s,", ppc_opts[i].opt);
 963       if (col > 66)
 964         {
 965           fprintf (stream, "\n");
 966           col = 0;
 967         }
 968     }
 969   fprintf (stream, "\n");
 970 }