opcodes/ppc-dis.c

   1 /* ppc-dis.c -- Disassemble PowerPC instructions
   2    Copyright (C) 1994-2017 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #include "sysdep.h"
  23 #include <stdio.h>
  24 #include "dis-asm.h"
  25 #include "elf-bfd.h"
  26 #include "elf/ppc.h"
  27 #include "opintl.h"
  28 #include "opcode/ppc.h"
  29 #include "libiberty.h"
  30
  31 /* This file provides several disassembler functions, all of which use
  32    the disassembler interface defined in dis-asm.h.  Several functions
  33    are provided because this file handles disassembly for the PowerPC
  34    in both big and little endian mode and also for the POWER (RS/6000)
  35    chip.  */
  36 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
  37                                ppc_cpu_t);
  38
  39 struct dis_private
  40 {
  41   /* Stash the result of parsing disassembler_options here.  */
  42   ppc_cpu_t dialect;
  43 } private;
  44
  45 #define POWERPC_DIALECT(INFO) \
  46   (((struct dis_private *) ((INFO)->private_data))->dialect)
  47
  48 struct ppc_mopt {
  49   /* Option string, without -m or -M prefix.  */
  50   const char *opt;
  51   /* CPU option flags.  */
  52   ppc_cpu_t cpu;
  53   /* Flags that should stay on, even when combined with another cpu
  54      option.  This should only be used for generic options like
  55      "-many" or "-maltivec" where it is reasonable to add some
  56      capability to another cpu selection.  The added flags are sticky
  57      so that, for example, "-many -me500" and "-me500 -many" result in
  58      the same assembler or disassembler behaviour.  Do not use
  59      "sticky" for specific cpus, as this will prevent that cpu's flags
  60      from overriding the defaults set in powerpc_init_dialect or a
  61      prior -m option.  */
  62   ppc_cpu_t sticky;
  63 };
  64
  65 struct ppc_mopt ppc_opts[] = {
  66   { "403",     PPC_OPCODE_PPC | PPC_OPCODE_403,
  67     0 },
  68   { "405",     PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
  69     0 },
  70   { "440",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  71                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  72     0 },
  73   { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  74                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  75     0 },
  76   { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_476
  77                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
  78     0 },
  79   { "601",     PPC_OPCODE_PPC | PPC_OPCODE_601,
  80     0 },
  81   { "603",     PPC_OPCODE_PPC,
  82     0 },
  83   { "604",     PPC_OPCODE_PPC,
  84     0 },
  85   { "620",     PPC_OPCODE_PPC | PPC_OPCODE_64,
  86     0 },
  87   { "7400",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  88     0 },
  89   { "7410",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  90     0 },
  91   { "7450",    PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
  92     0 },
  93   { "7455",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  94     0 },
  95   { "750cl",   PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
  96     , 0 },
  97   { "821",     PPC_OPCODE_PPC | PPC_OPCODE_860,
  98     0 },
  99   { "850",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 100     0 },
 101   { "860",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 102     0 },
 103   { "a2",      (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
 104                 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
 105                 | PPC_OPCODE_A2),
 106     0 },
 107   { "altivec", PPC_OPCODE_PPC,
 108     PPC_OPCODE_ALTIVEC },
 109   { "any",     PPC_OPCODE_PPC,
 110     PPC_OPCODE_ANY },
 111   { "booke",   PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
 112     0 },
 113   { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
 114     0 },
 115   { "cell",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 116                 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
 117     0 },
 118   { "com",     PPC_OPCODE_COMMON,
 119     0 },
 120   { "e200z4",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
 121                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 122                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 123                 | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4),
 124     0 },
 125   { "e300",    PPC_OPCODE_PPC | PPC_OPCODE_E300,
 126     0 },
 127   { "e500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 128                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 129                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 130                 | PPC_OPCODE_E500),
 131     0 },
 132   { "e500mc",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 133                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 134                 | PPC_OPCODE_E500MC),
 135     0 },
 136   { "e500mc64",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 137                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 138                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
 139                 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 140     0 },
 141   { "e5500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 142                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 143                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 144                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 145                 | PPC_OPCODE_POWER7),
 146     0 },
 147   { "e6500",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 148                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 149                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
 150                 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
 151                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 152     0 },
 153   { "e500x2",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 154                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 155                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 156                 | PPC_OPCODE_E500),
 157     0 },
 158   { "efs",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
 159     0 },
 160   { "power4",  PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
 161     0 },
 162   { "power5",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 163                 | PPC_OPCODE_POWER5),
 164     0 },
 165   { "power6",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 166                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 167     0 },
 168   { "power7",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 169                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 170                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 171     0 },
 172   { "power8",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 173                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 174                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
 175                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 176     0 },
 177   { "power9",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 178                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 179                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 180                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 181     0 },
 182   { "ppc",     PPC_OPCODE_PPC,
 183     0 },
 184   { "ppc32",   PPC_OPCODE_PPC,
 185     0 },
 186   { "32",      PPC_OPCODE_PPC,
 187     0 },
 188   { "ppc64",   PPC_OPCODE_PPC | PPC_OPCODE_64,
 189     0 },
 190   { "64",      PPC_OPCODE_PPC | PPC_OPCODE_64,
 191     0 },
 192   { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
 193     0 },
 194   { "ppcps",   PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
 195     0 },
 196   { "pwr",     PPC_OPCODE_POWER,
 197     0 },
 198   { "pwr2",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
 199     0 },
 200   { "pwr4",    PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
 201     0 },
 202   { "pwr5",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 203                 | PPC_OPCODE_POWER5),
 204     0 },
 205   { "pwr5x",   (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 206                 | PPC_OPCODE_POWER5),
 207     0 },
 208   { "pwr6",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 209                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 210     0 },
 211   { "pwr7",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 212                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 213                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 214     0 },
 215   { "pwr8",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 216                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 217                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
 218                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 219     0 },
 220   { "pwr9",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 221                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 222                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 223                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 224     0 },
 225   { "pwrx",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
 226     0 },
 227   { "raw",     PPC_OPCODE_PPC,
 228     PPC_OPCODE_RAW },
 229   { "spe",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
 230     PPC_OPCODE_SPE },
 231   { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
 232                 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
 233     0 },
 234   { "vle",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
 235                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 236                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 237                 | PPC_OPCODE_E500),
 238     PPC_OPCODE_VLE },
 239   { "vsx",     PPC_OPCODE_PPC,
 240     PPC_OPCODE_VSX },
 241 };
 242
 243 /* Switch between Booke and VLE dialects for interlinked dumps.  */
 244 static ppc_cpu_t
 245 get_powerpc_dialect (struct disassemble_info *info)
 246 {
 247   ppc_cpu_t dialect = 0;
 248
 249   dialect = POWERPC_DIALECT (info);
 250
 251   /* Disassemble according to the section headers flags for VLE-mode.  */
 252   if (dialect & PPC_OPCODE_VLE
 253       && info->section != NULL && info->section->owner != NULL
 254       && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
 255       && elf_object_id (info->section->owner) == PPC32_ELF_DATA
 256       && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
 257     return dialect;
 258   else
 259     return dialect & ~ PPC_OPCODE_VLE;
 260 }
 261
 262 /* Handle -m and -M options that set cpu type, and .machine arg.  */
 263
 264 ppc_cpu_t
 265 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
 266 {
 267   unsigned int i;
 268
 269   for (i = 0; i < ARRAY_SIZE (ppc_opts); i++)
 270     if (disassembler_options_cmp (ppc_opts[i].opt, arg) == 0)
 271       {
 272         if (ppc_opts[i].sticky)
 273           {
 274             *sticky |= ppc_opts[i].sticky;
 275             if ((ppc_cpu & ~*sticky) != 0)
 276               break;
 277           }
 278         ppc_cpu = ppc_opts[i].cpu;
 279         break;
 280       }
 281   if (i >= ARRAY_SIZE (ppc_opts))
 282     return 0;
 283
 284   ppc_cpu |= *sticky;
 285   return ppc_cpu;
 286 }
 287
 288 /* Determine which set of machines to disassemble for.  */
 289
 290 static void
 291 powerpc_init_dialect (struct disassemble_info *info)
 292 {
 293   ppc_cpu_t dialect = 0;
 294   ppc_cpu_t sticky = 0;
 295   struct dis_private *priv = calloc (sizeof (*priv), 1);
 296
 297   if (priv == NULL)
 298     priv = &private;
 299
 300   switch (info->mach)
 301     {
 302     case bfd_mach_ppc_403:
 303     case bfd_mach_ppc_403gc:
 304       dialect = ppc_parse_cpu (dialect, &sticky, "403");
 305       break;
 306     case bfd_mach_ppc_405:
 307       dialect = ppc_parse_cpu (dialect, &sticky, "405");
 308       break;
 309     case bfd_mach_ppc_601:
 310       dialect = ppc_parse_cpu (dialect, &sticky, "601");
 311       break;
 312     case bfd_mach_ppc_a35:
 313     case bfd_mach_ppc_rs64ii:
 314     case bfd_mach_ppc_rs64iii:
 315       dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
 316       break;
 317     case bfd_mach_ppc_e500:
 318       dialect = ppc_parse_cpu (dialect, &sticky, "e500");
 319       break;
 320     case bfd_mach_ppc_e500mc:
 321       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
 322       break;
 323     case bfd_mach_ppc_e500mc64:
 324       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
 325       break;
 326     case bfd_mach_ppc_e5500:
 327       dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
 328       break;
 329     case bfd_mach_ppc_e6500:
 330       dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
 331       break;
 332     case bfd_mach_ppc_titan:
 333       dialect = ppc_parse_cpu (dialect, &sticky, "titan");
 334       break;
 335     case bfd_mach_ppc_vle:
 336       dialect = ppc_parse_cpu (dialect, &sticky, "vle");
 337       break;
 338     default:
 339       dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY;
 340       break;
 341     }
 342
 343   const char *opt;
 344   FOR_EACH_DISASSEMBLER_OPTION (opt, info->disassembler_options)
 345     {
 346       ppc_cpu_t new_cpu = 0;
 347
 348       if (disassembler_options_cmp (opt, "32") == 0)
 349         dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
 350       else if (disassembler_options_cmp (opt, "64") == 0)
 351         dialect |= PPC_OPCODE_64;
 352       else if ((new_cpu = ppc_parse_cpu (dialect, &sticky, opt)) != 0)
 353         dialect = new_cpu;
 354       else
 355         fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), opt);
 356     }
 357
 358   info->private_data = priv;
 359   POWERPC_DIALECT(info) = dialect;
 360 }
 361
 362 #define PPC_OPCD_SEGS 64
 363 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
 364 #define VLE_OPCD_SEGS 32
 365 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
 366
 367 /* Calculate opcode table indices to speed up disassembly,
 368    and init dialect.  */
 369
 370 void
 371 disassemble_init_powerpc (struct disassemble_info *info)
 372 {
 373   int i;
 374   unsigned short last;
 375
 376   if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
 377     {
 378
 379       i = powerpc_num_opcodes;
 380       while (--i >= 0)
 381         {
 382           unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
 383
 384           powerpc_opcd_indices[op] = i;
 385         }
 386
 387       last = powerpc_num_opcodes;
 388       for (i = PPC_OPCD_SEGS; i > 0; --i)
 389         {
 390           if (powerpc_opcd_indices[i] == 0)
 391             powerpc_opcd_indices[i] = last;
 392           last = powerpc_opcd_indices[i];
 393         }
 394
 395       i = vle_num_opcodes;
 396       while (--i >= 0)
 397         {
 398           unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
 399           unsigned seg = VLE_OP_TO_SEG (op);
 400
 401           vle_opcd_indices[seg] = i;
 402         }
 403
 404       last = vle_num_opcodes;
 405       for (i = VLE_OPCD_SEGS; i > 0; --i)
 406         {
 407           if (vle_opcd_indices[i] == 0)
 408             vle_opcd_indices[i] = last;
 409           last = vle_opcd_indices[i];
 410         }
 411     }
 412
 413   if (info->arch == bfd_arch_powerpc)
 414     powerpc_init_dialect (info);
 415 }
 416
 417 /* Print a big endian PowerPC instruction.  */
 418
 419 int
 420 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 421 {
 422   return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
 423 }
 424
 425 /* Print a little endian PowerPC instruction.  */
 426
 427 int
 428 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 429 {
 430   return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
 431 }
 432
 433 /* Print a POWER (RS/6000) instruction.  */
 434
 435 int
 436 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
 437 {
 438   return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
 439 }
 440
 441 /* Extract the operand value from the PowerPC or POWER instruction.  */
 442
 443 static long
 444 operand_value_powerpc (const struct powerpc_operand *operand,
 445                        unsigned long insn, ppc_cpu_t dialect)
 446 {
 447   long value;
 448   int invalid;
 449   /* Extract the value from the instruction.  */
 450   if (operand->extract)
 451     value = (*operand->extract) (insn, dialect, &invalid);
 452   else
 453     {
 454       if (operand->shift >= 0)
 455         value = (insn >> operand->shift) & operand->bitm;
 456       else
 457         value = (insn << -operand->shift) & operand->bitm;
 458       if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
 459         {
 460           /* BITM is always some number of zeros followed by some
 461              number of ones, followed by some number of zeros.  */
 462           unsigned long top = operand->bitm;
 463           /* top & -top gives the rightmost 1 bit, so this
 464              fills in any trailing zeros.  */
 465           top |= (top & -top) - 1;
 466           top &= ~(top >> 1);
 467           value = (value ^ top) - top;
 468         }
 469     }
 470
 471   return value;
 472 }
 473
 474 /* Determine whether the optional operand(s) should be printed.  */
 475
 476 static int
 477 skip_optional_operands (const unsigned char *opindex,
 478                         unsigned long insn, ppc_cpu_t dialect)
 479 {
 480   const struct powerpc_operand *operand;
 481
 482   for (; *opindex != 0; opindex++)
 483     {
 484       operand = &powerpc_operands[*opindex];
 485       if ((operand->flags & PPC_OPERAND_NEXT) != 0
 486           || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
 487               && operand_value_powerpc (operand, insn, dialect) !=
 488                  ppc_optional_operand_value (operand)))
 489         return 0;
 490     }
 491
 492   return 1;
 493 }
 494
 495 /* Find a match for INSN in the opcode table, given machine DIALECT.  */
 496
 497 static const struct powerpc_opcode *
 498 lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
 499 {
 500   const struct powerpc_opcode *opcode, *opcode_end, *last;
 501   unsigned long op;
 502
 503   /* Get the major opcode of the instruction.  */
 504   op = PPC_OP (insn);
 505
 506   /* Find the first match in the opcode table for this major opcode.  */
 507   opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
 508   last = NULL;
 509   for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
 510        opcode < opcode_end;
 511        ++opcode)
 512     {
 513       const unsigned char *opindex;
 514       const struct powerpc_operand *operand;
 515       int invalid;
 516
 517       if ((insn & opcode->mask) != opcode->opcode
 518           || ((dialect & PPC_OPCODE_ANY) == 0
 519               && ((opcode->flags & dialect) == 0
 520                   || (opcode->deprecated & dialect) != 0)))
 521         continue;
 522
 523       /* Check validity of operands.  */
 524       invalid = 0;
 525       for (opindex = opcode->operands; *opindex != 0; opindex++)
 526         {
 527           operand = powerpc_operands + *opindex;
 528           if (operand->extract)
 529             (*operand->extract) (insn, dialect, &invalid);
 530         }
 531       if (invalid)
 532         continue;
 533
 534       if ((dialect & PPC_OPCODE_RAW) == 0)
 535         return opcode;
 536
 537       /* The raw machine insn is one that is not a specialization.  */
 538       if (last == NULL
 539           || (last->mask & ~opcode->mask) != 0)
 540         last = opcode;
 541     }
 542
 543   return last;
 544 }
 545
 546 /* Find a match for INSN in the VLE opcode table.  */
 547
 548 static const struct powerpc_opcode *
 549 lookup_vle (unsigned long insn)
 550 {
 551   const struct powerpc_opcode *opcode;
 552   const struct powerpc_opcode *opcode_end;
 553   unsigned op, seg;
 554
 555   op = PPC_OP (insn);
 556   if (op >= 0x20 && op <= 0x37)
 557     {
 558       /* This insn has a 4-bit opcode.  */
 559       op &= 0x3c;
 560     }
 561   seg = VLE_OP_TO_SEG (op);
 562
 563   /* Find the first match in the opcode table for this major opcode.  */
 564   opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
 565   for (opcode = vle_opcodes + vle_opcd_indices[seg];
 566        opcode < opcode_end;
 567        ++opcode)
 568     {
 569       unsigned long table_opcd = opcode->opcode;
 570       unsigned long table_mask = opcode->mask;
 571       bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
 572       unsigned long insn2;
 573       const unsigned char *opindex;
 574       const struct powerpc_operand *operand;
 575       int invalid;
 576
 577       insn2 = insn;
 578       if (table_op_is_short)
 579         insn2 >>= 16;
 580       if ((insn2 & table_mask) != table_opcd)
 581         continue;
 582
 583       /* Check validity of operands.  */
 584       invalid = 0;
 585       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 586         {
 587           operand = powerpc_operands + *opindex;
 588           if (operand->extract)
 589             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 590         }
 591       if (invalid)
 592         continue;
 593
 594       return opcode;
 595     }
 596
 597   return NULL;
 598 }
 599
 600 /* Print a PowerPC or POWER instruction.  */
 601
 602 static int
 603 print_insn_powerpc (bfd_vma memaddr,
 604                     struct disassemble_info *info,
 605                     int bigendian,
 606                     ppc_cpu_t dialect)
 607 {
 608   bfd_byte buffer[4];
 609   int status;
 610   unsigned long insn;
 611   const struct powerpc_opcode *opcode;
 612   bfd_boolean insn_is_short;
 613
 614   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
 615   if (status != 0)
 616     {
 617       /* The final instruction may be a 2-byte VLE insn.  */
 618       if ((dialect & PPC_OPCODE_VLE) != 0)
 619         {
 620           /* Clear buffer so unused bytes will not have garbage in them.  */
 621           buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
 622           status = (*info->read_memory_func) (memaddr, buffer, 2, info);
 623           if (status != 0)
 624             {
 625               (*info->memory_error_func) (status, memaddr, info);
 626               return -1;
 627             }
 628         }
 629       else
 630         {
 631           (*info->memory_error_func) (status, memaddr, info);
 632           return -1;
 633         }
 634     }
 635
 636   if (bigendian)
 637     insn = bfd_getb32 (buffer);
 638   else
 639     insn = bfd_getl32 (buffer);
 640
 641   /* Get the major opcode of the insn.  */
 642   opcode = NULL;
 643   insn_is_short = FALSE;
 644   if ((dialect & PPC_OPCODE_VLE) != 0)
 645     {
 646       opcode = lookup_vle (insn);
 647       if (opcode != NULL)
 648         insn_is_short = PPC_OP_SE_VLE(opcode->mask);
 649     }
 650   if (opcode == NULL)
 651     opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY);
 652   if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
 653     opcode = lookup_powerpc (insn, dialect);
 654
 655   if (opcode != NULL)
 656     {
 657       const unsigned char *opindex;
 658       const struct powerpc_operand *operand;
 659       int need_comma;
 660       int need_paren;
 661       int skip_optional;
 662
 663       if (opcode->operands[0] != 0)
 664         (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
 665       else
 666         (*info->fprintf_func) (info->stream, "%s", opcode->name);
 667
 668       if (insn_is_short)
 669         /* The operands will be fetched out of the 16-bit instruction.  */
 670         insn >>= 16;
 671
 672       /* Now extract and print the operands.  */
 673       need_comma = 0;
 674       need_paren = 0;
 675       skip_optional = -1;
 676       for (opindex = opcode->operands; *opindex != 0; opindex++)
 677         {
 678           long value;
 679
 680           operand = powerpc_operands + *opindex;
 681
 682           /* Operands that are marked FAKE are simply ignored.  We
 683              already made sure that the extract function considered
 684              the instruction to be valid.  */
 685           if ((operand->flags & PPC_OPERAND_FAKE) != 0)
 686             continue;
 687
 688           /* If all of the optional operands have the value zero,
 689              then don't print any of them.  */
 690           if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
 691             {
 692               if (skip_optional < 0)
 693                 skip_optional = skip_optional_operands (opindex, insn,
 694                                                         dialect);
 695               if (skip_optional)
 696                 continue;
 697             }
 698
 699           value = operand_value_powerpc (operand, insn, dialect);
 700
 701           if (need_comma)
 702             {
 703               (*info->fprintf_func) (info->stream, ",");
 704               need_comma = 0;
 705             }
 706
 707           /* Print the operand as directed by the flags.  */
 708           if ((operand->flags & PPC_OPERAND_GPR) != 0
 709               || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
 710             (*info->fprintf_func) (info->stream, "r%ld", value);
 711           else if ((operand->flags & PPC_OPERAND_FPR) != 0)
 712             (*info->fprintf_func) (info->stream, "f%ld", value);
 713           else if ((operand->flags & PPC_OPERAND_VR) != 0)
 714             (*info->fprintf_func) (info->stream, "v%ld", value);
 715           else if ((operand->flags & PPC_OPERAND_VSR) != 0)
 716             (*info->fprintf_func) (info->stream, "vs%ld", value);
 717           else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
 718             (*info->print_address_func) (memaddr + value, info);
 719           else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
 720             (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
 721           else if ((operand->flags & PPC_OPERAND_FSL) != 0)
 722             (*info->fprintf_func) (info->stream, "fsl%ld", value);
 723           else if ((operand->flags & PPC_OPERAND_FCR) != 0)
 724             (*info->fprintf_func) (info->stream, "fcr%ld", value);
 725           else if ((operand->flags & PPC_OPERAND_UDI) != 0)
 726             (*info->fprintf_func) (info->stream, "%ld", value);
 727           else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
 728                    && (((dialect & PPC_OPCODE_PPC) != 0)
 729                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 730             (*info->fprintf_func) (info->stream, "cr%ld", value);
 731           else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
 732                    && (((dialect & PPC_OPCODE_PPC) != 0)
 733                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 734             {
 735               static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
 736               int cr;
 737               int cc;
 738
 739               cr = value >> 2;
 740               if (cr != 0)
 741                 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
 742               cc = value & 3;
 743               (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
 744             }
 745           else
 746             (*info->fprintf_func) (info->stream, "%d", (int) value);
 747
 748           if (need_paren)
 749             {
 750               (*info->fprintf_func) (info->stream, ")");
 751               need_paren = 0;
 752             }
 753
 754           if ((operand->flags & PPC_OPERAND_PARENS) == 0)
 755             need_comma = 1;
 756           else
 757             {
 758               (*info->fprintf_func) (info->stream, "(");
 759               need_paren = 1;
 760             }
 761         }
 762
 763       /* We have found and printed an instruction.
 764          If it was a short VLE instruction we have more to do.  */
 765       if (insn_is_short)
 766         {
 767           memaddr += 2;
 768           return 2;
 769         }
 770       else
 771         /* Otherwise, return.  */
 772         return 4;
 773     }
 774
 775   /* We could not find a match.  */
 776   (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
 777
 778   return 4;
 779 }
 780
 781 const disasm_options_t *
 782 disassembler_options_powerpc (void)
 783 {
 784   static disasm_options_t *opts = NULL;
 785
 786   if (opts == NULL)
 787     {
 788       size_t i, num_options = ARRAY_SIZE (ppc_opts);
 789       opts = XNEW (disasm_options_t);
 790       opts->name = XNEWVEC (const char *, num_options + 1);
 791       for (i = 0; i < num_options; i++)
 792         opts->name[i] = ppc_opts[i].opt;
 793       /* The array we return must be NULL terminated.  */
 794       opts->name[i] = NULL;
 795       opts->description = NULL;
 796     }
 797
 798   return opts;
 799 }
 800
 801 void
 802 print_ppc_disassembler_options (FILE *stream)
 803 {
 804   unsigned int i, col;
 805
 806   fprintf (stream, _("\n\
 807 The following PPC specific disassembler options are supported for use with\n\
 808 the -M switch:\n"));
 809
 810   for (col = 0, i = 0; i < ARRAY_SIZE (ppc_opts); i++)
 811     {
 812       col += fprintf (stream, " %s,", ppc_opts[i].opt);
 813       if (col > 66)
 814         {
 815           fprintf (stream, "\n");
 816           col = 0;
 817         }
 818     }
 819   fprintf (stream, "\n");
 820 }