opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright (C) 1994-2016 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #include "sysdep.h"
  23 #include <stdio.h>
  24 #include "opcode/ppc.h"
  25 #include "opintl.h"
  26
  27 /* This file holds the PowerPC opcode table.  The opcode table
  28    includes almost all of the extended instruction mnemonics.  This
  29    permits the disassembler to use them, and simplifies the assembler
  30    logic, at the cost of increasing the table size.  The table is
  31    strictly constant data, so the compiler should be able to put it in
  32    the .text section.
  33
  34    This file also holds the operand table.  All knowledge about
  35    inserting operands into instructions and vice-versa is kept in this
  36    file.  */
  37 \f
  38 /* Local insertion and extraction functions.  */
  39
  40 static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
  41 static long extract_arx (unsigned long, ppc_cpu_t, int *);
  42 static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
  43 static long extract_ary (unsigned long, ppc_cpu_t, int *);
  44 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
  45 static long extract_bat (unsigned long, ppc_cpu_t, int *);
  46 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
  47 static long extract_bba (unsigned long, ppc_cpu_t, int *);
  48 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
  49 static long extract_bdm (unsigned long, ppc_cpu_t, int *);
  50 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
  51 static long extract_bdp (unsigned long, ppc_cpu_t, int *);
  52 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
  53 static long extract_bo (unsigned long, ppc_cpu_t, int *);
  54 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
  55 static long extract_boe (unsigned long, ppc_cpu_t, int *);
  56 static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **);
  57 static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **);
  58 static long extract_dcmxs (unsigned long, ppc_cpu_t, int *);
  59 static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **);
  60 static long extract_dxd (unsigned long, ppc_cpu_t, int *);
  61 static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **);
  62 static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
  63 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
  64 static long extract_fxm (unsigned long, ppc_cpu_t, int *);
  65 static unsigned long insert_l0 (unsigned long, long, ppc_cpu_t, const char **);
  66 static long extract_l0 (unsigned long, ppc_cpu_t, int *);
  67 static unsigned long insert_l1 (unsigned long, long, ppc_cpu_t, const char **);
  68 static long extract_l1 (unsigned long, ppc_cpu_t, int *);
  69 static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
  70 static long extract_li20 (unsigned long, ppc_cpu_t, int *);
  71 static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
  72 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
  73 static long extract_mbe (unsigned long, ppc_cpu_t, int *);
  74 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
  75 static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
  76 static long extract_nb (unsigned long, ppc_cpu_t, int *);
  77 static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
  78 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
  79 static long extract_nsi (unsigned long, ppc_cpu_t, int *);
  80 static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
  81 static long extract_oimm (unsigned long, ppc_cpu_t, int *);
  82 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
  83 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
  84 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
  85 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
  86 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
  87 static long extract_rbs (unsigned long, ppc_cpu_t, int *);
  88 static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
  89 static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
  90 static long extract_rx (unsigned long, ppc_cpu_t, int *);
  91 static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
  92 static long extract_ry (unsigned long, ppc_cpu_t, int *);
  93 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
  94 static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
  95 static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
  96 static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
  97 static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
  98 static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
  99 static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
 100 static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
 101 static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
 102 static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
 103 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
 104 static long extract_spr (unsigned long, ppc_cpu_t, int *);
 105 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
 106 static long extract_sprg (unsigned long, ppc_cpu_t, int *);
 107 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
 108 static long extract_tbr (unsigned long, ppc_cpu_t, int *);
 109 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
 110 static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
 111 static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **);
 112 static long extract_xtq6 (unsigned long, ppc_cpu_t, int *);
 113 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
 114 static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
 115 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
 116 static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
 117 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
 118 static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
 119 static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
 120 static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
 121 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
 122 static long extract_dm (unsigned long, ppc_cpu_t, int *);
 123 static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
 124 static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
 125 static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
 126 static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
 127 static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
 128 static long extract_vleui (unsigned long, ppc_cpu_t, int *);
 129 static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
 130 static long extract_vleil (unsigned long, ppc_cpu_t, int *);
 131 \f
 132 /* The operands table.
 133
 134    The fields are bitm, shift, insert, extract, flags.
 135
 136    We used to put parens around the various additions, like the one
 137    for BA just below.  However, that caused trouble with feeble
 138    compilers with a limit on depth of a parenthesized expression, like
 139    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
 140    omit the parens, since the macros are never used in a context where
 141    the addition will be ambiguous.  */
 142
 143 const struct powerpc_operand powerpc_operands[] =
 144 {
 145   /* The zero index is used to indicate the end of the list of
 146      operands.  */
 147 #define UNUSED 0
 148   { 0, 0, NULL, NULL, 0 },
 149
 150   /* The BA field in an XL form instruction.  */
 151 #define BA UNUSED + 1
 152   /* The BI field in a B form or XL form instruction.  */
 153 #define BI BA
 154 #define BI_MASK (0x1f << 16)
 155   { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
 156
 157   /* The BA field in an XL form instruction when it must be the same
 158      as the BT field in the same instruction.  */
 159 #define BAT BA + 1
 160   { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 161
 162   /* The BB field in an XL form instruction.  */
 163 #define BB BAT + 1
 164 #define BB_MASK (0x1f << 11)
 165   { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
 166
 167   /* The BB field in an XL form instruction when it must be the same
 168      as the BA field in the same instruction.  */
 169 #define BBA BB + 1
 170   /* The VB field in a VX form instruction when it must be the same
 171      as the VA field in the same instruction.  */
 172 #define VBA BBA
 173   { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 174
 175   /* The BD field in a B form instruction.  The lower two bits are
 176      forced to zero.  */
 177 #define BD BBA + 1
 178   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 179
 180   /* The BD field in a B form instruction when absolute addressing is
 181      used.  */
 182 #define BDA BD + 1
 183   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 184
 185   /* The BD field in a B form instruction when the - modifier is used.
 186      This sets the y bit of the BO field appropriately.  */
 187 #define BDM BDA + 1
 188   { 0xfffc, 0, insert_bdm, extract_bdm,
 189     PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 190
 191   /* The BD field in a B form instruction when the - modifier is used
 192      and absolute address is used.  */
 193 #define BDMA BDM + 1
 194   { 0xfffc, 0, insert_bdm, extract_bdm,
 195     PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 196
 197   /* The BD field in a B form instruction when the + modifier is used.
 198      This sets the y bit of the BO field appropriately.  */
 199 #define BDP BDMA + 1
 200   { 0xfffc, 0, insert_bdp, extract_bdp,
 201     PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 202
 203   /* The BD field in a B form instruction when the + modifier is used
 204      and absolute addressing is used.  */
 205 #define BDPA BDP + 1
 206   { 0xfffc, 0, insert_bdp, extract_bdp,
 207     PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 208
 209   /* The BF field in an X or XL form instruction.  */
 210 #define BF BDPA + 1
 211   /* The CRFD field in an X form instruction.  */
 212 #define CRFD BF
 213   /* The CRD field in an XL form instruction.  */
 214 #define CRD BF
 215   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
 216
 217   /* The BF field in an X or XL form instruction.  */
 218 #define BFF BF + 1
 219   { 0x7, 23, NULL, NULL, 0 },
 220
 221   /* An optional BF field.  This is used for comparison instructions,
 222      in which an omitted BF field is taken as zero.  */
 223 #define OBF BFF + 1
 224   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
 225
 226   /* The BFA field in an X or XL form instruction.  */
 227 #define BFA OBF + 1
 228   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
 229
 230   /* The BO field in a B form instruction.  Certain values are
 231      illegal.  */
 232 #define BO BFA + 1
 233 #define BO_MASK (0x1f << 21)
 234   { 0x1f, 21, insert_bo, extract_bo, 0 },
 235
 236   /* The BO field in a B form instruction when the + or - modifier is
 237      used.  This is like the BO field, but it must be even.  */
 238 #define BOE BO + 1
 239   { 0x1e, 21, insert_boe, extract_boe, 0 },
 240
 241 #define BH BOE + 1
 242   { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 243
 244   /* The BT field in an X or XL form instruction.  */
 245 #define BT BH + 1
 246   { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
 247
 248   /* The BI16 field in a BD8 form instruction.  */
 249 #define BI16 BT + 1
 250   { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
 251
 252   /* The BI32 field in a BD15 form instruction.  */
 253 #define BI32 BI16 + 1
 254   { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
 255
 256   /* The BO32 field in a BD15 form instruction.  */
 257 #define BO32 BI32 + 1
 258   { 0x3, 20, NULL, NULL, 0 },
 259
 260   /* The B8 field in a BD8 form instruction.  */
 261 #define B8 BO32 + 1
 262   { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 263
 264   /* The B15 field in a BD15 form instruction.  The lowest bit is
 265      forced to zero.  */
 266 #define B15 B8 + 1
 267   { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 268
 269   /* The B24 field in a BD24 form instruction.  The lowest bit is
 270      forced to zero.  */
 271 #define B24 B15 + 1
 272   { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 273
 274   /* The condition register number portion of the BI field in a B form
 275      or XL form instruction.  This is used for the extended
 276      conditional branch mnemonics, which set the lower two bits of the
 277      BI field.  This field is optional.  */
 278 #define CR B24 + 1
 279   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
 280
 281   /* The CRB field in an X form instruction.  */
 282 #define CRB CR + 1
 283   /* The MB field in an M form instruction.  */
 284 #define MB CRB
 285 #define MB_MASK (0x1f << 6)
 286   { 0x1f, 6, NULL, NULL, 0 },
 287
 288   /* The CRD32 field in an XL form instruction.  */
 289 #define CRD32 CRB + 1
 290   { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
 291
 292   /* The CRFS field in an X form instruction.  */
 293 #define CRFS CRD32 + 1
 294   { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
 295
 296 #define CRS CRFS + 1
 297   { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
 298
 299   /* The CT field in an X form instruction.  */
 300 #define CT CRS + 1
 301   /* The MO field in an mbar instruction.  */
 302 #define MO CT
 303   { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 304
 305   /* The D field in a D form instruction.  This is a displacement off
 306      a register, and implies that the next operand is a register in
 307      parentheses.  */
 308 #define D CT + 1
 309   { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 310
 311   /* The D8 field in a D form instruction.  This is a displacement off
 312      a register, and implies that the next operand is a register in
 313      parentheses.  */
 314 #define D8 D + 1
 315   { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 316
 317   /* The DCMX field in an X form instruction.  */
 318 #define DCMX D8 + 1
 319   { 0x7f, 16, NULL, NULL, 0 },
 320
 321   /* The split DCMX field in an X form instruction.  */
 322 #define DCMXS DCMX + 1
 323   { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 },
 324
 325   /* The DQ field in a DQ form instruction.  This is like D, but the
 326      lower four bits are forced to zero. */
 327 #define DQ DCMXS + 1
 328   { 0xfff0, 0, NULL, NULL,
 329     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
 330
 331   /* The DS field in a DS form instruction.  This is like D, but the
 332      lower two bits are forced to zero.  */
 333 #define DS DQ + 1
 334   { 0xfffc, 0, NULL, NULL,
 335     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 336
 337   /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
 338      unsigned imediate */
 339 #define DUIS DS + 1
 340 #define BHRBE DUIS
 341   { 0x3ff, 11, NULL, NULL, 0 },
 342
 343   /* The split D field in a DX form instruction.  */
 344 #define DXD DUIS + 1
 345   { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd,
 346     PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
 347
 348   /* The split ND field in a DX form instruction.
 349      This is the same as the DX field, only negated.  */
 350 #define NDXD DXD + 1
 351   { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn,
 352     PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
 353
 354   /* The E field in a wrteei instruction.  */
 355   /* And the W bit in the pair singles instructions.  */
 356   /* And the ST field in a VX form instruction.  */
 357 #define E NDXD + 1
 358 #define PSW E
 359 #define ST E
 360   { 0x1, 15, NULL, NULL, 0 },
 361
 362   /* The FL1 field in a POWER SC form instruction.  */
 363 #define FL1 E + 1
 364   /* The U field in an X form instruction.  */
 365 #define U FL1
 366   { 0xf, 12, NULL, NULL, 0 },
 367
 368   /* The FL2 field in a POWER SC form instruction.  */
 369 #define FL2 FL1 + 1
 370   { 0x7, 2, NULL, NULL, 0 },
 371
 372   /* The FLM field in an XFL form instruction.  */
 373 #define FLM FL2 + 1
 374   { 0xff, 17, NULL, NULL, 0 },
 375
 376   /* The FRA field in an X or A form instruction.  */
 377 #define FRA FLM + 1
 378 #define FRA_MASK (0x1f << 16)
 379   { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
 380
 381   /* The FRAp field of DFP instructions.  */
 382 #define FRAp FRA + 1
 383   { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
 384
 385   /* The FRB field in an X or A form instruction.  */
 386 #define FRB FRAp + 1
 387 #define FRB_MASK (0x1f << 11)
 388   { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
 389
 390   /* The FRBp field of DFP instructions.  */
 391 #define FRBp FRB + 1
 392   { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
 393
 394   /* The FRC field in an A form instruction.  */
 395 #define FRC FRBp + 1
 396 #define FRC_MASK (0x1f << 6)
 397   { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
 398
 399   /* The FRS field in an X form instruction or the FRT field in a D, X
 400      or A form instruction.  */
 401 #define FRS FRC + 1
 402 #define FRT FRS
 403   { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
 404
 405   /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
 406      instructions.  */
 407 #define FRSp FRS + 1
 408 #define FRTp FRSp
 409   { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
 410
 411   /* The FXM field in an XFX instruction.  */
 412 #define FXM FRSp + 1
 413   { 0xff, 12, insert_fxm, extract_fxm, 0 },
 414
 415   /* Power4 version for mfcr.  */
 416 #define FXM4 FXM + 1
 417   { 0xff, 12, insert_fxm, extract_fxm,
 418     PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
 419   /* If the FXM4 operand is ommitted, use the sentinel value -1.  */
 420   { -1, -1, NULL, NULL, 0},
 421
 422   /* The IMM20 field in an LI instruction.  */
 423 #define IMM20 FXM4 + 2
 424   { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
 425
 426   /* The L field in a D or X form instruction.  */
 427 #define L IMM20 + 1
 428   /* The R field in a HTM X form instruction.  */
 429 #define HTM_R L
 430   { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 431
 432   /* The L field in an X form instruction which must be zero.  */
 433 #define L0 L + 1
 434   { 0x1, 21, insert_l0, extract_l0, PPC_OPERAND_OPTIONAL },
 435
 436   /* The L field in an X form instruction which must be one.  */
 437 #define L1 L0 + 1
 438   { 0x1, 21, insert_l1, extract_l1, 0 },
 439
 440   /* The LEV field in a POWER SVC form instruction.  */
 441 #define SVC_LEV L1 + 1
 442   { 0x7f, 5, NULL, NULL, 0 },
 443
 444   /* The LEV field in an SC form instruction.  */
 445 #define LEV SVC_LEV + 1
 446   { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
 447
 448   /* The LI field in an I form instruction.  The lower two bits are
 449      forced to zero.  */
 450 #define LI LEV + 1
 451   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 452
 453   /* The LI field in an I form instruction when used as an absolute
 454      address.  */
 455 #define LIA LI + 1
 456   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 457
 458   /* The LS or WC field in an X (sync or wait) form instruction.  */
 459 #define LS LIA + 1
 460 #define WC LS
 461   { 0x3, 21, insert_ls, NULL, PPC_OPERAND_OPTIONAL },
 462
 463   /* The ME field in an M form instruction.  */
 464 #define ME LS + 1
 465 #define ME_MASK (0x1f << 1)
 466   { 0x1f, 1, NULL, NULL, 0 },
 467
 468   /* The MB and ME fields in an M form instruction expressed a single
 469      operand which is a bitmask indicating which bits to select.  This
 470      is a two operand form using PPC_OPERAND_NEXT.  See the
 471      description in opcode/ppc.h for what this means.  */
 472 #define MBE ME + 1
 473   { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 474   { -1, 0, insert_mbe, extract_mbe, 0 },
 475
 476   /* The MB or ME field in an MD or MDS form instruction.  The high
 477      bit is wrapped to the low end.  */
 478 #define MB6 MBE + 2
 479 #define ME6 MB6
 480 #define MB6_MASK (0x3f << 5)
 481   { 0x3f, 5, insert_mb6, extract_mb6, 0 },
 482
 483   /* The NB field in an X form instruction.  The value 32 is stored as
 484      0.  */
 485 #define NB MB6 + 1
 486   { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
 487
 488   /* The NBI field in an lswi instruction, which has special value
 489      restrictions.  The value 32 is stored as 0.  */
 490 #define NBI NB + 1
 491   { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
 492
 493   /* The NSI field in a D form instruction.  This is the same as the
 494      SI field, only negated.  */
 495 #define NSI NBI + 1
 496   { 0xffff, 0, insert_nsi, extract_nsi,
 497     PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 498
 499   /* The NSI field in a D form instruction when we accept a wide range
 500      of positive values.  */
 501 #define NSISIGNOPT NSI + 1
 502   { 0xffff, 0, NULL, NULL,
 503     PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 504
 505   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
 506 #define RA NSISIGNOPT + 1
 507 #define RA_MASK (0x1f << 16)
 508   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
 509
 510   /* As above, but 0 in the RA field means zero, not r0.  */
 511 #define RA0 RA + 1
 512   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
 513
 514   /* The RA field in the DQ form lq or an lswx instruction, which have special
 515      value restrictions.  */
 516 #define RAQ RA0 + 1
 517 #define RAX RAQ
 518   { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
 519
 520   /* The RA field in a D or X form instruction which is an updating
 521      load, which means that the RA field may not be zero and may not
 522      equal the RT field.  */
 523 #define RAL RAQ + 1
 524   { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
 525
 526   /* The RA field in an lmw instruction, which has special value
 527      restrictions.  */
 528 #define RAM RAL + 1
 529   { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
 530
 531   /* The RA field in a D or X form instruction which is an updating
 532      store or an updating floating point load, which means that the RA
 533      field may not be zero.  */
 534 #define RAS RAM + 1
 535   { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
 536
 537   /* The RA field of the tlbwe, dccci and iccci instructions,
 538      which are optional.  */
 539 #define RAOPT RAS + 1
 540   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 541
 542   /* The RB field in an X, XO, M, or MDS form instruction.  */
 543 #define RB RAOPT + 1
 544 #define RB_MASK (0x1f << 11)
 545   { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
 546
 547   /* The RB field in an X form instruction when it must be the same as
 548      the RS field in the instruction.  This is used for extended
 549      mnemonics like mr.  */
 550 #define RBS RB + 1
 551   { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 552
 553   /* The RB field in an lswx instruction, which has special value
 554      restrictions.  */
 555 #define RBX RBS + 1
 556   { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR },
 557
 558   /* The RB field of the dccci and iccci instructions, which are optional.  */
 559 #define RBOPT RBX + 1
 560   { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 561
 562   /* The RC register field in an maddld, maddhd or maddhdu instruction.  */
 563 #define RC RBOPT + 1
 564   { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR },
 565
 566   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 567      instruction or the RT field in a D, DS, X, XFX or XO form
 568      instruction.  */
 569 #define RS RC + 1
 570 #define RT RS
 571 #define RT_MASK (0x1f << 21)
 572 #define RD RS
 573   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
 574
 575   /* The RS and RT fields of the DS form stq and DQ form lq instructions,
 576      which have special value restrictions.  */
 577 #define RSQ RS + 1
 578 #define RTQ RSQ
 579   { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
 580
 581   /* The RS field of the tlbwe instruction, which is optional.  */
 582 #define RSO RSQ + 1
 583 #define RTO RSO
 584   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 585
 586   /* The RX field of the SE_RR form instruction.  */
 587 #define RX RSO + 1
 588   { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
 589
 590   /* The ARX field of the SE_RR form instruction.  */
 591 #define ARX RX + 1
 592   { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
 593
 594   /* The RY field of the SE_RR form instruction.  */
 595 #define RY ARX + 1
 596 #define RZ RY
 597   { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
 598
 599   /* The ARY field of the SE_RR form instruction.  */
 600 #define ARY RY + 1
 601   { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
 602
 603   /* The SCLSCI8 field in a D form instruction.  */
 604 #define SCLSCI8 ARY + 1
 605   { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
 606
 607   /* The SCLSCI8N field in a D form instruction.  This is the same as the
 608      SCLSCI8 field, only negated.  */
 609 #define SCLSCI8N SCLSCI8 + 1
 610   { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
 611     PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 612
 613   /* The SD field of the SD4 form instruction.  */
 614 #define SE_SD SCLSCI8N + 1
 615   { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
 616
 617   /* The SD field of the SD4 form instruction, for halfword.  */
 618 #define SE_SDH SE_SD + 1
 619   { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
 620
 621   /* The SD field of the SD4 form instruction, for word.  */
 622 #define SE_SDW SE_SDH + 1
 623   { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
 624
 625   /* The SH field in an X or M form instruction.  */
 626 #define SH SE_SDW + 1
 627 #define SH_MASK (0x1f << 11)
 628   /* The other UIMM field in a EVX form instruction.  */
 629 #define EVUIMM SH
 630   /* The FC field in an atomic X form instruction.  */
 631 #define FC SH
 632   { 0x1f, 11, NULL, NULL, 0 },
 633
 634   /* The SI field in a HTM X form instruction.  */
 635 #define HTM_SI SH + 1
 636   { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },
 637
 638   /* The SH field in an MD form instruction.  This is split.  */
 639 #define SH6 HTM_SI + 1
 640 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 641   { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
 642
 643   /* The SH field of the tlbwe instruction, which is optional.  */
 644 #define SHO SH6 + 1
 645   { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 646
 647   /* The SI field in a D form instruction.  */
 648 #define SI SHO + 1
 649   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
 650
 651   /* The SI field in a D form instruction when we accept a wide range
 652      of positive values.  */
 653 #define SISIGNOPT SI + 1
 654   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 655
 656   /* The SI8 field in a D form instruction.  */
 657 #define SI8 SISIGNOPT + 1
 658   { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
 659
 660   /* The SPR field in an XFX form instruction.  This is flipped--the
 661      lower 5 bits are stored in the upper 5 and vice- versa.  */
 662 #define SPR SI8 + 1
 663 #define PMR SPR
 664 #define TMR SPR
 665 #define SPR_MASK (0x3ff << 11)
 666   { 0x3ff, 11, insert_spr, extract_spr, 0 },
 667
 668   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 669 #define SPRBAT SPR + 1
 670 #define SPRBAT_MASK (0x3 << 17)
 671   { 0x3, 17, NULL, NULL, 0 },
 672
 673   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 674 #define SPRG SPRBAT + 1
 675   { 0x1f, 16, insert_sprg, extract_sprg, 0 },
 676
 677   /* The SR field in an X form instruction.  */
 678 #define SR SPRG + 1
 679   /* The 4-bit UIMM field in a VX form instruction.  */
 680 #define UIMM4 SR
 681   { 0xf, 16, NULL, NULL, 0 },
 682
 683   /* The STRM field in an X AltiVec form instruction.  */
 684 #define STRM SR + 1
 685   /* The T field in a tlbilx form instruction.  */
 686 #define T STRM
 687   { 0x3, 21, NULL, NULL, 0 },
 688
 689   /* The ESYNC field in an X (sync) form instruction.  */
 690 #define ESYNC STRM + 1
 691   { 0xf, 16, insert_esync, NULL, PPC_OPERAND_OPTIONAL },
 692
 693   /* The SV field in a POWER SC form instruction.  */
 694 #define SV ESYNC + 1
 695   { 0x3fff, 2, NULL, NULL, 0 },
 696
 697   /* The TBR field in an XFX form instruction.  This is like the SPR
 698      field, but it is optional.  */
 699 #define TBR SV + 1
 700   { 0x3ff, 11, insert_tbr, extract_tbr,
 701     PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
 702   /* If the TBR operand is ommitted, use the value 268.  */
 703   { -1, 268, NULL, NULL, 0},
 704
 705   /* The TO field in a D or X form instruction.  */
 706 #define TO TBR + 2
 707 #define DUI TO
 708 #define TO_MASK (0x1f << 21)
 709   { 0x1f, 21, NULL, NULL, 0 },
 710
 711   /* The UI field in a D form instruction.  */
 712 #define UI TO + 1
 713   { 0xffff, 0, NULL, NULL, 0 },
 714
 715 #define UISIGNOPT UI + 1
 716   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT },
 717
 718   /* The IMM field in an SE_IM5 instruction.  */
 719 #define UI5 UISIGNOPT + 1
 720   { 0x1f, 4, NULL, NULL, 0 },
 721
 722   /* The OIMM field in an SE_OIM5 instruction.  */
 723 #define OIMM5 UI5 + 1
 724   { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
 725
 726   /* The UI7 field in an SE_LI instruction.  */
 727 #define UI7 OIMM5 + 1
 728   { 0x7f, 4, NULL, NULL, 0 },
 729
 730   /* The VA field in a VA, VX or VXR form instruction.  */
 731 #define VA UI7 + 1
 732   { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
 733
 734   /* The VB field in a VA, VX or VXR form instruction.  */
 735 #define VB VA + 1
 736   { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
 737
 738   /* The VC field in a VA form instruction.  */
 739 #define VC VB + 1
 740   { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
 741
 742   /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
 743 #define VD VC + 1
 744 #define VS VD
 745   { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
 746
 747   /* The SIMM field in a VX form instruction, and TE in Z form.  */
 748 #define SIMM VD + 1
 749 #define TE SIMM
 750   { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
 751
 752   /* The UIMM field in a VX form instruction.  */
 753 #define UIMM SIMM + 1
 754 #define DCTL UIMM
 755   { 0x1f, 16, NULL, NULL, 0 },
 756
 757   /* The 3-bit UIMM field in a VX form instruction.  */
 758 #define UIMM3 UIMM + 1
 759   { 0x7, 16, NULL, NULL, 0 },
 760
 761   /* The 6-bit UIM field in a X form instruction.  */
 762 #define UIM6 UIMM3 + 1
 763   { 0x3f, 16, NULL, NULL, 0 },
 764
 765   /* The SIX field in a VX form instruction.  */
 766 #define SIX UIM6 + 1
 767   { 0xf, 11, NULL, NULL, 0 },
 768
 769   /* The PS field in a VX form instruction.  */
 770 #define PS SIX + 1
 771   { 0x1, 9, NULL, NULL, 0 },
 772
 773   /* The SHB field in a VA form instruction.  */
 774 #define SHB PS + 1
 775   { 0xf, 6, NULL, NULL, 0 },
 776
 777   /* The other UIMM field in a half word EVX form instruction.  */
 778 #define EVUIMM_2 SHB + 1
 779   { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
 780
 781   /* The other UIMM field in a word EVX form instruction.  */
 782 #define EVUIMM_4 EVUIMM_2 + 1
 783   { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
 784
 785   /* The other UIMM field in a double EVX form instruction.  */
 786 #define EVUIMM_8 EVUIMM_4 + 1
 787   { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
 788
 789   /* The WS field.  */
 790 #define WS EVUIMM_8 + 1
 791   { 0x7, 11, NULL, NULL, 0 },
 792
 793   /* PowerPC paired singles extensions.  */
 794   /* W bit in the pair singles instructions for x type instructions.  */
 795 #define PSWM WS + 1
 796   /* The BO16 field in a BD8 form instruction.  */
 797 #define BO16 PSWM
 798   {  0x1, 10, 0, 0, 0 },
 799
 800   /* IDX bits for quantization in the pair singles instructions.  */
 801 #define PSQ PSWM + 1
 802   {  0x7, 12, 0, 0, 0 },
 803
 804   /* IDX bits for quantization in the pair singles x-type instructions.  */
 805 #define PSQM PSQ + 1
 806   {  0x7, 7, 0, 0, 0 },
 807
 808   /* Smaller D field for quantization in the pair singles instructions.  */
 809 #define PSD PSQM + 1
 810   {  0xfff, 0, 0, 0,  PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 811
 812   /* The L field in an mtmsrd or A form instruction or R or W in an X form.  */
 813 #define A_L PSD + 1
 814 #define W A_L
 815 #define X_R A_L
 816   { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
 817
 818 #define RMC A_L + 1
 819   { 0x3, 9, NULL, NULL, 0 },
 820
 821 #define R RMC + 1
 822   { 0x1, 16, NULL, NULL, 0 },
 823
 824 #define RIC R + 1
 825   { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL },
 826
 827 #define PRS RIC + 1
 828   { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
 829
 830 #define SP PRS + 1
 831   { 0x3, 19, NULL, NULL, 0 },
 832
 833 #define S SP + 1
 834   { 0x1, 20, NULL, NULL, 0 },
 835
 836   /* The S field in a XL form instruction.  */
 837 #define SXL S + 1
 838   { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
 839   /* If the SXL operand is ommitted, use the value 1.  */
 840   { -1, 1, NULL, NULL, 0},
 841
 842   /* SH field starting at bit position 16.  */
 843 #define SH16 SXL + 2
 844   /* The DCM and DGM fields in a Z form instruction.  */
 845 #define DCM SH16
 846 #define DGM DCM
 847   { 0x3f, 10, NULL, NULL, 0 },
 848
 849   /* The EH field in larx instruction.  */
 850 #define EH SH16 + 1
 851   { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
 852
 853   /* The L field in an mtfsf or XFL form instruction.  */
 854   /* The A field in a HTM X form instruction.  */
 855 #define XFL_L EH + 1
 856 #define HTM_A XFL_L
 857   { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
 858
 859   /* Xilinx APU related masks and macros */
 860 #define FCRT XFL_L + 1
 861 #define FCRT_MASK (0x1f << 21)
 862   { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
 863
 864   /* Xilinx FSL related masks and macros */
 865 #define FSL FCRT + 1
 866 #define FSL_MASK (0x1f << 11)
 867   { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
 868
 869   /* Xilinx UDI related masks and macros */
 870 #define URT FSL + 1
 871   { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
 872
 873 #define URA URT + 1
 874   { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
 875
 876 #define URB URA + 1
 877   { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
 878
 879 #define URC URB + 1
 880   { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
 881
 882   /* The VLESIMM field in a D form instruction.  */
 883 #define VLESIMM URC + 1
 884   { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
 885     PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 886
 887   /* The VLENSIMM field in a D form instruction.  */
 888 #define VLENSIMM VLESIMM + 1
 889   { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
 890     PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 891
 892   /* The VLEUIMM field in a D form instruction.  */
 893 #define VLEUIMM VLENSIMM + 1
 894   { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
 895
 896   /* The VLEUIMML field in a D form instruction.  */
 897 #define VLEUIMML VLEUIMM + 1
 898   { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
 899
 900   /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
 901 #define XS6 VLEUIMML + 1
 902 #define XT6 XS6
 903   { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
 904
 905   /* The XT and XS fields in an DQ form VSX instruction.  This is split.  */
 906 #define XSQ6 XT6 + 1
 907 #define XTQ6 XSQ6
 908   { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR },
 909
 910   /* The XA field in an XX3 form instruction.  This is split.  */
 911 #define XA6 XTQ6 + 1
 912   { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
 913
 914   /* The XB field in an XX2 or XX3 form instruction.  This is split.  */
 915 #define XB6 XA6 + 1
 916   { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
 917
 918   /* The XB field in an XX3 form instruction when it must be the same as
 919      the XA field in the instruction.  This is used in extended mnemonics
 920      like xvmovdp.  This is split.  */
 921 #define XB6S XB6 + 1
 922   { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
 923
 924   /* The XC field in an XX4 form instruction.  This is split.  */
 925 #define XC6 XB6S + 1
 926   { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
 927
 928   /* The DM or SHW field in an XX3 form instruction.  */
 929 #define DM XC6 + 1
 930 #define SHW DM
 931   { 0x3, 8, NULL, NULL, 0 },
 932
 933   /* The DM field in an extended mnemonic XX3 form instruction.  */
 934 #define DMEX DM + 1
 935   { 0x3, 8, insert_dm, extract_dm, 0 },
 936
 937   /* The UIM field in an XX2 form instruction.  */
 938 #define UIM DMEX + 1
 939   /* The 2-bit UIMM field in a VX form instruction.  */
 940 #define UIMM2 UIM
 941   /* The 2-bit L field in a darn instruction.  */
 942 #define LRAND UIM
 943   { 0x3, 16, NULL, NULL, 0 },
 944
 945 #define ERAT_T UIM + 1
 946   { 0x7, 21, NULL, NULL, 0 },
 947
 948 #define IH ERAT_T + 1
 949   { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 950
 951   /* The 8-bit IMM8 field in a XX1 form instruction.  */
 952 #define IMM8 IH + 1
 953   { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
 954 };
 955
 956 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
 957                                            / sizeof (powerpc_operands[0]));
 958
 959 /* The functions used to insert and extract complicated operands.  */
 960
 961 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs.  */
 962
 963 static unsigned long
 964 insert_arx (unsigned long insn,
 965             long value,
 966             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 967             const char **errmsg ATTRIBUTE_UNUSED)
 968 {
 969   if (value >= 8 && value < 24)
 970     return insn | ((value - 8) & 0xf);
 971   else
 972     {
 973       *errmsg = _("invalid register");
 974       return 0;
 975     }
 976 }
 977
 978 static long
 979 extract_arx (unsigned long insn,
 980              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 981              int *invalid ATTRIBUTE_UNUSED)
 982 {
 983   return (insn & 0xf) + 8;
 984 }
 985
 986 static unsigned long
 987 insert_ary (unsigned long insn,
 988             long value,
 989             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 990             const char **errmsg ATTRIBUTE_UNUSED)
 991 {
 992   if (value >= 8 && value < 24)
 993     return insn | (((value - 8) & 0xf) << 4);
 994   else
 995     {
 996       *errmsg = _("invalid register");
 997       return 0;
 998     }
 999 }
1000
1001 static long
1002 extract_ary (unsigned long insn,
1003              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1004              int *invalid ATTRIBUTE_UNUSED)
1005 {
1006   return ((insn >> 4) & 0xf) + 8;
1007 }
1008
1009 static unsigned long
1010 insert_rx (unsigned long insn,
1011            long value,
1012            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1013            const char **errmsg)
1014 {
1015   if (value >= 0 && value < 8)
1016     return insn | value;
1017   else if (value >= 24 && value <= 31)
1018     return insn | (value - 16);
1019   else
1020     {
1021       *errmsg = _("invalid register");
1022       return 0;
1023     }
1024 }
1025
1026 static long
1027 extract_rx (unsigned long insn,
1028             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1029             int *invalid ATTRIBUTE_UNUSED)
1030 {
1031   int value = insn & 0xf;
1032   if (value >= 0 && value < 8)
1033     return value;
1034   else
1035     return value + 16;
1036 }
1037
1038 static unsigned long
1039 insert_ry (unsigned long insn,
1040            long value,
1041            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1042            const char **errmsg)
1043 {
1044   if (value >= 0 && value < 8)
1045     return insn | (value << 4);
1046   else if (value >= 24 && value <= 31)
1047     return insn | ((value - 16) << 4);
1048   else
1049     {
1050       *errmsg = _("invalid register");
1051       return 0;
1052     }
1053 }
1054
1055 static long
1056 extract_ry (unsigned long insn,
1057             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1058             int *invalid ATTRIBUTE_UNUSED)
1059 {
1060   int value = (insn >> 4) & 0xf;
1061   if (value >= 0 && value < 8)
1062     return value;
1063   else
1064     return value + 16;
1065 }
1066
1067 /* The BA field in an XL form instruction when it must be the same as
1068    the BT field in the same instruction.  This operand is marked FAKE.
1069    The insertion function just copies the BT field into the BA field,
1070    and the extraction function just checks that the fields are the
1071    same.  */
1072
1073 static unsigned long
1074 insert_bat (unsigned long insn,
1075             long value ATTRIBUTE_UNUSED,
1076             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1077             const char **errmsg ATTRIBUTE_UNUSED)
1078 {
1079   return insn | (((insn >> 21) & 0x1f) << 16);
1080 }
1081
1082 static long
1083 extract_bat (unsigned long insn,
1084              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1085              int *invalid)
1086 {
1087   if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
1088     *invalid = 1;
1089   return 0;
1090 }
1091
1092 /* The BB field in an XL form instruction when it must be the same as
1093    the BA field in the same instruction.  This operand is marked FAKE.
1094    The insertion function just copies the BA field into the BB field,
1095    and the extraction function just checks that the fields are the
1096    same.  */
1097
1098 static unsigned long
1099 insert_bba (unsigned long insn,
1100             long value ATTRIBUTE_UNUSED,
1101             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1102             const char **errmsg ATTRIBUTE_UNUSED)
1103 {
1104   return insn | (((insn >> 16) & 0x1f) << 11);
1105 }
1106
1107 static long
1108 extract_bba (unsigned long insn,
1109              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1110              int *invalid)
1111 {
1112   if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1113     *invalid = 1;
1114   return 0;
1115 }
1116
1117 /* The BD field in a B form instruction when the - modifier is used.
1118    This modifier means that the branch is not expected to be taken.
1119    For chips built to versions of the architecture prior to version 2
1120    (ie. not Power4 compatible), we set the y bit of the BO field to 1
1121    if the offset is negative.  When extracting, we require that the y
1122    bit be 1 and that the offset be positive, since if the y bit is 0
1123    we just want to print the normal form of the instruction.
1124    Power4 compatible targets use two bits, "a", and "t", instead of
1125    the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
1126    "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
1127    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
1128    for branch on CTR.  We only handle the taken/not-taken hint here.
1129    Note that we don't relax the conditions tested here when
1130    disassembling with -Many because insns using extract_bdm and
1131    extract_bdp always occur in pairs.  One or the other will always
1132    be valid.  */
1133
1134 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1135
1136 static unsigned long
1137 insert_bdm (unsigned long insn,
1138             long value,
1139             ppc_cpu_t dialect,
1140             const char **errmsg ATTRIBUTE_UNUSED)
1141 {
1142   if ((dialect & ISA_V2) == 0)
1143     {
1144       if ((value & 0x8000) != 0)
1145         insn |= 1 << 21;
1146     }
1147   else
1148     {
1149       if ((insn & (0x14 << 21)) == (0x04 << 21))
1150         insn |= 0x02 << 21;
1151       else if ((insn & (0x14 << 21)) == (0x10 << 21))
1152         insn |= 0x08 << 21;
1153     }
1154   return insn | (value & 0xfffc);
1155 }
1156
1157 static long
1158 extract_bdm (unsigned long insn,
1159              ppc_cpu_t dialect,
1160              int *invalid)
1161 {
1162   if ((dialect & ISA_V2) == 0)
1163     {
1164       if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
1165         *invalid = 1;
1166     }
1167   else
1168     {
1169       if ((insn & (0x17 << 21)) != (0x06 << 21)
1170           && (insn & (0x1d << 21)) != (0x18 << 21))
1171         *invalid = 1;
1172     }
1173
1174   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1175 }
1176
1177 /* The BD field in a B form instruction when the + modifier is used.
1178    This is like BDM, above, except that the branch is expected to be
1179    taken.  */
1180
1181 static unsigned long
1182 insert_bdp (unsigned long insn,
1183             long value,
1184             ppc_cpu_t dialect,
1185             const char **errmsg ATTRIBUTE_UNUSED)
1186 {
1187   if ((dialect & ISA_V2) == 0)
1188     {
1189       if ((value & 0x8000) == 0)
1190         insn |= 1 << 21;
1191     }
1192   else
1193     {
1194       if ((insn & (0x14 << 21)) == (0x04 << 21))
1195         insn |= 0x03 << 21;
1196       else if ((insn & (0x14 << 21)) == (0x10 << 21))
1197         insn |= 0x09 << 21;
1198     }
1199   return insn | (value & 0xfffc);
1200 }
1201
1202 static long
1203 extract_bdp (unsigned long insn,
1204              ppc_cpu_t dialect,
1205              int *invalid)
1206 {
1207   if ((dialect & ISA_V2) == 0)
1208     {
1209       if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1210         *invalid = 1;
1211     }
1212   else
1213     {
1214       if ((insn & (0x17 << 21)) != (0x07 << 21)
1215           && (insn & (0x1d << 21)) != (0x19 << 21))
1216         *invalid = 1;
1217     }
1218
1219   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1220 }
1221
1222 static inline int
1223 valid_bo_pre_v2 (long value)
1224 {
1225   /* Certain encodings have bits that are required to be zero.
1226      These are (z must be zero, y may be anything):
1227          0000y
1228          0001y
1229          001zy
1230          0100y
1231          0101y
1232          011zy
1233          1z00y
1234          1z01y
1235          1z1zz
1236   */
1237   if ((value & 0x14) == 0)
1238     return 1;
1239   else if ((value & 0x14) == 0x4)
1240     return (value & 0x2) == 0;
1241   else if ((value & 0x14) == 0x10)
1242     return (value & 0x8) == 0;
1243   else
1244     return value == 0x14;
1245 }
1246
1247 static inline int
1248 valid_bo_post_v2 (long value)
1249 {
1250   /* Certain encodings have bits that are required to be zero.
1251      These are (z must be zero, a & t may be anything):
1252          0000z
1253          0001z
1254          001at
1255          0100z
1256          0101z
1257          011at
1258          1a00t
1259          1a01t
1260          1z1zz
1261   */
1262   if ((value & 0x14) == 0)
1263     return (value & 0x1) == 0;
1264   else if ((value & 0x14) == 0x14)
1265     return value == 0x14;
1266   else
1267     return 1;
1268 }
1269
1270 /* Check for legal values of a BO field.  */
1271
1272 static int
1273 valid_bo (long value, ppc_cpu_t dialect, int extract)
1274 {
1275   int valid_y = valid_bo_pre_v2 (value);
1276   int valid_at = valid_bo_post_v2 (value);
1277
1278   /* When disassembling with -Many, accept either encoding on the
1279      second pass through opcodes.  */
1280   if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
1281     return valid_y || valid_at;
1282   if ((dialect & ISA_V2) == 0)
1283     return valid_y;
1284   else
1285     return valid_at;
1286 }
1287
1288 /* The BO field in a B form instruction.  Warn about attempts to set
1289    the field to an illegal value.  */
1290
1291 static unsigned long
1292 insert_bo (unsigned long insn,
1293            long value,
1294            ppc_cpu_t dialect,
1295            const char **errmsg)
1296 {
1297   if (!valid_bo (value, dialect, 0))
1298     *errmsg = _("invalid conditional option");
1299   else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1300     *errmsg = _("invalid counter access");
1301   return insn | ((value & 0x1f) << 21);
1302 }
1303
1304 static long
1305 extract_bo (unsigned long insn,
1306             ppc_cpu_t dialect,
1307             int *invalid)
1308 {
1309   long value;
1310
1311   value = (insn >> 21) & 0x1f;
1312   if (!valid_bo (value, dialect, 1))
1313     *invalid = 1;
1314   return value;
1315 }
1316
1317 /* The BO field in a B form instruction when the + or - modifier is
1318    used.  This is like the BO field, but it must be even.  When
1319    extracting it, we force it to be even.  */
1320
1321 static unsigned long
1322 insert_boe (unsigned long insn,
1323             long value,
1324             ppc_cpu_t dialect,
1325             const char **errmsg)
1326 {
1327   if (!valid_bo (value, dialect, 0))
1328     *errmsg = _("invalid conditional option");
1329   else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1330     *errmsg = _("invalid counter access");
1331   else if ((value & 1) != 0)
1332     *errmsg = _("attempt to set y bit when using + or - modifier");
1333
1334   return insn | ((value & 0x1f) << 21);
1335 }
1336
1337 static long
1338 extract_boe (unsigned long insn,
1339              ppc_cpu_t dialect,
1340              int *invalid)
1341 {
1342   long value;
1343
1344   value = (insn >> 21) & 0x1f;
1345   if (!valid_bo (value, dialect, 1))
1346     *invalid = 1;
1347   return value & 0x1e;
1348 }
1349
1350 /* The DCMX field in a X form instruction when the field is split
1351    into separate DC, DM and DX fields.  */
1352
1353 static unsigned long
1354 insert_dcmxs (unsigned long insn,
1355             long value,
1356             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1357             const char **errmsg ATTRIBUTE_UNUSED)
1358 {
1359   return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40);
1360 }
1361
1362 static long
1363 extract_dcmxs (unsigned long insn,
1364              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1365              int *invalid ATTRIBUTE_UNUSED)
1366 {
1367   return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1368 }
1369
1370 /* The D field in a DX form instruction when the field is split
1371    into separate D0, D1 and D2 fields.  */
1372
1373 static unsigned long
1374 insert_dxd (unsigned long insn,
1375             long value,
1376             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1377             const char **errmsg ATTRIBUTE_UNUSED)
1378 {
1379   return insn | (value & 0xffc1) | ((value & 0x3e) << 15);
1380 }
1381
1382 static long
1383 extract_dxd (unsigned long insn,
1384              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1385              int *invalid ATTRIBUTE_UNUSED)
1386 {
1387   unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e);
1388   return (dxd ^ 0x8000) - 0x8000;
1389 }
1390
1391 static unsigned long
1392 insert_dxdn (unsigned long insn,
1393             long value,
1394             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1395             const char **errmsg ATTRIBUTE_UNUSED)
1396 {
1397   return insert_dxd (insn, -value, dialect, errmsg);
1398 }
1399
1400 static long
1401 extract_dxdn (unsigned long insn,
1402              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1403              int *invalid ATTRIBUTE_UNUSED)
1404 {
1405   return -extract_dxd (insn, dialect, invalid);
1406 }
1407
1408 /* FXM mask in mfcr and mtcrf instructions.  */
1409
1410 static unsigned long
1411 insert_fxm (unsigned long insn,
1412             long value,
1413             ppc_cpu_t dialect,
1414             const char **errmsg)
1415 {
1416   /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1417      one bit of the mask field is set.  */
1418   if ((insn & (1 << 20)) != 0)
1419     {
1420       if (value == 0 || (value & -value) != value)
1421         {
1422           *errmsg = _("invalid mask field");
1423           value = 0;
1424         }
1425     }
1426
1427   /* If only one bit of the FXM field is set, we can use the new form
1428      of the instruction, which is faster.  Unlike the Power4 branch hint
1429      encoding, this is not backward compatible.  Do not generate the
1430      new form unless -mpower4 has been given, or -many and the two
1431      operand form of mfcr was used.  */
1432   else if (value > 0
1433            && (value & -value) == value
1434            && ((dialect & PPC_OPCODE_POWER4) != 0
1435                || ((dialect & PPC_OPCODE_ANY) != 0
1436                    && (insn & (0x3ff << 1)) == 19 << 1)))
1437     insn |= 1 << 20;
1438
1439   /* Any other value on mfcr is an error.  */
1440   else if ((insn & (0x3ff << 1)) == 19 << 1)
1441     {
1442       /* A value of -1 means we used the one operand form of
1443          mfcr which is valid.  */
1444       if (value != -1)
1445         *errmsg = _("invalid mfcr mask");
1446       value = 0;
1447     }
1448
1449   return insn | ((value & 0xff) << 12);
1450 }
1451
1452 static long
1453 extract_fxm (unsigned long insn,
1454              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1455              int *invalid)
1456 {
1457   long mask = (insn >> 12) & 0xff;
1458
1459   /* Is this a Power4 insn?  */
1460   if ((insn & (1 << 20)) != 0)
1461     {
1462       /* Exactly one bit of MASK should be set.  */
1463       if (mask == 0 || (mask & -mask) != mask)
1464         *invalid = 1;
1465     }
1466
1467   /* Check that non-power4 form of mfcr has a zero MASK.  */
1468   else if ((insn & (0x3ff << 1)) == 19 << 1)
1469     {
1470       if (mask != 0)
1471         *invalid = 1;
1472       else
1473         mask = -1;
1474     }
1475
1476   return mask;
1477 }
1478
1479 /* The L field in an X form instruction which must have the value zero.  */
1480
1481 static unsigned long
1482 insert_l0 (unsigned long insn,
1483            long value,
1484            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1485            const char **errmsg)
1486 {
1487   if (value != 0)
1488     *errmsg = _("invalid operand constant");
1489   return insn & ~(0x1 << 21);
1490 }
1491
1492 static long
1493 extract_l0 (unsigned long insn,
1494             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1495             int *invalid)
1496 {
1497   long value;
1498
1499   value = (insn >> 21) & 0x1;
1500   if (value != 0)
1501     *invalid = 1;
1502   return value;
1503 }
1504
1505 /* The L field in an X form instruction which must have the value one.  */
1506
1507 static unsigned long
1508 insert_l1 (unsigned long insn,
1509            long value,
1510            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1511            const char **errmsg)
1512 {
1513   if (value != 1)
1514     *errmsg = _("invalid operand constant");
1515   return insn | (0x1 << 21);
1516 }
1517
1518 static long
1519 extract_l1 (unsigned long insn,
1520             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1521             int *invalid)
1522 {
1523   long value;
1524
1525   value = (insn >> 21) & 0x1;
1526   if (value != 1)
1527     *invalid = 1;
1528   return value;
1529 }
1530
1531 static unsigned long
1532 insert_li20 (unsigned long insn,
1533              long value,
1534              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1535              const char **errmsg ATTRIBUTE_UNUSED)
1536 {
1537   return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff);
1538 }
1539
1540 static long
1541 extract_li20 (unsigned long insn,
1542               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1543               int *invalid ATTRIBUTE_UNUSED)
1544 {
1545   long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1546
1547   return ext
1548          | (((insn >> 11) & 0xf) << 16)
1549          | (((insn >> 17) & 0xf) << 12)
1550          | (((insn >> 16) & 0x1) << 11)
1551          | (insn & 0x7ff);
1552 }
1553
1554 /* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
1555    For SYNC, some L values are reserved:
1556      * Value 3 is reserved on newer server cpus.
1557      * Values 2 and 3 are reserved on all other cpus.  */
1558
1559 static unsigned long
1560 insert_ls (unsigned long insn,
1561            long value,
1562            ppc_cpu_t dialect,
1563            const char **errmsg)
1564 {
1565   /* For SYNC, some L values are illegal.  */
1566   if (((insn >> 1) & 0x3ff) == 598)
1567     {
1568       long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
1569       if (value > max_lvalue)
1570         {
1571           *errmsg = _("illegal L operand value");
1572           return insn;
1573         }
1574     }
1575
1576   return insn | ((value & 0x3) << 21);
1577 }
1578
1579 /* The 4-bit E field in a sync instruction that accepts 2 operands.
1580    If ESYNC is non-zero, then the L field must be either 0 or 1 and
1581    the complement of ESYNC-bit2.  */
1582
1583 static unsigned long
1584 insert_esync (unsigned long insn,
1585               long value,
1586               ppc_cpu_t dialect,
1587               const char **errmsg)
1588 {
1589   unsigned long ls = (insn >> 21) & 0x03;
1590
1591   if (value == 0)
1592     {
1593       if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
1594           || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
1595         *errmsg = _("illegal L operand value");
1596       return insn;
1597     }
1598
1599   if ((ls & ~0x1)
1600       || (((value >> 1) & 0x1) ^ ls) == 0)
1601         *errmsg = _("incompatible L operand value");
1602
1603   return insn | ((value & 0xf) << 16);
1604 }
1605
1606 /* The MB and ME fields in an M form instruction expressed as a single
1607    operand which is itself a bitmask.  The extraction function always
1608    marks it as invalid, since we never want to recognize an
1609    instruction which uses a field of this type.  */
1610
1611 static unsigned long
1612 insert_mbe (unsigned long insn,
1613             long value,
1614             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1615             const char **errmsg)
1616 {
1617   unsigned long uval, mask;
1618   int mb, me, mx, count, last;
1619
1620   uval = value;
1621
1622   if (uval == 0)
1623     {
1624       *errmsg = _("illegal bitmask");
1625       return insn;
1626     }
1627
1628   mb = 0;
1629   me = 32;
1630   if ((uval & 1) != 0)
1631     last = 1;
1632   else
1633     last = 0;
1634   count = 0;
1635
1636   /* mb: location of last 0->1 transition */
1637   /* me: location of last 1->0 transition */
1638   /* count: # transitions */
1639
1640   for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1641     {
1642       if ((uval & mask) && !last)
1643         {
1644           ++count;
1645           mb = mx;
1646           last = 1;
1647         }
1648       else if (!(uval & mask) && last)
1649         {
1650           ++count;
1651           me = mx;
1652           last = 0;
1653         }
1654     }
1655   if (me == 0)
1656     me = 32;
1657
1658   if (count != 2 && (count != 0 || ! last))
1659     *errmsg = _("illegal bitmask");
1660
1661   return insn | (mb << 6) | ((me - 1) << 1);
1662 }
1663
1664 static long
1665 extract_mbe (unsigned long insn,
1666              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1667              int *invalid)
1668 {
1669   long ret;
1670   int mb, me;
1671   int i;
1672
1673   *invalid = 1;
1674
1675   mb = (insn >> 6) & 0x1f;
1676   me = (insn >> 1) & 0x1f;
1677   if (mb < me + 1)
1678     {
1679       ret = 0;
1680       for (i = mb; i <= me; i++)
1681         ret |= 1L << (31 - i);
1682     }
1683   else if (mb == me + 1)
1684     ret = ~0;
1685   else /* (mb > me + 1) */
1686     {
1687       ret = ~0;
1688       for (i = me + 1; i < mb; i++)
1689         ret &= ~(1L << (31 - i));
1690     }
1691   return ret;
1692 }
1693
1694 /* The MB or ME field in an MD or MDS form instruction.  The high bit
1695    is wrapped to the low end.  */
1696
1697 static unsigned long
1698 insert_mb6 (unsigned long insn,
1699             long value,
1700             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1701             const char **errmsg ATTRIBUTE_UNUSED)
1702 {
1703   return insn | ((value & 0x1f) << 6) | (value & 0x20);
1704 }
1705
1706 static long
1707 extract_mb6 (unsigned long insn,
1708              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1709              int *invalid ATTRIBUTE_UNUSED)
1710 {
1711   return ((insn >> 6) & 0x1f) | (insn & 0x20);
1712 }
1713
1714 /* The NB field in an X form instruction.  The value 32 is stored as
1715    0.  */
1716
1717 static long
1718 extract_nb (unsigned long insn,
1719             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1720             int *invalid ATTRIBUTE_UNUSED)
1721 {
1722   long ret;
1723
1724   ret = (insn >> 11) & 0x1f;
1725   if (ret == 0)
1726     ret = 32;
1727   return ret;
1728 }
1729
1730 /* The NB field in an lswi instruction, which has special value
1731    restrictions.  The value 32 is stored as 0.  */
1732
1733 static unsigned long
1734 insert_nbi (unsigned long insn,
1735             long value,
1736             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1737             const char **errmsg ATTRIBUTE_UNUSED)
1738 {
1739   long rtvalue = (insn & RT_MASK) >> 21;
1740   long ravalue = (insn & RA_MASK) >> 16;
1741
1742   if (value == 0)
1743     value = 32;
1744   if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1745                                                      : ravalue))
1746     *errmsg = _("address register in load range");
1747   return insn | ((value & 0x1f) << 11);
1748 }
1749
1750 /* The NSI field in a D form instruction.  This is the same as the SI
1751    field, only negated.  The extraction function always marks it as
1752    invalid, since we never want to recognize an instruction which uses
1753    a field of this type.  */
1754
1755 static unsigned long
1756 insert_nsi (unsigned long insn,
1757             long value,
1758             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1759             const char **errmsg ATTRIBUTE_UNUSED)
1760 {
1761   return insn | (-value & 0xffff);
1762 }
1763
1764 static long
1765 extract_nsi (unsigned long insn,
1766              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1767              int *invalid)
1768 {
1769   *invalid = 1;
1770   return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1771 }
1772
1773 /* The RA field in a D or X form instruction which is an updating
1774    load, which means that the RA field may not be zero and may not
1775    equal the RT field.  */
1776
1777 static unsigned long
1778 insert_ral (unsigned long insn,
1779             long value,
1780             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1781             const char **errmsg)
1782 {
1783   if (value == 0
1784       || (unsigned long) value == ((insn >> 21) & 0x1f))
1785     *errmsg = "invalid register operand when updating";
1786   return insn | ((value & 0x1f) << 16);
1787 }
1788
1789 /* The RA field in an lmw instruction, which has special value
1790    restrictions.  */
1791
1792 static unsigned long
1793 insert_ram (unsigned long insn,
1794             long value,
1795             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1796             const char **errmsg)
1797 {
1798   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1799     *errmsg = _("index register in load range");
1800   return insn | ((value & 0x1f) << 16);
1801 }
1802
1803 /* The RA field in the DQ form lq or an lswx instruction, which have special
1804    value restrictions.  */
1805
1806 static unsigned long
1807 insert_raq (unsigned long insn,
1808             long value,
1809             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1810             const char **errmsg)
1811 {
1812   long rtvalue = (insn & RT_MASK) >> 21;
1813
1814   if (value == rtvalue)
1815     *errmsg = _("source and target register operands must be different");
1816   return insn | ((value & 0x1f) << 16);
1817 }
1818
1819 /* The RA field in a D or X form instruction which is an updating
1820    store or an updating floating point load, which means that the RA
1821    field may not be zero.  */
1822
1823 static unsigned long
1824 insert_ras (unsigned long insn,
1825             long value,
1826             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1827             const char **errmsg)
1828 {
1829   if (value == 0)
1830     *errmsg = _("invalid register operand when updating");
1831   return insn | ((value & 0x1f) << 16);
1832 }
1833
1834 /* The RB field in an X form instruction when it must be the same as
1835    the RS field in the instruction.  This is used for extended
1836    mnemonics like mr.  This operand is marked FAKE.  The insertion
1837    function just copies the BT field into the BA field, and the
1838    extraction function just checks that the fields are the same.  */
1839
1840 static unsigned long
1841 insert_rbs (unsigned long insn,
1842             long value ATTRIBUTE_UNUSED,
1843             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1844             const char **errmsg ATTRIBUTE_UNUSED)
1845 {
1846   return insn | (((insn >> 21) & 0x1f) << 11);
1847 }
1848
1849 static long
1850 extract_rbs (unsigned long insn,
1851              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1852              int *invalid)
1853 {
1854   if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1855     *invalid = 1;
1856   return 0;
1857 }
1858
1859 /* The RB field in an lswx instruction, which has special value
1860    restrictions.  */
1861
1862 static unsigned long
1863 insert_rbx (unsigned long insn,
1864             long value,
1865             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1866             const char **errmsg)
1867 {
1868   long rtvalue = (insn & RT_MASK) >> 21;
1869
1870   if (value == rtvalue)
1871     *errmsg = _("source and target register operands must be different");
1872   return insn | ((value & 0x1f) << 11);
1873 }
1874
1875 /* The SCI8 field is made up of SCL and {U,N}I8 fields.  */
1876 static unsigned long
1877 insert_sci8 (unsigned long insn,
1878              long value,
1879              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1880              const char **errmsg)
1881 {
1882   unsigned int fill_scale = 0;
1883   unsigned long ui8 = value;
1884
1885   if ((ui8 & 0xffffff00) == 0)
1886     ;
1887   else if ((ui8 & 0xffffff00) == 0xffffff00)
1888     fill_scale = 0x400;
1889   else if ((ui8 & 0xffff00ff) == 0)
1890     {
1891       fill_scale = 1 << 8;
1892       ui8 >>= 8;
1893     }
1894   else if ((ui8 & 0xffff00ff) == 0xffff00ff)
1895     {
1896       fill_scale = 0x400 | (1 << 8);
1897       ui8 >>= 8;
1898     }
1899   else if ((ui8 & 0xff00ffff) == 0)
1900     {
1901       fill_scale = 2 << 8;
1902       ui8 >>= 16;
1903     }
1904   else if ((ui8 & 0xff00ffff) == 0xff00ffff)
1905     {
1906       fill_scale = 0x400 | (2 << 8);
1907       ui8 >>= 16;
1908     }
1909   else if ((ui8 & 0x00ffffff) == 0)
1910     {
1911       fill_scale = 3 << 8;
1912       ui8 >>= 24;
1913     }
1914   else if ((ui8 & 0x00ffffff) == 0x00ffffff)
1915     {
1916       fill_scale = 0x400 | (3 << 8);
1917       ui8 >>= 24;
1918     }
1919   else
1920     {
1921       *errmsg = _("illegal immediate value");
1922       ui8 = 0;
1923     }
1924
1925   return insn | fill_scale | (ui8 & 0xff);
1926 }
1927
1928 static long
1929 extract_sci8 (unsigned long insn,
1930               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1931               int *invalid ATTRIBUTE_UNUSED)
1932 {
1933   int fill = insn & 0x400;
1934   int scale_factor = (insn & 0x300) >> 5;
1935   long value = (insn & 0xff) << scale_factor;
1936
1937   if (fill != 0)
1938     value |= ~((long) 0xff << scale_factor);
1939   return value;
1940 }
1941
1942 static unsigned long
1943 insert_sci8n (unsigned long insn,
1944               long value,
1945               ppc_cpu_t dialect,
1946               const char **errmsg)
1947 {
1948   return insert_sci8 (insn, -value, dialect, errmsg);
1949 }
1950
1951 static long
1952 extract_sci8n (unsigned long insn,
1953                ppc_cpu_t dialect,
1954                int *invalid)
1955 {
1956   return -extract_sci8 (insn, dialect, invalid);
1957 }
1958
1959 static unsigned long
1960 insert_sd4h (unsigned long insn,
1961              long value,
1962              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1963              const char **errmsg ATTRIBUTE_UNUSED)
1964 {
1965   return insn | ((value & 0x1e) << 7);
1966 }
1967
1968 static long
1969 extract_sd4h (unsigned long insn,
1970               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1971               int *invalid ATTRIBUTE_UNUSED)
1972 {
1973   return ((insn >> 8) & 0xf) << 1;
1974 }
1975
1976 static unsigned long
1977 insert_sd4w (unsigned long insn,
1978              long value,
1979              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1980              const char **errmsg ATTRIBUTE_UNUSED)
1981 {
1982   return insn | ((value & 0x3c) << 6);
1983 }
1984
1985 static long
1986 extract_sd4w (unsigned long insn,
1987               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1988               int *invalid ATTRIBUTE_UNUSED)
1989 {
1990   return ((insn >> 8) & 0xf) << 2;
1991 }
1992
1993 static unsigned long
1994 insert_oimm (unsigned long insn,
1995              long value,
1996              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1997              const char **errmsg ATTRIBUTE_UNUSED)
1998 {
1999   return insn | (((value - 1) & 0x1f) << 4);
2000 }
2001
2002 static long
2003 extract_oimm (unsigned long insn,
2004               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2005               int *invalid ATTRIBUTE_UNUSED)
2006 {
2007   return ((insn >> 4) & 0x1f) + 1;
2008 }
2009
2010 /* The SH field in an MD form instruction.  This is split.  */
2011
2012 static unsigned long
2013 insert_sh6 (unsigned long insn,
2014             long value,
2015             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2016             const char **errmsg ATTRIBUTE_UNUSED)
2017 {
2018   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
2019 }
2020
2021 static long
2022 extract_sh6 (unsigned long insn,
2023              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2024              int *invalid ATTRIBUTE_UNUSED)
2025 {
2026   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
2027 }
2028
2029 /* The SPR field in an XFX form instruction.  This is flipped--the
2030    lower 5 bits are stored in the upper 5 and vice- versa.  */
2031
2032 static unsigned long
2033 insert_spr (unsigned long insn,
2034             long value,
2035             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2036             const char **errmsg ATTRIBUTE_UNUSED)
2037 {
2038   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2039 }
2040
2041 static long
2042 extract_spr (unsigned long insn,
2043              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2044              int *invalid ATTRIBUTE_UNUSED)
2045 {
2046   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
2047 }
2048
2049 /* Some dialects have 8 SPRG registers instead of the standard 4.  */
2050 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405 | PPC_OPCODE_VLE)
2051
2052 static unsigned long
2053 insert_sprg (unsigned long insn,
2054              long value,
2055              ppc_cpu_t dialect,
2056              const char **errmsg)
2057 {
2058   if (value > 7
2059       || (value > 3 && (dialect & ALLOW8_SPRG) == 0))
2060     *errmsg = _("invalid sprg number");
2061
2062   /* If this is mfsprg4..7 then use spr 260..263 which can be read in
2063      user mode.  Anything else must use spr 272..279.  */
2064   if (value <= 3 || (insn & 0x100) != 0)
2065     value |= 0x10;
2066
2067   return insn | ((value & 0x17) << 16);
2068 }
2069
2070 static long
2071 extract_sprg (unsigned long insn,
2072               ppc_cpu_t dialect,
2073               int *invalid)
2074 {
2075   unsigned long val = (insn >> 16) & 0x1f;
2076
2077   /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
2078      If not BOOKE, 405 or VLE, then both use only 272..275.  */
2079   if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
2080       || (val - 0x10 > 7 && (insn & 0x100) != 0)
2081       || val <= 3
2082       || (val & 8) != 0)
2083     *invalid = 1;
2084   return val & 7;
2085 }
2086
2087 /* The TBR field in an XFX instruction.  This is just like SPR, but it
2088    is optional.  */
2089
2090 static unsigned long
2091 insert_tbr (unsigned long insn,
2092             long value,
2093             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2094             const char **errmsg)
2095 {
2096   if (value != 268 && value != 269)
2097     *errmsg = _("invalid tbr number");
2098   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2099 }
2100
2101 static long
2102 extract_tbr (unsigned long insn,
2103              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2104              int *invalid)
2105 {
2106   long ret;
2107
2108   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
2109   if (ret != 268 && ret != 269)
2110     *invalid = 1;
2111   return ret;
2112 }
2113
2114 /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
2115
2116 static unsigned long
2117 insert_xt6 (unsigned long insn,
2118             long value,
2119             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2120             const char **errmsg ATTRIBUTE_UNUSED)
2121 {
2122   return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
2123 }
2124
2125 static long
2126 extract_xt6 (unsigned long insn,
2127              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2128              int *invalid ATTRIBUTE_UNUSED)
2129 {
2130   return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
2131 }
2132
2133 /* The XT and XS fields in an DQ form VSX instruction.  This is split.  */
2134 static unsigned long
2135 insert_xtq6 (unsigned long insn,
2136             long value,
2137             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2138             const char **errmsg ATTRIBUTE_UNUSED)
2139 {
2140   return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2);
2141 }
2142
2143 static long
2144 extract_xtq6 (unsigned long insn,
2145              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2146              int *invalid ATTRIBUTE_UNUSED)
2147 {
2148   return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f);
2149 }
2150
2151 /* The XA field in an XX3 form instruction.  This is split.  */
2152
2153 static unsigned long
2154 insert_xa6 (unsigned long insn,
2155             long value,
2156             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2157             const char **errmsg ATTRIBUTE_UNUSED)
2158 {
2159   return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
2160 }
2161
2162 static long
2163 extract_xa6 (unsigned long insn,
2164              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2165              int *invalid ATTRIBUTE_UNUSED)
2166 {
2167   return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
2168 }
2169
2170 /* The XB field in an XX3 form instruction.  This is split.  */
2171
2172 static unsigned long
2173 insert_xb6 (unsigned long insn,
2174             long value,
2175             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2176             const char **errmsg ATTRIBUTE_UNUSED)
2177 {
2178   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
2179 }
2180
2181 static long
2182 extract_xb6 (unsigned long insn,
2183              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2184              int *invalid ATTRIBUTE_UNUSED)
2185 {
2186   return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
2187 }
2188
2189 /* The XB field in an XX3 form instruction when it must be the same as
2190    the XA field in the instruction.  This is used for extended
2191    mnemonics like xvmovdp.  This operand is marked FAKE.  The insertion
2192    function just copies the XA field into the XB field, and the
2193    extraction function just checks that the fields are the same.  */
2194
2195 static unsigned long
2196 insert_xb6s (unsigned long insn,
2197             long value ATTRIBUTE_UNUSED,
2198             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2199             const char **errmsg ATTRIBUTE_UNUSED)
2200 {
2201   return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
2202 }
2203
2204 static long
2205 extract_xb6s (unsigned long insn,
2206              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2207              int *invalid)
2208 {
2209   if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
2210       || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
2211     *invalid = 1;
2212   return 0;
2213 }
2214
2215 /* The XC field in an XX4 form instruction.  This is split.  */
2216
2217 static unsigned long
2218 insert_xc6 (unsigned long insn,
2219             long value,
2220             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2221             const char **errmsg ATTRIBUTE_UNUSED)
2222 {
2223   return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
2224 }
2225
2226 static long
2227 extract_xc6 (unsigned long insn,
2228              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2229              int *invalid ATTRIBUTE_UNUSED)
2230 {
2231   return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
2232 }
2233
2234 static unsigned long
2235 insert_dm (unsigned long insn,
2236            long value,
2237            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2238            const char **errmsg)
2239 {
2240   if (value != 0 && value != 1)
2241     *errmsg = _("invalid constant");
2242   return insn | (((value) ? 3 : 0) << 8);
2243 }
2244
2245 static long
2246 extract_dm (unsigned long insn,
2247             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2248             int *invalid)
2249 {
2250   long value;
2251
2252   value = (insn >> 8) & 3;
2253   if (value != 0 && value != 3)
2254     *invalid = 1;
2255   return (value) ? 1 : 0;
2256 }
2257
2258 /* The VLESIMM field in an I16A form instruction.  This is split.  */
2259
2260 static unsigned long
2261 insert_vlesi (unsigned long insn,
2262             long value,
2263             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2264             const char **errmsg ATTRIBUTE_UNUSED)
2265 {
2266   return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2267 }
2268
2269 static long
2270 extract_vlesi (unsigned long insn,
2271              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2272              int *invalid ATTRIBUTE_UNUSED)
2273 {
2274   long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2275   value = (value ^ 0x8000) - 0x8000;
2276   return value;
2277 }
2278
2279 static unsigned long
2280 insert_vlensi (unsigned long insn,
2281             long value,
2282             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2283             const char **errmsg ATTRIBUTE_UNUSED)
2284 {
2285   value = -value;
2286   return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2287 }
2288 static long
2289 extract_vlensi (unsigned long insn,
2290              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2291              int *invalid ATTRIBUTE_UNUSED)
2292 {
2293   long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2294   value = (value ^ 0x8000) - 0x8000;
2295   /* Don't use for disassembly.  */
2296   *invalid = 1;
2297   return -value;
2298 }
2299
2300 /* The VLEUIMM field in an I16A form instruction.  This is split.  */
2301
2302 static unsigned long
2303 insert_vleui (unsigned long insn,
2304             long value,
2305             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2306             const char **errmsg ATTRIBUTE_UNUSED)
2307 {
2308   return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2309 }
2310
2311 static long
2312 extract_vleui (unsigned long insn,
2313              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2314              int *invalid ATTRIBUTE_UNUSED)
2315 {
2316   return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2317 }
2318
2319 /* The VLEUIMML field in an I16L form instruction.  This is split.  */
2320
2321 static unsigned long
2322 insert_vleil (unsigned long insn,
2323             long value,
2324             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2325             const char **errmsg ATTRIBUTE_UNUSED)
2326 {
2327   return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
2328 }
2329
2330 static long
2331 extract_vleil (unsigned long insn,
2332              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2333              int *invalid ATTRIBUTE_UNUSED)
2334 {
2335   return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
2336 }
2337
2338 \f
2339 /* Macros used to form opcodes.  */
2340
2341 /* The main opcode.  */
2342 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2343 #define OP_MASK OP (0x3f)
2344
2345 /* The main opcode combined with a trap code in the TO field of a D
2346    form instruction.  Used for extended mnemonics for the trap
2347    instructions.  */
2348 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2349 #define OPTO_MASK (OP_MASK | TO_MASK)
2350
2351 /* The main opcode combined with a comparison size bit in the L field
2352    of a D form or X form instruction.  Used for extended mnemonics for
2353    the comparison instructions.  */
2354 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2355 #define OPL_MASK OPL (0x3f,1)
2356
2357 /* The main opcode combined with an update code in D form instruction.
2358    Used for extended mnemonics for VLE memory instructions.  */
2359 #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2360 #define OPVUP_MASK OPVUP (0x3f,  0xff)
2361
2362 /* An A form instruction.  */
2363 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2364 #define A_MASK A (0x3f, 0x1f, 1)
2365
2366 /* An A_MASK with the FRB field fixed.  */
2367 #define AFRB_MASK (A_MASK | FRB_MASK)
2368
2369 /* An A_MASK with the FRC field fixed.  */
2370 #define AFRC_MASK (A_MASK | FRC_MASK)
2371
2372 /* An A_MASK with the FRA and FRC fields fixed.  */
2373 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2374
2375 /* An AFRAFRC_MASK, but with L bit clear.  */
2376 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2377
2378 /* A B form instruction.  */
2379 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2380 #define B_MASK B (0x3f, 1, 1)
2381
2382 /* A BD8 form instruction.  This is a 16-bit instruction.  */
2383 #define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2384 #define BD8_MASK BD8 (0x3f, 1, 1)
2385
2386 /* Another BD8 form instruction.  This is a 16-bit instruction.  */
2387 #define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2388 #define BD8IO_MASK BD8IO (0x1f)
2389
2390 /* A BD8 form instruction for simplified mnemonics.  */
2391 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2392 /* A mask that excludes BO32 and BI32.  */
2393 #define EBD8IO1_MASK 0xf800
2394 /* A mask that includes BO32 and excludes BI32.  */
2395 #define EBD8IO2_MASK 0xfc00
2396 /* A mask that include BO32 AND BI32.  */
2397 #define EBD8IO3_MASK 0xff00
2398
2399 /* A BD15 form instruction.  */
2400 #define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2401 #define BD15_MASK BD15 (0x3f, 0xf, 1)
2402
2403 /* A BD15 form instruction for extended conditional branch mnemonics.  */
2404 #define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2405 #define EBD15_MASK 0xfff00001
2406
2407 /* A BD15 form instruction for extended conditional branch mnemonics with BI.  */
2408 #define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2409                                     | (((aa) & 0xf) << 22) \
2410                                     | (((bo) & 0x3) << 20) \
2411                                     | (((bi) & 0x3) << 16) \
2412                                     | ((lk) & 1)
2413 #define EBD15BI_MASK  0xfff30001
2414
2415 /* A BD24 form instruction.  */
2416 #define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2417 #define BD24_MASK BD24 (0x3f, 1, 1)
2418
2419 /* A B form instruction setting the BO field.  */
2420 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2421 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2422
2423 /* A BBO_MASK with the y bit of the BO field removed.  This permits
2424    matching a conditional branch regardless of the setting of the y
2425    bit.  Similarly for the 'at' bits used for power4 branch hints.  */
2426 #define Y_MASK   (((unsigned long) 1) << 21)
2427 #define AT1_MASK (((unsigned long) 3) << 21)
2428 #define AT2_MASK (((unsigned long) 9) << 21)
2429 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
2430 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
2431
2432 /* A B form instruction setting the BO field and the condition bits of
2433    the BI field.  */
2434 #define BBOCB(op, bo, cb, aa, lk) \
2435   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2436 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2437
2438 /* A BBOCB_MASK with the y bit of the BO field removed.  */
2439 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
2440 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2441 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
2442
2443 /* A BBOYCB_MASK in which the BI field is fixed.  */
2444 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
2445 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
2446
2447 /* A VLE C form instruction.  */
2448 #define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2449 #define C_LK_MASK C_LK(0x7fff, 1)
2450 #define C(x) ((((unsigned long)(x)) & 0xffff))
2451 #define C_MASK C(0xffff)
2452
2453 /* An Context form instruction.  */
2454 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
2455 #define CTX_MASK CTX(0x3f, 0x7)
2456
2457 /* An User Context form instruction.  */
2458 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
2459 #define UCTX_MASK UCTX(0x3f, 0x1f)
2460
2461 /* The main opcode mask with the RA field clear.  */
2462 #define DRA_MASK (OP_MASK | RA_MASK)
2463
2464 /* A DQ form VSX instruction.  */
2465 #define DQX(op, xop) (OP (op) | ((xop) & 0x7))
2466 #define DQX_MASK DQX (0x3f, 7)
2467
2468 /* A DS form instruction.  */
2469 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2470 #define DS_MASK DSO (0x3f, 3)
2471
2472 /* An DX form instruction.  */
2473 #define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2474 #define DX_MASK DX (0x3f, 0x1f)
2475
2476 /* An EVSEL form instruction.  */
2477 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2478 #define EVSEL_MASK EVSEL(0x3f, 0xff)
2479
2480 /* An IA16 form instruction.  */
2481 #define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2482 #define IA16_MASK IA16(0x3f, 0x1f)
2483
2484 /* An I16A form instruction.  */
2485 #define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2486 #define I16A_MASK I16A(0x3f, 0x1f)
2487
2488 /* An I16L form instruction.  */
2489 #define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2490 #define I16L_MASK I16L(0x3f, 0x1f)
2491
2492 /* An IM7 form instruction.  */
2493 #define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2494 #define IM7_MASK IM7(0x1f)
2495
2496 /* An M form instruction.  */
2497 #define M(op, rc) (OP (op) | ((rc) & 1))
2498 #define M_MASK M (0x3f, 1)
2499
2500 /* An LI20 form instruction.  */
2501 #define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2502 #define LI20_MASK LI20(0x3f, 0x1)
2503
2504 /* An M form instruction with the ME field specified.  */
2505 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2506
2507 /* An M_MASK with the MB and ME fields fixed.  */
2508 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2509
2510 /* An M_MASK with the SH and ME fields fixed.  */
2511 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2512
2513 /* An MD form instruction.  */
2514 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2515 #define MD_MASK MD (0x3f, 0x7, 1)
2516
2517 /* An MD_MASK with the MB field fixed.  */
2518 #define MDMB_MASK (MD_MASK | MB6_MASK)
2519
2520 /* An MD_MASK with the SH field fixed.  */
2521 #define MDSH_MASK (MD_MASK | SH6_MASK)
2522
2523 /* An MDS form instruction.  */
2524 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2525 #define MDS_MASK MDS (0x3f, 0xf, 1)
2526
2527 /* An MDS_MASK with the MB field fixed.  */
2528 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
2529
2530 /* An SC form instruction.  */
2531 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2532 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2533
2534 /* An SCI8 form instruction.  */
2535 #define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2536 #define SCI8_MASK SCI8(0x3f, 0x1f)
2537
2538 /* An SCI8 form instruction.  */
2539 #define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2540 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2541
2542 /* An SD4 form instruction.  This is a 16-bit instruction.  */
2543 #define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
2544 #define SD4_MASK SD4(0xf)
2545
2546 /* An SE_IM5 form instruction.  This is a 16-bit instruction.  */
2547 #define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2548 #define SE_IM5_MASK SE_IM5(0x3f, 1)
2549
2550 /* An SE_R form instruction.  This is a 16-bit instruction.  */
2551 #define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2552 #define SE_R_MASK SE_R(0x3f, 0x3f)
2553
2554 /* An SE_RR form instruction.  This is a 16-bit instruction.  */
2555 #define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2556 #define SE_RR_MASK SE_RR(0x3f, 3)
2557
2558 /* A VX form instruction.  */
2559 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2560
2561 /* The mask for an VX form instruction.  */
2562 #define VX_MASK VX(0x3f, 0x7ff)
2563
2564 /* A VX_MASK with the VA field fixed.  */
2565 #define VXVA_MASK (VX_MASK | (0x1f << 16))
2566
2567 /* A VX_MASK with the VB field fixed.  */
2568 #define VXVB_MASK (VX_MASK | (0x1f << 11))
2569
2570 /* A VX_MASK with the VA and VB fields fixed.  */
2571 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2572
2573 /* A VX_MASK with the VD and VA fields fixed.  */
2574 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2575
2576 /* A VX_MASK with a UIMM4 field.  */
2577 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2578
2579 /* A VX_MASK with a UIMM3 field.  */
2580 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2581
2582 /* A VX_MASK with a UIMM2 field.  */
2583 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2584
2585 /* A VX_MASK with a PS field.  */
2586 #define VXPS_MASK (VX_MASK & ~(0x1 << 9))
2587
2588 /* A VX_MASK with the VA field fixed with a PS field.  */
2589 #define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
2590
2591 /* A VA form instruction.  */
2592 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
2593
2594 /* The mask for an VA form instruction.  */
2595 #define VXA_MASK VXA(0x3f, 0x3f)
2596
2597 /* A VXA_MASK with a SHB field.  */
2598 #define VXASHB_MASK (VXA_MASK | (1 << 10))
2599
2600 /* A VXR form instruction.  */
2601 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2602
2603 /* The mask for a VXR form instruction.  */
2604 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
2605
2606 /* A VX form instruction with a VA tertiary opcode.  */
2607 #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
2608
2609 /* An X form instruction.  */
2610 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2611
2612 /* A X form instruction for Quad-Precision FP Instructions.  */
2613 #define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
2614
2615 /* An EX form instruction.  */
2616 #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2617
2618 /* The mask for an EX form instruction.  */
2619 #define EX_MASK EX (0x3f, 0x7ff)
2620
2621 /* An XX2 form instruction.  */
2622 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2623
2624 /* A XX2 form instruction with the VA bits specified.  */
2625 #define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
2626
2627 /* An XX3 form instruction.  */
2628 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2629
2630 /* An XX3 form instruction with the RC bit specified.  */
2631 #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2632
2633 /* An XX4 form instruction.  */
2634 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
2635
2636 /* A Z form instruction.  */
2637 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2638
2639 /* An X form instruction with the RC bit specified.  */
2640 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2641
2642 /* A X form instruction for Quad-Precision FP Instructions with RC bit.  */
2643 #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
2644
2645 /* A Z form instruction with the RC bit specified.  */
2646 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2647
2648 /* The mask for an X form instruction.  */
2649 #define X_MASK XRC (0x3f, 0x3ff, 1)
2650
2651 /* The mask for an X form instruction with the BF bits specified.  */
2652 #define XBF_MASK (X_MASK | (3 << 21))
2653
2654 /* An X form wait instruction with everything filled in except the WC field.  */
2655 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2656
2657 /* The mask for an XX1 form instruction.  */
2658 #define XX1_MASK X (0x3f, 0x3ff)
2659
2660 /* An XX1_MASK with the RB field fixed.  */
2661 #define XX1RB_MASK (XX1_MASK | RB_MASK)
2662
2663 /* The mask for an XX2 form instruction.  */
2664 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2665
2666 /* The mask for an XX2 form instruction with the UIM bits specified.  */
2667 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2668
2669 /* The mask for an XX2 form instruction with the 4 UIM bits specified.  */
2670 #define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
2671
2672 /* The mask for an XX2 form instruction with the BF bits specified.  */
2673 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2674
2675 /* The mask for an XX2 form instruction with the BF and DCMX bits specified.  */
2676 #define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
2677
2678 /* The mask for an XX2 form instruction with a split DCMX bits specified.  */
2679 #define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
2680
2681 /* The mask for an XX3 form instruction.  */
2682 #define XX3_MASK XX3 (0x3f, 0xff)
2683
2684 /* The mask for an XX3 form instruction with the BF bits specified.  */
2685 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2686
2687 /* The mask for an XX3 form instruction with the DM or SHW bits specified.  */
2688 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
2689 #define XX3SHW_MASK XX3DM_MASK
2690
2691 /* The mask for an XX4 form instruction.  */
2692 #define XX4_MASK XX4 (0x3f, 0x3)
2693
2694 /* An X form wait instruction with everything filled in except the WC field.  */
2695 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2696
2697 /* The mask for a Z form instruction.  */
2698 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
2699 #define Z2_MASK ZRC (0x3f, 0xff, 1)
2700
2701 /* An X_MASK with the RA/VA field fixed.  */
2702 #define XRA_MASK (X_MASK | RA_MASK)
2703 #define XVA_MASK XRA_MASK
2704
2705 /* An XRA_MASK with the A_L/W field clear.  */
2706 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
2707 #define XRLA_MASK XWRA_MASK
2708
2709 /* An X_MASK with the RB field fixed.  */
2710 #define XRB_MASK (X_MASK | RB_MASK)
2711
2712 /* An X_MASK with the RT field fixed.  */
2713 #define XRT_MASK (X_MASK | RT_MASK)
2714
2715 /* An XRT_MASK mask with the L bits clear.  */
2716 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2717
2718 /* An X_MASK with the RA and RB fields fixed.  */
2719 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2720
2721 /* An XBF_MASK with the RA and RB fields fixed.  */
2722 #define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
2723
2724 /* An XRARB_MASK, but with the L bit clear.  */
2725 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2726
2727 /* An XRARB_MASK, but with the L bits in a darn instruction clear.  */
2728 #define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16))
2729
2730 /* An X_MASK with the RT and RA fields fixed.  */
2731 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2732
2733 /* An X_MASK with the RT and RB fields fixed.  */
2734 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
2735
2736 /* An XRTRA_MASK, but with L bit clear.  */
2737 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2738
2739 /* An X_MASK with the RT, RA and RB fields fixed.  */
2740 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
2741
2742 /* An XRTRARB_MASK, but with L bit clear.  */
2743 #define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))
2744
2745 /* An XRTRARB_MASK, but with A bit clear.  */
2746 #define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))
2747
2748 /* An XRTRARB_MASK, but with BF bits clear.  */
2749 #define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))
2750
2751 /* An X form instruction with the L bit specified.  */
2752 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
2753
2754 /* An X form instruction with the L bits specified.  */
2755 #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2756
2757 /* An X form instruction with the L bit and RC bit specified.  */
2758 #define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21))
2759
2760 /* An X form instruction with RT fields specified */
2761 #define XRT(op, xop, rt) (X ((op), (xop)) \
2762         | ((((unsigned long)(rt)) & 0x1f) << 21))
2763
2764 /* An X form instruction with RT and RA fields specified */
2765 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2766         | ((((unsigned long)(rt)) & 0x1f) << 21) \
2767         | ((((unsigned long)(ra)) & 0x1f) << 16))
2768
2769 /* The mask for an X form comparison instruction.  */
2770 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
2771
2772 /* The mask for an X form comparison instruction with the L field
2773    fixed.  */
2774 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
2775
2776 /* An X form trap instruction with the TO field specified.  */
2777 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
2778 #define XTO_MASK (X_MASK | TO_MASK)
2779
2780 /* An X form tlb instruction with the SH field specified.  */
2781 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
2782 #define XTLB_MASK (X_MASK | SH_MASK)
2783
2784 /* An X form sync instruction.  */
2785 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2786
2787 /* An X form sync instruction with everything filled in except the LS field.  */
2788 #define XSYNC_MASK (0xff9fffff)
2789
2790 /* An X form sync instruction with everything filled in except the L and E fields.  */
2791 #define XSYNCLE_MASK (0xff90ffff)
2792
2793 /* An X_MASK, but with the EH bit clear.  */
2794 #define XEH_MASK (X_MASK & ~((unsigned long )1))
2795
2796 /* An X form AltiVec dss instruction.  */
2797 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2798 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2799
2800 /* An XFL form instruction.  */
2801 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2802 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
2803
2804 /* An X form isel instruction.  */
2805 #define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2806 #define XISEL_MASK      XISEL(0x3f, 0x1f)
2807
2808 /* An XL form instruction with the LK field set to 0.  */
2809 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2810
2811 /* An XL form instruction which uses the LK field.  */
2812 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2813
2814 /* The mask for an XL form instruction.  */
2815 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
2816
2817 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear.  */
2818 #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
2819
2820 /* An XL form instruction which explicitly sets the BO field.  */
2821 #define XLO(op, bo, xop, lk) \
2822   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2823 #define XLO_MASK (XL_MASK | BO_MASK)
2824
2825 /* An XL form instruction which explicitly sets the y bit of the BO
2826    field.  */
2827 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
2828 #define XLYLK_MASK (XL_MASK | Y_MASK)
2829
2830 /* An XL form instruction which sets the BO field and the condition
2831    bits of the BI field.  */
2832 #define XLOCB(op, bo, cb, xop, lk) \
2833   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
2834 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2835
2836 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
2837 #define XLBB_MASK (XL_MASK | BB_MASK)
2838 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2839 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2840
2841 /* A mask for branch instructions using the BH field.  */
2842 #define XLBH_MASK (XL_MASK | (0x1c << 11))
2843
2844 /* An XL_MASK with the BO and BB fields fixed.  */
2845 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2846
2847 /* An XL_MASK with the BO, BI and BB fields fixed.  */
2848 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2849
2850 /* An X form mbar instruction with MO field.  */
2851 #define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2852
2853 /* An XO form instruction.  */
2854 #define XO(op, xop, oe, rc) \
2855   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
2856 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2857
2858 /* An XO_MASK with the RB field fixed.  */
2859 #define XORB_MASK (XO_MASK | RB_MASK)
2860
2861 /* An XOPS form instruction for paired singles.  */
2862 #define XOPS(op, xop, rc) \
2863   (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2864 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2865
2866
2867 /* An XS form instruction.  */
2868 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
2869 #define XS_MASK XS (0x3f, 0x1ff, 1)
2870
2871 /* A mask for the FXM version of an XFX form instruction.  */
2872 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
2873
2874 /* An XFX form instruction with the FXM field filled in.  */
2875 #define XFXM(op, xop, fxm, p4) \
2876   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2877    | ((unsigned long)(p4) << 20))
2878
2879 /* An XFX form instruction with the SPR field filled in.  */
2880 #define XSPR(op, xop, spr) \
2881   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
2882 #define XSPR_MASK (X_MASK | SPR_MASK)
2883
2884 /* An XFX form instruction with the SPR field filled in except for the
2885    SPRBAT field.  */
2886 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2887
2888 /* An XFX form instruction with the SPR field filled in except for the
2889    SPRG field.  */
2890 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
2891
2892 /* An X form instruction with everything filled in except the E field.  */
2893 #define XE_MASK (0xffff7fff)
2894
2895 /* An X form user context instruction.  */
2896 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
2897 #define XUC_MASK      XUC(0x3f, 0x1f)
2898
2899 /* An XW form instruction.  */
2900 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2901 /* The mask for a G form instruction. rc not supported at present.  */
2902 #define XW_MASK XW (0x3f, 0x3f, 0)
2903
2904 /* An APU form instruction.  */
2905 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2906
2907 /* The mask for an APU form instruction.  */
2908 #define APU_MASK APU (0x3f, 0x3ff, 1)
2909 #define APU_RT_MASK (APU_MASK | RT_MASK)
2910 #define APU_RA_MASK (APU_MASK | RA_MASK)
2911
2912 /* The BO encodings used in extended conditional branch mnemonics.  */
2913 #define BODNZF  (0x0)
2914 #define BODNZFP (0x1)
2915 #define BODZF   (0x2)
2916 #define BODZFP  (0x3)
2917 #define BODNZT  (0x8)
2918 #define BODNZTP (0x9)
2919 #define BODZT   (0xa)
2920 #define BODZTP  (0xb)
2921
2922 #define BOF     (0x4)
2923 #define BOFP    (0x5)
2924 #define BOFM4   (0x6)
2925 #define BOFP4   (0x7)
2926 #define BOT     (0xc)
2927 #define BOTP    (0xd)
2928 #define BOTM4   (0xe)
2929 #define BOTP4   (0xf)
2930
2931 #define BODNZ   (0x10)
2932 #define BODNZP  (0x11)
2933 #define BODZ    (0x12)
2934 #define BODZP   (0x13)
2935 #define BODNZM4 (0x18)
2936 #define BODNZP4 (0x19)
2937 #define BODZM4  (0x1a)
2938 #define BODZP4  (0x1b)
2939
2940 #define BOU     (0x14)
2941
2942 /* The BO16 encodings used in extended VLE conditional branch mnemonics.  */
2943 #define BO16F   (0x0)
2944 #define BO16T   (0x1)
2945
2946 /* The BO32 encodings used in extended VLE conditional branch mnemonics.  */
2947 #define BO32F   (0x0)
2948 #define BO32T   (0x1)
2949 #define BO32DNZ (0x2)
2950 #define BO32DZ  (0x3)
2951
2952 /* The BI condition bit encodings used in extended conditional branch
2953    mnemonics.  */
2954 #define CBLT    (0)
2955 #define CBGT    (1)
2956 #define CBEQ    (2)
2957 #define CBSO    (3)
2958
2959 /* The TO encodings used in extended trap mnemonics.  */
2960 #define TOLGT   (0x1)
2961 #define TOLLT   (0x2)
2962 #define TOEQ    (0x4)
2963 #define TOLGE   (0x5)
2964 #define TOLNL   (0x5)
2965 #define TOLLE   (0x6)
2966 #define TOLNG   (0x6)
2967 #define TOGT    (0x8)
2968 #define TOGE    (0xc)
2969 #define TONL    (0xc)
2970 #define TOLT    (0x10)
2971 #define TOLE    (0x14)
2972 #define TONG    (0x14)
2973 #define TONE    (0x18)
2974 #define TOU     (0x1f)
2975 \f
2976 /* Smaller names for the flags so each entry in the opcodes table will
2977    fit on a single line.  */
2978 #define PPCNONE 0
2979 #undef  PPC
2980 #define PPC     PPC_OPCODE_PPC
2981 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2982 #define POWER4  PPC_OPCODE_POWER4
2983 #define POWER5  PPC_OPCODE_POWER5
2984 #define POWER6  PPC_OPCODE_POWER6
2985 #define POWER7  PPC_OPCODE_POWER7
2986 #define POWER8  PPC_OPCODE_POWER8
2987 #define POWER9  PPC_OPCODE_POWER9
2988 #define CELL    PPC_OPCODE_CELL
2989 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
2990 #define NON32   (PPC_OPCODE_64 | PPC_OPCODE_POWER4      \
2991                  | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
2992 #define PPC403  PPC_OPCODE_403
2993 #define PPC405  PPC_OPCODE_405
2994 #define PPC440  PPC_OPCODE_440
2995 #define PPC464  PPC440
2996 #define PPC476  PPC_OPCODE_476
2997 #define PPC750  PPC_OPCODE_750
2998 #define PPC7450 PPC_OPCODE_7450
2999 #define PPC860  PPC_OPCODE_860
3000 #define PPCPS   PPC_OPCODE_PPCPS
3001 #define PPCVEC  PPC_OPCODE_ALTIVEC
3002 #define PPCVEC2 PPC_OPCODE_ALTIVEC2
3003 #define PPCVEC3 PPC_OPCODE_ALTIVEC2
3004 #define PPCVSX  PPC_OPCODE_VSX
3005 #define PPCVSX2 PPC_OPCODE_VSX
3006 #define PPCVSX3 PPC_OPCODE_VSX3
3007 #define POWER   PPC_OPCODE_POWER
3008 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
3009 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
3010 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
3011 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
3012 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
3013 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
3014 #define MFDEC1  PPC_OPCODE_POWER
3015 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
3016 #define BOOKE   PPC_OPCODE_BOOKE
3017 #define NO371   PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS | PPC_OPCODE_VLE
3018 #define PPCE300 PPC_OPCODE_E300
3019 #define PPCSPE  PPC_OPCODE_SPE | PPC_OPCODE_VLE
3020 #define PPCISEL PPC_OPCODE_ISEL | PPC_OPCODE_VLE
3021 #define PPCEFS  PPC_OPCODE_EFS | PPC_OPCODE_VLE
3022 #define PPCBRLK PPC_OPCODE_BRLOCK
3023 #define PPCPMR  PPC_OPCODE_PMR
3024 #define PPCTMR  PPC_OPCODE_TMR
3025 #define PPCCHLK PPC_OPCODE_CACHELCK
3026 #define PPCRFMCI        PPC_OPCODE_RFMCI
3027 #define E500MC  PPC_OPCODE_E500MC
3028 #define PPCA2   PPC_OPCODE_A2
3029 #define TITAN   PPC_OPCODE_TITAN
3030 #define MULHW   PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN | PPC_OPCODE_VLE
3031 #define E500    PPC_OPCODE_E500
3032 #define E6500   PPC_OPCODE_E6500
3033 #define PPCVLE  PPC_OPCODE_VLE
3034 #define PPCHTM  PPC_OPCODE_HTM
3035 /* The list of embedded processors that use the embedded operand ordering
3036    for the 3 operand dcbt and dcbtst instructions.  */
3037 #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
3038                  | PPC_OPCODE_A2 | PPC_OPCODE_VLE)
3039
3040
3041 \f
3042 /* The opcode table.
3043
3044    The format of the opcode table is:
3045
3046    NAME         OPCODE          MASK         FLAGS      ANTI            {OPERANDS}
3047
3048    NAME is the name of the instruction.
3049    OPCODE is the instruction opcode.
3050    MASK is the opcode mask; this is used to tell the disassembler
3051      which bits in the actual opcode must match OPCODE.
3052    FLAGS are flags indicating which processors support the instruction.
3053    ANTI indicates which processors don't support the instruction.
3054    OPERANDS is the list of operands.
3055
3056    The disassembler reads the table in order and prints the first
3057    instruction which matches, so this table is sorted to put more
3058    specific instructions before more general instructions.
3059
3060    This table must be sorted by major opcode.  Please try to keep it
3061    vaguely sorted within major opcode too, except of course where
3062    constrained otherwise by disassembler operation.  */
3063
3064 const struct powerpc_opcode powerpc_opcodes[] = {
3065 {"attn",        X(0,256),       X_MASK,   POWER4|PPCA2, PPC476,         {0}},
3066 {"tdlgti",      OPTO(2,TOLGT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
3067 {"tdllti",      OPTO(2,TOLLT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
3068 {"tdeqi",       OPTO(2,TOEQ),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
3069 {"tdlgei",      OPTO(2,TOLGE),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
3070 {"tdlnli",      OPTO(2,TOLNL),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
3071 {"tdllei",      OPTO(2,TOLLE),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
3072 {"tdlngi",      OPTO(2,TOLNG),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
3073 {"tdgti",       OPTO(2,TOGT),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
3074 {"tdgei",       OPTO(2,TOGE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
3075 {"tdnli",       OPTO(2,TONL),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
3076 {"tdlti",       OPTO(2,TOLT),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
3077 {"tdlei",       OPTO(2,TOLE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
3078 {"tdngi",       OPTO(2,TONG),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
3079 {"tdnei",       OPTO(2,TONE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
3080 {"tdui",        OPTO(2,TOU),    OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
3081 {"tdi",         OP(2),          OP_MASK,     PPC64,     PPCNONE,        {TO, RA, SI}},
3082
3083 {"twlgti",      OPTO(3,TOLGT),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
3084 {"tlgti",       OPTO(3,TOLGT),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
3085 {"twllti",      OPTO(3,TOLLT),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
3086 {"tllti",       OPTO(3,TOLLT),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
3087 {"tweqi",       OPTO(3,TOEQ),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
3088 {"teqi",        OPTO(3,TOEQ),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
3089 {"twlgei",      OPTO(3,TOLGE),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
3090 {"tlgei",       OPTO(3,TOLGE),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
3091 {"twlnli",      OPTO(3,TOLNL),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
3092 {"tlnli",       OPTO(3,TOLNL),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
3093 {"twllei",      OPTO(3,TOLLE),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
3094 {"tllei",       OPTO(3,TOLLE),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
3095 {"twlngi",      OPTO(3,TOLNG),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
3096 {"tlngi",       OPTO(3,TOLNG),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
3097 {"twgti",       OPTO(3,TOGT),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
3098 {"tgti",        OPTO(3,TOGT),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
3099 {"twgei",       OPTO(3,TOGE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
3100 {"tgei",        OPTO(3,TOGE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
3101 {"twnli",       OPTO(3,TONL),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
3102 {"tnli",        OPTO(3,TONL),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
3103 {"twlti",       OPTO(3,TOLT),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
3104 {"tlti",        OPTO(3,TOLT),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
3105 {"twlei",       OPTO(3,TOLE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
3106 {"tlei",        OPTO(3,TOLE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
3107 {"twngi",       OPTO(3,TONG),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
3108 {"tngi",        OPTO(3,TONG),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
3109 {"twnei",       OPTO(3,TONE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
3110 {"tnei",        OPTO(3,TONE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
3111 {"twui",        OPTO(3,TOU),    OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
3112 {"tui",         OPTO(3,TOU),    OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
3113 {"twi",         OP(3),          OP_MASK,     PPCCOM,    PPCNONE,        {TO, RA, SI}},
3114 {"ti",          OP(3),          OP_MASK,     PWRCOM,    PPCNONE,        {TO, RA, SI}},
3115
3116 {"ps_cmpu0",    X  (4,   0),    XBF_MASK,    PPCPS,     PPCNONE,        {BF, FRA, FRB}},
3117 {"vaddubm",     VX (4,   0),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3118 {"vmul10cuq",   VX (4,   1),    VXVB_MASK,   PPCVEC3,       PPCNONE,    {VD, VA}},
3119 {"vmaxub",      VX (4,   2),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3120 {"vrlb",        VX (4,   4),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3121 {"vcmpequb",    VXR(4,   6,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3122 {"vcmpneb",     VXR(4,   7,0),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
3123 {"vmuloub",     VX (4,   8),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3124 {"vaddfp",      VX (4,  10),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3125 {"psq_lx",      XW (4,   6,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRT,RA,RB,PSWM,PSQM}},
3126 {"vmrghb",      VX (4,  12),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3127 {"psq_stx",     XW (4,   7,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRS,RA,RB,PSWM,PSQM}},
3128 {"vpkuhum",     VX (4,  14),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3129 {"mulhhwu",     XRC(4,   8,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3130 {"mulhhwu.",    XRC(4,   8,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3131 {"ps_sum0",     A  (4,  10,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
3132 {"ps_sum0.",    A  (4,  10,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
3133 {"ps_sum1",     A  (4,  11,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
3134 {"ps_sum1.",    A  (4,  11,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
3135 {"ps_muls0",    A  (4,  12,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
3136 {"machhwu",     XO (4,  12,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3137 {"ps_muls0.",   A  (4,  12,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
3138 {"machhwu.",    XO (4,  12,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3139 {"ps_muls1",    A  (4,  13,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
3140 {"ps_muls1.",   A  (4,  13,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
3141 {"ps_madds0",   A  (4,  14,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
3142 {"ps_madds0.",  A  (4,  14,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
3143 {"ps_madds1",   A  (4,  15,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
3144 {"ps_madds1.",  A  (4,  15,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
3145 {"vmhaddshs",   VXA(4,  32),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
3146 {"vmhraddshs",  VXA(4,  33),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
3147 {"vmladduhm",   VXA(4,  34),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
3148 {"ps_div",      A  (4,  18,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3149 {"vmsumubm",    VXA(4,  36),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
3150 {"ps_div.",     A  (4,  18,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3151 {"vmsummbm",    VXA(4,  37),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
3152 {"vmsumuhm",    VXA(4,  38),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
3153 {"vmsumuhs",    VXA(4,  39),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
3154 {"ps_sub",      A  (4,  20,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3155 {"vmsumshm",    VXA(4,  40),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
3156 {"ps_sub.",     A  (4,  20,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3157 {"vmsumshs",    VXA(4,  41),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
3158 {"ps_add",      A  (4,  21,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3159 {"vsel",        VXA(4,  42),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
3160 {"ps_add.",     A  (4,  21,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3161 {"vperm",       VXA(4,  43),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
3162 {"vsldoi",      VXA(4,  44),    VXASHB_MASK, PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, SHB}},
3163 {"vpermxor",    VXA(4,  45),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
3164 {"ps_sel",      A  (4,  23,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
3165 {"vmaddfp",     VXA(4,  46),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VC, VB}},
3166 {"ps_sel.",     A  (4,  23,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
3167 {"vnmsubfp",    VXA(4,  47),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VC, VB}},
3168 {"ps_res",      A  (4,  24,0), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
3169 {"maddhd",      VXA(4,  48),    VXA_MASK,    POWER9,    PPCNONE,        {RT, RA, RB, RC}},
3170 {"ps_res.",     A  (4,  24,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
3171 {"maddhdu",     VXA(4,  49),    VXA_MASK,    POWER9,    PPCNONE,        {RT, RA, RB, RC}},
3172 {"ps_mul",      A  (4,  25,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
3173 {"ps_mul.",     A  (4,  25,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
3174 {"maddld",      VXA(4,  51),    VXA_MASK,    POWER9,    PPCNONE,        {RT, RA, RB, RC}},
3175 {"ps_rsqrte",   A  (4,  26,0), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
3176 {"ps_rsqrte.",  A  (4,  26,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
3177 {"ps_msub",     A  (4,  28,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
3178 {"ps_msub.",    A  (4,  28,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
3179 {"ps_madd",     A  (4,  29,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
3180 {"ps_madd.",    A  (4,  29,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
3181 {"vpermr",      VXA(4,  59),    VXA_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB, VC}},
3182 {"ps_nmsub",    A  (4,  30,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
3183 {"vaddeuqm",    VXA(4,  60),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
3184 {"ps_nmsub.",   A  (4,  30,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
3185 {"vaddecuq",    VXA(4,  61),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
3186 {"ps_nmadd",    A  (4,  31,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
3187 {"vsubeuqm",    VXA(4,  62),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
3188 {"ps_nmadd.",   A  (4,  31,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
3189 {"vsubecuq",    VXA(4,  63),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
3190 {"ps_cmpo0",    X  (4,  32),    XBF_MASK,    PPCPS,     PPCNONE,        {BF, FRA, FRB}},
3191 {"vadduhm",     VX (4,  64),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3192 {"vmul10ecuq",  VX (4,  65),    VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
3193 {"vmaxuh",      VX (4,  66),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3194 {"vrlh",        VX (4,  68),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3195 {"vcmpequh",    VXR(4,  70,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3196 {"vcmpneh",     VXR(4,  71,0),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
3197 {"vmulouh",     VX (4,  72),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3198 {"vsubfp",      VX (4,  74),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3199 {"psq_lux",     XW (4,  38,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRT,RA,RB,PSWM,PSQM}},
3200 {"vmrghh",      VX (4,  76),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3201 {"psq_stux",    XW (4,  39,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRS,RA,RB,PSWM,PSQM}},
3202 {"vpkuwum",     VX (4,  78),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3203 {"ps_neg",      XRC(4,  40,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
3204 {"mulhhw",      XRC(4,  40,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3205 {"ps_neg.",     XRC(4,  40,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
3206 {"mulhhw.",     XRC(4,  40,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3207 {"machhw",      XO (4,  44,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3208 {"machhw.",     XO (4,  44,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3209 {"nmachhw",     XO (4,  46,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3210 {"nmachhw.",    XO (4,  46,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3211 {"ps_cmpu1",    X  (4,  64),    XBF_MASK,    PPCPS,     PPCNONE,        {BF, FRA, FRB}},
3212 {"vadduwm",     VX (4,  128),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3213 {"vmaxuw",      VX (4,  130),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3214 {"vrlw",        VX (4,  132),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3215 {"vrlwmi",      VX (4,  133),   VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
3216 {"vcmpequw",    VXR(4,  134,0), VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3217 {"vcmpnew",     VXR(4,  135,0), VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
3218 {"vmulouw",     VX (4,  136),   VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3219 {"vmuluwm",     VX (4,  137),   VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3220 {"vmrghw",      VX (4,  140),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3221 {"vpkuhus",     VX (4,  142),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3222 {"ps_mr",       XRC(4,  72,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
3223 {"ps_mr.",      XRC(4,  72,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
3224 {"machhwsu",    XO (4,  76,0,0),XO_MASK,     MULHW|PPCVLE,  PPCNONE,    {RT, RA, RB}},
3225 {"machhwsu.",   XO (4,  76,0,1),XO_MASK,     MULHW|PPCVLE,  PPCNONE,    {RT, RA, RB}},
3226 {"ps_cmpo1",    X  (4,  96),    XBF_MASK,    PPCPS,     PPCNONE,        {BF, FRA, FRB}},
3227 {"vaddudm",     VX (4, 192),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3228 {"vmaxud",      VX (4, 194),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3229 {"vrld",        VX (4, 196),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3230 {"vrldmi",      VX (4, 197),    VX_MASK,     PPCVEC3,   PPCNONE,        {VD, VA, VB}},
3231 {"vcmpeqfp",    VXR(4, 198,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3232 {"vcmpequd",    VXR(4, 199,0),  VXR_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3233 {"vpkuwus",     VX (4, 206),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3234 {"machhws",     XO (4, 108,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3235 {"machhws.",    XO (4, 108,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3236 {"nmachhws",    XO (4, 110,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3237 {"nmachhws.",   XO (4, 110,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3238 {"vadduqm",     VX (4, 256),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3239 {"vmaxsb",      VX (4, 258),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3240 {"vslb",        VX (4, 260),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3241 {"vcmpnezb",    VXR(4, 263,0),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
3242 {"vmulosb",     VX (4, 264),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3243 {"vrefp",       VX (4, 266),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3244 {"vmrglb",      VX (4, 268),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3245 {"vpkshus",     VX (4, 270),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3246 {"ps_nabs",     XRC(4, 136,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
3247 {"mulchwu",     XRC(4, 136,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3248 {"ps_nabs.",    XRC(4, 136,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
3249 {"mulchwu.",    XRC(4, 136,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3250 {"macchwu",     XO (4, 140,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3251 {"macchwu.",    XO (4, 140,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3252 {"vaddcuq",     VX (4, 320),    VX_MASK,     PPCVEC2,      PPCNONE,     {VD, VA, VB}},
3253 {"vmaxsh",      VX (4, 322),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3254 {"vslh",        VX (4, 324),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3255 {"vcmpnezh",    VXR(4, 327,0),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
3256 {"vmulosh",     VX (4, 328),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3257 {"vrsqrtefp",   VX (4, 330),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3258 {"vmrglh",      VX (4, 332),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3259 {"vpkswus",     VX (4, 334),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3260 {"mulchw",      XRC(4, 168,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3261 {"mulchw.",     XRC(4, 168,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3262 {"macchw",      XO (4, 172,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3263 {"macchw.",     XO (4, 172,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3264 {"nmacchw",     XO (4, 174,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3265 {"nmacchw.",    XO (4, 174,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3266 {"vaddcuw",     VX (4, 384),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3267 {"vmaxsw",      VX (4, 386),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3268 {"vslw",        VX (4, 388),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3269 {"vrlwnm",      VX (4, 389),    VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
3270 {"vcmpnezw",    VXR(4, 391,0),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
3271 {"vmulosw",     VX (4, 392),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3272 {"vexptefp",    VX (4, 394),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3273 {"vmrglw",      VX (4, 396),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3274 {"vpkshss",     VX (4, 398),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3275 {"macchwsu",    XO (4, 204,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3276 {"macchwsu.",   XO (4, 204,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3277 {"vmaxsd",      VX (4, 450),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3278 {"vsl",         VX (4, 452),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3279 {"vrldnm",      VX (4, 453),    VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
3280 {"vcmpgefp",    VXR(4, 454,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3281 {"vlogefp",     VX (4, 458),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3282 {"vpkswss",     VX (4, 462),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3283 {"macchws",     XO (4, 236,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3284 {"macchws.",    XO (4, 236,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3285 {"nmacchws",    XO (4, 238,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3286 {"nmacchws.",   XO (4, 238,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3287 {"evaddw",      VX (4, 512),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3288 {"vaddubs",     VX (4, 512),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3289 {"vmul10uq",    VX (4, 513),    VXVB_MASK,   PPCVEC3,       PPCNONE,    {VD, VA}},
3290 {"evaddiw",     VX (4, 514),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB, UIMM}},
3291 {"vminub",      VX (4, 514),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3292 {"evsubfw",     VX (4, 516),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3293 {"evsubw",      VX (4, 516),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, RA}},
3294 {"vsrb",        VX (4, 516),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3295 {"evsubifw",    VX (4, 518),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, UIMM, RB}},
3296 {"evsubiw",     VX (4, 518),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, UIMM}},
3297 {"vcmpgtub",    VXR(4, 518,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3298 {"evabs",       VX (4, 520),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3299 {"vmuleub",     VX (4, 520),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3300 {"evneg",       VX (4, 521),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3301 {"evextsb",     VX (4, 522),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3302 {"vrfin",       VX (4, 522),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3303 {"evextsh",     VX (4, 523),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3304 {"evrndw",      VX (4, 524),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3305 {"vspltb",      VX (4, 524),    VXUIMM4_MASK,PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM4}},
3306 {"vextractub",  VX (4, 525),    VXUIMM4_MASK,PPCVEC3,       PPCNONE,    {VD, VB, UIMM4}},
3307 {"evcntlzw",    VX (4, 525),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3308 {"evcntlsw",    VX (4, 526),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3309 {"vupkhsb",     VX (4, 526),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3310 {"brinc",       VX (4, 527),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3311 {"ps_abs",      XRC(4, 264,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
3312 {"ps_abs.",     XRC(4, 264,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
3313 {"evand",       VX (4, 529),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3314 {"evandc",      VX (4, 530),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3315 {"evxor",       VX (4, 534),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3316 {"evmr",        VX (4, 535),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, BBA}},
3317 {"evor",        VX (4, 535),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3318 {"evnor",       VX (4, 536),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3319 {"evnot",       VX (4, 536),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, BBA}},
3320 {"get",         APU(4, 268,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
3321 {"eveqv",       VX (4, 537),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3322 {"evorc",       VX (4, 539),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3323 {"evnand",      VX (4, 542),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3324 {"evsrwu",      VX (4, 544),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3325 {"evsrws",      VX (4, 545),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3326 {"evsrwiu",     VX (4, 546),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
3327 {"evsrwis",     VX (4, 547),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
3328 {"evslw",       VX (4, 548),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3329 {"evslwi",      VX (4, 550),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
3330 {"evrlw",       VX (4, 552),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3331 {"evsplati",    VX (4, 553),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, SIMM}},
3332 {"evrlwi",      VX (4, 554),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
3333 {"evsplatfi",   VX (4, 555),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, SIMM}},
3334 {"evmergehi",   VX (4, 556),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3335 {"evmergelo",   VX (4, 557),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3336 {"evmergehilo", VX (4, 558),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3337 {"evmergelohi", VX (4, 559),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3338 {"evcmpgtu",    VX (4, 560),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3339 {"evcmpgts",    VX (4, 561),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3340 {"evcmpltu",    VX (4, 562),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3341 {"evcmplts",    VX (4, 563),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3342 {"evcmpeq",     VX (4, 564),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3343 {"cget",        APU(4, 284,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
3344 {"vadduhs",     VX (4, 576),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3345 {"vmul10euq",   VX (4, 577),    VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
3346 {"vminuh",      VX (4, 578),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3347 {"vsrh",        VX (4, 580),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3348 {"vcmpgtuh",    VXR(4, 582,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3349 {"vmuleuh",     VX (4, 584),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3350 {"vrfiz",       VX (4, 586),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3351 {"vsplth",      VX (4, 588),    VXUIMM3_MASK,PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM3}},
3352 {"vextractuh",  VX (4, 589),    VXUIMM4_MASK,PPCVEC3,       PPCNONE,    {VD, VB, UIMM4}},
3353 {"vupkhsh",     VX (4, 590),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3354 {"nget",        APU(4, 300,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
3355 {"evsel",       EVSEL(4,79),    EVSEL_MASK,  PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB, CRFS}},
3356 {"ncget",       APU(4, 316,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
3357 {"evfsadd",     VX (4, 640),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3358 {"vadduws",     VX (4, 640),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3359 {"evfssub",     VX (4, 641),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3360 {"vminuw",      VX (4, 642),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3361 {"evfsabs",     VX (4, 644),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3362 {"vsrw",        VX (4, 644),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3363 {"evfsnabs",    VX (4, 645),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3364 {"evfsneg",     VX (4, 646),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3365 {"vcmpgtuw",    VXR(4, 646,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3366 {"vmuleuw",     VX (4, 648),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3367 {"evfsmul",     VX (4, 648),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3368 {"evfsdiv",     VX (4, 649),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3369 {"vrfip",       VX (4, 650),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3370 {"evfscmpgt",   VX (4, 652),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3371 {"vspltw",      VX (4, 652),    VXUIMM2_MASK,PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM2}},
3372 {"vextractuw",  VX (4, 653),    VXUIMM4_MASK,PPCVEC3,       PPCNONE,    {VD, VB, UIMM4}},
3373 {"evfscmplt",   VX (4, 653),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3374 {"evfscmpeq",   VX (4, 654),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3375 {"vupklsb",     VX (4, 654),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3376 {"evfscfui",    VX (4, 656),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3377 {"evfscfsi",    VX (4, 657),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3378 {"evfscfuf",    VX (4, 658),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3379 {"evfscfsf",    VX (4, 659),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3380 {"evfsctui",    VX (4, 660),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3381 {"evfsctsi",    VX (4, 661),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3382 {"evfsctuf",    VX (4, 662),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3383 {"evfsctsf",    VX (4, 663),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3384 {"evfsctuiz",   VX (4, 664),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3385 {"put",         APU(4, 332,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
3386 {"evfsctsiz",   VX (4, 666),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3387 {"evfststgt",   VX (4, 668),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3388 {"evfststlt",   VX (4, 669),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3389 {"evfststeq",   VX (4, 670),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3390 {"cput",        APU(4, 348,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
3391 {"efsadd",      VX (4, 704),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3392 {"efssub",      VX (4, 705),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3393 {"vminud",      VX (4, 706),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3394 {"efsabs",      VX (4, 708),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3395 {"vsr",         VX (4, 708),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3396 {"efsnabs",     VX (4, 709),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3397 {"efsneg",      VX (4, 710),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3398 {"vcmpgtfp",    VXR(4, 710,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3399 {"vcmpgtud",    VXR(4, 711,0),  VXR_MASK,    PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3400 {"efsmul",      VX (4, 712),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3401 {"efsdiv",      VX (4, 713),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3402 {"vrfim",       VX (4, 714),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3403 {"efscmpgt",    VX (4, 716),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3404 {"vextractd",   VX (4, 717),    VXUIMM4_MASK,PPCVEC3,       PPCNONE,    {VD, VB, UIMM4}},
3405 {"efscmplt",    VX (4, 717),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3406 {"efscmpeq",    VX (4, 718),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3407 {"vupklsh",     VX (4, 718),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3408 {"efscfd",      VX (4, 719),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3409 {"efscfui",     VX (4, 720),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3410 {"efscfsi",     VX (4, 721),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3411 {"efscfuf",     VX (4, 722),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3412 {"efscfsf",     VX (4, 723),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3413 {"efsctui",     VX (4, 724),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3414 {"efsctsi",     VX (4, 725),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3415 {"efsctuf",     VX (4, 726),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3416 {"efsctsf",     VX (4, 727),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3417 {"efsctuiz",    VX (4, 728),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3418 {"nput",        APU(4, 364,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
3419 {"efsctsiz",    VX (4, 730),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3420 {"efststgt",    VX (4, 732),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3421 {"efststlt",    VX (4, 733),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3422 {"efststeq",    VX (4, 734),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3423 {"efdadd",      VX (4, 736),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3424 {"efdsub",      VX (4, 737),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3425 {"efdcfuid",    VX (4, 738),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3426 {"efdcfsid",    VX (4, 739),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3427 {"efdabs",      VX (4, 740),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3428 {"efdnabs",     VX (4, 741),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3429 {"efdneg",      VX (4, 742),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3430 {"efdmul",      VX (4, 744),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3431 {"efddiv",      VX (4, 745),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3432 {"efdctuidz",   VX (4, 746),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3433 {"efdctsidz",   VX (4, 747),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3434 {"efdcmpgt",    VX (4, 748),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3435 {"efdcmplt",    VX (4, 749),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3436 {"efdcmpeq",    VX (4, 750),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3437 {"efdcfs",      VX (4, 751),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3438 {"efdcfui",     VX (4, 752),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3439 {"efdcfsi",     VX (4, 753),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3440 {"efdcfuf",     VX (4, 754),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3441 {"efdcfsf",     VX (4, 755),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3442 {"efdctui",     VX (4, 756),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3443 {"efdctsi",     VX (4, 757),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3444 {"efdctuf",     VX (4, 758),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3445 {"efdctsf",     VX (4, 759),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3446 {"efdctuiz",    VX (4, 760),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3447 {"ncput",       APU(4, 380,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
3448 {"efdctsiz",    VX (4, 762),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3449 {"efdtstgt",    VX (4, 764),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3450 {"efdtstlt",    VX (4, 765),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3451 {"efdtsteq",    VX (4, 766),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3452 {"evlddx",      VX (4, 768),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3453 {"vaddsbs",     VX (4, 768),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3454 {"evldd",       VX (4, 769),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3455 {"evldwx",      VX (4, 770),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3456 {"vminsb",      VX (4, 770),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3457 {"evldw",       VX (4, 771),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3458 {"evldhx",      VX (4, 772),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3459 {"vsrab",       VX (4, 772),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3460 {"evldh",       VX (4, 773),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3461 {"vcmpgtsb",    VXR(4, 774,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3462 {"evlhhesplatx",VX (4, 776),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3463 {"vmulesb",     VX (4, 776),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3464 {"evlhhesplat", VX (4, 777),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_2, RA}},
3465 {"vcfux",       VX (4, 778),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3466 {"vcuxwfp",     VX (4, 778),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3467 {"evlhhousplatx",VX(4, 780),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3468 {"vspltisb",    VX (4, 780),    VXVB_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
3469 {"vinsertb",    VX (4, 781),    VXUIMM4_MASK,PPCVEC3,       PPCNONE,    {VD, VB, UIMM4}},
3470 {"evlhhousplat",VX (4, 781),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_2, RA}},
3471 {"evlhhossplatx",VX(4, 782),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3472 {"vpkpx",       VX (4, 782),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3473 {"evlhhossplat",VX (4, 783),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_2, RA}},
3474 {"mullhwu",     XRC(4, 392,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3475 {"evlwhex",     VX (4, 784),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3476 {"mullhwu.",    XRC(4, 392,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3477 {"evlwhe",      VX (4, 785),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3478 {"evlwhoux",    VX (4, 788),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3479 {"evlwhou",     VX (4, 789),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3480 {"evlwhosx",    VX (4, 790),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3481 {"evlwhos",     VX (4, 791),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3482 {"maclhwu",     XO (4, 396,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3483 {"evlwwsplatx", VX (4, 792),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3484 {"maclhwu.",    XO (4, 396,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3485 {"evlwwsplat",  VX (4, 793),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3486 {"evlwhsplatx", VX (4, 796),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3487 {"evlwhsplat",  VX (4, 797),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3488 {"evstddx",     VX (4, 800),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3489 {"evstdd",      VX (4, 801),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3490 {"evstdwx",     VX (4, 802),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3491 {"evstdw",      VX (4, 803),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3492 {"evstdhx",     VX (4, 804),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3493 {"evstdh",      VX (4, 805),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3494 {"evstwhex",    VX (4, 816),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3495 {"evstwhe",     VX (4, 817),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3496 {"evstwhox",    VX (4, 820),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3497 {"evstwho",     VX (4, 821),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3498 {"evstwwex",    VX (4, 824),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3499 {"evstwwe",     VX (4, 825),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3500 {"evstwwox",    VX (4, 828),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3501 {"evstwwo",     VX (4, 829),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3502 {"vaddshs",     VX (4, 832),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3503 {"bcdcpsgn.",   VX (4, 833),    VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
3504 {"vminsh",      VX (4, 834),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3505 {"vsrah",       VX (4, 836),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3506 {"vcmpgtsh",    VXR(4, 838,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3507 {"vmulesh",     VX (4, 840),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3508 {"vcfsx",       VX (4, 842),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3509 {"vcsxwfp",     VX (4, 842),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3510 {"vspltish",    VX (4, 844),    VXVB_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
3511 {"vinserth",    VX (4, 845),    VXUIMM4_MASK,PPCVEC3,       PPCNONE,    {VD, VB, UIMM4}},
3512 {"vupkhpx",     VX (4, 846),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3513 {"mullhw",      XRC(4, 424,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3514 {"mullhw.",     XRC(4, 424,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3515 {"maclhw",      XO (4, 428,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3516 {"maclhw.",     XO (4, 428,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3517 {"nmaclhw",     XO (4, 430,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3518 {"nmaclhw.",    XO (4, 430,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3519 {"vaddsws",     VX (4, 896),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3520 {"vminsw",      VX (4, 898),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3521 {"vsraw",       VX (4, 900),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3522 {"vcmpgtsw",    VXR(4, 902,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3523 {"vmulesw",     VX (4, 904),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3524 {"vctuxs",      VX (4, 906),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3525 {"vcfpuxws",    VX (4, 906),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3526 {"vspltisw",    VX (4, 908),    VXVB_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
3527 {"vinsertw",    VX (4, 909),    VXUIMM4_MASK,PPCVEC3,       PPCNONE,    {VD, VB, UIMM4}},
3528 {"maclhwsu",    XO (4, 460,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3529 {"maclhwsu.",   XO (4, 460,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3530 {"vminsd",      VX (4, 962),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3531 {"vsrad",       VX (4, 964),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3532 {"vcmpbfp",     VXR(4, 966,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3533 {"vcmpgtsd",    VXR(4, 967,0),  VXR_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3534 {"vctsxs",      VX (4, 970),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3535 {"vcfpsxws",    VX (4, 970),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3536 {"vinsertd",    VX (4, 973),    VXUIMM4_MASK,PPCVEC3,       PPCNONE,    {VD, VB, UIMM4}},
3537 {"vupklpx",     VX (4, 974),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3538 {"maclhws",     XO (4, 492,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3539 {"maclhws.",    XO (4, 492,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3540 {"nmaclhws",    XO (4, 494,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3541 {"nmaclhws.",   XO (4, 494,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3542 {"vsububm",     VX (4,1024),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3543 {"bcdadd.",     VX (4,1025),    VXPS_MASK,   PPCVEC2,       PPCNONE,    {VD, VA, VB, PS}},
3544 {"vavgub",      VX (4,1026),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3545 {"vabsdub",     VX (4,1027),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3546 {"evmhessf",    VX (4,1027),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3547 {"vand",        VX (4,1028),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3548 {"vcmpequb.",   VXR(4,   6,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3549 {"vcmpneb.",    VXR(4,   7,1),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
3550 {"udi0fcm.",    APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3551 {"udi0fcm",     APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3552 {"evmhossf",    VX (4,1031),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3553 {"vpmsumb",     VX (4,1032),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3554 {"evmheumi",    VX (4,1032),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3555 {"evmhesmi",    VX (4,1033),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3556 {"vmaxfp",      VX (4,1034),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3557 {"evmhesmf",    VX (4,1035),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3558 {"evmhoumi",    VX (4,1036),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3559 {"vslo",        VX (4,1036),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3560 {"evmhosmi",    VX (4,1037),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3561 {"evmhosmf",    VX (4,1039),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3562 {"machhwuo",    XO (4,  12,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3563 {"machhwuo.",   XO (4,  12,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3564 {"ps_merge00",  XOPS(4,528,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3565 {"ps_merge00.", XOPS(4,528,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3566 {"evmhessfa",   VX (4,1059),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3567 {"evmhossfa",   VX (4,1063),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3568 {"evmheumia",   VX (4,1064),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3569 {"evmhesmia",   VX (4,1065),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3570 {"evmhesmfa",   VX (4,1067),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3571 {"evmhoumia",   VX (4,1068),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3572 {"evmhosmia",   VX (4,1069),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3573 {"evmhosmfa",   VX (4,1071),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3574 {"vsubuhm",     VX (4,1088),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3575 {"bcdsub.",     VX (4,1089),    VXPS_MASK,   PPCVEC2,       PPCNONE,    {VD, VA, VB, PS}},
3576 {"vavguh",      VX (4,1090),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3577 {"vabsduh",     VX (4,1091),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3578 {"vandc",       VX (4,1092),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3579 {"vcmpequh.",   VXR(4,  70,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3580 {"udi1fcm.",    APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3581 {"udi1fcm",     APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3582 {"vcmpneh.",    VXR(4,  71,1),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
3583 {"evmwhssf",    VX (4,1095),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3584 {"vpmsumh",     VX (4,1096),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3585 {"evmwlumi",    VX (4,1096),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3586 {"vminfp",      VX (4,1098),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3587 {"evmwhumi",    VX (4,1100),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3588 {"vsro",        VX (4,1100),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3589 {"evmwhsmi",    VX (4,1101),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3590 {"vpkudum",     VX (4,1102),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3591 {"evmwhsmf",    VX (4,1103),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3592 {"evmwssf",     VX (4,1107),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3593 {"machhwo",     XO (4,  44,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3594 {"evmwumi",     VX (4,1112),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3595 {"machhwo.",    XO (4,  44,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3596 {"evmwsmi",     VX (4,1113),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3597 {"evmwsmf",     VX (4,1115),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3598 {"nmachhwo",    XO (4,  46,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3599 {"nmachhwo.",   XO (4,  46,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3600 {"ps_merge01",  XOPS(4,560,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3601 {"ps_merge01.", XOPS(4,560,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3602 {"evmwhssfa",   VX (4,1127),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3603 {"evmwlumia",   VX (4,1128),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3604 {"evmwhumia",   VX (4,1132),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3605 {"evmwhsmia",   VX (4,1133),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3606 {"evmwhsmfa",   VX (4,1135),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3607 {"evmwssfa",    VX (4,1139),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3608 {"evmwumia",    VX (4,1144),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3609 {"evmwsmia",    VX (4,1145),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3610 {"evmwsmfa",    VX (4,1147),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3611 {"vsubuwm",     VX (4,1152),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3612 {"bcdus.",      VX (4,1153),    VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
3613 {"vavguw",      VX (4,1154),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3614 {"vabsduw",     VX (4,1155),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3615 {"vmr",         VX (4,1156),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VBA}},
3616 {"vor",         VX (4,1156),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3617 {"vcmpnew.",    VXR(4, 135,1),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
3618 {"vpmsumw",     VX (4,1160),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3619 {"vcmpequw.",   VXR(4, 134,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3620 {"udi2fcm.",    APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3621 {"udi2fcm",     APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3622 {"machhwsuo",   XO (4,  76,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3623 {"machhwsuo.",  XO (4,  76,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3624 {"ps_merge10",  XOPS(4,592,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3625 {"ps_merge10.", XOPS(4,592,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3626 {"vsubudm",     VX (4,1216),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3627 {"evaddusiaaw", VX (4,1216),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3628 {"bcds.",       VX (4,1217),    VXPS_MASK,   PPCVEC3,       PPCNONE,    {VD, VA, VB, PS}},
3629 {"evaddssiaaw", VX (4,1217),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3630 {"evsubfusiaaw",VX (4,1218),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3631 {"evsubfssiaaw",VX (4,1219),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3632 {"evmra",       VX (4,1220),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3633 {"vxor",        VX (4,1220),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3634 {"evdivws",     VX (4,1222),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3635 {"vcmpeqfp.",   VXR(4, 198,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3636 {"udi3fcm.",    APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3637 {"vcmpequd.",   VXR(4, 199,1),  VXR_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3638 {"udi3fcm",     APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3639 {"evdivwu",     VX (4,1223),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3640 {"vpmsumd",     VX (4,1224),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3641 {"evaddumiaaw", VX (4,1224),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3642 {"evaddsmiaaw", VX (4,1225),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3643 {"evsubfumiaaw",VX (4,1226),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3644 {"evsubfsmiaaw",VX (4,1227),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3645 {"vpkudus",     VX (4,1230),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3646 {"machhwso",    XO (4, 108,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3647 {"machhwso.",   XO (4, 108,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3648 {"nmachhwso",   XO (4, 110,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3649 {"nmachhwso.",  XO (4, 110,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3650 {"ps_merge11",  XOPS(4,624,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3651 {"ps_merge11.", XOPS(4,624,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3652 {"vsubuqm",     VX (4,1280),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3653 {"evmheusiaaw", VX (4,1280),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3654 {"bcdtrunc.",   VX (4,1281),    VXPS_MASK,   PPCVEC3,       PPCNONE,    {VD, VA, VB, PS}},
3655 {"evmhessiaaw", VX (4,1281),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3656 {"vavgsb",      VX (4,1282),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3657 {"evmhessfaaw", VX (4,1283),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3658 {"evmhousiaaw", VX (4,1284),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3659 {"vnot",        VX (4,1284),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VBA}},
3660 {"vnor",        VX (4,1284),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3661 {"evmhossiaaw", VX (4,1285),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3662 {"udi4fcm.",    APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3663 {"udi4fcm",     APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3664 {"vcmpnezb.",   VXR(4, 263,1),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
3665 {"evmhossfaaw", VX (4,1287),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3666 {"evmheumiaaw", VX (4,1288),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3667 {"vcipher",     VX (4,1288),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3668 {"vcipherlast", VX (4,1289),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3669 {"evmhesmiaaw", VX (4,1289),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3670 {"evmhesmfaaw", VX (4,1291),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3671 {"vgbbd",       VX (4,1292),    VXVA_MASK,   PPCVEC2,       PPCNONE,    {VD, VB}},
3672 {"evmhoumiaaw", VX (4,1292),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3673 {"evmhosmiaaw", VX (4,1293),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3674 {"evmhosmfaaw", VX (4,1295),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3675 {"macchwuo",    XO (4, 140,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3676 {"macchwuo.",   XO (4, 140,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3677 {"evmhegumiaa", VX (4,1320),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3678 {"evmhegsmiaa", VX (4,1321),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3679 {"evmhegsmfaa", VX (4,1323),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3680 {"evmhogumiaa", VX (4,1324),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3681 {"evmhogsmiaa", VX (4,1325),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3682 {"evmhogsmfaa", VX (4,1327),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3683 {"vsubcuq",     VX (4,1344),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3684 {"evmwlusiaaw", VX (4,1344),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3685 {"bcdutrunc.",  VX (4,1345),    VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
3686 {"evmwlssiaaw", VX (4,1345),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3687 {"vavgsh",      VX (4,1346),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3688 {"vorc",        VX (4,1348),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3689 {"udi5fcm.",    APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3690 {"udi5fcm",     APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3691 {"vcmpnezh.",   VXR(4, 327,1),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
3692 {"vncipher",    VX (4,1352),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3693 {"evmwlumiaaw", VX (4,1352),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3694 {"vncipherlast",VX (4,1353),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3695 {"evmwlsmiaaw", VX (4,1353),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3696 {"vbpermq",     VX (4,1356),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3697 {"vpksdus",     VX (4,1358),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3698 {"evmwssfaa",   VX (4,1363),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3699 {"macchwo",     XO (4, 172,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3700 {"evmwumiaa",   VX (4,1368),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3701 {"macchwo.",    XO (4, 172,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3702 {"evmwsmiaa",   VX (4,1369),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3703 {"evmwsmfaa",   VX (4,1371),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3704 {"nmacchwo",    XO (4, 174,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3705 {"nmacchwo.",   XO (4, 174,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3706 {"evmheusianw", VX (4,1408),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3707 {"vsubcuw",     VX (4,1408),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3708 {"evmhessianw", VX (4,1409),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3709 {"bcdctsq.",    VXVA(4,1409,0), VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
3710 {"bcdcfsq.",    VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3,       PPCNONE,    {VD, VB, PS}},
3711 {"bcdctz.",     VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3,       PPCNONE,    {VD, VB, PS}},
3712 {"bcdctn.",     VXVA(4,1409,5), VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
3713 {"bcdcfz.",     VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3,       PPCNONE,    {VD, VB, PS}},
3714 {"bcdcfn.",     VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3,       PPCNONE,    {VD, VB, PS}},
3715 {"bcdsetsgn.",  VXVA(4,1409,31),VXVAPS_MASK, PPCVEC3,       PPCNONE,    {VD, VB, PS}},
3716 {"vavgsw",      VX (4,1410),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3717 {"evmhessfanw", VX (4,1411),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3718 {"vnand",       VX (4,1412),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3719 {"evmhousianw", VX (4,1412),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3720 {"evmhossianw", VX (4,1413),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3721 {"udi6fcm.",    APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3722 {"udi6fcm",     APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3723 {"vcmpnezw.",   VXR(4, 391,1),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
3724 {"evmhossfanw", VX (4,1415),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3725 {"evmheumianw", VX (4,1416),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3726 {"evmhesmianw", VX (4,1417),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3727 {"evmhesmfanw", VX (4,1419),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3728 {"evmhoumianw", VX (4,1420),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3729 {"evmhosmianw", VX (4,1421),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3730 {"evmhosmfanw", VX (4,1423),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3731 {"macchwsuo",   XO (4, 204,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3732 {"macchwsuo.",  XO (4, 204,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3733 {"evmhegumian", VX (4,1448),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3734 {"evmhegsmian", VX (4,1449),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3735 {"evmhegsmfan", VX (4,1451),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3736 {"evmhogumian", VX (4,1452),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3737 {"evmhogsmian", VX (4,1453),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3738 {"evmhogsmfan", VX (4,1455),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3739 {"evmwlusianw", VX (4,1472),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3740 {"bcdsr.",      VX (4,1473),    VXPS_MASK,   PPCVEC3,       PPCNONE,    {VD, VA, VB, PS}},
3741 {"evmwlssianw", VX (4,1473),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3742 {"vsld",        VX (4,1476),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3743 {"vcmpgefp.",   VXR(4, 454,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3744 {"udi7fcm.",    APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3745 {"udi7fcm",     APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3746 {"vsbox",       VX (4,1480),    VXVB_MASK,   PPCVEC2,       PPCNONE,    {VD, VA}},
3747 {"evmwlumianw", VX (4,1480),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3748 {"evmwlsmianw", VX (4,1481),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3749 {"vbpermd",     VX (4,1484),    VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
3750 {"vpksdss",     VX (4,1486),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3751 {"evmwssfan",   VX (4,1491),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3752 {"macchwso",    XO (4, 236,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3753 {"evmwumian",   VX (4,1496),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3754 {"macchwso.",   XO (4, 236,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3755 {"evmwsmian",   VX (4,1497),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3756 {"evmwsmfan",   VX (4,1499),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3757 {"nmacchwso",   XO (4, 238,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3758 {"nmacchwso.",  XO (4, 238,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3759 {"vsububs",     VX (4,1536),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3760 {"vclzlsbb",    VXVA(4,1538,0), VXVA_MASK,   PPCVEC3,       PPCNONE,    {RT, VB}},
3761 {"vctzlsbb",    VXVA(4,1538,1), VXVA_MASK,   PPCVEC3,       PPCNONE,    {RT, VB}},
3762 {"vnegw",       VXVA(4,1538,6), VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
3763 {"vnegd",       VXVA(4,1538,7), VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
3764 {"vprtybw",     VXVA(4,1538,8), VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
3765 {"vprtybd",     VXVA(4,1538,9), VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
3766 {"vprtybq",     VXVA(4,1538,10),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
3767 {"vextsb2w",    VXVA(4,1538,16),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
3768 {"vextsh2w",    VXVA(4,1538,17),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
3769 {"vextsb2d",    VXVA(4,1538,24),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
3770 {"vextsh2d",    VXVA(4,1538,25),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
3771 {"vextsw2d",    VXVA(4,1538,26),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
3772 {"vctzb",       VXVA(4,1538,28),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
3773 {"vctzh",       VXVA(4,1538,29),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
3774 {"vctzw",       VXVA(4,1538,30),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
3775 {"vctzd",       VXVA(4,1538,31),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
3776 {"mfvscr",      VX (4,1540),    VXVAVB_MASK, PPCVEC|PPCVLE, PPCNONE,    {VD}},
3777 {"vcmpgtub.",   VXR(4, 518,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3778 {"udi8fcm.",    APU(4, 771,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3779 {"udi8fcm",     APU(4, 771,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3780 {"vsum4ubs",    VX (4,1544),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3781 {"vextublx",    VX (4,1549),    VX_MASK,     PPCVEC3,       PPCNONE,    {RT, RA, VB}},
3782 {"vsubuhs",     VX (4,1600),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3783 {"mtvscr",      VX (4,1604),    VXVDVA_MASK, PPCVEC|PPCVLE, PPCNONE,    {VB}},
3784 {"vcmpgtuh.",   VXR(4, 582,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3785 {"vsum4shs",    VX (4,1608),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3786 {"udi9fcm.",    APU(4, 804,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3787 {"udi9fcm",     APU(4, 804,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3788 {"vextuhlx",    VX (4,1613),    VX_MASK,     PPCVEC3,   PPCNONE,        {RT, RA, VB}},
3789 {"vupkhsw",     VX (4,1614),    VXVA_MASK,   PPCVEC2,       PPCNONE,    {VD, VB}},
3790 {"vsubuws",     VX (4,1664),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3791 {"vshasigmaw",  VX (4,1666),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, ST, SIX}},
3792 {"veqv",        VX (4,1668),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3793 {"vcmpgtuw.",   VXR(4, 646,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3794 {"udi10fcm.",   APU(4, 835,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3795 {"udi10fcm",    APU(4, 835,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3796 {"vsum2sws",    VX (4,1672),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3797 {"vmrgow",      VX (4,1676),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3798 {"vextuwlx",    VX (4,1677),    VX_MASK,     PPCVEC3,   PPCNONE,        {RT, RA, VB}},
3799 {"vshasigmad",  VX (4,1730),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, ST, SIX}},
3800 {"vsrd",        VX (4,1732),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3801 {"vcmpgtfp.",   VXR(4, 710,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3802 {"udi11fcm.",   APU(4, 867,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3803 {"vcmpgtud.",   VXR(4, 711,1),  VXR_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3804 {"udi11fcm",    APU(4, 867,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3805 {"vupklsw",     VX (4,1742),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
3806 {"vsubsbs",     VX (4,1792),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3807 {"vclzb",       VX (4,1794),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
3808 {"vpopcntb",    VX (4,1795),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
3809 {"vsrv",        VX (4,1796),    VX_MASK,     PPCVEC3,   PPCNONE,        {VD, VA, VB}},
3810 {"vcmpgtsb.",   VXR(4, 774,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3811 {"udi12fcm.",   APU(4, 899,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3812 {"udi12fcm",    APU(4, 899,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3813 {"vsum4sbs",    VX (4,1800),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3814 {"vextubrx",    VX (4,1805),    VX_MASK,     PPCVEC3,   PPCNONE,        {RT, RA, VB}},
3815 {"maclhwuo",    XO (4, 396,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3816 {"maclhwuo.",   XO (4, 396,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3817 {"vsubshs",     VX (4,1856),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3818 {"vclzh",       VX (4,1858),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
3819 {"vpopcnth",    VX (4,1859),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
3820 {"vslv",        VX (4,1860),    VX_MASK,     PPCVEC3,   PPCNONE,        {VD, VA, VB}},
3821 {"vcmpgtsh.",   VXR(4, 838,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3822 {"vextuhrx",    VX (4,1869),    VX_MASK,     PPCVEC3,   PPCNONE,        {RT, RA, VB}},
3823 {"udi13fcm.",   APU(4, 931,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3824 {"udi13fcm",    APU(4, 931,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3825 {"maclhwo",     XO (4, 428,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3826 {"maclhwo.",    XO (4, 428,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3827 {"nmaclhwo",    XO (4, 430,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3828 {"nmaclhwo.",   XO (4, 430,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3829 {"vsubsws",     VX (4,1920),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3830 {"vclzw",       VX (4,1922),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
3831 {"vpopcntw",    VX (4,1923),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
3832 {"vcmpgtsw.",   VXR(4, 902,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3833 {"udi14fcm.",   APU(4, 963,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3834 {"udi14fcm",    APU(4, 963,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3835 {"vsumsws",     VX (4,1928),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3836 {"vmrgew",      VX (4,1932),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3837 {"vextuwrx",    VX (4,1933),    VX_MASK,     PPCVEC3,   PPCNONE,        {RT, RA, VB}},
3838 {"maclhwsuo",   XO (4, 460,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3839 {"maclhwsuo.",  XO (4, 460,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3840 {"vclzd",       VX (4,1986),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
3841 {"vpopcntd",    VX (4,1987),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
3842 {"vcmpbfp.",    VXR(4, 966,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
3843 {"udi15fcm.",   APU(4, 995,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3844 {"vcmpgtsd.",   VXR(4, 967,1),  VXR_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3845 {"udi15fcm",    APU(4, 995,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3846 {"maclhwso",    XO (4, 492,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3847 {"maclhwso.",   XO (4, 492,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3848 {"nmaclhwso",   XO (4, 494,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3849 {"nmaclhwso.",  XO (4, 494,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3850 {"dcbz_l",      X  (4,1014),    XRT_MASK,    PPCPS,     PPCNONE,        {RA, RB}},
3851
3852 {"mulli",       OP(7),          OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
3853 {"muli",        OP(7),          OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
3854
3855 {"subfic",      OP(8),          OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
3856 {"sfi",         OP(8),          OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
3857
3858 {"dozi",        OP(9),          OP_MASK,     M601,      PPCNONE,        {RT, RA, SI}},
3859
3860 {"cmplwi",      OPL(10,0),      OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, UISIGNOPT}},
3861 {"cmpldi",      OPL(10,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, UISIGNOPT}},
3862 {"cmpli",       OP(10),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, UISIGNOPT}},
3863 {"cmpli",       OP(10),         OP_MASK,     PWRCOM,    PPC,            {BF, RA, UISIGNOPT}},
3864
3865 {"cmpwi",       OPL(11,0),      OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, SI}},
3866 {"cmpdi",       OPL(11,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, SI}},
3867 {"cmpi",        OP(11),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, SI}},
3868 {"cmpi",        OP(11),         OP_MASK,     PWRCOM,    PPC,            {BF, RA, SI}},
3869
3870 {"addic",       OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
3871 {"ai",          OP(12),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
3872 {"subic",       OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, NSI}},
3873
3874 {"addic.",      OP(13),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
3875 {"ai.",         OP(13),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
3876 {"subic.",      OP(13),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, NSI}},
3877
3878 {"li",          OP(14),         DRA_MASK,    PPCCOM,    PPCNONE,        {RT, SI}},
3879 {"lil",         OP(14),         DRA_MASK,    PWRCOM,    PPCNONE,        {RT, SI}},
3880 {"addi",        OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, SI}},
3881 {"cal",         OP(14),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
3882 {"subi",        OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, NSI}},
3883 {"la",          OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RA0}},
3884
3885 {"lis",         OP(15),         DRA_MASK,    PPCCOM,    PPCNONE,        {RT, SISIGNOPT}},
3886 {"liu",         OP(15),         DRA_MASK,    PWRCOM,    PPCNONE,        {RT, SISIGNOPT}},
3887 {"addis",       OP(15),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, SISIGNOPT}},
3888 {"cau",         OP(15),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA0, SISIGNOPT}},
3889 {"subis",       OP(15),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, NSISIGNOPT}},
3890
3891 {"bdnz-",    BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
3892 {"bdnz+",    BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
3893 {"bdnz",     BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BD}},
3894 {"bdn",      BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BD}},
3895 {"bdnzl-",   BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
3896 {"bdnzl+",   BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
3897 {"bdnzl",    BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BD}},
3898 {"bdnl",     BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BD}},
3899 {"bdnza-",   BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
3900 {"bdnza+",   BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
3901 {"bdnza",    BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDA}},
3902 {"bdna",     BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BDA}},
3903 {"bdnzla-",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
3904 {"bdnzla+",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
3905 {"bdnzla",   BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDA}},
3906 {"bdnla",    BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BDA}},
3907 {"bdz-",     BBO(16,BODZ,0,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
3908 {"bdz+",     BBO(16,BODZ,0,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
3909 {"bdz",      BBO(16,BODZ,0,0),          BBOATBI_MASK,  COM,      PPCNONE,       {BD}},
3910 {"bdzl-",    BBO(16,BODZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
3911 {"bdzl+",    BBO(16,BODZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
3912 {"bdzl",     BBO(16,BODZ,0,1),          BBOATBI_MASK,  COM,      PPCNONE,       {BD}},
3913 {"bdza-",    BBO(16,BODZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
3914 {"bdza+",    BBO(16,BODZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
3915 {"bdza",     BBO(16,BODZ,1,0),          BBOATBI_MASK,  COM,      PPCNONE,       {BDA}},
3916 {"bdzla-",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
3917 {"bdzla+",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
3918 {"bdzla",    BBO(16,BODZ,1,1),          BBOATBI_MASK,  COM,      PPCNONE,       {BDA}},
3919
3920 {"bge-",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3921 {"bge+",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3922 {"bge",      BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3923 {"bnl-",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3924 {"bnl+",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3925 {"bnl",      BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3926 {"bgel-",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3927 {"bgel+",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3928 {"bgel",     BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3929 {"bnll-",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3930 {"bnll+",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3931 {"bnll",     BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3932 {"bgea-",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3933 {"bgea+",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3934 {"bgea",     BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3935 {"bnla-",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3936 {"bnla+",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3937 {"bnla",     BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3938 {"bgela-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3939 {"bgela+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3940 {"bgela",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3941 {"bnlla-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3942 {"bnlla+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3943 {"bnlla",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3944 {"ble-",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3945 {"ble+",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3946 {"ble",      BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3947 {"bng-",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3948 {"bng+",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3949 {"bng",      BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3950 {"blel-",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3951 {"blel+",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3952 {"blel",     BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3953 {"bngl-",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3954 {"bngl+",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3955 {"bngl",     BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3956 {"blea-",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3957 {"blea+",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3958 {"blea",     BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3959 {"bnga-",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3960 {"bnga+",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3961 {"bnga",     BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3962 {"blela-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3963 {"blela+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3964 {"blela",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3965 {"bngla-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3966 {"bngla+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3967 {"bngla",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3968 {"bne-",     BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3969 {"bne+",     BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3970 {"bne",      BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3971 {"bnel-",    BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3972 {"bnel+",    BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3973 {"bnel",     BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3974 {"bnea-",    BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3975 {"bnea+",    BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3976 {"bnea",     BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3977 {"bnela-",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3978 {"bnela+",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3979 {"bnela",    BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3980 {"bns-",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3981 {"bns+",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3982 {"bns",      BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3983 {"bnu-",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3984 {"bnu+",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3985 {"bnu",      BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
3986 {"bnsl-",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3987 {"bnsl+",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3988 {"bnsl",     BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3989 {"bnul-",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3990 {"bnul+",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3991 {"bnul",     BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
3992 {"bnsa-",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3993 {"bnsa+",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3994 {"bnsa",     BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3995 {"bnua-",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3996 {"bnua+",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3997 {"bnua",     BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
3998 {"bnsla-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3999 {"bnsla+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
4000 {"bnsla",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
4001 {"bnula-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
4002 {"bnula+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
4003 {"bnula",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
4004
4005 {"blt-",     BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
4006 {"blt+",     BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
4007 {"blt",      BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
4008 {"bltl-",    BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
4009 {"bltl+",    BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
4010 {"bltl",     BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
4011 {"blta-",    BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
4012 {"blta+",    BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
4013 {"blta",     BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
4014 {"bltla-",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
4015 {"bltla+",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
4016 {"bltla",    BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
4017 {"bgt-",     BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
4018 {"bgt+",     BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
4019 {"bgt",      BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
4020 {"bgtl-",    BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
4021 {"bgtl+",    BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
4022 {"bgtl",     BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
4023 {"bgta-",    BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
4024 {"bgta+",    BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
4025 {"bgta",     BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
4026 {"bgtla-",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
4027 {"bgtla+",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
4028 {"bgtla",    BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
4029 {"beq-",     BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
4030 {"beq+",     BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
4031 {"beq",      BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
4032 {"beql-",    BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
4033 {"beql+",    BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
4034 {"beql",     BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
4035 {"beqa-",    BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
4036 {"beqa+",    BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
4037 {"beqa",     BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
4038 {"beqla-",   BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
4039 {"beqla+",   BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
4040 {"beqla",    BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
4041 {"bso-",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
4042 {"bso+",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
4043 {"bso",      BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
4044 {"bun-",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
4045 {"bun+",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
4046 {"bun",      BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
4047 {"bsol-",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
4048 {"bsol+",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
4049 {"bsol",     BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
4050 {"bunl-",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
4051 {"bunl+",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
4052 {"bunl",     BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
4053 {"bsoa-",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
4054 {"bsoa+",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
4055 {"bsoa",     BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
4056 {"buna-",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
4057 {"buna+",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
4058 {"buna",     BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
4059 {"bsola-",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
4060 {"bsola+",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
4061 {"bsola",    BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
4062 {"bunla-",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
4063 {"bunla+",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
4064 {"bunla",    BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
4065
4066 {"bdnzf-",   BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
4067 {"bdnzf+",   BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
4068 {"bdnzf",    BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
4069 {"bdnzfl-",  BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
4070 {"bdnzfl+",  BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
4071 {"bdnzfl",   BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
4072 {"bdnzfa-",  BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
4073 {"bdnzfa+",  BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
4074 {"bdnzfa",   BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
4075 {"bdnzfla-", BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
4076 {"bdnzfla+", BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
4077 {"bdnzfla",  BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
4078 {"bdzf-",    BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
4079 {"bdzf+",    BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
4080 {"bdzf",     BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
4081 {"bdzfl-",   BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
4082 {"bdzfl+",   BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
4083 {"bdzfl",    BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
4084 {"bdzfa-",   BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
4085 {"bdzfa+",   BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
4086 {"bdzfa",    BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
4087 {"bdzfla-",  BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
4088 {"bdzfla+",  BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
4089 {"bdzfla",   BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
4090
4091 {"bf-",      BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
4092 {"bf+",      BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
4093 {"bf",       BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
4094 {"bbf",      BBO(16,BOF,0,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
4095 {"bfl-",     BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
4096 {"bfl+",     BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
4097 {"bfl",      BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
4098 {"bbfl",     BBO(16,BOF,0,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
4099 {"bfa-",     BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
4100 {"bfa+",     BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
4101 {"bfa",      BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
4102 {"bbfa",     BBO(16,BOF,1,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
4103 {"bfla-",    BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
4104 {"bfla+",    BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
4105 {"bfla",     BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
4106 {"bbfla",    BBO(16,BOF,1,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
4107
4108 {"bdnzt-",   BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
4109 {"bdnzt+",   BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
4110 {"bdnzt",    BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
4111 {"bdnztl-",  BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
4112 {"bdnztl+",  BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
4113 {"bdnztl",   BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
4114 {"bdnzta-",  BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
4115 {"bdnzta+",  BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
4116 {"bdnzta",   BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
4117 {"bdnztla-", BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
4118 {"bdnztla+", BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
4119 {"bdnztla",  BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
4120 {"bdzt-",    BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
4121 {"bdzt+",    BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
4122 {"bdzt",     BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
4123 {"bdztl-",   BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
4124 {"bdztl+",   BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
4125 {"bdztl",    BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
4126 {"bdzta-",   BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
4127 {"bdzta+",   BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
4128 {"bdzta",    BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
4129 {"bdztla-",  BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
4130 {"bdztla+",  BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
4131 {"bdztla",   BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
4132
4133 {"bt-",      BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
4134 {"bt+",      BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
4135 {"bt",       BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
4136 {"bbt",      BBO(16,BOT,0,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
4137 {"btl-",     BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
4138 {"btl+",     BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
4139 {"btl",      BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
4140 {"bbtl",     BBO(16,BOT,0,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
4141 {"bta-",     BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
4142 {"bta+",     BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
4143 {"bta",      BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
4144 {"bbta",     BBO(16,BOT,1,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
4145 {"btla-",    BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
4146 {"btla+",    BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
4147 {"btla",     BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
4148 {"bbtla",    BBO(16,BOT,1,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
4149
4150 {"bc-",         B(16,0,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDM}},
4151 {"bc+",         B(16,0,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDP}},
4152 {"bc",          B(16,0,0),      B_MASK,      COM,       PPCNONE,        {BO, BI, BD}},
4153 {"bcl-",        B(16,0,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDM}},
4154 {"bcl+",        B(16,0,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDP}},
4155 {"bcl",         B(16,0,1),      B_MASK,      COM,       PPCNONE,        {BO, BI, BD}},
4156 {"bca-",        B(16,1,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDMA}},
4157 {"bca+",        B(16,1,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDPA}},
4158 {"bca",         B(16,1,0),      B_MASK,      COM,       PPCNONE,        {BO, BI, BDA}},
4159 {"bcla-",       B(16,1,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDMA}},
4160 {"bcla+",       B(16,1,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDPA}},
4161 {"bcla",        B(16,1,1),      B_MASK,      COM,       PPCNONE,        {BO, BI, BDA}},
4162
4163 {"svc",         SC(17,0,0),     SC_MASK,     POWER,     PPCNONE,        {SVC_LEV, FL1, FL2}},
4164 {"svcl",        SC(17,0,1),     SC_MASK,     POWER,     PPCNONE,        {SVC_LEV, FL1, FL2}},
4165 {"sc",          SC(17,1,0),     SC_MASK,     PPC,       PPCNONE,        {LEV}},
4166 {"svca",        SC(17,1,0),     SC_MASK,     PWRCOM,    PPCNONE,        {SV}},
4167 {"svcla",       SC(17,1,1),     SC_MASK,     POWER,     PPCNONE,        {SV}},
4168
4169 {"b",           B(18,0,0),      B_MASK,      COM,       PPCNONE,        {LI}},
4170 {"bl",          B(18,0,1),      B_MASK,      COM,       PPCNONE,        {LI}},
4171 {"ba",          B(18,1,0),      B_MASK,      COM,       PPCNONE,        {LIA}},
4172 {"bla",         B(18,1,1),      B_MASK,      COM,       PPCNONE,        {LIA}},
4173
4174 {"mcrf",      XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE,        {BF, BFA}},
4175
4176 {"addpcis",   DX(19,2),         DX_MASK,     POWER9,    PPCNONE,        {RT, DXD}},
4177 {"subpcis",   DX(19,2),         DX_MASK,     POWER9,    PPCNONE,        {RT, NDXD}},
4178
4179 {"bdnzlr",   XLO(19,BODNZ,16,0),        XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
4180 {"bdnzlr-",  XLO(19,BODNZ,16,0),        XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
4181 {"bdnzlrl",  XLO(19,BODNZ,16,1),        XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
4182 {"bdnzlrl-", XLO(19,BODNZ,16,1),        XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
4183 {"bdnzlr+",  XLO(19,BODNZP,16,0),       XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
4184 {"bdnzlrl+", XLO(19,BODNZP,16,1),       XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
4185 {"bdzlr",    XLO(19,BODZ,16,0),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
4186 {"bdzlr-",   XLO(19,BODZ,16,0),         XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
4187 {"bdzlrl",   XLO(19,BODZ,16,1),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
4188 {"bdzlrl-",  XLO(19,BODZ,16,1),         XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
4189 {"bdzlr+",   XLO(19,BODZP,16,0),        XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
4190 {"bdzlrl+",  XLO(19,BODZP,16,1),        XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
4191 {"blr",      XLO(19,BOU,16,0),          XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
4192 {"br",       XLO(19,BOU,16,0),          XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
4193 {"blrl",     XLO(19,BOU,16,1),          XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
4194 {"brl",      XLO(19,BOU,16,1),          XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
4195 {"bdnzlr-",  XLO(19,BODNZM4,16,0),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
4196 {"bdnzlrl-", XLO(19,BODNZM4,16,1),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
4197 {"bdnzlr+",  XLO(19,BODNZP4,16,0),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
4198 {"bdnzlrl+", XLO(19,BODNZP4,16,1),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
4199 {"bdzlr-",   XLO(19,BODZM4,16,0),       XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
4200 {"bdzlrl-",  XLO(19,BODZM4,16,1),       XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
4201 {"bdzlr+",   XLO(19,BODZP4,16,0),       XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
4202 {"bdzlrl+",  XLO(19,BODZP4,16,1),       XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
4203
4204 {"bgelr",    XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4205 {"bgelr-",   XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4206 {"bger",     XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4207 {"bnllr",    XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4208 {"bnllr-",   XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4209 {"bnlr",     XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4210 {"bgelrl",   XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4211 {"bgelrl-",  XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4212 {"bgerl",    XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4213 {"bnllrl",   XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4214 {"bnllrl-",  XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4215 {"bnlrl",    XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4216 {"blelr",    XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4217 {"blelr-",   XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4218 {"bler",     XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4219 {"bnglr",    XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4220 {"bnglr-",   XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4221 {"bngr",     XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4222 {"blelrl",   XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4223 {"blelrl-",  XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4224 {"blerl",    XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4225 {"bnglrl",   XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4226 {"bnglrl-",  XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4227 {"bngrl",    XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4228 {"bnelr",    XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4229 {"bnelr-",   XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4230 {"bner",     XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4231 {"bnelrl",   XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4232 {"bnelrl-",  XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4233 {"bnerl",    XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4234 {"bnslr",    XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4235 {"bnslr-",   XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4236 {"bnsr",     XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4237 {"bnulr",    XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4238 {"bnulr-",   XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4239 {"bnslrl",   XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4240 {"bnslrl-",  XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4241 {"bnsrl",    XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4242 {"bnulrl",   XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4243 {"bnulrl-",  XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4244 {"bgelr+",   XLOCB(19,BOFP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4245 {"bnllr+",   XLOCB(19,BOFP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4246 {"bgelrl+",  XLOCB(19,BOFP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4247 {"bnllrl+",  XLOCB(19,BOFP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4248 {"blelr+",   XLOCB(19,BOFP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4249 {"bnglr+",   XLOCB(19,BOFP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4250 {"blelrl+",  XLOCB(19,BOFP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4251 {"bnglrl+",  XLOCB(19,BOFP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4252 {"bnelr+",   XLOCB(19,BOFP,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4253 {"bnelrl+",  XLOCB(19,BOFP,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4254 {"bnslr+",   XLOCB(19,BOFP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4255 {"bnulr+",   XLOCB(19,BOFP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4256 {"bnslrl+",  XLOCB(19,BOFP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4257 {"bnulrl+",  XLOCB(19,BOFP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4258 {"bgelr-",   XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4259 {"bnllr-",   XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4260 {"bgelrl-",  XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4261 {"bnllrl-",  XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4262 {"blelr-",   XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4263 {"bnglr-",   XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4264 {"blelrl-",  XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4265 {"bnglrl-",  XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4266 {"bnelr-",   XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4267 {"bnelrl-",  XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4268 {"bnslr-",   XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4269 {"bnulr-",   XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4270 {"bnslrl-",  XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4271 {"bnulrl-",  XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4272 {"bgelr+",   XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4273 {"bnllr+",   XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4274 {"bgelrl+",  XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4275 {"bnllrl+",  XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4276 {"blelr+",   XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4277 {"bnglr+",   XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4278 {"blelrl+",  XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4279 {"bnglrl+",  XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4280 {"bnelr+",   XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4281 {"bnelrl+",  XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4282 {"bnslr+",   XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4283 {"bnulr+",   XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4284 {"bnslrl+",  XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4285 {"bnulrl+",  XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4286 {"bltlr",    XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4287 {"bltlr-",   XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4288 {"bltr",     XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4289 {"bltlrl",   XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4290 {"bltlrl-",  XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4291 {"bltrl",    XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4292 {"bgtlr",    XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4293 {"bgtlr-",   XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4294 {"bgtr",     XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4295 {"bgtlrl",   XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4296 {"bgtlrl-",  XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4297 {"bgtrl",    XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4298 {"beqlr",    XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4299 {"beqlr-",   XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4300 {"beqr",     XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4301 {"beqlrl",   XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4302 {"beqlrl-",  XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4303 {"beqrl",    XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4304 {"bsolr",    XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4305 {"bsolr-",   XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4306 {"bsor",     XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4307 {"bunlr",    XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4308 {"bunlr-",   XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4309 {"bsolrl",   XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4310 {"bsolrl-",  XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4311 {"bsorl",    XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
4312 {"bunlrl",   XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4313 {"bunlrl-",  XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4314 {"bltlr+",   XLOCB(19,BOTP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4315 {"bltlrl+",  XLOCB(19,BOTP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4316 {"bgtlr+",   XLOCB(19,BOTP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4317 {"bgtlrl+",  XLOCB(19,BOTP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4318 {"beqlr+",   XLOCB(19,BOTP,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4319 {"beqlrl+",  XLOCB(19,BOTP,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4320 {"bsolr+",   XLOCB(19,BOTP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4321 {"bunlr+",   XLOCB(19,BOTP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4322 {"bsolrl+",  XLOCB(19,BOTP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4323 {"bunlrl+",  XLOCB(19,BOTP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4324 {"bltlr-",   XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4325 {"bltlrl-",  XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4326 {"bgtlr-",   XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4327 {"bgtlrl-",  XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4328 {"beqlr-",   XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4329 {"beqlrl-",  XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4330 {"bsolr-",   XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4331 {"bunlr-",   XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4332 {"bsolrl-",  XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4333 {"bunlrl-",  XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4334 {"bltlr+",   XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4335 {"bltlrl+",  XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4336 {"bgtlr+",   XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4337 {"bgtlrl+",  XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4338 {"beqlr+",   XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4339 {"beqlrl+",  XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4340 {"bsolr+",   XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4341 {"bunlr+",   XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4342 {"bsolrl+",  XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4343 {"bunlrl+",  XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4344
4345 {"bdnzflr",  XLO(19,BODNZF,16,0),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4346 {"bdnzflr-", XLO(19,BODNZF,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4347 {"bdnzflrl", XLO(19,BODNZF,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4348 {"bdnzflrl-",XLO(19,BODNZF,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4349 {"bdnzflr+", XLO(19,BODNZFP,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4350 {"bdnzflrl+",XLO(19,BODNZFP,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4351 {"bdzflr",   XLO(19,BODZF,16,0),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4352 {"bdzflr-",  XLO(19,BODZF,16,0),        XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4353 {"bdzflrl",  XLO(19,BODZF,16,1),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4354 {"bdzflrl-", XLO(19,BODZF,16,1),        XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4355 {"bdzflr+",  XLO(19,BODZFP,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4356 {"bdzflrl+", XLO(19,BODZFP,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4357 {"bflr",     XLO(19,BOF,16,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4358 {"bflr-",    XLO(19,BOF,16,0),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4359 {"bbfr",     XLO(19,BOF,16,0),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
4360 {"bflrl",    XLO(19,BOF,16,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4361 {"bflrl-",   XLO(19,BOF,16,1),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4362 {"bbfrl",    XLO(19,BOF,16,1),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
4363 {"bflr+",    XLO(19,BOFP,16,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4364 {"bflrl+",   XLO(19,BOFP,16,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4365 {"bflr-",    XLO(19,BOFM4,16,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4366 {"bflrl-",   XLO(19,BOFM4,16,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4367 {"bflr+",    XLO(19,BOFP4,16,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4368 {"bflrl+",   XLO(19,BOFP4,16,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4369 {"bdnztlr",  XLO(19,BODNZT,16,0),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4370 {"bdnztlr-", XLO(19,BODNZT,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4371 {"bdnztlrl", XLO(19,BODNZT,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4372 {"bdnztlrl-",XLO(19,BODNZT,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4373 {"bdnztlr+", XLO(19,BODNZTP,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4374 {"bdnztlrl+",XLO(19,BODNZTP,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4375 {"bdztlr",   XLO(19,BODZT,16,0),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4376 {"bdztlr-",  XLO(19,BODZT,16,0),        XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4377 {"bdztlrl",  XLO(19,BODZT,16,1),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4378 {"bdztlrl-", XLO(19,BODZT,16,1),        XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4379 {"bdztlr+",  XLO(19,BODZTP,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4380 {"bdztlrl+", XLO(19,BODZTP,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4381 {"btlr",     XLO(19,BOT,16,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4382 {"btlr-",    XLO(19,BOT,16,0),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4383 {"bbtr",     XLO(19,BOT,16,0),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
4384 {"btlrl",    XLO(19,BOT,16,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4385 {"btlrl-",   XLO(19,BOT,16,1),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4386 {"bbtrl",    XLO(19,BOT,16,1),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
4387 {"btlr+",    XLO(19,BOTP,16,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4388 {"btlrl+",   XLO(19,BOTP,16,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4389 {"btlr-",    XLO(19,BOTM4,16,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4390 {"btlrl-",   XLO(19,BOTM4,16,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4391 {"btlr+",    XLO(19,BOTP4,16,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4392 {"btlrl+",   XLO(19,BOTP4,16,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4393
4394 {"bclr-",    XLYLK(19,16,0,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4395 {"bclrl-",   XLYLK(19,16,0,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4396 {"bclr+",    XLYLK(19,16,1,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4397 {"bclrl+",   XLYLK(19,16,1,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4398 {"bclr",     XLLK(19,16,0),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
4399 {"bcr",      XLLK(19,16,0),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
4400 {"bclrl",    XLLK(19,16,1),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
4401 {"bcrl",     XLLK(19,16,1),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
4402
4403 {"rfid",        XL(19,18),      0xffffffff,  PPC64,     PPCNONE,        {0}},
4404
4405 {"crnot",       XL(19,33),      XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
4406 {"crnor",       XL(19,33),      XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
4407 {"rfmci",       X(19,38),   0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}},
4408
4409 {"rfdi",        XL(19,39),      0xffffffff,  E500MC,    PPCNONE,        {0}},
4410 {"rfi",         XL(19,50),      0xffffffff,  COM,       PPCNONE,        {0}},
4411 {"rfci",        XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {0}},
4412
4413 {"rfsvc",       XL(19,82),      0xffffffff,  POWER,     PPCNONE,        {0}},
4414
4415 {"rfgi",        XL(19,102),   0xffffffff, E500MC|PPCA2, PPCNONE,        {0}},
4416
4417 {"crandc",      XL(19,129),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
4418
4419 {"rfebb",       XL(19,146),     XLS_MASK,    POWER8,    PPCNONE,        {SXL}},
4420
4421 {"isync",       XL(19,150),     0xffffffff,  PPCCOM,    PPCNONE,        {0}},
4422 {"ics",         XL(19,150),     0xffffffff,  PWRCOM,    PPCNONE,        {0}},
4423
4424 {"crclr",       XL(19,193),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
4425 {"crxor",       XL(19,193),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
4426
4427 {"dnh",         X(19,198),      X_MASK,      E500MC,    PPCNONE,        {DUI, DUIS}},
4428
4429 {"crnand",      XL(19,225),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
4430
4431 {"crand",       XL(19,257),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
4432
4433 {"hrfid",       XL(19,274),     0xffffffff, POWER5|CELL, PPC476,        {0}},
4434
4435 {"crset",       XL(19,289),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
4436 {"creqv",       XL(19,289),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
4437
4438 {"urfid",       XL(19,306),     0xffffffff,  POWER9,    PPCNONE,        {0}},
4439 {"stop",        XL(19,370),     0xffffffff,  POWER9,    PPCNONE,        {0}},
4440
4441 {"doze",        XL(19,402),     0xffffffff,  POWER6,    POWER9,         {0}},
4442
4443 {"crorc",       XL(19,417),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
4444
4445 {"nap",         XL(19,434),     0xffffffff,  POWER6,    POWER9,         {0}},
4446
4447 {"crmove",      XL(19,449),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
4448 {"cror",        XL(19,449),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
4449
4450 {"sleep",       XL(19,466),     0xffffffff,  POWER6,    POWER9,         {0}},
4451 {"rvwinkle",    XL(19,498),     0xffffffff,  POWER6,    POWER9,         {0}},
4452
4453 {"bctr",    XLO(19,BOU,528,0),          XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
4454 {"bctrl",   XLO(19,BOU,528,1),          XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
4455
4456 {"bgectr",  XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4457 {"bgectr-", XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4458 {"bnlctr",  XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4459 {"bnlctr-", XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4460 {"bgectrl", XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4461 {"bgectrl-",XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4462 {"bnlctrl", XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4463 {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4464 {"blectr",  XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4465 {"blectr-", XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4466 {"bngctr",  XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4467 {"bngctr-", XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4468 {"blectrl", XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4469 {"blectrl-",XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4470 {"bngctrl", XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4471 {"bngctrl-",XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4472 {"bnectr",  XLOCB(19,BOF,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4473 {"bnectr-", XLOCB(19,BOF,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4474 {"bnectrl", XLOCB(19,BOF,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4475 {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4476 {"bnsctr",  XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4477 {"bnsctr-", XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4478 {"bnuctr",  XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4479 {"bnuctr-", XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4480 {"bnsctrl", XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4481 {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4482 {"bnuctrl", XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4483 {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4484 {"bgectr+", XLOCB(19,BOFP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4485 {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4486 {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4487 {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4488 {"blectr+", XLOCB(19,BOFP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4489 {"bngctr+", XLOCB(19,BOFP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4490 {"blectrl+",XLOCB(19,BOFP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4491 {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4492 {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4493 {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4494 {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4495 {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4496 {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4497 {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4498 {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4499 {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4500 {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4501 {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4502 {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4503 {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4504 {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4505 {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4506 {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4507 {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4508 {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4509 {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4510 {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4511 {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4512 {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4513 {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4514 {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4515 {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4516 {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4517 {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4518 {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4519 {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4520 {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4521 {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4522 {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4523 {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4524 {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4525 {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4526 {"bltctr",  XLOCB(19,BOT,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4527 {"bltctr-", XLOCB(19,BOT,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4528 {"bltctrl", XLOCB(19,BOT,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4529 {"bltctrl-",XLOCB(19,BOT,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4530 {"bgtctr",  XLOCB(19,BOT,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4531 {"bgtctr-", XLOCB(19,BOT,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4532 {"bgtctrl", XLOCB(19,BOT,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4533 {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4534 {"beqctr",  XLOCB(19,BOT,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4535 {"beqctr-", XLOCB(19,BOT,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4536 {"beqctrl", XLOCB(19,BOT,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4537 {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4538 {"bsoctr",  XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4539 {"bsoctr-", XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4540 {"bunctr",  XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4541 {"bunctr-", XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4542 {"bsoctrl", XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4543 {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4544 {"bunctrl", XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4545 {"bunctrl-",XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4546 {"bltctr+", XLOCB(19,BOTP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4547 {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4548 {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4549 {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4550 {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4551 {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4552 {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4553 {"bunctr+", XLOCB(19,BOTP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4554 {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4555 {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4556 {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4557 {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4558 {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4559 {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4560 {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4561 {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4562 {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4563 {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4564 {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4565 {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4566 {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4567 {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4568 {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4569 {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4570 {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4571 {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4572 {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4573 {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4574 {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4575 {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4576
4577 {"bfctr",   XLO(19,BOF,528,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4578 {"bfctr-",  XLO(19,BOF,528,0),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4579 {"bfctrl",  XLO(19,BOF,528,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4580 {"bfctrl-", XLO(19,BOF,528,1),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4581 {"bfctr+",  XLO(19,BOFP,528,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4582 {"bfctrl+", XLO(19,BOFP,528,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4583 {"bfctr-",  XLO(19,BOFM4,528,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4584 {"bfctrl-", XLO(19,BOFM4,528,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4585 {"bfctr+",  XLO(19,BOFP4,528,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4586 {"bfctrl+", XLO(19,BOFP4,528,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4587 {"btctr",   XLO(19,BOT,528,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4588 {"btctr-",  XLO(19,BOT,528,0),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4589 {"btctrl",  XLO(19,BOT,528,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4590 {"btctrl-", XLO(19,BOT,528,1),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4591 {"btctr+",  XLO(19,BOTP,528,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4592 {"btctrl+", XLO(19,BOTP,528,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4593 {"btctr-",  XLO(19,BOTM4,528,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4594 {"btctrl-", XLO(19,BOTM4,528,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4595 {"btctr+",  XLO(19,BOTP4,528,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4596 {"btctrl+", XLO(19,BOTP4,528,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4597
4598 {"bcctr-",  XLYLK(19,528,0,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4599 {"bcctrl-", XLYLK(19,528,0,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4600 {"bcctr+",  XLYLK(19,528,1,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4601 {"bcctrl+", XLYLK(19,528,1,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4602 {"bcctr",   XLLK(19,528,0),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
4603 {"bcc",     XLLK(19,528,0),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
4604 {"bcctrl",  XLLK(19,528,1),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
4605 {"bccl",    XLLK(19,528,1),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
4606
4607 {"bctar-",  XLYLK(19,560,0,0),          XLYBB_MASK,    POWER8,   PPCNONE,       {BOE, BI}},
4608 {"bctarl-", XLYLK(19,560,0,1),          XLYBB_MASK,    POWER8,   PPCNONE,       {BOE, BI}},
4609 {"bctar+",  XLYLK(19,560,1,0),          XLYBB_MASK,    POWER8,   PPCNONE,       {BOE, BI}},
4610 {"bctarl+", XLYLK(19,560,1,1),          XLYBB_MASK,    POWER8,   PPCNONE,       {BOE, BI}},
4611 {"bctar",   XLLK(19,560,0),             XLBH_MASK,     POWER8,   PPCNONE,       {BO, BI, BH}},
4612 {"bctarl",  XLLK(19,560,1),             XLBH_MASK,     POWER8,   PPCNONE,       {BO, BI, BH}},
4613
4614 {"rlwimi",      M(20,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4615 {"rlimi",       M(20,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4616
4617 {"rlwimi.",     M(20,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4618 {"rlimi.",      M(20,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4619
4620 {"rotlwi",      MME(21,31,0),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, SH}},
4621 {"clrlwi",      MME(21,31,0),   MSHME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, MB}},
4622 {"rlwinm",      M(21,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4623 {"rlinm",       M(21,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4624 {"rotlwi.",     MME(21,31,1),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, SH}},
4625 {"clrlwi.",     MME(21,31,1),   MSHME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, MB}},
4626 {"rlwinm.",     M(21,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4627 {"rlinm.",      M(21,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4628
4629 {"rlmi",        M(22,0),        M_MASK,      M601,      PPCNONE,        {RA, RS, RB, MBE, ME}},
4630 {"rlmi.",       M(22,1),        M_MASK,      M601,      PPCNONE,        {RA, RS, RB, MBE, ME}},
4631
4632 {"rotlw",       MME(23,31,0),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, RB}},
4633 {"rlwnm",       M(23,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
4634 {"rlnm",        M(23,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
4635 {"rotlw.",      MME(23,31,1),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, RB}},
4636 {"rlwnm.",      M(23,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
4637 {"rlnm.",       M(23,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
4638
4639 {"nop",         OP(24),         0xffffffff,  PPCCOM,    PPCNONE,        {0}},
4640 {"ori",         OP(24),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4641 {"oril",        OP(24),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4642
4643 {"oris",        OP(25),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4644 {"oriu",        OP(25),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4645
4646 {"xnop",        OP(26),         0xffffffff,  PPCCOM,    PPCNONE,        {0}},
4647 {"xori",        OP(26),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4648 {"xoril",       OP(26),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4649
4650 {"xoris",       OP(27),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4651 {"xoriu",       OP(27),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4652
4653 {"andi.",       OP(28),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4654 {"andil.",      OP(28),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4655
4656 {"andis.",      OP(29),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4657 {"andiu.",      OP(29),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4658
4659 {"rotldi",      MD(30,0,0),     MDMB_MASK,   PPC64,     PPCNONE,        {RA, RS, SH6}},
4660 {"clrldi",      MD(30,0,0),     MDSH_MASK,   PPC64,     PPCNONE,        {RA, RS, MB6}},
4661 {"rldicl",      MD(30,0,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4662 {"rotldi.",     MD(30,0,1),     MDMB_MASK,   PPC64,     PPCNONE,        {RA, RS, SH6}},
4663 {"clrldi.",     MD(30,0,1),     MDSH_MASK,   PPC64,     PPCNONE,        {RA, RS, MB6}},
4664 {"rldicl.",     MD(30,0,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4665
4666 {"rldicr",      MD(30,1,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, ME6}},
4667 {"rldicr.",     MD(30,1,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, ME6}},
4668
4669 {"rldic",       MD(30,2,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4670 {"rldic.",      MD(30,2,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4671
4672 {"rldimi",      MD(30,3,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4673 {"rldimi.",     MD(30,3,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4674
4675 {"rotld",       MDS(30,8,0),    MDSMB_MASK,  PPC64,     PPCNONE,        {RA, RS, RB}},
4676 {"rldcl",       MDS(30,8,0),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, MB6}},
4677 {"rotld.",      MDS(30,8,1),    MDSMB_MASK,  PPC64,     PPCNONE,        {RA, RS, RB}},
4678 {"rldcl.",      MDS(30,8,1),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, MB6}},
4679
4680 {"rldcr",       MDS(30,9,0),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, ME6}},
4681 {"rldcr.",      MDS(30,9,1),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, ME6}},
4682
4683 {"cmpw",        XOPL(31,0,0),   XCMPL_MASK,  PPCCOM,    PPCNONE,        {OBF, RA, RB}},
4684 {"cmpd",        XOPL(31,0,1),   XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
4685 {"cmp",         X(31,0),        XCMP_MASK,   PPC|PPCVLE, PPCNONE,       {BF, L, RA, RB}},
4686 {"cmp",         X(31,0),        XCMPL_MASK,  PWRCOM,    PPC,            {BF, RA, RB}},
4687
4688 {"twlgt",       XTO(31,4,TOLGT), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4689 {"tlgt",        XTO(31,4,TOLGT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4690 {"twllt",       XTO(31,4,TOLLT), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4691 {"tllt",        XTO(31,4,TOLLT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4692 {"tweq",        XTO(31,4,TOEQ),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4693 {"teq",         XTO(31,4,TOEQ),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4694 {"twlge",       XTO(31,4,TOLGE), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4695 {"tlge",        XTO(31,4,TOLGE), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4696 {"twlnl",       XTO(31,4,TOLNL), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4697 {"tlnl",        XTO(31,4,TOLNL), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4698 {"twlle",       XTO(31,4,TOLLE), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4699 {"tlle",        XTO(31,4,TOLLE), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4700 {"twlng",       XTO(31,4,TOLNG), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4701 {"tlng",        XTO(31,4,TOLNG), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4702 {"twgt",        XTO(31,4,TOGT),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4703 {"tgt",         XTO(31,4,TOGT),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4704 {"twge",        XTO(31,4,TOGE),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4705 {"tge",         XTO(31,4,TOGE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4706 {"twnl",        XTO(31,4,TONL),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4707 {"tnl",         XTO(31,4,TONL),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4708 {"twlt",        XTO(31,4,TOLT),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4709 {"tlt",         XTO(31,4,TOLT),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4710 {"twle",        XTO(31,4,TOLE),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4711 {"tle",         XTO(31,4,TOLE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4712 {"twng",        XTO(31,4,TONG),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4713 {"tng",         XTO(31,4,TONG),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4714 {"twne",        XTO(31,4,TONE),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4715 {"tne",         XTO(31,4,TONE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4716 {"trap",        XTO(31,4,TOU),   0xffffffff, PPCCOM|PPCVLE, PPCNONE,    {0}},
4717 {"twu",         XTO(31,4,TOU),   XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4718 {"tu",          XTO(31,4,TOU),   XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4719 {"tw",          X(31,4),         X_MASK, PPCCOM|PPCVLE, PPCNONE,        {TO, RA, RB}},
4720 {"t",           X(31,4),         X_MASK,     PWRCOM,    PPCNONE,        {TO, RA, RB}},
4721
4722 {"lvsl",        X(31,6),        X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4723 {"lvebx",       X(31,7),        X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4724 {"lbfcmx",      APU(31,7,0),    APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4725
4726 {"subfc",       XO(31,8,0,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4727 {"sf",          XO(31,8,0,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4728 {"subc",        XO(31,8,0,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
4729 {"subfc.",      XO(31,8,0,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4730 {"sf.",         XO(31,8,0,1),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4731 {"subc.",       XO(31,8,0,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
4732
4733 {"mulhdu",      XO(31,9,0,0),   XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4734 {"mulhdu.",     XO(31,9,0,1),   XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4735
4736 {"addc",        XO(31,10,0,0),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4737 {"a",           XO(31,10,0,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4738 {"addc.",       XO(31,10,0,1),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4739 {"a.",          XO(31,10,0,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4740
4741 {"mulhwu",      XO(31,11,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4742 {"mulhwu.",     XO(31,11,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4743
4744 {"lxsiwzx",     X(31,12),       XX1_MASK,    PPCVSX2,   PPCNONE,        {XT6, RA0, RB}},
4745
4746 {"isellt",      X(31,15),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA0, RB}},
4747
4748 {"tlbilxlpid",  XTO(31,18,0),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
4749 {"tlbilxpid",   XTO(31,18,1),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
4750 {"tlbilxva",    XTO(31,18,3),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {RA0, RB}},
4751 {"tlbilx",      X(31,18),       X_MASK,   E500MC|PPCA2, PPCNONE,        {T, RA0, RB}},
4752
4753 {"mfcr",        XFXM(31,19,0,0), XFXFXM_MASK, COM|PPCVLE, PPCNONE,      {RT, FXM4}},
4754 {"mfocrf",      XFXM(31,19,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE,      {RT, FXM}},
4755
4756 {"lwarx",       X(31,20),       XEH_MASK,    PPC|PPCVLE, PPCNONE,       {RT, RA0, RB, EH}},
4757
4758 {"ldx",         X(31,21),       X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RA0, RB}},
4759
4760 {"icbt",        X(31,22),       X_MASK,      BOOKE|PPCE300|PPCA2|PPC476|PPCVLE, PPCNONE, {CT, RA0, RB}},
4761
4762 {"lwzx",        X(31,23),       X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RT, RA0, RB}},
4763 {"lx",          X(31,23),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4764
4765 {"slw",         XRC(31,24,0),   X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RA, RS, RB}},
4766 {"sl",          XRC(31,24,0),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4767 {"slw.",        XRC(31,24,1),   X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RA, RS, RB}},
4768 {"sl.",         XRC(31,24,1),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4769
4770 {"cntlzw",      XRC(31,26,0),   XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
4771 {"cntlz",       XRC(31,26,0),   XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
4772 {"cntlzw.",     XRC(31,26,1),   XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
4773 {"cntlz.",      XRC(31,26,1),   XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
4774
4775 {"sld",         XRC(31,27,0),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4776 {"sld.",        XRC(31,27,1),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4777
4778 {"and",         XRC(31,28,0),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4779 {"and.",        XRC(31,28,1),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4780
4781 {"maskg",       XRC(31,29,0),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
4782 {"maskg.",      XRC(31,29,1),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
4783
4784 {"ldepx",       X(31,29),       X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4785
4786 {"waitasec",    X(31,30),       XRTRARB_MASK,POWER8,    POWER9,         {0}},
4787 {"wait",        X(31,30),       XWC_MASK,    POWER9,    PPCNONE,        {WC}},
4788
4789 {"lwepx",       X(31,31),       X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4790
4791 {"cmplw",       XOPL(31,32,0),  XCMPL_MASK,  PPCCOM|PPCVLE, PPCNONE,    {OBF, RA, RB}},
4792 {"cmpld",       XOPL(31,32,1),  XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
4793 {"cmpl",        X(31,32),       XCMP_MASK,   PPC|PPCVLE, PPCNONE,       {BF, L, RA, RB}},
4794 {"cmpl",        X(31,32),       XCMPL_MASK,  PWRCOM,    PPC,            {BF, RA, RB}},
4795
4796 {"lvsr",        X(31,38),       X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4797 {"lvehx",       X(31,39),       X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4798 {"lhfcmx",      APU(31,39,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4799
4800 {"mviwsplt",    X(31,46),       X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA, RB}},
4801
4802 {"iselgt",      X(31,47),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA0, RB}},
4803
4804 {"lvewx",       X(31,71),       X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4805
4806 {"addg6s",      XO(31,74,0,0),  XO_MASK,     POWER6,    PPCNONE,        {RT, RA, RB}},
4807
4808 {"lxsiwax",     X(31,76),       XX1_MASK,    PPCVSX2,   PPCNONE,        {XT6, RA0, RB}},
4809
4810 {"iseleq",      X(31,79),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA0, RB}},
4811
4812 {"isel",        XISEL(31,15), XISEL_MASK, PPCISEL|TITAN|PPCVLE, PPCNONE, {RT, RA0, RB, CRB}},
4813
4814 {"subf",        XO(31,40,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4815 {"sub",         XO(31,40,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RB, RA}},
4816 {"subf.",       XO(31,40,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4817 {"sub.",        XO(31,40,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RB, RA}},
4818
4819 {"mfvsrd",      X(31,51),       XX1RB_MASK,   PPCVSX2,  PPCNONE,        {RA, XS6}},
4820 {"mffprd",      X(31,51),       XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {RA, FRS}},
4821 {"mfvrd",       X(31,51)|1,     XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {RA, VS}},
4822 {"eratilx",     X(31,51),       X_MASK,      PPCA2,     PPCNONE,        {ERAT_T, RA, RB}},
4823
4824 {"lbarx",       X(31,52),       XEH_MASK,    POWER8|PPCVLE, PPCNONE,    {RT, RA0, RB, EH}},
4825
4826 {"ldux",        X(31,53),       X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RAL, RB}},
4827
4828 {"dcbst",       X(31,54),       XRT_MASK,    PPC|PPCVLE, PPCNONE,       {RA0, RB}},
4829
4830 {"lwzux",       X(31,55),       X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RT, RAL, RB}},
4831 {"lux",         X(31,55),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4832
4833 {"cntlzd",      XRC(31,58,0),   XRB_MASK,    PPC64|PPCVLE, PPCNONE,     {RA, RS}},
4834 {"cntlzd.",     XRC(31,58,1),   XRB_MASK,    PPC64|PPCVLE, PPCNONE,     {RA, RS}},
4835
4836 {"andc",        XRC(31,60,0),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4837 {"andc.",       XRC(31,60,1),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4838
4839 {"waitrsv",     X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, PPCNONE,    {0}},
4840 {"waitimpl",    X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, PPCNONE,    {0}},
4841 {"wait",        X(31,62),       XWC_MASK,    E500MC|PPCA2|PPCVLE, PPCNONE, {WC}},
4842
4843 {"dcbstep",     XRT(31,63,0),   XRT_MASK,    E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
4844
4845 {"tdlgt",       XTO(31,68,TOLGT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4846 {"tdllt",       XTO(31,68,TOLLT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4847 {"tdeq",        XTO(31,68,TOEQ),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4848 {"tdlge",       XTO(31,68,TOLGE), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4849 {"tdlnl",       XTO(31,68,TOLNL), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4850 {"tdlle",       XTO(31,68,TOLLE), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4851 {"tdlng",       XTO(31,68,TOLNG), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4852 {"tdgt",        XTO(31,68,TOGT),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4853 {"tdge",        XTO(31,68,TOGE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4854 {"tdnl",        XTO(31,68,TONL),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4855 {"tdlt",        XTO(31,68,TOLT),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4856 {"tdle",        XTO(31,68,TOLE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4857 {"tdng",        XTO(31,68,TONG),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4858 {"tdne",        XTO(31,68,TONE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4859 {"tdu",         XTO(31,68,TOU),   XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4860 {"td",          X(31,68),       X_MASK,      PPC64|PPCVLE, PPCNONE,     {TO, RA, RB}},
4861
4862 {"lwfcmx",      APU(31,71,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4863 {"mulhd",       XO(31,73,0,0),  XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4864 {"mulhd.",      XO(31,73,0,1),  XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4865
4866 {"mulhw",       XO(31,75,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4867 {"mulhw.",      XO(31,75,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4868
4869 {"dlmzb",       XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN|PPCVLE, PPCNONE, {RA, RS, RB}},
4870 {"dlmzb.",      XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN|PPCVLE, PPCNONE, {RA, RS, RB}},
4871
4872 {"mtsrd",       X(31,82),  XRB_MASK|(1<<20), PPC64,     PPCNONE,        {SR, RS}},
4873
4874 {"mfmsr",       X(31,83),       XRARB_MASK,  COM|PPCVLE, PPCNONE,       {RT}},
4875
4876 {"ldarx",       X(31,84),       XEH_MASK,    PPC64|PPCVLE, PPCNONE,     {RT, RA0, RB, EH}},
4877
4878 {"dcbfl",       XOPL(31,86,1),  XRT_MASK,    POWER5,    PPC476,         {RA0, RB}},
4879 {"dcbf",        X(31,86),       XLRT_MASK,   PPC|PPCVLE, PPCNONE,       {RA0, RB, L}},
4880
4881 {"lbzx",        X(31,87),       X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
4882
4883 {"lbepx",       X(31,95),       X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4884
4885 {"dni",         XRC(31,97,1),   XRB_MASK,    E6500,     PPCNONE,        {DUI, DCTL}},
4886
4887 {"lvx",         X(31,103),      X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4888 {"lqfcmx",      APU(31,103,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4889
4890 {"neg",         XO(31,104,0,0), XORB_MASK,   COM|PPCVLE, PPCNONE,       {RT, RA}},
4891 {"neg.",        XO(31,104,0,1), XORB_MASK,   COM|PPCVLE, PPCNONE,       {RT, RA}},
4892
4893 {"mul",         XO(31,107,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4894 {"mul.",        XO(31,107,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4895
4896 {"mvidsplt",    X(31,110),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA, RB}},
4897
4898 {"mtsrdin",     X(31,114),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
4899
4900 {"mffprwz",     X(31,115),      XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {RA, FRS}},
4901 {"mfvrwz",      X(31,115)|1,    XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {RA, VS}},
4902 {"mfvsrwz",     X(31,115),      XX1RB_MASK,   PPCVSX2,  PPCNONE,        {RA, XS6}},
4903
4904 {"lharx",       X(31,116),      XEH_MASK,    POWER8|PPCVLE, PPCNONE,    {RT, RA0, RB, EH}},
4905
4906 {"clf",         X(31,118),      XTO_MASK,    POWER,     PPCNONE,        {RA, RB}},
4907
4908 {"lbzux",       X(31,119),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RAL, RB}},
4909
4910 {"popcntb",     X(31,122),      XRB_MASK,    POWER5|PPCVLE, PPCNONE,    {RA, RS}},
4911
4912 {"not",         XRC(31,124,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
4913 {"nor",         XRC(31,124,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4914 {"not.",        XRC(31,124,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
4915 {"nor.",        XRC(31,124,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4916
4917 {"dcbfep",      XRT(31,127,0),  XRT_MASK,    E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
4918
4919 {"setb",        X(31,128),      XRB_MASK|(3<<16), POWER9, PPCNONE,      {RT, BFA}},
4920
4921 {"wrtee",       X(31,131),      XRARB_MASK,  PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RS}},
4922
4923 {"dcbtstls",    X(31,134),      X_MASK,      PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
4924
4925 {"stvebx",      X(31,135),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA0, RB}},
4926 {"stbfcmx",     APU(31,135,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4927
4928 {"subfe",       XO(31,136,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4929 {"sfe",         XO(31,136,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4930 {"subfe.",      XO(31,136,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4931 {"sfe.",        XO(31,136,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4932
4933 {"adde",        XO(31,138,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4934 {"ae",          XO(31,138,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4935 {"adde.",       XO(31,138,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4936 {"ae.",         XO(31,138,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4937
4938 {"stxsiwx",     X(31,140),      XX1_MASK,    PPCVSX2,   PPCNONE,        {XS6, RA0, RB}},
4939
4940 {"msgsndp",     XRTRA(31,142,0,0), XRTRA_MASK, POWER8,  PPCNONE,        {RB}},
4941 {"dcbtstlse",   X(31,142),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA0, RB}},
4942
4943 {"mtcr",        XFXM(31,144,0xff,0), XRARB_MASK, COM,   PPCNONE,        {RS}},
4944 {"mtcrf",       XFXM(31,144,0,0), XFXFXM_MASK, COM|PPCVLE, PPCNONE,     {FXM, RS}},
4945 {"mtocrf",      XFXM(31,144,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE,     {FXM, RS}},
4946
4947 {"mtmsr",       X(31,146),      XRLARB_MASK, COM|PPCVLE, PPCNONE,       {RS, A_L}},
4948
4949 {"mtsle",       X(31,147),    XRTLRARB_MASK, POWER8,    PPCNONE,        {L}},
4950
4951 {"eratsx",      XRC(31,147,0),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
4952 {"eratsx.",     XRC(31,147,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
4953
4954 {"stdx",        X(31,149),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RS, RA0, RB}},
4955
4956 {"stwcx.",      XRC(31,150,1),  X_MASK,      PPC|PPCVLE, PPCNONE,       {RS, RA0, RB}},
4957
4958 {"stwx",        X(31,151),      X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RS, RA0, RB}},
4959 {"stx",         X(31,151),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA, RB}},
4960
4961 {"slq",         XRC(31,152,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4962 {"slq.",        XRC(31,152,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4963
4964 {"sle",         XRC(31,153,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4965 {"sle.",        XRC(31,153,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4966
4967 {"prtyw",       X(31,154),      XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}},
4968
4969 {"stdepx",      X(31,157),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
4970
4971 {"stwepx",      X(31,159),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
4972
4973 {"wrteei",      X(31,163),      XE_MASK,     PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {E}},
4974
4975 {"dcbtls",      X(31,166),      X_MASK,      PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
4976
4977 {"stvehx",      X(31,167),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA0, RB}},
4978 {"sthfcmx",     APU(31,167,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4979
4980 {"msgclrp",     XRTRA(31,174,0,0), XRTRA_MASK, POWER8,  PPCNONE,        {RB}},
4981 {"dcbtlse",     X(31,174),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA0, RB}},
4982
4983 {"mtmsrd",      X(31,178),      XRLARB_MASK, PPC64,     PPCNONE,        {RS, A_L}},
4984
4985 {"mtvsrd",      X(31,179),      XX1RB_MASK,   PPCVSX2,  PPCNONE,        {XT6, RA}},
4986 {"mtfprd",      X(31,179),      XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {FRT, RA}},
4987 {"mtvrd",       X(31,179)|1,    XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {VD, RA}},
4988 {"eratre",      X(31,179),      X_MASK,      PPCA2,     PPCNONE,        {RT, RA, WS}},
4989
4990 {"stdux",       X(31,181),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RS, RAS, RB}},
4991
4992 {"stqcx.",      XRC(31,182,1),  X_MASK,      POWER8,    PPCNONE,        {RSQ, RA0, RB}},
4993 {"wchkall",     X(31,182),      X_MASK,      PPCA2,     PPCNONE,        {OBF}},
4994
4995 {"stwux",       X(31,183),      X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RS, RAS, RB}},
4996 {"stux",        X(31,183),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
4997
4998 {"sliq",        XRC(31,184,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4999 {"sliq.",       XRC(31,184,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5000
5001 {"prtyd",       X(31,186),      XRB_MASK, POWER6|PPCA2, PPCNONE,        {RA, RS}},
5002
5003 {"cmprb",       X(31,192),      XCMP_MASK,   POWER9,    PPCNONE,        {BF, L, RA, RB}},
5004
5005 {"icblq.",      XRC(31,198,1),  X_MASK,      E6500,     PPCNONE,        {CT, RA0, RB}},
5006
5007 {"stvewx",      X(31,199),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA0, RB}},
5008 {"stwfcmx",     APU(31,199,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5009
5010 {"subfze",      XO(31,200,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
5011 {"sfze",        XO(31,200,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5012 {"subfze.",     XO(31,200,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
5013 {"sfze.",       XO(31,200,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5014
5015 {"addze",       XO(31,202,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
5016 {"aze",         XO(31,202,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5017 {"addze.",      XO(31,202,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
5018 {"aze.",        XO(31,202,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5019
5020 {"msgsnd",      XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}},
5021
5022 {"mtsr",        X(31,210), XRB_MASK|(1<<20), COM,       NON32,          {SR, RS}},
5023
5024 {"mtfprwa",     X(31,211),      XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {FRT, RA}},
5025 {"mtvrwa",      X(31,211)|1,    XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {VD, RA}},
5026 {"mtvsrwa",     X(31,211),      XX1RB_MASK,   PPCVSX2,  PPCNONE,        {XT6, RA}},
5027 {"eratwe",      X(31,211),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA, WS}},
5028
5029 {"ldawx.",      XRC(31,212,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
5030
5031 {"stdcx.",      XRC(31,214,1),  X_MASK,      PPC64|PPCVLE, PPCNONE,     {RS, RA0, RB}},
5032
5033 {"stbx",        X(31,215),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RA0, RB}},
5034
5035 {"sllq",        XRC(31,216,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5036 {"sllq.",       XRC(31,216,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5037
5038 {"sleq",        XRC(31,217,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5039 {"sleq.",       XRC(31,217,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5040
5041 {"stbepx",      X(31,223),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
5042
5043 {"cmpeqb",      X(31,224),      XCMPL_MASK,   POWER9,   PPCNONE,        {BF, RA, RB}},
5044
5045 {"icblc",       X(31,230),      X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
5046
5047 {"stvx",        X(31,231),      X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VS, RA0, RB}},
5048 {"stqfcmx",     APU(31,231,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5049
5050 {"subfme",      XO(31,232,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
5051 {"sfme",        XO(31,232,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5052 {"subfme.",     XO(31,232,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
5053 {"sfme.",       XO(31,232,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5054
5055 {"mulld",       XO(31,233,0,0), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
5056 {"mulld.",      XO(31,233,0,1), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
5057
5058 {"addme",       XO(31,234,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
5059 {"ame",         XO(31,234,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5060 {"addme.",      XO(31,234,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
5061 {"ame.",        XO(31,234,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5062
5063 {"mullw",       XO(31,235,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5064 {"muls",        XO(31,235,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5065 {"mullw.",      XO(31,235,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5066 {"muls.",       XO(31,235,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5067
5068 {"icblce",      X(31,238),      X_MASK,      PPCCHLK,   E500MC|PPCA2,   {CT, RA, RB}},
5069 {"msgclr",      XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}},
5070 {"mtsrin",      X(31,242),      XRA_MASK,    PPC,       NON32,          {RS, RB}},
5071 {"mtsri",       X(31,242),      XRA_MASK,    POWER,     NON32,          {RS, RB}},
5072
5073 {"mtfprwz",     X(31,243),      XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {FRT, RA}},
5074 {"mtvrwz",      X(31,243)|1,    XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {VD, RA}},
5075 {"mtvsrwz",     X(31,243),      XX1RB_MASK,   PPCVSX2,  PPCNONE,        {XT6, RA}},
5076
5077 {"dcbtstt",     XRT(31,246,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA0, RB}},
5078 {"dcbtst",      X(31,246),      X_MASK,      POWER4,    DCBT_EO,        {RA0, RB, CT}},
5079 {"dcbtst",      X(31,246),      X_MASK,      DCBT_EO,   PPCNONE,        {CT, RA0, RB}},
5080 {"dcbtst",      X(31,246),      X_MASK,      PPC,       POWER4|DCBT_EO, {RA0, RB}},
5081
5082 {"stbux",       X(31,247),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RAS, RB}},
5083
5084 {"slliq",       XRC(31,248,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5085 {"slliq.",      XRC(31,248,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5086
5087 {"bpermd",      X(31,252),      X_MASK,   POWER7|PPCA2, PPCNONE,        {RA, RS, RB}},
5088
5089 {"dcbtstep",    XRT(31,255,0),  X_MASK,   E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
5090
5091 {"mfdcrx",      X(31,259),      X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RS, RA}},
5092 {"mfdcrx.",     XRC(31,259,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA}},
5093
5094 {"lvexbx",      X(31,261),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5095
5096 {"icbt",        X(31,262),      XRT_MASK,    PPC403,    PPCNONE,        {RA, RB}},
5097
5098 {"lvepxl",      X(31,263),      X_MASK,      PPCVEC2|PPCVLE, PPCNONE,   {VD, RA0, RB}},
5099
5100 {"ldfcmx",      APU(31,263,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5101 {"doz",         XO(31,264,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5102 {"doz.",        XO(31,264,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5103
5104 {"modud",       X(31,265),      X_MASK,      POWER9,    PPCNONE,        {RT, RA, RB}},
5105
5106 {"add",         XO(31,266,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5107 {"cax",         XO(31,266,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5108 {"add.",        XO(31,266,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5109 {"cax.",        XO(31,266,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5110
5111 {"moduw",       X(31,267),      X_MASK,      POWER9,    PPCNONE,        {RT, RA, RB}},
5112
5113 {"lxvx",        X(31,268),      XX1_MASK|1<<6, PPCVSX3, PPCNONE,        {XT6, RA0, RB}},
5114 {"lxvl",        X(31,269),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XT6, RA0, RB}},
5115
5116 {"ehpriv",      X(31,270),      0xffffffff, E500MC|PPCA2|PPCVLE, PPCNONE, {0}},
5117
5118 {"tlbiel",      X(31,274),      X_MASK|1<<20,POWER9,    PPC476,         {RB, RSO, RIC, PRS, X_R}},
5119 {"tlbiel",      X(31,274),      XRTLRA_MASK, POWER4,    POWER9|PPC476,  {RB, L}},
5120
5121 {"mfapidi",     X(31,275),      X_MASK,      BOOKE,     E500|TITAN,     {RT, RA}},
5122
5123 {"lqarx",       X(31,276),      XEH_MASK,    POWER8,    PPCNONE,        {RTQ, RAX, RBX, EH}},
5124
5125 {"lscbx",       XRC(31,277,0),  X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
5126 {"lscbx.",      XRC(31,277,1),  X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
5127
5128 {"dcbtt",       XRT(31,278,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA0, RB}},
5129 {"dcbt",        X(31,278),      X_MASK,      POWER4,    DCBT_EO,        {RA0, RB, CT}},
5130 {"dcbt",        X(31,278),      X_MASK,      DCBT_EO,   PPCNONE,        {CT, RA0, RB}},
5131 {"dcbt",        X(31,278),      X_MASK,      PPC,       POWER4|DCBT_EO, {RA0, RB}},
5132
5133 {"lhzx",        X(31,279),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
5134
5135 {"cdtbcd",      X(31,282),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
5136
5137 {"eqv",         XRC(31,284,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5138 {"eqv.",        XRC(31,284,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5139
5140 {"lhepx",       X(31,287),      X_MASK,   E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
5141
5142 {"mfdcrux",     X(31,291),      X_MASK,      PPC464|PPCVLE, PPCNONE,    {RS, RA}},
5143
5144 {"lvexhx",      X(31,293),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5145 {"lvepx",       X(31,295),      X_MASK,      PPCVEC2|PPCVLE, PPCNONE,   {VD, RA0, RB}},
5146
5147 {"lxvll",       X(31,301),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XT6, RA0, RB}},
5148
5149 {"mfbhrbe",     X(31,302),      X_MASK,      POWER8,    PPCNONE,        {RT, BHRBE}},
5150
5151 {"tlbie",       X(31,306),      X_MASK|1<<20,POWER9,    TITAN,          {RB, RS, RIC, PRS, X_R}},
5152 {"tlbie",       X(31,306),      XRA_MASK,    POWER7,    POWER9|TITAN,   {RB, RS}},
5153 {"tlbie",       X(31,306),      XRTLRA_MASK, PPC,       E500|POWER7|TITAN,      {RB, L}},
5154 {"tlbi",        X(31,306),      XRT_MASK,    POWER,     PPCNONE,        {RA0, RB}},
5155
5156 {"mfvsrld",     X(31,307),      XX1RB_MASK,  PPCVSX3,   PPCNONE,        {RA, XS6}},
5157
5158 {"ldmx",        X(31,309),      X_MASK,      POWER9,    PPCNONE,        {RT, RA0, RB}},
5159
5160 {"eciwx",       X(31,310),      X_MASK,      PPC,       E500|TITAN,     {RT, RA0, RB}},
5161
5162 {"lhzux",       X(31,311),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RAL, RB}},
5163
5164 {"cbcdtd",      X(31,314),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
5165
5166 {"xor",         XRC(31,316,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5167 {"xor.",        XRC(31,316,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5168
5169 {"dcbtep",      XRT(31,319,0),  X_MASK,   E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
5170
5171 {"mfexisr",     XSPR(31,323, 64), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5172 {"mfexier",     XSPR(31,323, 66), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5173 {"mfbr0",       XSPR(31,323,128), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5174 {"mfbr1",       XSPR(31,323,129), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5175 {"mfbr2",       XSPR(31,323,130), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5176 {"mfbr3",       XSPR(31,323,131), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5177 {"mfbr4",       XSPR(31,323,132), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5178 {"mfbr5",       XSPR(31,323,133), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5179 {"mfbr6",       XSPR(31,323,134), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5180 {"mfbr7",       XSPR(31,323,135), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5181 {"mfbear",      XSPR(31,323,144), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5182 {"mfbesr",      XSPR(31,323,145), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5183 {"mfiocr",      XSPR(31,323,160), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5184 {"mfdmacr0",    XSPR(31,323,192), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5185 {"mfdmact0",    XSPR(31,323,193), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5186 {"mfdmada0",    XSPR(31,323,194), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5187 {"mfdmasa0",    XSPR(31,323,195), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5188 {"mfdmacc0",    XSPR(31,323,196), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5189 {"mfdmacr1",    XSPR(31,323,200), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5190 {"mfdmact1",    XSPR(31,323,201), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5191 {"mfdmada1",    XSPR(31,323,202), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5192 {"mfdmasa1",    XSPR(31,323,203), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5193 {"mfdmacc1",    XSPR(31,323,204), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5194 {"mfdmacr2",    XSPR(31,323,208), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5195 {"mfdmact2",    XSPR(31,323,209), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5196 {"mfdmada2",    XSPR(31,323,210), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5197 {"mfdmasa2",    XSPR(31,323,211), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5198 {"mfdmacc2",    XSPR(31,323,212), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5199 {"mfdmacr3",    XSPR(31,323,216), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5200 {"mfdmact3",    XSPR(31,323,217), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5201 {"mfdmada3",    XSPR(31,323,218), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5202 {"mfdmasa3",    XSPR(31,323,219), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5203 {"mfdmacc3",    XSPR(31,323,220), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5204 {"mfdmasr",     XSPR(31,323,224), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5205 {"mfdcr",       X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, E500|TITAN, {RT, SPR}},
5206 {"mfdcr.",      XRC(31,323,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, SPR}},
5207
5208 {"lvexwx",      X(31,325),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5209
5210 {"dcread",      X(31,326),      X_MASK,  PPC476|TITAN,  PPCNONE,        {RT, RA0, RB}},
5211
5212 {"div",         XO(31,331,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5213 {"div.",        XO(31,331,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5214
5215 {"lxvdsx",      X(31,332),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
5216
5217 {"mfpmr",       X(31,334),      X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {RT, PMR}},
5218 {"mftmr",       X(31,366),      X_MASK, PPCTMR|E6500,   PPCNONE,        {RT, TMR}},
5219
5220 {"slbsync",     X(31,338),      0xffffffff,  POWER9,    PPCNONE,        {0}},
5221
5222 {"mfmq",        XSPR(31,339,  0), XSPR_MASK, M601,      PPCNONE,        {RT}},
5223 {"mfxer",       XSPR(31,339,  1), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RT}},
5224 {"mfrtcu",      XSPR(31,339,  4), XSPR_MASK, COM,       TITAN,          {RT}},
5225 {"mfrtcl",      XSPR(31,339,  5), XSPR_MASK, COM,       TITAN,          {RT}},
5226 {"mfdec",       XSPR(31,339,  6), XSPR_MASK, MFDEC1,    PPCNONE,        {RT}},
5227 {"mflr",        XSPR(31,339,  8), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RT}},
5228 {"mfctr",       XSPR(31,339,  9), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RT}},
5229 {"mfdscr",      XSPR(31,339, 17), XSPR_MASK, POWER6,    PPCNONE,        {RT}},
5230 {"mftid",       XSPR(31,339, 17), XSPR_MASK, POWER,     PPCNONE,        {RT}},
5231 {"mfdsisr",     XSPR(31,339, 18), XSPR_MASK, COM,       TITAN,          {RT}},
5232 {"mfdar",       XSPR(31,339, 19), XSPR_MASK, COM,       TITAN,          {RT}},
5233 {"mfdec",       XSPR(31,339, 22), XSPR_MASK, MFDEC2,    MFDEC1,         {RT}},
5234 {"mfsdr0",      XSPR(31,339, 24), XSPR_MASK, POWER,     PPCNONE,        {RT}},
5235 {"mfsdr1",      XSPR(31,339, 25), XSPR_MASK, COM,       TITAN,          {RT}},
5236 {"mfsrr0",      XSPR(31,339, 26), XSPR_MASK, COM,       PPCNONE,        {RT}},
5237 {"mfsrr1",      XSPR(31,339, 27), XSPR_MASK, COM,       PPCNONE,        {RT}},
5238 {"mfcfar",      XSPR(31,339, 28), XSPR_MASK, POWER6,    PPCNONE,        {RT}},
5239 {"mfpid",       XSPR(31,339, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5240 {"mfcsrr0",     XSPR(31,339, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5241 {"mfcsrr1",     XSPR(31,339, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5242 {"mfdear",      XSPR(31,339, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5243 {"mfesr",       XSPR(31,339, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5244 {"mfivpr",      XSPR(31,339, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5245 {"mfctrl",      XSPR(31,339,136), XSPR_MASK, POWER4,    PPCNONE,        {RT}},
5246 {"mfcmpa",      XSPR(31,339,144), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5247 {"mfcmpb",      XSPR(31,339,145), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5248 {"mfcmpc",      XSPR(31,339,146), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5249 {"mfcmpd",      XSPR(31,339,147), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5250 {"mficr",       XSPR(31,339,148), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5251 {"mfder",       XSPR(31,339,149), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5252 {"mfcounta",    XSPR(31,339,150), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5253 {"mfcountb",    XSPR(31,339,151), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5254 {"mfcmpe",      XSPR(31,339,152), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5255 {"mfcmpf",      XSPR(31,339,153), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5256 {"mfcmpg",      XSPR(31,339,154), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5257 {"mfcmph",      XSPR(31,339,155), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5258 {"mflctrl1",    XSPR(31,339,156), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5259 {"mflctrl2",    XSPR(31,339,157), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5260 {"mfictrl",     XSPR(31,339,158), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5261 {"mfbar",       XSPR(31,339,159), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5262 {"mfvrsave",    XSPR(31,339,256), XSPR_MASK, PPCVEC,    PPCNONE,        {RT}},
5263 {"mfusprg0",    XSPR(31,339,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5264 {"mfsprg",      XSPR(31,339,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE,      {RT, SPRG}},
5265 {"mfsprg4",     XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
5266 {"mfsprg5",     XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
5267 {"mfsprg6",     XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
5268 {"mfsprg7",     XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
5269 {"mftbu",       XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE|PPCVLE, PPCNONE, {RT}},
5270 {"mftb",        X(31,339),        X_MASK,    POWER4|BOOKE|PPCVLE, PPCNONE, {RT, TBR}},
5271 {"mftbl",       XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE|PPCVLE, PPCNONE, {RT}},
5272 {"mfsprg0",     XSPR(31,339,272), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
5273 {"mfsprg1",     XSPR(31,339,273), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
5274 {"mfsprg2",     XSPR(31,339,274), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
5275 {"mfsprg3",     XSPR(31,339,275), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
5276 {"mfasr",       XSPR(31,339,280), XSPR_MASK, PPC64,     PPCNONE,        {RT}},
5277 {"mfear",       XSPR(31,339,282), XSPR_MASK, PPC,       TITAN,          {RT}},
5278 {"mfpir",       XSPR(31,339,286), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5279 {"mfpvr",       XSPR(31,339,287), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
5280 {"mfdbsr",      XSPR(31,339,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5281 {"mfdbcr0",     XSPR(31,339,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5282 {"mfdbcr1",     XSPR(31,339,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5283 {"mfdbcr2",     XSPR(31,339,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5284 {"mfiac1",      XSPR(31,339,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5285 {"mfiac2",      XSPR(31,339,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5286 {"mfiac3",      XSPR(31,339,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5287 {"mfiac4",      XSPR(31,339,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5288 {"mfdac1",      XSPR(31,339,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5289 {"mfdac2",      XSPR(31,339,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5290 {"mfdvc1",      XSPR(31,339,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5291 {"mfdvc2",      XSPR(31,339,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5292 {"mftsr",       XSPR(31,339,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5293 {"mftcr",       XSPR(31,339,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5294 {"mfivor0",     XSPR(31,339,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5295 {"mfivor1",     XSPR(31,339,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5296 {"mfivor2",     XSPR(31,339,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5297 {"mfivor3",     XSPR(31,339,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5298 {"mfivor4",     XSPR(31,339,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5299 {"mfivor5",     XSPR(31,339,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5300 {"mfivor6",     XSPR(31,339,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5301 {"mfivor7",     XSPR(31,339,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5302 {"mfivor8",     XSPR(31,339,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5303 {"mfivor9",     XSPR(31,339,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5304 {"mfivor10",    XSPR(31,339,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5305 {"mfivor11",    XSPR(31,339,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5306 {"mfivor12",    XSPR(31,339,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5307 {"mfivor13",    XSPR(31,339,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5308 {"mfivor14",    XSPR(31,339,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5309 {"mfivor15",    XSPR(31,339,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
5310 {"mfspefscr",   XSPR(31,339,512), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
5311 {"mfbbear",     XSPR(31,339,513), XSPR_MASK, PPCBRLK,   PPCNONE,        {RT}},
5312 {"mfbbtar",     XSPR(31,339,514), XSPR_MASK, PPCBRLK,   PPCNONE,        {RT}},
5313 {"mfivor32",    XSPR(31,339,528), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
5314 {"mfibatu",     XSPR(31,339,528), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
5315 {"mfivor33",    XSPR(31,339,529), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
5316 {"mfibatl",     XSPR(31,339,529), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
5317 {"mfivor34",    XSPR(31,339,530), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
5318 {"mfivor35",    XSPR(31,339,531), XSPR_MASK, PPCPMR,    PPCNONE,        {RT}},
5319 {"mfdbatu",     XSPR(31,339,536), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
5320 {"mfdbatl",     XSPR(31,339,537), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
5321 {"mfic_cst",    XSPR(31,339,560), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5322 {"mfic_adr",    XSPR(31,339,561), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5323 {"mfic_dat",    XSPR(31,339,562), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5324 {"mfdc_cst",    XSPR(31,339,568), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5325 {"mfdc_adr",    XSPR(31,339,569), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5326 {"mfdc_dat",    XSPR(31,339,570), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5327 {"mfmcsrr0",    XSPR(31,339,570), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
5328 {"mfmcsrr1",    XSPR(31,339,571), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
5329 {"mfmcsr",      XSPR(31,339,572), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
5330 {"mfmcar",      XSPR(31,339,573), XSPR_MASK, PPCRFMCI,  TITAN,          {RT}},
5331 {"mfdpdr",      XSPR(31,339,630), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5332 {"mfdpir",      XSPR(31,339,631), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5333 {"mfimmr",      XSPR(31,339,638), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5334 {"mfmi_ctr",    XSPR(31,339,784), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5335 {"mfmi_ap",     XSPR(31,339,786), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5336 {"mfmi_epn",    XSPR(31,339,787), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5337 {"mfmi_twc",    XSPR(31,339,789), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5338 {"mfmi_rpn",    XSPR(31,339,790), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5339 {"mfmd_ctr",    XSPR(31,339,792), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5340 {"mfm_casid",   XSPR(31,339,793), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5341 {"mfmd_ap",     XSPR(31,339,794), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5342 {"mfmd_epn",    XSPR(31,339,795), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5343 {"mfmd_twb",    XSPR(31,339,796), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5344 {"mfmd_twc",    XSPR(31,339,797), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5345 {"mfmd_rpn",    XSPR(31,339,798), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5346 {"mfm_tw",      XSPR(31,339,799), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5347 {"mfmi_dbcam",  XSPR(31,339,816), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5348 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5349 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5350 {"mfmd_dbcam",  XSPR(31,339,824), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5351 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5352 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
5353 {"mfivndx",     XSPR(31,339,880), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
5354 {"mfdvndx",     XSPR(31,339,881), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
5355 {"mfivlim",     XSPR(31,339,882), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
5356 {"mfdvlim",     XSPR(31,339,883), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
5357 {"mfclcsr",     XSPR(31,339,884), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
5358 {"mfccr1",      XSPR(31,339,888), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
5359 {"mfppr",       XSPR(31,339,896), XSPR_MASK, POWER7,    PPCNONE,        {RT}},
5360 {"mfppr32",     XSPR(31,339,898), XSPR_MASK, POWER7,    PPCNONE,        {RT}},
5361 {"mfrstcfg",    XSPR(31,339,923), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
5362 {"mfdcdbtrl",   XSPR(31,339,924), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
5363 {"mfdcdbtrh",   XSPR(31,339,925), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
5364 {"mficdbtr",    XSPR(31,339,927), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
5365 {"mfummcr0",    XSPR(31,339,936), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5366 {"mfupmc1",     XSPR(31,339,937), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5367 {"mfupmc2",     XSPR(31,339,938), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5368 {"mfusia",      XSPR(31,339,939), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5369 {"mfummcr1",    XSPR(31,339,940), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5370 {"mfupmc3",     XSPR(31,339,941), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5371 {"mfupmc4",     XSPR(31,339,942), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5372 {"mfzpr",       XSPR(31,339,944), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5373 {"mfpid",       XSPR(31,339,945), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5374 {"mfmmucr",     XSPR(31,339,946), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
5375 {"mfccr0",      XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, PPCNONE,     {RT}},
5376 {"mfiac3",      XSPR(31,339,948), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
5377 {"mfiac4",      XSPR(31,339,949), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
5378 {"mfdvc1",      XSPR(31,339,950), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
5379 {"mfdvc2",      XSPR(31,339,951), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
5380 {"mfmmcr0",     XSPR(31,339,952), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5381 {"mfpmc1",      XSPR(31,339,953), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5382 {"mfsgr",       XSPR(31,339,953), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5383 {"mfdcwr",      XSPR(31,339,954), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5384 {"mfpmc2",      XSPR(31,339,954), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5385 {"mfsia",       XSPR(31,339,955), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5386 {"mfsler",      XSPR(31,339,955), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
5387 {"mfmmcr1",     XSPR(31,339,956), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5388 {"mfsu0r",      XSPR(31,339,956), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
5389 {"mfdbcr1",     XSPR(31,339,957), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
5390 {"mfpmc3",      XSPR(31,339,957), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5391 {"mfpmc4",      XSPR(31,339,958), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5392 {"mficdbdr",    XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, PPCNONE,     {RT}},
5393 {"mfesr",       XSPR(31,339,980), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5394 {"mfdear",      XSPR(31,339,981), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5395 {"mfevpr",      XSPR(31,339,982), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5396 {"mfcdbcr",     XSPR(31,339,983), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5397 {"mftsr",       XSPR(31,339,984), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5398 {"mftcr",       XSPR(31,339,986), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5399 {"mfpit",       XSPR(31,339,987), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5400 {"mftbhi",      XSPR(31,339,988), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5401 {"mftblo",      XSPR(31,339,989), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5402 {"mfsrr2",      XSPR(31,339,990), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5403 {"mfsrr3",      XSPR(31,339,991), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5404 {"mfdbsr",      XSPR(31,339,1008), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5405 {"mfdbcr0",     XSPR(31,339,1010), XSPR_MASK, PPC405,   PPCNONE,        {RT}},
5406 {"mfdbdr",      XSPR(31,339,1011), XSPR_MASK, TITAN,    PPCNONE,        {RS}},
5407 {"mfiac1",      XSPR(31,339,1012), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5408 {"mfiac2",      XSPR(31,339,1013), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5409 {"mfdac1",      XSPR(31,339,1014), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5410 {"mfdac2",      XSPR(31,339,1015), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5411 {"mfl2cr",      XSPR(31,339,1017), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
5412 {"mfdccr",      XSPR(31,339,1018), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5413 {"mficcr",      XSPR(31,339,1019), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5414 {"mfictc",      XSPR(31,339,1019), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
5415 {"mfpbl1",      XSPR(31,339,1020), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5416 {"mfthrm1",     XSPR(31,339,1020), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
5417 {"mfpbu1",      XSPR(31,339,1021), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5418 {"mfthrm2",     XSPR(31,339,1021), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
5419 {"mfpbl2",      XSPR(31,339,1022), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5420 {"mfthrm3",     XSPR(31,339,1022), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
5421 {"mfpbu2",      XSPR(31,339,1023), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5422 {"mfspr",       X(31,339),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, SPR}},
5423
5424 {"lwax",        X(31,341),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RA0, RB}},
5425
5426 {"dst",         XDSS(31,342,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
5427
5428 {"lhax",        X(31,343),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
5429
5430 {"lvxl",        X(31,359),      X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
5431
5432 {"abs",         XO(31,360,0,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5433 {"abs.",        XO(31,360,0,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5434
5435 {"divs",        XO(31,363,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5436 {"divs.",       XO(31,363,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5437
5438 {"lxvwsx",      X(31,364),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XT6, RA0, RB}},
5439
5440 {"tlbia",       X(31,370),      0xffffffff,  PPC,       E500|TITAN,     {0}},
5441
5442 {"mftbu",       XSPR(31,371,269), XSPR_MASK, PPC,       NO371|POWER4,   {RT}},
5443 {"mftb",        X(31,371),      X_MASK,      PPC,       NO371|POWER4,   {RT, TBR}},
5444 {"mftbl",       XSPR(31,371,268), XSPR_MASK, PPC,       NO371|POWER4,   {RT}},
5445
5446 {"lwaux",       X(31,373),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RAL, RB}},
5447
5448 {"dstst",       XDSS(31,374,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
5449
5450 {"lhaux",       X(31,375),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RAL, RB}},
5451
5452 {"popcntw",     X(31,378),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
5453
5454 {"mtdcrx",      X(31,387),      X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RA, RS}},
5455 {"mtdcrx.",     XRC(31,387,1),  X_MASK,      PPCA2,     PPCNONE,        {RA, RS}},
5456
5457 {"stvexbx",     X(31,389),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5458
5459 {"dcblc",       X(31,390),      X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
5460 {"stdfcmx",     APU(31,391,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5461
5462 {"divdeu",      XO(31,393,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5463 {"divdeu.",     XO(31,393,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5464 {"divweu",      XO(31,395,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5465 {"divweu.",     XO(31,395,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5466
5467 {"stxvx",       X(31,396),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XS6, RA0, RB}},
5468 {"stxvl",       X(31,397),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XS6, RA0, RB}},
5469
5470 {"dcblce",      X(31,398),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA, RB}},
5471
5472 {"slbmte",      X(31,402),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
5473
5474 {"mtvsrws",     X(31,403),      XX1RB_MASK,  PPCVSX3,   PPCNONE,        {XT6, RA}},
5475
5476 {"pbt.",        XRC(31,404,1),  X_MASK,      POWER8,    PPCNONE,        {RS, RA0, RB}},
5477
5478 {"icswx",       XRC(31,406,0),  X_MASK,   POWER7|PPCA2, PPCNONE,        {RS, RA, RB}},
5479 {"icswx.",      XRC(31,406,1),  X_MASK,   POWER7|PPCA2, PPCNONE,        {RS, RA, RB}},
5480
5481 {"sthx",        X(31,407),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RA0, RB}},
5482
5483 {"orc",         XRC(31,412,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5484 {"orc.",        XRC(31,412,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5485
5486 {"sthepx",      X(31,415),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
5487
5488 {"mtdcrux",     X(31,419),      X_MASK,      PPC464|PPCVLE, PPCNONE,    {RA, RS}},
5489
5490 {"stvexhx",     X(31,421),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5491
5492 {"dcblq.",      XRC(31,422,1),  X_MASK,      E6500,     PPCNONE,        {CT, RA0, RB}},
5493
5494 {"divde",       XO(31,425,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5495 {"divde.",      XO(31,425,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5496 {"divwe",       XO(31,427,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5497 {"divwe.",      XO(31,427,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5498
5499 {"stxvll",      X(31,429),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XS6, RA0, RB}},
5500
5501 {"clrbhrb",     X(31,430),      0xffffffff,  POWER8,    PPCNONE,        {0}},
5502
5503 {"slbie",       X(31,434),      XRTRA_MASK,  PPC64,     PPCNONE,        {RB}},
5504
5505 {"mtvsrdd",     X(31,435),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XT6, RA0, RB}},
5506
5507 {"ecowx",       X(31,438),      X_MASK,      PPC,       E500|TITAN,     {RT, RA0, RB}},
5508
5509 {"sthux",       X(31,439),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RAS, RB}},
5510
5511 {"mdors",       0x7f9ce378,     0xffffffff,  E500MC,    PPCNONE,        {0}},
5512
5513 {"miso",        0x7f5ad378,     0xffffffff,  E6500,     PPCNONE,        {0}},
5514
5515 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
5516    "or rX,rX,rX", with rX being r27, r29 and r30 respectively.  */
5517 {"yield",       0x7f7bdb78,     0xffffffff,  POWER7,     PPCNONE,       {0}},
5518 {"mdoio",       0x7fbdeb78,     0xffffffff,  POWER7,     PPCNONE,       {0}},
5519 {"mdoom",       0x7fdef378,     0xffffffff,  POWER7,     PPCNONE,       {0}},
5520 {"mr",          XRC(31,444,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RBS}},
5521 {"or",          XRC(31,444,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5522 {"mr.",         XRC(31,444,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RBS}},
5523 {"or.",         XRC(31,444,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5524
5525 {"mtexisr",     XSPR(31,451, 64), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5526 {"mtexier",     XSPR(31,451, 66), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5527 {"mtbr0",       XSPR(31,451,128), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5528 {"mtbr1",       XSPR(31,451,129), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5529 {"mtbr2",       XSPR(31,451,130), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5530 {"mtbr3",       XSPR(31,451,131), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5531 {"mtbr4",       XSPR(31,451,132), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5532 {"mtbr5",       XSPR(31,451,133), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5533 {"mtbr6",       XSPR(31,451,134), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5534 {"mtbr7",       XSPR(31,451,135), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5535 {"mtbear",      XSPR(31,451,144), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5536 {"mtbesr",      XSPR(31,451,145), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5537 {"mtiocr",      XSPR(31,451,160), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5538 {"mtdmacr0",    XSPR(31,451,192), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5539 {"mtdmact0",    XSPR(31,451,193), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5540 {"mtdmada0",    XSPR(31,451,194), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5541 {"mtdmasa0",    XSPR(31,451,195), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5542 {"mtdmacc0",    XSPR(31,451,196), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5543 {"mtdmacr1",    XSPR(31,451,200), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5544 {"mtdmact1",    XSPR(31,451,201), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5545 {"mtdmada1",    XSPR(31,451,202), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5546 {"mtdmasa1",    XSPR(31,451,203), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5547 {"mtdmacc1",    XSPR(31,451,204), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5548 {"mtdmacr2",    XSPR(31,451,208), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5549 {"mtdmact2",    XSPR(31,451,209), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5550 {"mtdmada2",    XSPR(31,451,210), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5551 {"mtdmasa2",    XSPR(31,451,211), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5552 {"mtdmacc2",    XSPR(31,451,212), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5553 {"mtdmacr3",    XSPR(31,451,216), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5554 {"mtdmact3",    XSPR(31,451,217), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5555 {"mtdmada3",    XSPR(31,451,218), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5556 {"mtdmasa3",    XSPR(31,451,219), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5557 {"mtdmacc3",    XSPR(31,451,220), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5558 {"mtdmasr",     XSPR(31,451,224), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5559 {"mtdcr",       X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, E500|TITAN, {SPR, RS}},
5560 {"mtdcr.",      XRC(31,451,1), X_MASK,       PPCA2,     PPCNONE,        {SPR, RS}},
5561
5562 {"stvexwx",     X(31,453),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5563
5564 {"dccci",       X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
5565 {"dci",         X(31,454),      XRARB_MASK, PPCA2|PPC476|PPCVLE, PPCNONE, {CT}},
5566
5567 {"divdu",       XO(31,457,0,0), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
5568 {"divdu.",      XO(31,457,0,1), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
5569
5570 {"divwu",       XO(31,459,0,0), XO_MASK,  PPC|PPCVLE,   PPCNONE,        {RT, RA, RB}},
5571 {"divwu.",      XO(31,459,0,1), XO_MASK,  PPC|PPCVLE,   PPCNONE,        {RT, RA, RB}},
5572
5573 {"mtpmr",       X(31,462),      X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {PMR, RS}},
5574 {"mttmr",       X(31,494),      X_MASK, PPCTMR|E6500,   PPCNONE,        {TMR, RS}},
5575
5576 {"slbieg",      X(31,466),      XRA_MASK,    POWER9,    PPCNONE,        {RS, RB}},
5577
5578 {"mtmq",        XSPR(31,467,  0), XSPR_MASK, M601,      PPCNONE,        {RS}},
5579 {"mtxer",       XSPR(31,467,  1), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
5580 {"mtlr",        XSPR(31,467,  8), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
5581 {"mtctr",       XSPR(31,467,  9), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
5582 {"mtdscr",      XSPR(31,467, 17), XSPR_MASK, POWER6,    PPCNONE,        {RS}},
5583 {"mttid",       XSPR(31,467, 17), XSPR_MASK, POWER,     PPCNONE,        {RS}},
5584 {"mtdsisr",     XSPR(31,467, 18), XSPR_MASK, COM,       TITAN,          {RS}},
5585 {"mtdar",       XSPR(31,467, 19), XSPR_MASK, COM,       TITAN,          {RS}},
5586 {"mtrtcu",      XSPR(31,467, 20), XSPR_MASK, COM,       TITAN,          {RS}},
5587 {"mtrtcl",      XSPR(31,467, 21), XSPR_MASK, COM,       TITAN,          {RS}},
5588 {"mtdec",       XSPR(31,467, 22), XSPR_MASK, COM,       PPCNONE,        {RS}},
5589 {"mtsdr0",      XSPR(31,467, 24), XSPR_MASK, POWER,     PPCNONE,        {RS}},
5590 {"mtsdr1",      XSPR(31,467, 25), XSPR_MASK, COM,       TITAN,          {RS}},
5591 {"mtsrr0",      XSPR(31,467, 26), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
5592 {"mtsrr1",      XSPR(31,467, 27), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
5593 {"mtcfar",      XSPR(31,467, 28), XSPR_MASK, POWER6,    PPCNONE,        {RS}},
5594 {"mtpid",       XSPR(31,467, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5595 {"mtdecar",     XSPR(31,467, 54), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5596 {"mtcsrr0",     XSPR(31,467, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5597 {"mtcsrr1",     XSPR(31,467, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5598 {"mtdear",      XSPR(31,467, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5599 {"mtesr",       XSPR(31,467, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5600 {"mtivpr",      XSPR(31,467, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5601 {"mtcmpa",      XSPR(31,467,144), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5602 {"mtcmpb",      XSPR(31,467,145), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5603 {"mtcmpc",      XSPR(31,467,146), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5604 {"mtcmpd",      XSPR(31,467,147), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5605 {"mticr",       XSPR(31,467,148), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5606 {"mtder",       XSPR(31,467,149), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5607 {"mtcounta",    XSPR(31,467,150), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5608 {"mtcountb",    XSPR(31,467,151), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5609 {"mtctrl",      XSPR(31,467,152), XSPR_MASK, POWER4,    PPCNONE,        {RS}},
5610 {"mtcmpe",      XSPR(31,467,152), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5611 {"mtcmpf",      XSPR(31,467,153), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5612 {"mtcmpg",      XSPR(31,467,154), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5613 {"mtcmph",      XSPR(31,467,155), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5614 {"mtlctrl1",    XSPR(31,467,156), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5615 {"mtlctrl2",    XSPR(31,467,157), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5616 {"mtictrl",     XSPR(31,467,158), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5617 {"mtbar",       XSPR(31,467,159), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5618 {"mtvrsave",    XSPR(31,467,256), XSPR_MASK, PPCVEC,    PPCNONE,        {RS}},
5619 {"mtusprg0",    XSPR(31,467,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5620 {"mtsprg",      XSPR(31,467,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE,      {SPRG, RS}},
5621 {"mtsprg0",     XSPR(31,467,272), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
5622 {"mtsprg1",     XSPR(31,467,273), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
5623 {"mtsprg2",     XSPR(31,467,274), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
5624 {"mtsprg3",     XSPR(31,467,275), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
5625 {"mtsprg4",     XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5626 {"mtsprg5",     XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5627 {"mtsprg6",     XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5628 {"mtsprg7",     XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5629 {"mtasr",       XSPR(31,467,280), XSPR_MASK, PPC64,     PPCNONE,        {RS}},
5630 {"mtear",       XSPR(31,467,282), XSPR_MASK, PPC,       TITAN,          {RS}},
5631 {"mttbl",       XSPR(31,467,284), XSPR_MASK, PPC,       PPCNONE,        {RS}},
5632 {"mttbu",       XSPR(31,467,285), XSPR_MASK, PPC,       PPCNONE,        {RS}},
5633 {"mtdbsr",      XSPR(31,467,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5634 {"mtdbcr0",     XSPR(31,467,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5635 {"mtdbcr1",     XSPR(31,467,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5636 {"mtdbcr2",     XSPR(31,467,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5637 {"mtiac1",      XSPR(31,467,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5638 {"mtiac2",      XSPR(31,467,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5639 {"mtiac3",      XSPR(31,467,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5640 {"mtiac4",      XSPR(31,467,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5641 {"mtdac1",      XSPR(31,467,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5642 {"mtdac2",      XSPR(31,467,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5643 {"mtdvc1",      XSPR(31,467,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5644 {"mtdvc2",      XSPR(31,467,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5645 {"mttsr",       XSPR(31,467,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5646 {"mttcr",       XSPR(31,467,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5647 {"mtivor0",     XSPR(31,467,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5648 {"mtivor1",     XSPR(31,467,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5649 {"mtivor2",     XSPR(31,467,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5650 {"mtivor3",     XSPR(31,467,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5651 {"mtivor4",     XSPR(31,467,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5652 {"mtivor5",     XSPR(31,467,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5653 {"mtivor6",     XSPR(31,467,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5654 {"mtivor7",     XSPR(31,467,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5655 {"mtivor8",     XSPR(31,467,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5656 {"mtivor9",     XSPR(31,467,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5657 {"mtivor10",    XSPR(31,467,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5658 {"mtivor11",    XSPR(31,467,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5659 {"mtivor12",    XSPR(31,467,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5660 {"mtivor13",    XSPR(31,467,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5661 {"mtivor14",    XSPR(31,467,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5662 {"mtivor15",    XSPR(31,467,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5663 {"mtspefscr",   XSPR(31,467,512), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
5664 {"mtbbear",     XSPR(31,467,513), XSPR_MASK, PPCBRLK,   PPCNONE,        {RS}},
5665 {"mtbbtar",     XSPR(31,467,514), XSPR_MASK, PPCBRLK,   PPCNONE,        {RS}},
5666 {"mtivor32",    XSPR(31,467,528), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
5667 {"mtibatu",     XSPR(31,467,528), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
5668 {"mtivor33",    XSPR(31,467,529), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
5669 {"mtibatl",     XSPR(31,467,529), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
5670 {"mtivor34",    XSPR(31,467,530), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
5671 {"mtivor35",    XSPR(31,467,531), XSPR_MASK, PPCPMR,    PPCNONE,        {RS}},
5672 {"mtdbatu",     XSPR(31,467,536), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
5673 {"mtdbatl",     XSPR(31,467,537), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
5674 {"mtmcsrr0",    XSPR(31,467,570), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE,  {RS}},
5675 {"mtmcsrr1",    XSPR(31,467,571), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE,  {RS}},
5676 {"mtmcsr",      XSPR(31,467,572), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RS}},
5677 {"mtivndx",     XSPR(31,467,880), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5678 {"mtdvndx",     XSPR(31,467,881), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5679 {"mtivlim",     XSPR(31,467,882), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5680 {"mtdvlim",     XSPR(31,467,883), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5681 {"mtclcsr",     XSPR(31,467,884), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5682 {"mtccr1",      XSPR(31,467,888), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5683 {"mtppr",       XSPR(31,467,896), XSPR_MASK, POWER7,    PPCNONE,        {RS}},
5684 {"mtppr32",     XSPR(31,467,898), XSPR_MASK, POWER7,    PPCNONE,        {RS}},
5685 {"mtummcr0",    XSPR(31,467,936), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5686 {"mtupmc1",     XSPR(31,467,937), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5687 {"mtupmc2",     XSPR(31,467,938), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5688 {"mtusia",      XSPR(31,467,939), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5689 {"mtummcr1",    XSPR(31,467,940), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5690 {"mtupmc3",     XSPR(31,467,941), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5691 {"mtupmc4",     XSPR(31,467,942), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5692 {"mtzpr",       XSPR(31,467,944), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5693 {"mtpid",       XSPR(31,467,945), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5694 {"mtrmmucr",    XSPR(31,467,946), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5695 {"mtccr0",      XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, PPCNONE,     {RS}},
5696 {"mtiac3",      XSPR(31,467,948), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5697 {"mtiac4",      XSPR(31,467,949), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5698 {"mtdvc1",      XSPR(31,467,950), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5699 {"mtdvc2",      XSPR(31,467,951), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5700 {"mtmmcr0",     XSPR(31,467,952), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5701 {"mtpmc1",      XSPR(31,467,953), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5702 {"mtsgr",       XSPR(31,467,953), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5703 {"mtdcwr",      XSPR(31,467,954), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5704 {"mtpmc2",      XSPR(31,467,954), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5705 {"mtsia",       XSPR(31,467,955), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5706 {"mtsler",      XSPR(31,467,955), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5707 {"mtmmcr1",     XSPR(31,467,956), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5708 {"mtsu0r",      XSPR(31,467,956), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5709 {"mtdbcr1",     XSPR(31,467,957), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5710 {"mtpmc3",      XSPR(31,467,957), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5711 {"mtpmc4",      XSPR(31,467,958), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5712 {"mticdbdr",    XSPR(31,467,979), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5713 {"mtesr",       XSPR(31,467,980), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5714 {"mtdear",      XSPR(31,467,981), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5715 {"mtevpr",      XSPR(31,467,982), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5716 {"mtcdbcr",     XSPR(31,467,983), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5717 {"mttsr",       XSPR(31,467,984), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5718 {"mttcr",       XSPR(31,467,986), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5719 {"mtpit",       XSPR(31,467,987), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5720 {"mttbhi",      XSPR(31,467,988), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5721 {"mttblo",      XSPR(31,467,989), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5722 {"mtsrr2",      XSPR(31,467,990), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5723 {"mtsrr3",      XSPR(31,467,991), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5724 {"mtdbsr",      XSPR(31,467,1008), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5725 {"mtdbdr",      XSPR(31,467,1011), XSPR_MASK, TITAN,    PPCNONE,        {RS}},
5726 {"mtdbcr0",     XSPR(31,467,1010), XSPR_MASK, PPC405,   PPCNONE,        {RS}},
5727 {"mtiac1",      XSPR(31,467,1012), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5728 {"mtiac2",      XSPR(31,467,1013), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5729 {"mtdac1",      XSPR(31,467,1014), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5730 {"mtdac2",      XSPR(31,467,1015), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5731 {"mtl2cr",      XSPR(31,467,1017), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5732 {"mtdccr",      XSPR(31,467,1018), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5733 {"mticcr",      XSPR(31,467,1019), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5734 {"mtictc",      XSPR(31,467,1019), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5735 {"mtpbl1",      XSPR(31,467,1020), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5736 {"mtthrm1",     XSPR(31,467,1020), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5737 {"mtpbu1",      XSPR(31,467,1021), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5738 {"mtthrm2",     XSPR(31,467,1021), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5739 {"mtpbl2",      XSPR(31,467,1022), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5740 {"mtthrm3",     XSPR(31,467,1022), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5741 {"mtpbu2",      XSPR(31,467,1023), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5742 {"mtspr",       X(31,467),      X_MASK,      COM|PPCVLE, PPCNONE,       {SPR, RS}},
5743
5744 {"dcbi",        X(31,470),      XRT_MASK,    PPC|PPCVLE, PPCNONE,       {RA0, RB}},
5745
5746 {"nand",        XRC(31,476,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5747 {"nand.",       XRC(31,476,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5748
5749 {"dsn",         X(31,483),      XRT_MASK,    E500MC|PPCVLE, PPCNONE,    {RA, RB}},
5750
5751 {"dcread",      X(31,486),      X_MASK,  PPC403|PPC440|PPCVLE, PPCA2|PPC476, {RT, RA0, RB}},
5752
5753 {"icbtls",      X(31,486),      X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
5754
5755 {"stvxl",       X(31,487),      X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VS, RA0, RB}},
5756
5757 {"nabs",        XO(31,488,0,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5758 {"nabs.",       XO(31,488,0,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5759
5760 {"divd",        XO(31,489,0,0), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
5761 {"divd.",       XO(31,489,0,1), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
5762
5763 {"divw",        XO(31,491,0,0), XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
5764 {"divw.",       XO(31,491,0,1), XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
5765
5766 {"icbtlse",     X(31,494),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA, RB}},
5767
5768 {"slbia",       X(31,498),      0xff1fffff,  POWER6,    PPCNONE,        {IH}},
5769 {"slbia",       X(31,498),      0xffffffff,  PPC64,     POWER6,         {0}},
5770
5771 {"cli",         X(31,502),      XRB_MASK,    POWER,     PPCNONE,        {RT, RA}},
5772
5773 {"popcntd",     X(31,506),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
5774
5775 {"cmpb",        X(31,508),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {RA, RS, RB}},
5776
5777 {"mcrxr",       X(31,512),      XBFRARB_MASK, COM|PPCVLE, POWER7,       {BF}},
5778
5779 {"lbdx",        X(31,515),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {RT, RA, RB}},
5780
5781 {"bblels",      X(31,518),      X_MASK,      PPCBRLK,   PPCNONE,        {0}},
5782
5783 {"lvlx",        X(31,519),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
5784 {"lbfcmux",     APU(31,519,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5785
5786 {"subfco",      XO(31,8,1,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5787 {"sfo",         XO(31,8,1,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5788 {"subco",       XO(31,8,1,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
5789 {"subfco.",     XO(31,8,1,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5790 {"sfo.",        XO(31,8,1,1),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5791 {"subco.",      XO(31,8,1,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
5792
5793 {"addco",       XO(31,10,1,0),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5794 {"ao",          XO(31,10,1,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5795 {"addco.",      XO(31,10,1,1),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5796 {"ao.",         XO(31,10,1,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5797
5798 {"lxsspx",      X(31,524),      XX1_MASK,    PPCVSX2,   PPCNONE,        {XT6, RA0, RB}},
5799
5800 {"clcs",        X(31,531),      XRB_MASK,    M601,      PPCNONE,        {RT, RA}},
5801
5802 {"ldbrx",       X(31,532),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RT, RA0, RB}},
5803
5804 {"lswx",        X(31,533),      X_MASK,  PPCCOM|PPCVLE, E500|E500MC,    {RT, RAX, RBX}},
5805 {"lsx",         X(31,533),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
5806
5807 {"lwbrx",       X(31,534),      X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RT, RA0, RB}},
5808 {"lbrx",        X(31,534),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
5809
5810 {"lfsx",        X(31,535),      X_MASK,      COM,       PPCEFS,         {FRT, RA0, RB}},
5811
5812 {"srw",         XRC(31,536,0),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
5813 {"sr",          XRC(31,536,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
5814 {"srw.",        XRC(31,536,1),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
5815 {"sr.",         XRC(31,536,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
5816
5817 {"rrib",        XRC(31,537,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5818 {"rrib.",       XRC(31,537,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5819
5820 {"cnttzw",      XRC(31,538,0),  XRB_MASK,    POWER9,    PPCNONE,        {RA, RS}},
5821 {"cnttzw.",     XRC(31,538,1),  XRB_MASK,    POWER9,    PPCNONE,        {RA, RS}},
5822
5823 {"srd",         XRC(31,539,0),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
5824 {"srd.",        XRC(31,539,1),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
5825
5826 {"maskir",      XRC(31,541,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5827 {"maskir.",     XRC(31,541,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5828
5829 {"lhdx",        X(31,547),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {RT, RA, RB}},
5830
5831 {"lvtrx",       X(31,549),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5832
5833 {"bbelr",       X(31,550),      X_MASK,      PPCBRLK,   PPCNONE,        {0}},
5834
5835 {"lvrx",        X(31,551),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
5836 {"lhfcmux",     APU(31,551,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5837
5838 {"subfo",       XO(31,40,1,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
5839 {"subo",        XO(31,40,1,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
5840 {"subfo.",      XO(31,40,1,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
5841 {"subo.",       XO(31,40,1,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
5842
5843 {"tlbsync",     X(31,566),      0xffffffff, PPC|PPCVLE, PPCNONE,        {0}},
5844
5845 {"lfsux",       X(31,567),      X_MASK,      COM,       PPCEFS,         {FRT, RAS, RB}},
5846
5847 {"cnttzd",      XRC(31,570,0),  XRB_MASK,    POWER9,    PPCNONE,        {RA, RS}},
5848 {"cnttzd.",     XRC(31,570,1),  XRB_MASK,    POWER9,    PPCNONE,        {RA, RS}},
5849
5850 {"mcrxrx",      X(31,576),      XBFRARB_MASK, POWER9,   PPCNONE,        {BF}},
5851
5852 {"lwdx",        X(31,579),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {RT, RA, RB}},
5853
5854 {"lvtlx",       X(31,581),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5855
5856 {"lwat",        X(31,582),      X_MASK,      POWER9,    PPCNONE,        {RT, RA0, FC}},
5857
5858 {"lwfcmux",     APU(31,583,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5859
5860 {"lxsdx",       X(31,588),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
5861
5862 {"mfsr",        X(31,595), XRB_MASK|(1<<20), COM,       NON32,          {RT, SR}},
5863
5864 {"lswi",        X(31,597),      X_MASK,  PPCCOM|PPCVLE, E500|E500MC,    {RT, RAX, NBI}},
5865 {"lsi",         X(31,597),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA0, NB}},
5866
5867 {"hwsync",      XSYNC(31,598,0), 0xffffffff, POWER4,    BOOKE|PPC476,   {0}},
5868 {"lwsync",      XSYNC(31,598,1), 0xffffffff, PPC,       E500,           {0}},
5869 {"ptesync",     XSYNC(31,598,2), 0xffffffff, PPC64,     PPCNONE,        {0}},
5870 {"sync",        X(31,598),      XSYNCLE_MASK,POWER9|E6500, PPCNONE,     {LS, ESYNC}},
5871 {"sync",        X(31,598),      XSYNC_MASK, PPCCOM|PPCVLE, BOOKE|PPC476|POWER9, {LS}},
5872 {"msync",       X(31,598),      0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
5873 {"sync",        X(31,598),      0xffffffff, BOOKE|PPC476, E6500,        {0}},
5874 {"lwsync",      X(31,598),      0xffffffff, E500,       PPCNONE,        {0}},
5875 {"dcs",         X(31,598),      0xffffffff,  PWRCOM,    PPCNONE,        {0}},
5876
5877 {"lfdx",        X(31,599),      X_MASK,      COM,       PPCEFS,         {FRT, RA0, RB}},
5878
5879 {"mffgpr",      XRC(31,607,0),  XRA_MASK,    POWER6,    POWER7,         {FRT, RB}},
5880 {"lfdepx",      X(31,607),      X_MASK,   E500MC|PPCA2|PPCVLE, PPCNONE, {FRT, RA0, RB}},
5881
5882 {"lddx",        X(31,611),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {RT, RA, RB}},
5883
5884 {"lvswx",       X(31,613),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5885
5886 {"ldat",        X(31,614),      X_MASK,      POWER9,    PPCNONE,        {RT, RA0, FC}},
5887
5888 {"lqfcmux",     APU(31,615,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5889
5890 {"nego",        XO(31,104,1,0), XORB_MASK,   COM|PPCVLE, PPCNONE,       {RT, RA}},
5891 {"nego.",       XO(31,104,1,1), XORB_MASK,   COM|PPCVLE, PPCNONE,       {RT, RA}},
5892
5893 {"mulo",        XO(31,107,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5894 {"mulo.",       XO(31,107,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5895
5896 {"mfsri",       X(31,627),      X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
5897
5898 {"dclst",       X(31,630),      XRB_MASK,    M601,      PPCNONE,        {RS, RA}},
5899
5900 {"lfdux",       X(31,631),      X_MASK,      COM,       PPCEFS,         {FRT, RAS, RB}},
5901
5902 {"stbdx",       X(31,643),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
5903
5904 {"stvlx",       X(31,647),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
5905 {"stbfcmux",    APU(31,647,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5906
5907 {"stxsspx",     X(31,652),      XX1_MASK,    PPCVSX2,   PPCNONE,        {XS6, RA0, RB}},
5908
5909 {"tbegin.",     XRC(31,654,1), XRTLRARB_MASK,PPCHTM,    PPCNONE,        {HTM_R}},
5910
5911 {"subfeo",      XO(31,136,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5912 {"sfeo",        XO(31,136,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5913 {"subfeo.",     XO(31,136,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5914 {"sfeo.",       XO(31,136,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5915
5916 {"addeo",       XO(31,138,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5917 {"aeo",         XO(31,138,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5918 {"addeo.",      XO(31,138,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5919 {"aeo.",        XO(31,138,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5920
5921 {"mfsrin",      X(31,659),      XRA_MASK,    PPC,       NON32,          {RT, RB}},
5922
5923 {"stdbrx",      X(31,660),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RS, RA0, RB}},
5924
5925 {"stswx",       X(31,661),      X_MASK, PPCCOM|PPCVLE,  E500|E500MC,    {RS, RA0, RB}},
5926 {"stsx",        X(31,661),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
5927
5928 {"stwbrx",      X(31,662),      X_MASK, PPCCOM|PPCVLE,  PPCNONE,        {RS, RA0, RB}},
5929 {"stbrx",       X(31,662),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
5930
5931 {"stfsx",       X(31,663),      X_MASK,      COM,       PPCEFS,         {FRS, RA0, RB}},
5932
5933 {"srq",         XRC(31,664,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5934 {"srq.",        XRC(31,664,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5935
5936 {"sre",         XRC(31,665,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5937 {"sre.",        XRC(31,665,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5938
5939 {"sthdx",       X(31,675),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
5940
5941 {"stvfrx",      X(31,677),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5942
5943 {"stvrx",       X(31,679),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
5944 {"sthfcmux",    APU(31,679,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5945
5946 {"tendall.",    XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, PPCNONE,   {0}},
5947 {"tend.",       XRC(31,686,1), XRTARARB_MASK, PPCHTM,   PPCNONE,        {HTM_A}},
5948
5949 {"stbcx.",      XRC(31,694,1),  X_MASK,      POWER8,    PPCNONE,        {RS, RA0, RB}},
5950
5951 {"stfsux",      X(31,695),      X_MASK,      COM,       PPCEFS,         {FRS, RAS, RB}},
5952
5953 {"sriq",        XRC(31,696,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5954 {"sriq.",       XRC(31,696,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5955
5956 {"stwdx",       X(31,707),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
5957
5958 {"stvflx",      X(31,709),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5959
5960 {"stwat",       X(31,710),      X_MASK,      POWER9,    PPCNONE,        {RS, RA0, FC}},
5961
5962 {"stwfcmux",    APU(31,711,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5963
5964 {"stxsdx",      X(31,716),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA0, RB}},
5965
5966 {"tcheck",      X(31,718),   XRTBFRARB_MASK, PPCHTM,    PPCNONE,        {BF}},
5967
5968 {"subfzeo",     XO(31,200,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
5969 {"sfzeo",       XO(31,200,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5970 {"subfzeo.",    XO(31,200,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
5971 {"sfzeo.",      XO(31,200,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5972
5973 {"addzeo",      XO(31,202,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
5974 {"azeo",        XO(31,202,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5975 {"addzeo.",     XO(31,202,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
5976 {"azeo.",       XO(31,202,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5977
5978 {"stswi",       X(31,725),      X_MASK, PPCCOM|PPCVLE,  E500|E500MC,    {RS, RA0, NB}},
5979 {"stsi",        X(31,725),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, NB}},
5980
5981 {"sthcx.",      XRC(31,726,1),  X_MASK,      POWER8,    PPCNONE,        {RS, RA0, RB}},
5982
5983 {"stfdx",       X(31,727),      X_MASK,      COM,       PPCEFS,         {FRS, RA0, RB}},
5984
5985 {"srlq",        XRC(31,728,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5986 {"srlq.",       XRC(31,728,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5987
5988 {"sreq",        XRC(31,729,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5989 {"sreq.",       XRC(31,729,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5990
5991 {"mftgpr",      XRC(31,735,0),  XRA_MASK,    POWER6,    POWER7,         {RT, FRB}},
5992 {"stfdepx",     X(31,735),      X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE,   {FRS, RA0, RB}},
5993
5994 {"stddx",       X(31,739),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
5995
5996 {"stvswx",      X(31,741),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5997
5998 {"stdat",       X(31,742),      X_MASK,      POWER9,    PPCNONE,        {RS, RA0, FC}},
5999
6000 {"stqfcmux",    APU(31,743,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
6001
6002 {"subfmeo",     XO(31,232,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
6003 {"sfmeo",       XO(31,232,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
6004 {"subfmeo.",    XO(31,232,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
6005 {"sfmeo.",      XO(31,232,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
6006
6007 {"mulldo",      XO(31,233,1,0), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
6008 {"mulldo.",     XO(31,233,1,1), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
6009
6010 {"addmeo",      XO(31,234,1,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
6011 {"ameo",        XO(31,234,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
6012 {"addmeo.",     XO(31,234,1,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
6013 {"ameo.",       XO(31,234,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
6014
6015 {"mullwo",      XO(31,235,1,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
6016 {"mulso",       XO(31,235,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
6017 {"mullwo.",     XO(31,235,1,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
6018 {"mulso.",      XO(31,235,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
6019
6020 {"tsuspend.",   XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM,  PPCNONE,        {0}},
6021 {"tresume.",    XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM,  PPCNONE,        {0}},
6022 {"tsr.",        XRC(31,750,1),    XRTLRARB_MASK,PPCHTM, PPCNONE,        {L}},
6023
6024 {"darn",        X(31,755),      XLRAND_MASK, POWER9,    PPCNONE,        {RT, LRAND}},
6025
6026 {"dcba",        X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}},
6027 {"dcbal",       XOPL(31,758,1), XRT_MASK,    E500MC,    PPCNONE,        {RA0, RB}},
6028
6029 {"stfdux",      X(31,759),      X_MASK,      COM,       PPCEFS,         {FRS, RAS, RB}},
6030
6031 {"srliq",       XRC(31,760,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
6032 {"srliq.",      XRC(31,760,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
6033
6034 {"lvsm",        X(31,773),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
6035
6036 {"copy_first",  XOPL(31,774,1), XRT_MASK,    POWER9,    PPCNONE,        {RA0, RB}},
6037 {"copy",        X(31,774),      XLRT_MASK,   POWER9,    PPCNONE,        {RA0, RB, L}},
6038
6039 {"stvepxl",     X(31,775),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
6040 {"lvlxl",       X(31,775),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
6041 {"ldfcmux",     APU(31,775,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
6042
6043 {"dozo",        XO(31,264,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
6044 {"dozo.",       XO(31,264,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
6045
6046 {"addo",        XO(31,266,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
6047 {"caxo",        XO(31,266,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
6048 {"addo.",       XO(31,266,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
6049 {"caxo.",       XO(31,266,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
6050
6051 {"modsd",       X(31,777),      X_MASK,      POWER9,    PPCNONE,        {RT, RA, RB}},
6052 {"modsw",       X(31,779),      X_MASK,      POWER9,    PPCNONE,        {RT, RA, RB}},
6053
6054 {"lxvw4x",      X(31,780),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
6055 {"lxsibzx",     X(31,781),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XT6, RA0, RB}},
6056
6057 {"tabortwc.",   XRC(31,782,1),  X_MASK,      PPCHTM,    PPCNONE,        {TO, RA, RB}},
6058
6059 {"tlbivax",     X(31,786),      XRT_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}},
6060
6061 {"lwzcix",      X(31,789),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
6062
6063 {"lhbrx",       X(31,790),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
6064
6065 {"lfdpx",       X(31,791),      X_MASK,      POWER6,    POWER7,         {FRTp, RA0, RB}},
6066 {"lfqx",        X(31,791),      X_MASK,      POWER2,    PPCNONE,        {FRT, RA, RB}},
6067
6068 {"sraw",        XRC(31,792,0),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
6069 {"sra",         XRC(31,792,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
6070 {"sraw.",       XRC(31,792,1),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
6071 {"sra.",        XRC(31,792,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
6072
6073 {"srad",        XRC(31,794,0),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
6074 {"srad.",       XRC(31,794,1),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
6075
6076 {"lfddx",       X(31,803),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {FRT, RA, RB}},
6077
6078 {"lvtrxl",      X(31,805),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
6079 {"stvepx",      X(31,807),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
6080 {"lvrxl",       X(31,807),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
6081
6082 {"lxvh8x",      X(31,812),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XT6, RA0, RB}},
6083 {"lxsihzx",     X(31,813),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XT6, RA0, RB}},
6084
6085 {"tabortdc.",   XRC(31,814,1),  X_MASK,      PPCHTM,    PPCNONE,        {TO, RA, RB}},
6086
6087 {"rac",         X(31,818),      X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
6088
6089 {"erativax",    X(31,819),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA0, RB}},
6090
6091 {"lhzcix",      X(31,821),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
6092
6093 {"dss",         XDSS(31,822,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {STRM}},
6094
6095 {"lfqux",       X(31,823),      X_MASK,      POWER2,    PPCNONE,        {FRT, RA, RB}},
6096
6097 {"srawi",       XRC(31,824,0),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, SH}},
6098 {"srai",        XRC(31,824,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH}},
6099 {"srawi.",      XRC(31,824,1),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, SH}},
6100 {"srai.",       XRC(31,824,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH}},
6101
6102 {"sradi",       XS(31,413,0),   XS_MASK,     PPC64|PPCVLE, PPCNONE,     {RA, RS, SH6}},
6103 {"sradi.",      XS(31,413,1),   XS_MASK,     PPC64|PPCVLE, PPCNONE,     {RA, RS, SH6}},
6104
6105 {"lvtlxl",      X(31,837),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
6106
6107 {"cp_abort",    X(31,838),      XRTRARB_MASK,POWER9,    PPCNONE,        {0}},
6108
6109 {"divo",        XO(31,331,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
6110 {"divo.",       XO(31,331,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
6111
6112 {"lxvd2x",      X(31,844),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
6113 {"lxvx",        X(31,844),      XX1_MASK,    POWER8,    POWER9|PPCVSX3, {XT6, RA0, RB}},
6114
6115 {"tabortwci.",  XRC(31,846,1),  X_MASK,      PPCHTM,    PPCNONE,        {TO, RA, HTM_SI}},
6116
6117 {"tlbsrx.",     XRC(31,850,1),  XRT_MASK,    PPCA2,     PPCNONE,        {RA0, RB}},
6118
6119 {"slbmfev",     X(31,851),      XRLA_MASK,   POWER9,    PPCNONE,        {RT, RB, A_L}},
6120 {"slbmfev",     X(31,851),      XRA_MASK,    PPC64,     POWER9,         {RT, RB}},
6121
6122 {"lbzcix",      X(31,853),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
6123
6124 {"eieio",       X(31,854),      0xffffffff,  PPC,   BOOKE|PPCA2|PPC476, {0}},
6125 {"mbar",        X(31,854),      X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {MO}},
6126 {"eieio",       XMBAR(31,854,1),0xffffffff,  E500,      PPCNONE,        {0}},
6127 {"eieio",       X(31,854),      0xffffffff, PPCA2|PPC476, PPCNONE,      {0}},
6128
6129 {"lfiwax",      X(31,855),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, RA0, RB}},
6130
6131 {"lvswxl",      X(31,869),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
6132
6133 {"abso",        XO(31,360,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
6134 {"abso.",       XO(31,360,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
6135
6136 {"divso",       XO(31,363,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
6137 {"divso.",      XO(31,363,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
6138
6139 {"lxvb16x",     X(31,876),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XT6, RA0, RB}},
6140
6141 {"tabortdci.",  XRC(31,878,1),  X_MASK,      PPCHTM,    PPCNONE,        {TO, RA, HTM_SI}},
6142
6143 {"rmieg",       X(31,882),      XRTRA_MASK,  POWER9,    PPCNONE,        {RB}},
6144
6145 {"ldcix",       X(31,885),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
6146
6147 {"msgsync",     X(31,886),      0xffffffff,  POWER9,    PPCNONE,        {0}},
6148
6149 {"lfiwzx",      X(31,887),      X_MASK,   POWER7|PPCA2, PPCNONE,        {FRT, RA0, RB}},
6150
6151 {"extswsli",    XS(31,445,0),   XS_MASK,     POWER9,    PPCNONE,        {RA, RS, SH6}},
6152 {"extswsli.",   XS(31,445,1),   XS_MASK,     POWER9,    PPCNONE,        {RA, RS, SH6}},
6153
6154 {"paste",       XRC(31,902,0),  XLRT_MASK,   POWER9,    PPCNONE,        {RA0, RB, L0}},
6155 {"paste_last",  XRCL(31,902,1,1),XRT_MASK,   POWER9,    PPCNONE,        {RA0, RB}},
6156 {"paste.",      XRC(31,902,1),  XLRT_MASK,   POWER9,    PPCNONE,        {RA0, RB, L1}},
6157
6158 {"stvlxl",      X(31,903),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
6159 {"stdfcmux",    APU(31,903,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
6160
6161 {"divdeuo",     XO(31,393,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
6162 {"divdeuo.",    XO(31,393,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
6163 {"divweuo",     XO(31,395,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
6164 {"divweuo.",    XO(31,395,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
6165
6166 {"stxvw4x",     X(31,908),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA0, RB}},
6167 {"stxsibx",     X(31,909),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XS6, RA0, RB}},
6168
6169 {"tabort.",     XRC(31,910,1),  XRTRB_MASK,  PPCHTM,    PPCNONE,        {RA}},
6170
6171 {"tlbsx",       XRC(31,914,0),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}},
6172 {"tlbsx.",      XRC(31,914,1),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}},
6173
6174 {"slbmfee",     X(31,915),      XRLA_MASK,   POWER9,    PPCNONE,        {RT, RB, A_L}},
6175 {"slbmfee",     X(31,915),      XRA_MASK,    PPC64,     POWER9,         {RT, RB}},
6176
6177 {"stwcix",      X(31,917),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
6178
6179 {"sthbrx",      X(31,918),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
6180
6181 {"stfdpx",      X(31,919),      X_MASK,      POWER6,    POWER7,         {FRSp, RA0, RB}},
6182 {"stfqx",       X(31,919),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA0, RB}},
6183
6184 {"sraq",        XRC(31,920,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
6185 {"sraq.",       XRC(31,920,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
6186
6187 {"srea",        XRC(31,921,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
6188 {"srea.",       XRC(31,921,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
6189
6190 {"extsh",       XRC(31,922,0),  XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
6191 {"exts",        XRC(31,922,0),  XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
6192 {"extsh.",      XRC(31,922,1),  XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
6193 {"exts.",       XRC(31,922,1),  XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
6194
6195 {"stfddx",      X(31,931),      X_MASK,      E500MC,    PPCNONE,        {FRS, RA, RB}},
6196
6197 {"stvfrxl",     X(31,933),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
6198
6199 {"wclrone",     XOPL2(31,934,2),XRT_MASK,    PPCA2,     PPCNONE,        {RA0, RB}},
6200 {"wclrall",     X(31,934),      XRARB_MASK,  PPCA2,     PPCNONE,        {L}},
6201 {"wclr",        X(31,934),      X_MASK,      PPCA2,     PPCNONE,        {L, RA0, RB}},
6202
6203 {"stvrxl",      X(31,935),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
6204
6205 {"divdeo",      XO(31,425,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
6206 {"divdeo.",     XO(31,425,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
6207 {"divweo",      XO(31,427,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
6208 {"divweo.",     XO(31,427,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
6209
6210 {"stxvh8x",     X(31,940),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XS6, RA0, RB}},
6211 {"stxsihx",     X(31,941),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XS6, RA0, RB}},
6212
6213 {"treclaim.",   XRC(31,942,1),  XRTRB_MASK,  PPCHTM,    PPCNONE,        {RA}},
6214
6215 {"tlbrehi",     XTLB(31,946,0), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
6216 {"tlbrelo",     XTLB(31,946,1), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
6217 {"tlbre",       X(31,946),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
6218
6219 {"sthcix",      X(31,949),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
6220
6221 {"icswepx",     XRC(31,950,0),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
6222 {"icswepx.",    XRC(31,950,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
6223
6224 {"stfqux",      X(31,951),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA, RB}},
6225
6226 {"sraiq",       XRC(31,952,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
6227 {"sraiq.",      XRC(31,952,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
6228
6229 {"extsb",       XRC(31,954,0),  XRB_MASK, PPC|PPCVLE,   PPCNONE,        {RA, RS}},
6230 {"extsb.",      XRC(31,954,1),  XRB_MASK, PPC|PPCVLE,   PPCNONE,        {RA, RS}},
6231
6232 {"stvflxl",     X(31,965),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
6233
6234 {"iccci",       X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
6235 {"ici",         X(31,966),      XRARB_MASK,  PPCA2|PPC476|PPCVLE, PPCNONE, {CT}},
6236
6237 {"divduo",      XO(31,457,1,0), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
6238 {"divduo.",     XO(31,457,1,1), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
6239
6240 {"divwuo",      XO(31,459,1,0), XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
6241 {"divwuo.",     XO(31,459,1,1), XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
6242
6243 {"stxvd2x",     X(31,972),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA0, RB}},
6244 {"stxvx",       X(31,972),      XX1_MASK,    POWER8,    POWER9|PPCVSX3, {XS6, RA0, RB}},
6245
6246 {"tlbld",       X(31,978),      XRTRA_MASK,  PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
6247 {"tlbwehi",     XTLB(31,978,0), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
6248 {"tlbwelo",     XTLB(31,978,1), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
6249 {"tlbwe",       X(31,978),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
6250
6251 {"slbfee.",     XRC(31,979,1),  XRA_MASK,    POWER6,    PPCNONE,        {RT, RB}},
6252
6253 {"stbcix",      X(31,981),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
6254
6255 {"icbi",        X(31,982),      XRT_MASK,    PPC|PPCVLE, PPCNONE,       {RA0, RB}},
6256
6257 {"stfiwx",      X(31,983),      X_MASK,      PPC,       PPCEFS,         {FRS, RA0, RB}},
6258
6259 {"extsw",       XRC(31,986,0),  XRB_MASK, PPC64|PPCVLE, PPCNONE,        {RA, RS}},
6260 {"extsw.",      XRC(31,986,1),  XRB_MASK, PPC64|PPCVLE, PPCNONE,        {RA, RS}},
6261
6262 {"icbiep",      XRT(31,991,0),  XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
6263
6264 {"stvswxl",     X(31,997),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
6265
6266 {"icread",      X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCVLE, PPCNONE, {RA0, RB}},
6267
6268 {"nabso",       XO(31,488,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
6269 {"nabso.",      XO(31,488,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
6270
6271 {"divdo",       XO(31,489,1,0), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
6272 {"divdo.",      XO(31,489,1,1), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
6273
6274 {"divwo",       XO(31,491,1,0), XO_MASK,   PPC|PPCVLE,  PPCNONE,        {RT, RA, RB}},
6275 {"divwo.",      XO(31,491,1,1), XO_MASK,   PPC|PPCVLE,  PPCNONE,        {RT, RA, RB}},
6276
6277 {"stxvb16x",    X(31,1004),     XX1_MASK,    PPCVSX3,   PPCNONE,        {XS6, RA0, RB}},
6278
6279 {"trechkpt.",   XRC(31,1006,1), XRTRARB_MASK,PPCHTM,    PPCNONE,        {0}},
6280
6281 {"tlbli",       X(31,1010),     XRTRA_MASK,  PPC,       TITAN,          {RB}},
6282
6283 {"stdcix",      X(31,1013),     X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
6284
6285 {"dcbz",        X(31,1014),     XRT_MASK,    PPC|PPCVLE, PPCNONE,       {RA0, RB}},
6286 {"dclz",        X(31,1014),     XRT_MASK,    PPC,       PPCNONE,        {RA0, RB}},
6287
6288 {"dcbzep",      XRT(31,1023,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
6289
6290 {"dcbzl",       XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476,       {RA0, RB}},
6291
6292 {"cctpl",       0x7c210b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
6293 {"cctpm",       0x7c421378,     0xffffffff,  CELL,      PPCNONE,        {0}},
6294 {"cctph",       0x7c631b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
6295
6296 {"dstt",        XDSS(31,342,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
6297 {"dststt",      XDSS(31,374,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
6298 {"dssall",      XDSS(31,822,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {0}},
6299
6300 {"db8cyc",      0x7f9ce378,     0xffffffff,  CELL,      PPCNONE,        {0}},
6301 {"db10cyc",     0x7fbdeb78,     0xffffffff,  CELL,      PPCNONE,        {0}},
6302 {"db12cyc",     0x7fdef378,     0xffffffff,  CELL,      PPCNONE,        {0}},
6303 {"db16cyc",     0x7ffffb78,     0xffffffff,  CELL,      PPCNONE,        {0}},
6304
6305 {"lwz",         OP(32),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RA0}},
6306 {"l",           OP(32),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
6307
6308 {"lwzu",        OP(33),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RAL}},
6309 {"lu",          OP(33),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
6310
6311 {"lbz",         OP(34),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
6312
6313 {"lbzu",        OP(35),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
6314
6315 {"stw",         OP(36),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RA0}},
6316 {"st",          OP(36),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
6317
6318 {"stwu",        OP(37),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RAS}},
6319 {"stu",         OP(37),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
6320
6321 {"stb",         OP(38),         OP_MASK,     COM,       PPCNONE,        {RS, D, RA0}},
6322
6323 {"stbu",        OP(39),         OP_MASK,     COM,       PPCNONE,        {RS, D, RAS}},
6324
6325 {"lhz",         OP(40),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
6326
6327 {"lhzu",        OP(41),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
6328
6329 {"lha",         OP(42),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
6330
6331 {"lhau",        OP(43),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
6332
6333 {"sth",         OP(44),         OP_MASK,     COM,       PPCNONE,        {RS, D, RA0}},
6334
6335 {"sthu",        OP(45),         OP_MASK,     COM,       PPCNONE,        {RS, D, RAS}},
6336
6337 {"lmw",         OP(46),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RAM}},
6338 {"lm",          OP(46),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
6339
6340 {"stmw",        OP(47),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RA0}},
6341 {"stm",         OP(47),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
6342
6343 {"lfs",         OP(48),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RA0}},
6344
6345 {"lfsu",        OP(49),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RAS}},
6346
6347 {"lfd",         OP(50),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RA0}},
6348
6349 {"lfdu",        OP(51),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RAS}},
6350
6351 {"stfs",        OP(52),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RA0}},
6352
6353 {"stfsu",       OP(53),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RAS}},
6354
6355 {"stfd",        OP(54),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RA0}},
6356
6357 {"stfdu",       OP(55),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RAS}},
6358
6359 {"lq",          OP(56),         OP_MASK,     POWER4,    PPC476,         {RTQ, DQ, RAQ}},
6360 {"psq_l",       OP(56),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
6361 {"lfq",         OP(56),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
6362
6363 {"lxsd",        DSO(57,2),      DS_MASK,     PPCVSX3,   PPCNONE,        {VD, DS, RA0}},
6364 {"lxssp",       DSO(57,3),      DS_MASK,     PPCVSX3,   PPCNONE,        {VD, DS, RA0}},
6365 {"lfdp",        OP(57),         OP_MASK,     POWER6,    POWER7,         {FRTp, DS, RA0}},
6366 {"psq_lu",      OP(57),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
6367 {"lfqu",        OP(57),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
6368
6369 {"ld",          DSO(58,0),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RA0}},
6370 {"ldu",         DSO(58,1),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RAL}},
6371 {"lwa",         DSO(58,2),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RA0}},
6372
6373 {"dadd",        XRC(59,2,0),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
6374 {"dadd.",       XRC(59,2,1),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
6375
6376 {"dqua",        ZRC(59,3,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRT,FRA,FRB,RMC}},
6377 {"dqua.",       ZRC(59,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRT,FRA,FRB,RMC}},
6378
6379 {"fdivs",       A(59,18,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
6380 {"fdivs.",      A(59,18,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
6381
6382 {"fsubs",       A(59,20,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
6383 {"fsubs.",      A(59,20,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
6384
6385 {"fadds",       A(59,21,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
6386 {"fadds.",      A(59,21,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
6387
6388 {"fsqrts",      A(59,22,0),    AFRAFRC_MASK, PPC,       TITAN,          {FRT, FRB}},
6389 {"fsqrts.",     A(59,22,1),    AFRAFRC_MASK, PPC,       TITAN,          {FRT, FRB}},
6390
6391 {"fres",        A(59,24,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
6392 {"fres",        A(59,24,0),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
6393 {"fres.",       A(59,24,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
6394 {"fres.",       A(59,24,1),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
6395
6396 {"fmuls",       A(59,25,0),     AFRB_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRC}},
6397 {"fmuls.",      A(59,25,1),     AFRB_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRC}},
6398
6399 {"frsqrtes",    A(59,26,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
6400 {"frsqrtes",    A(59,26,0),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
6401 {"frsqrtes.",   A(59,26,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
6402 {"frsqrtes.",   A(59,26,1),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
6403
6404 {"fmsubs",      A(59,28,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
6405 {"fmsubs.",     A(59,28,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
6406
6407 {"fmadds",      A(59,29,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
6408 {"fmadds.",     A(59,29,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
6409
6410 {"fnmsubs",     A(59,30,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
6411 {"fnmsubs.",    A(59,30,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
6412
6413 {"fnmadds",     A(59,31,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
6414 {"fnmadds.",    A(59,31,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
6415
6416 {"dmul",        XRC(59,34,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
6417 {"dmul.",       XRC(59,34,1),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
6418
6419 {"drrnd",       ZRC(59,35,0),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
6420 {"drrnd.",      ZRC(59,35,1),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
6421
6422 {"dscli",       ZRC(59,66,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
6423 {"dscli.",      ZRC(59,66,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
6424
6425 {"dquai",       ZRC(59,67,0),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT,FRB,RMC}},
6426 {"dquai.",      ZRC(59,67,1),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT,FRB,RMC}},
6427
6428 {"dscri",       ZRC(59,98,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
6429 {"dscri.",      ZRC(59,98,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
6430
6431 {"drintx",      ZRC(59,99,0),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
6432 {"drintx.",     ZRC(59,99,1),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
6433
6434 {"dcmpo",       X(59,130),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
6435
6436 {"dtstex",      X(59,162),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
6437 {"dtstdc",      Z(59,194),      Z_MASK,      POWER6,    PPCNONE,        {BF,  FRA, DCM}},
6438 {"dtstdg",      Z(59,226),      Z_MASK,      POWER6,    PPCNONE,        {BF,  FRA, DGM}},
6439
6440 {"drintn",      ZRC(59,227,0),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
6441 {"drintn.",     ZRC(59,227,1),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
6442
6443 {"dctdp",       XRC(59,258,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
6444 {"dctdp.",      XRC(59,258,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
6445
6446 {"dctfix",      XRC(59,290,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
6447 {"dctfix.",     XRC(59,290,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
6448
6449 {"ddedpd",      XRC(59,322,0),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
6450 {"ddedpd.",     XRC(59,322,1),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
6451
6452 {"dxex",        XRC(59,354,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
6453 {"dxex.",       XRC(59,354,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
6454
6455 {"dsub",        XRC(59,514,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
6456 {"dsub.",       XRC(59,514,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
6457
6458 {"ddiv",        XRC(59,546,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
6459 {"ddiv.",       XRC(59,546,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
6460
6461 {"dcmpu",       X(59,642),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
6462
6463 {"dtstsf",      X(59,674),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
6464 {"dtstsfi",     X(59,675),      X_MASK|1<<22,POWER9,    PPCNONE,        {BF, UIM6, FRB}},
6465
6466 {"drsp",        XRC(59,770,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
6467 {"drsp.",       XRC(59,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
6468
6469 {"dcffix",      XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE,        {FRT, FRB}},
6470 {"dcffix.",     XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE,        {FRT, FRB}},
6471
6472 {"denbcd",      XRC(59,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
6473 {"denbcd.",     XRC(59,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
6474
6475 {"fcfids",      XRC(59,846,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6476 {"fcfids.",     XRC(59,846,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6477
6478 {"diex",        XRC(59,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
6479 {"diex.",       XRC(59,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
6480
6481 {"fcfidus",     XRC(59,974,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6482 {"fcfidus.",    XRC(59,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6483
6484 {"xsaddsp",     XX3(60,0),      XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6485 {"xsmaddasp",   XX3(60,1),      XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6486 {"xxsldwi",     XX3(60,2),      XX3SHW_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6, SHW}},
6487 {"xscmpeqdp",   XX3(60,3),      XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
6488 {"xsrsqrtesp",  XX2(60,10),     XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
6489 {"xssqrtsp",    XX2(60,11),     XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
6490 {"xxsel",       XX4(60,3),      XX4_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6, XC6}},
6491 {"xssubsp",     XX3(60,8),      XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6492 {"xsmaddmsp",   XX3(60,9),      XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6493 {"xxspltd",     XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCNONE,        {XT6, XA6, XB6S, DMEX}},
6494 {"xxmrghd",     XX3(60,10),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6495 {"xxswapd",     XX3(60,10)|(2<<8), XX3_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
6496 {"xxmrgld",     XX3(60,10)|(3<<8), XX3_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6497 {"xxpermdi",    XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCNONE,        {XT6, XA6, XB6, DM}},
6498 {"xscmpgtdp",   XX3(60,11),     XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
6499 {"xsresp",      XX2(60,26),     XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
6500 {"xsmulsp",     XX3(60,16),     XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6501 {"xsmsubasp",   XX3(60,17),     XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6502 {"xxmrghw",     XX3(60,18),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6503 {"xscmpgedp",   XX3(60,19),     XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
6504 {"xsdivsp",     XX3(60,24),     XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6505 {"xsmsubmsp",   XX3(60,25),     XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6506 {"xxperm",      XX3(60,26),     XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
6507 {"xsadddp",     XX3(60,32),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6508 {"xsmaddadp",   XX3(60,33),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6509 {"xscmpudp",    XX3(60,35),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
6510 {"xscvdpuxws",  XX2(60,72),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6511 {"xsrdpi",      XX2(60,73),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6512 {"xsrsqrtedp",  XX2(60,74),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6513 {"xssqrtdp",    XX2(60,75),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6514 {"xssubdp",     XX3(60,40),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6515 {"xsmaddmdp",   XX3(60,41),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6516 {"xscmpodp",    XX3(60,43),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
6517 {"xscvdpsxws",  XX2(60,88),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6518 {"xsrdpiz",     XX2(60,89),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6519 {"xsredp",      XX2(60,90),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6520 {"xsmuldp",     XX3(60,48),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6521 {"xsmsubadp",   XX3(60,49),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6522 {"xxmrglw",     XX3(60,50),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6523 {"xsrdpip",     XX2(60,105),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6524 {"xstsqrtdp",   XX2(60,106),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
6525 {"xsrdpic",     XX2(60,107),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6526 {"xsdivdp",     XX3(60,56),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6527 {"xsmsubmdp",   XX3(60,57),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6528 {"xxpermr",     XX3(60,58),     XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
6529 {"xscmpexpdp",  XX3(60,59),     XX3BF_MASK,  PPCVSX3,   PPCNONE,        {BF, XA6, XB6}},
6530 {"xsrdpim",     XX2(60,121),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6531 {"xstdivdp",    XX3(60,61),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
6532 {"xvaddsp",     XX3(60,64),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6533 {"xvmaddasp",   XX3(60,65),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6534 {"xvcmpeqsp",   XX3RC(60,67,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6535 {"xvcmpeqsp.",  XX3RC(60,67,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6536 {"xvcvspuxws",  XX2(60,136),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6537 {"xvrspi",      XX2(60,137),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6538 {"xvrsqrtesp",  XX2(60,138),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6539 {"xvsqrtsp",    XX2(60,139),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6540 {"xvsubsp",     XX3(60,72),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6541 {"xvmaddmsp",   XX3(60,73),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6542 {"xvcmpgtsp",   XX3RC(60,75,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6543 {"xvcmpgtsp.",  XX3RC(60,75,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6544 {"xvcvspsxws",  XX2(60,152),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6545 {"xvrspiz",     XX2(60,153),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6546 {"xvresp",      XX2(60,154),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6547 {"xvmulsp",     XX3(60,80),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6548 {"xvmsubasp",   XX3(60,81),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6549 {"xxspltw",     XX2(60,164),    XX2UIM_MASK, PPCVSX,    PPCNONE,        {XT6, XB6, UIM}},
6550 {"xxextractuw", XX2(60,165),    XX2UIM4_MASK,PPCVSX3,   PPCNONE,        {XT6, XB6, UIMM4}},
6551 {"xvcmpgesp",   XX3RC(60,83,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6552 {"xvcmpgesp.",  XX3RC(60,83,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6553 {"xvcvuxwsp",   XX2(60,168),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6554 {"xvrspip",     XX2(60,169),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6555 {"xvtsqrtsp",   XX2(60,170),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
6556 {"xvrspic",     XX2(60,171),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6557 {"xvdivsp",     XX3(60,88),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6558 {"xvmsubmsp",   XX3(60,89),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6559 {"xxspltib",    X(60,360),      XX1_MASK|3<<19, PPCVSX3,PPCNONE,        {XT6, IMM8}},
6560 {"xxinsertw",   XX2(60,181),    XX2UIM4_MASK,PPCVSX3,   PPCNONE,        {XT6, XB6, UIMM4}},
6561 {"xvcvsxwsp",   XX2(60,184),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6562 {"xvrspim",     XX2(60,185),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6563 {"xvtdivsp",    XX3(60,93),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
6564 {"xvadddp",     XX3(60,96),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6565 {"xvmaddadp",   XX3(60,97),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6566 {"xvcmpeqdp",   XX3RC(60,99,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6567 {"xvcmpeqdp.",  XX3RC(60,99,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6568 {"xvcvdpuxws",  XX2(60,200),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6569 {"xvrdpi",      XX2(60,201),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6570 {"xvrsqrtedp",  XX2(60,202),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6571 {"xvsqrtdp",    XX2(60,203),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6572 {"xvsubdp",     XX3(60,104),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6573 {"xvmaddmdp",   XX3(60,105),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6574 {"xvcmpgtdp",   XX3RC(60,107,0), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6575 {"xvcmpgtdp.",  XX3RC(60,107,1), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6576 {"xvcvdpsxws",  XX2(60,216),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6577 {"xvrdpiz",     XX2(60,217),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6578 {"xvredp",      XX2(60,218),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6579 {"xvmuldp",     XX3(60,112),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6580 {"xvmsubadp",   XX3(60,113),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6581 {"xvcmpgedp",   XX3RC(60,115,0), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6582 {"xvcmpgedp.",  XX3RC(60,115,1), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6583 {"xvcvuxwdp",   XX2(60,232),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6584 {"xvrdpip",     XX2(60,233),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6585 {"xvtsqrtdp",   XX2(60,234),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
6586 {"xvrdpic",     XX2(60,235),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6587 {"xvdivdp",     XX3(60,120),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6588 {"xvmsubmdp",   XX3(60,121),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6589 {"xvcvsxwdp",   XX2(60,248),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6590 {"xvrdpim",     XX2(60,249),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6591 {"xvtdivdp",    XX3(60,125),    XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
6592 {"xsmaxcdp",    XX3(60,128),    XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
6593 {"xsnmaddasp",  XX3(60,129),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6594 {"xxland",      XX3(60,130),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6595 {"xscvdpsp",    XX2(60,265),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6596 {"xscvdpspn",   XX2(60,267),    XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
6597 {"xsmincdp",    XX3(60,136),    XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
6598 {"xsnmaddmsp",  XX3(60,137),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6599 {"xxlandc",     XX3(60,138),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6600 {"xsrsp",       XX2(60,281),    XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
6601 {"xsmaxjdp",    XX3(60,144),    XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
6602 {"xsnmsubasp",  XX3(60,145),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6603 {"xxlor",       XX3(60,146),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6604 {"xscvuxdsp",   XX2(60,296),    XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
6605 {"xststdcsp",   XX2(60,298),    XX2BFD_MASK, PPCVSX3,   PPCNONE,        {BF, XB6, DCMX}},
6606 {"xsminjdp",    XX3(60,152),    XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
6607 {"xsnmsubmsp",  XX3(60,153),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6608 {"xxlxor",      XX3(60,154),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6609 {"xscvsxdsp",   XX2(60,312),    XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
6610 {"xsmaxdp",     XX3(60,160),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6611 {"xsnmaddadp",  XX3(60,161),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6612 {"xxlnor",      XX3(60,162),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6613 {"xscvdpuxds",  XX2(60,328),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6614 {"xscvspdp",    XX2(60,329),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6615 {"xscvspdpn",   XX2(60,331),    XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
6616 {"xsmindp",     XX3(60,168),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6617 {"xsnmaddmdp",  XX3(60,169),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6618 {"xxlorc",      XX3(60,170),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6619 {"xscvdpsxds",  XX2(60,344),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6620 {"xsabsdp",     XX2(60,345),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6621 {"xsxexpdp",    XX2VA(60,347,0),XX2_MASK|1,  PPCVSX3,   PPCNONE,        {RT, XB6}},
6622 {"xsxsigdp",    XX2VA(60,347,1),XX2_MASK|1,  PPCVSX3,   PPCNONE,        {RT, XB6}},
6623 {"xscvhpdp",    XX2VA(60,347,16),XX2_MASK,   PPCVSX3,   PPCNONE,        {XT6, XB6}},
6624 {"xscvdphp",    XX2VA(60,347,17),XX2_MASK,   PPCVSX3,   PPCNONE,        {XT6, XB6}},
6625 {"xscpsgndp",   XX3(60,176),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6626 {"xsnmsubadp",  XX3(60,177),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6627 {"xxlnand",     XX3(60,178),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6628 {"xscvuxddp",   XX2(60,360),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6629 {"xsnabsdp",    XX2(60,361),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6630 {"xststdcdp",   XX2(60,362),    XX2BFD_MASK, PPCVSX3,   PPCNONE,        {BF, XB6, DCMX}},
6631 {"xsnmsubmdp",  XX3(60,185),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6632 {"xxleqv",      XX3(60,186),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6633 {"xscvsxddp",   XX2(60,376),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6634 {"xsnegdp",     XX2(60,377),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6635 {"xvmaxsp",     XX3(60,192),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6636 {"xvnmaddasp",  XX3(60,193),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6637 {"xvcvspuxds",  XX2(60,392),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6638 {"xvcvdpsp",    XX2(60,393),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6639 {"xvminsp",     XX3(60,200),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6640 {"xvnmaddmsp",  XX3(60,201),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6641 {"xvcvspsxds",  XX2(60,408),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6642 {"xvabssp",     XX2(60,409),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6643 {"xvmovsp",     XX3(60,208),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
6644 {"xvcpsgnsp",   XX3(60,208),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6645 {"xvnmsubasp",  XX3(60,209),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6646 {"xvcvuxdsp",   XX2(60,424),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6647 {"xvnabssp",    XX2(60,425),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6648 {"xvtstdcsp",   XX2(60,426),    XX2DCMXS_MASK,PPCVSX3,  PPCNONE,        {XT6, XB6, DCMXS}},
6649 {"xviexpsp",    XX3(60,216),    XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
6650 {"xvnmsubmsp",  XX3(60,217),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6651 {"xvcvsxdsp",   XX2(60,440),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6652 {"xvnegsp",     XX2(60,441),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6653 {"xvmaxdp",     XX3(60,224),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6654 {"xvnmaddadp",  XX3(60,225),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6655 {"xvcvdpuxds",  XX2(60,456),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6656 {"xvcvspdp",    XX2(60,457),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6657 {"xsiexpdp",    X(60,918),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XT6, RA, RB}},
6658 {"xvmindp",     XX3(60,232),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6659 {"xvnmaddmdp",  XX3(60,233),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6660 {"xvcvdpsxds",  XX2(60,472),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6661 {"xvabsdp",     XX2(60,473),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6662 {"xvxexpdp",    XX2VA(60,475,0),XX2_MASK,    PPCVSX3,   PPCNONE,        {XT6, XB6}},
6663 {"xvxsigdp",    XX2VA(60,475,1),XX2_MASK,    PPCVSX3,   PPCNONE,        {XT6, XB6}},
6664 {"xxbrh",       XX2VA(60,475,7),XX2_MASK,    PPCVSX3,   PPCNONE,        {XT6, XB6}},
6665 {"xvxexpsp",    XX2VA(60,475,8),XX2_MASK,    PPCVSX3,   PPCNONE,        {XT6, XB6}},
6666 {"xvxsigsp",    XX2VA(60,475,9),XX2_MASK,    PPCVSX3,   PPCNONE,        {XT6, XB6}},
6667 {"xxbrw",       XX2VA(60,475,15),XX2_MASK,   PPCVSX3,   PPCNONE,        {XT6, XB6}},
6668 {"xxbrd",       XX2VA(60,475,23),XX2_MASK,   PPCVSX3,   PPCNONE,        {XT6, XB6}},
6669 {"xvcvhpsp",    XX2VA(60,475,24),XX2_MASK,   PPCVSX3,   PPCNONE,        {XT6, XB6}},
6670 {"xvcvsphp",    XX2VA(60,475,25),XX2_MASK,   PPCVSX3,   PPCNONE,        {XT6, XB6}},
6671 {"xxbrq",       XX2VA(60,475,31),XX2_MASK,   PPCVSX3,   PPCNONE,        {XT6, XB6}},
6672 {"xvmovdp",     XX3(60,240),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
6673 {"xvcpsgndp",   XX3(60,240),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6674 {"xvnmsubadp",  XX3(60,241),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6675 {"xvcvuxddp",   XX2(60,488),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6676 {"xvnabsdp",    XX2(60,489),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6677 {"xvtstdcdp",   XX2(60,490),    XX2DCMXS_MASK,PPCVSX3,  PPCNONE,        {XT6, XB6, DCMXS}},
6678 {"xviexpdp",    XX3(60,248),    XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
6679 {"xvnmsubmdp",  XX3(60,249),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6680 {"xvcvsxddp",   XX2(60,504),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6681 {"xvnegdp",     XX2(60,505),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6682
6683 {"psq_st",      OP(60),         OP_MASK,     PPCPS,     PPCNONE,        {FRS,PSD,RA,PSW,PSQ}},
6684 {"stfq",        OP(60),         OP_MASK,     POWER2,    PPCNONE,        {FRS, D, RA}},
6685
6686 {"lxv",         DQX(61,1),      DQX_MASK,    PPCVSX3,   PPCNONE,        {XTQ6, DQ, RA0}},
6687 {"stxv",        DQX(61,5),      DQX_MASK,    PPCVSX3,   PPCNONE,        {XSQ6, DQ, RA0}},
6688 {"stxsd",       DSO(61,2),      DS_MASK,     PPCVSX3,   PPCNONE,        {VS, DS, RA0}},
6689 {"stxssp",      DSO(61,3),      DS_MASK,     PPCVSX3,   PPCNONE,        {VS, DS, RA0}},
6690 {"stfdp",       OP(61),         OP_MASK,     POWER6,    POWER7,         {FRSp, DS, RA0}},
6691 {"psq_stu",     OP(61),         OP_MASK,     PPCPS,     PPCNONE,        {FRS,PSD,RA,PSW,PSQ}},
6692 {"stfqu",       OP(61),         OP_MASK,     POWER2,    PPCNONE,        {FRS, D, RA}},
6693
6694 {"std",         DSO(62,0),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RA0}},
6695 {"stdu",        DSO(62,1),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RAS}},
6696 {"stq",         DSO(62,2),      DS_MASK,     POWER4,    PPC476,         {RSQ, DS, RA0}},
6697
6698 {"fcmpu",       X(63,0),        XBF_MASK,    COM,       PPCEFS,         {BF, FRA, FRB}},
6699
6700 {"daddq",       XRC(63,2,0),    X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6701 {"daddq.",      XRC(63,2,1),    X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6702
6703 {"dquaq",       ZRC(63,3,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRAp, FRBp, RMC}},
6704 {"dquaq.",      ZRC(63,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRAp, FRBp, RMC}},
6705
6706 {"xsaddqp",     XRC(63,4,0),    X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
6707 {"xsaddqpo",    XRC(63,4,1),    X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
6708
6709 {"xsrqpi",      ZRC(63,5,0),    Z2_MASK,     PPCVSX3,   PPCNONE,        {R, VD, VB, RMC}},
6710 {"xsrqpix",     ZRC(63,5,1),    Z2_MASK,     PPCVSX3,   PPCNONE,        {R, VD, VB, RMC}},
6711
6712 {"fcpsgn",      XRC(63,8,0),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
6713 {"fcpsgn.",     XRC(63,8,1),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
6714
6715 {"frsp",        XRC(63,12,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6716 {"frsp.",       XRC(63,12,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6717
6718 {"fctiw",       XRC(63,14,0),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
6719 {"fcir",        XRC(63,14,0),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
6720 {"fctiw.",      XRC(63,14,1),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
6721 {"fcir.",       XRC(63,14,1),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
6722
6723 {"fctiwz",      XRC(63,15,0),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
6724 {"fcirz",       XRC(63,15,0),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
6725 {"fctiwz.",     XRC(63,15,1),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
6726 {"fcirz.",      XRC(63,15,1),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
6727
6728 {"fdiv",        A(63,18,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
6729 {"fd",          A(63,18,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
6730 {"fdiv.",       A(63,18,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
6731 {"fd.",         A(63,18,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
6732
6733 {"fsub",        A(63,20,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
6734 {"fs",          A(63,20,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
6735 {"fsub.",       A(63,20,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
6736 {"fs.",         A(63,20,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
6737
6738 {"fadd",        A(63,21,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
6739 {"fa",          A(63,21,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
6740 {"fadd.",       A(63,21,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
6741 {"fa.",         A(63,21,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
6742
6743 {"fsqrt",       A(63,22,0),    AFRAFRC_MASK, PPCPWR2,   TITAN,          {FRT, FRB}},
6744 {"fsqrt.",      A(63,22,1),    AFRAFRC_MASK, PPCPWR2,   TITAN,          {FRT, FRB}},
6745
6746 {"fsel",        A(63,23,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
6747 {"fsel.",       A(63,23,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
6748
6749 {"fre",         A(63,24,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
6750 {"fre",         A(63,24,0),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
6751 {"fre.",        A(63,24,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
6752 {"fre.",        A(63,24,1),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
6753
6754 {"fmul",        A(63,25,0),     AFRB_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRC}},
6755 {"fm",          A(63,25,0),     AFRB_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRC}},
6756 {"fmul.",       A(63,25,1),     AFRB_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRC}},
6757 {"fm.",         A(63,25,1),     AFRB_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRC}},
6758
6759 {"frsqrte",     A(63,26,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
6760 {"frsqrte",     A(63,26,0),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
6761 {"frsqrte.",    A(63,26,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
6762 {"frsqrte.",    A(63,26,1),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
6763
6764 {"fmsub",       A(63,28,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6765 {"fms",         A(63,28,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6766 {"fmsub.",      A(63,28,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6767 {"fms.",        A(63,28,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6768
6769 {"fmadd",       A(63,29,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6770 {"fma",         A(63,29,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6771 {"fmadd.",      A(63,29,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6772 {"fma.",        A(63,29,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6773
6774 {"fnmsub",      A(63,30,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6775 {"fnms",        A(63,30,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6776 {"fnmsub.",     A(63,30,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6777 {"fnms.",       A(63,30,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6778
6779 {"fnmadd",      A(63,31,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6780 {"fnma",        A(63,31,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6781 {"fnmadd.",     A(63,31,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6782 {"fnma.",       A(63,31,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6783
6784 {"fcmpo",       X(63,32),       XBF_MASK,    COM,       PPCEFS,         {BF, FRA, FRB}},
6785
6786 {"dmulq",       XRC(63,34,0),   X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6787 {"dmulq.",      XRC(63,34,1),   X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6788
6789 {"drrndq",      ZRC(63,35,0),   Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRA, FRBp, RMC}},
6790 {"drrndq.",     ZRC(63,35,1),   Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRA, FRBp, RMC}},
6791
6792 {"xsmulqp",     XRC(63,36,0),   X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
6793 {"xsmulqpo",    XRC(63,36,1),   X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
6794
6795 {"xsrqpxp",     Z(63,37),       Z2_MASK,     PPCVSX3,   PPCNONE,        {R, VD, VB, RMC}},
6796
6797 {"mtfsb1",      XRC(63,38,0),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
6798 {"mtfsb1.",     XRC(63,38,1),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
6799
6800 {"fneg",        XRC(63,40,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6801 {"fneg.",       XRC(63,40,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6802
6803 {"mcrfs",      X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE,        {BF, BFA}},
6804
6805 {"dscliq",      ZRC(63,66,0),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
6806 {"dscliq.",     ZRC(63,66,1),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
6807
6808 {"dquaiq",      ZRC(63,67,0),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRTp, FRBp, RMC}},
6809 {"dquaiq.",     ZRC(63,67,1),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRTp, FRBp, RMC}},
6810
6811 {"mtfsb0",      XRC(63,70,0),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
6812 {"mtfsb0.",     XRC(63,70,1),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
6813
6814 {"fmr",         XRC(63,72,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6815 {"fmr.",        XRC(63,72,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6816
6817 {"dscriq",      ZRC(63,98,0),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
6818 {"dscriq.",     ZRC(63,98,1),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
6819
6820 {"drintxq",     ZRC(63,99,0),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
6821 {"drintxq.",    ZRC(63,99,1),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
6822
6823 {"xscpsgnqp",   X(63,100),      X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
6824
6825 {"ftdiv",       X(63,128),      XBF_MASK,    POWER7,    PPCNONE,        {BF, FRA, FRB}},
6826
6827 {"dcmpoq",      X(63,130),      X_MASK,      POWER6,    PPCNONE,        {BF, FRAp, FRBp}},
6828
6829 {"xscmpoqp",    X(63,132),      XBF_MASK,    PPCVSX3,   PPCNONE,        {BF, VA, VB}},
6830
6831 {"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
6832 {"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
6833 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
6834 {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
6835
6836 {"fnabs",       XRC(63,136,0),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6837 {"fnabs.",      XRC(63,136,1),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6838
6839 {"fctiwu",      XRC(63,142,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
6840 {"fctiwu.",     XRC(63,142,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
6841 {"fctiwuz",     XRC(63,143,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
6842 {"fctiwuz.",    XRC(63,143,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
6843
6844 {"ftsqrt",      X(63,160),      XBF_MASK|FRA_MASK, POWER7, PPCNONE,     {BF, FRB}},
6845
6846 {"dtstexq",     X(63,162),      X_MASK,      POWER6,    PPCNONE,        {BF, FRAp, FRBp}},
6847
6848 {"xscmpexpqp",  X(63,164),      XBF_MASK,    PPCVSX3,   PPCNONE,        {BF, VA, VB}},
6849
6850 {"dtstdcq",     Z(63,194),      Z_MASK,      POWER6,    PPCNONE,        {BF, FRAp, DCM}},
6851 {"dtstdgq",     Z(63,226),      Z_MASK,      POWER6,    PPCNONE,        {BF, FRAp, DGM}},
6852
6853 {"drintnq",     ZRC(63,227,0),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
6854 {"drintnq.",    ZRC(63,227,1),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
6855
6856 {"dctqpq",      XRC(63,258,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
6857 {"dctqpq.",     XRC(63,258,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
6858
6859 {"fabs",        XRC(63,264,0),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6860 {"fabs.",       XRC(63,264,1),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6861
6862 {"dctfixq",     XRC(63,290,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
6863 {"dctfixq.",    XRC(63,290,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
6864
6865 {"ddedpdq",     XRC(63,322,0),  X_MASK,      POWER6,    PPCNONE,        {SP, FRTp, FRBp}},
6866 {"ddedpdq.",    XRC(63,322,1),  X_MASK,      POWER6,    PPCNONE,        {SP, FRTp, FRBp}},
6867
6868 {"dxexq",       XRC(63,354,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
6869 {"dxexq.",      XRC(63,354,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
6870
6871 {"xsmaddqp",    XRC(63,388,0),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
6872 {"xsmaddqpo",   XRC(63,388,1),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
6873
6874 {"frin",        XRC(63,392,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6875 {"frin.",       XRC(63,392,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6876
6877 {"xsmsubqp",    XRC(63,420,0),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
6878 {"xsmsubqpo",   XRC(63,420,1),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
6879
6880 {"friz",        XRC(63,424,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6881 {"friz.",       XRC(63,424,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6882
6883 {"xsnmaddqp",   XRC(63,452,0),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
6884 {"xsnmaddqpo",  XRC(63,452,1),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
6885
6886 {"frip",        XRC(63,456,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6887 {"frip.",       XRC(63,456,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6888
6889 {"xsnmsubqp",   XRC(63,484,0),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
6890 {"xsnmsubqpo",  XRC(63,484,1),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
6891
6892 {"frim",        XRC(63,488,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6893 {"frim.",       XRC(63,488,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6894
6895 {"dsubq",       XRC(63,514,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6896 {"dsubq.",      XRC(63,514,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6897
6898 {"xssubqp",     XRC(63,516,0),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
6899 {"xssubqpo",    XRC(63,516,1),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
6900
6901 {"ddivq",       XRC(63,546,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6902 {"ddivq.",      XRC(63,546,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6903
6904 {"xsdivqp",     XRC(63,548,0),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
6905 {"xsdivqpo",    XRC(63,548,1),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
6906
6907 {"mffs",        XRC(63,583,0),  XRARB_MASK,  COM,       PPCEFS,         {FRT}},
6908 {"mffs.",       XRC(63,583,1),  XRARB_MASK,  COM,       PPCEFS,         {FRT}},
6909
6910 {"dcmpuq",      X(63,642),      X_MASK,      POWER6,    PPCNONE,        {BF, FRAp, FRBp}},
6911
6912 {"xscmpuqp",    X(63,644),      XBF_MASK,    PPCVSX3,   PPCNONE,        {BF, VA, VB}},
6913
6914 {"dtstsfq",     X(63,674),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRBp}},
6915 {"dtstsfiq",    X(63,675),      X_MASK|1<<22,POWER9,    PPCNONE,        {BF, UIM6, FRBp}},
6916
6917 {"xststdcqp",   X(63,708),      X_MASK,      PPCVSX3,   PPCNONE,        {BF, VB, DCMX}},
6918
6919 {"mtfsf",       XFL(63,711,0),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
6920 {"mtfsf",       XFL(63,711,0),  XFL_MASK,    COM, POWER6|PPCA2|PPC476|PPCEFS,   {FLM, FRB}},
6921 {"mtfsf.",      XFL(63,711,1),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
6922 {"mtfsf.",      XFL(63,711,1),  XFL_MASK,    COM, POWER6|PPCA2|PPC476|PPCEFS,   {FLM, FRB}},
6923
6924 {"drdpq",       XRC(63,770,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRBp}},
6925 {"drdpq.",      XRC(63,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRBp}},
6926
6927 {"dcffixq",     XRC(63,802,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
6928 {"dcffixq.",    XRC(63,802,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
6929
6930 {"xsabsqp",     XVA(63,804,0),  XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
6931 {"xsxexpqp",    XVA(63,804,2),  XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
6932 {"xsnabsqp",    XVA(63,804,8),  XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
6933 {"xsnegqp",     XVA(63,804,16), XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
6934 {"xsxsigqp",    XVA(63,804,18), XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
6935 {"xssqrtqp",    XVARC(63,804,27,0), XVA_MASK, PPCVSX3,  PPCNONE,        {VD, VB}},
6936 {"xssqrtqpo",   XVARC(63,804,27,1), XVA_MASK, PPCVSX3,  PPCNONE,        {VD, VB}},
6937
6938 {"fctid",       XRC(63,814,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6939 {"fctid",       XRC(63,814,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6940 {"fctid.",      XRC(63,814,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6941 {"fctid.",      XRC(63,814,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6942
6943 {"fctidz",      XRC(63,815,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6944 {"fctidz",      XRC(63,815,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6945 {"fctidz.",     XRC(63,815,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6946 {"fctidz.",     XRC(63,815,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6947
6948 {"denbcdq",     XRC(63,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRTp, FRBp}},
6949 {"denbcdq.",    XRC(63,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRTp, FRBp}},
6950
6951 {"xscvqpuwz",   XVA(63,836,1),  XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
6952 {"xscvudqp",    XVA(63,836,2),  XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
6953 {"xscvqpswz",   XVA(63,836,9),  XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
6954 {"xscvsdqp",    XVA(63,836,10), XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
6955 {"xscvqpudz",   XVA(63,836,17), XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
6956 {"xscvqpdp",    XVARC(63,836,20,0), XVA_MASK, PPCVSX3,  PPCNONE,        {VD, VB}},
6957 {"xscvqpdpo",   XVARC(63,836,20,1), XVA_MASK, PPCVSX3,  PPCNONE,        {VD, VB}},
6958 {"xscvdpqp",    XVA(63,836,22), XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
6959 {"xscvqpsdz",   XVA(63,836,25), XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
6960
6961 {"fmrgow",      X(63,838),      X_MASK,      PPCVSX2,   PPCNONE,        {FRT, FRA, FRB}},
6962
6963 {"fcfid",       XRC(63,846,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6964 {"fcfid",       XRC(63,846,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6965 {"fcfid.",      XRC(63,846,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6966 {"fcfid.",      XRC(63,846,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6967
6968 {"diexq",       XRC(63,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRA, FRBp}},
6969 {"diexq.",      XRC(63,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRA, FRBp}},
6970
6971 {"xsiexpqp",    X(63,868),      X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
6972
6973 {"fctidu",      XRC(63,942,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6974 {"fctidu.",     XRC(63,942,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6975
6976 {"fctiduz",     XRC(63,943,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6977 {"fctiduz.",    XRC(63,943,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6978
6979 {"fmrgew",      X(63,966),      X_MASK,      PPCVSX2,   PPCNONE,        {FRT, FRA, FRB}},
6980
6981 {"fcfidu",      XRC(63,974,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6982 {"fcfidu.",     XRC(63,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6983 };
6984
6985 const int powerpc_num_opcodes =
6986   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
6987 \f
6988 /* The VLE opcode table.
6989
6990    The format of this opcode table is the same as the main opcode table.  */
6991
6992 const struct powerpc_opcode vle_opcodes[] = {
6993
6994 {"se_illegal",  C(0),           C_MASK,         PPCVLE, PPCNONE,        {}},
6995 {"se_isync",    C(1),           C_MASK,         PPCVLE, PPCNONE,        {}},
6996 {"se_sc",       C(2),           C_MASK,         PPCVLE, PPCNONE,        {}},
6997 {"se_blr",      C_LK(2,0),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
6998 {"se_blrl",     C_LK(2,1),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
6999 {"se_bctr",     C_LK(3,0),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
7000 {"se_bctrl",    C_LK(3,1),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
7001 {"se_rfi",      C(8),           C_MASK,         PPCVLE, PPCNONE,        {}},
7002 {"se_rfci",     C(9),           C_MASK,         PPCVLE, PPCNONE,        {}},
7003 {"se_rfdi",     C(10),          C_MASK,         PPCVLE, PPCNONE,        {}},
7004 {"se_rfmci",    C(11),          C_MASK,         PPCVLE, PPCNONE,        {}},
7005 {"se_not",      SE_R(0,2),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
7006 {"se_neg",      SE_R(0,3),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
7007 {"se_mflr",     SE_R(0,8),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
7008 {"se_mtlr",     SE_R(0,9),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
7009 {"se_mfctr",    SE_R(0,10),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
7010 {"se_mtctr",    SE_R(0,11),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
7011 {"se_extzb",    SE_R(0,12),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
7012 {"se_extsb",    SE_R(0,13),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
7013 {"se_extzh",    SE_R(0,14),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
7014 {"se_extsh",    SE_R(0,15),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
7015 {"se_mr",       SE_RR(0,1),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
7016 {"se_mtar",     SE_RR(0,2),     SE_RR_MASK,     PPCVLE, PPCNONE,        {ARX, RY}},
7017 {"se_mfar",     SE_RR(0,3),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, ARY}},
7018 {"se_add",      SE_RR(1,0),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
7019 {"se_mullw",    SE_RR(1,1),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
7020 {"se_sub",      SE_RR(1,2),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
7021 {"se_subf",     SE_RR(1,3),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
7022 {"se_cmp",      SE_RR(3,0),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
7023 {"se_cmpl",     SE_RR(3,1),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
7024 {"se_cmph",     SE_RR(3,2),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
7025 {"se_cmphl",    SE_RR(3,3),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
7026
7027 {"e_cmpi",      SCI8BF(6,0,21), SCI8BF_MASK,    PPCVLE, PPCNONE,        {CRD32, RA, SCLSCI8}},
7028 {"e_cmpli",     SCI8BF(6,1,21), SCI8BF_MASK,    PPCVLE, PPCNONE,        {CRD32, RA, SCLSCI8}},
7029 {"e_addi",      SCI8(6,16),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
7030 {"e_subi",      SCI8(6,16),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8N}},
7031 {"e_addi.",     SCI8(6,17),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
7032 {"e_addic",     SCI8(6,18),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
7033 {"e_subic",     SCI8(6,18),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8N}},
7034 {"e_addic.",    SCI8(6,19),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
7035 {"e_subic.",    SCI8(6,19),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8N}},
7036 {"e_mulli",     SCI8(6,20),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
7037 {"e_subfic",    SCI8(6,22),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
7038 {"e_subfic.",   SCI8(6,23),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
7039 {"e_andi",      SCI8(6,24),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
7040 {"e_andi.",     SCI8(6,25),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
7041 {"e_nop",       SCI8(6,26),     0xffffffff,     PPCVLE, PPCNONE,        {0}},
7042 {"e_ori",       SCI8(6,26),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
7043 {"e_ori.",      SCI8(6,27),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
7044 {"e_xori",      SCI8(6,28),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
7045 {"e_xori.",     SCI8(6,29),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
7046 {"e_lbzu",      OPVUP(6,0),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
7047 {"e_lhau",      OPVUP(6,3),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
7048 {"e_lhzu",      OPVUP(6,1),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
7049 {"e_lmw",       OPVUP(6,8),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
7050 {"e_lwzu",      OPVUP(6,2),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
7051 {"e_stbu",      OPVUP(6,4),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
7052 {"e_sthu",      OPVUP(6,5),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
7053 {"e_stwu",      OPVUP(6,6),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
7054 {"e_stmw",      OPVUP(6,9),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
7055 {"e_add16i",    OP(7),          OP_MASK,        PPCVLE, PPCNONE,        {RT, RA, SI}},
7056 {"e_la",        OP(7),          OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
7057 {"e_sub16i",    OP(7),          OP_MASK,        PPCVLE, PPCNONE,        {RT, RA, NSI}},
7058
7059 {"se_addi",     SE_IM5(8,0),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
7060 {"se_cmpli",    SE_IM5(8,1),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
7061 {"se_subi",     SE_IM5(9,0),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
7062 {"se_subi.",    SE_IM5(9,1),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
7063 {"se_cmpi",     SE_IM5(10,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
7064 {"se_bmaski",   SE_IM5(11,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
7065 {"se_andi",     SE_IM5(11,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
7066
7067 {"e_lbz",       OP(12),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
7068 {"e_stb",       OP(13),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
7069 {"e_lha",       OP(14),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
7070
7071 {"se_srw",      SE_RR(16,0),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
7072 {"se_sraw",     SE_RR(16,1),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
7073 {"se_slw",      SE_RR(16,2),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
7074 {"se_nop",      SE_RR(17,0),    0xffff,         PPCVLE, PPCNONE,        {0}},
7075 {"se_or",       SE_RR(17,0),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
7076 {"se_andc",     SE_RR(17,1),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
7077 {"se_and",      SE_RR(17,2),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
7078 {"se_and.",     SE_RR(17,3),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
7079 {"se_li",       IM7(9),         IM7_MASK,       PPCVLE, PPCNONE,        {RX, UI7}},
7080
7081 {"e_lwz",       OP(20),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
7082 {"e_stw",       OP(21),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
7083 {"e_lhz",       OP(22),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
7084 {"e_sth",       OP(23),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
7085
7086 {"se_bclri",    SE_IM5(24,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
7087 {"se_bgeni",    SE_IM5(24,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
7088 {"se_bseti",    SE_IM5(25,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
7089 {"se_btsti",    SE_IM5(25,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
7090 {"se_srwi",     SE_IM5(26,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
7091 {"se_srawi",    SE_IM5(26,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
7092 {"se_slwi",     SE_IM5(27,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
7093
7094 {"e_lis",       I16L(28,28),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
7095 {"e_and2is.",   I16L(28,29),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
7096 {"e_or2is",     I16L(28,26),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
7097 {"e_and2i.",    I16L(28,25),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
7098 {"e_or2i",      I16L(28,24),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
7099 {"e_cmphl16i",  IA16(28,23),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLEUIMM}},
7100 {"e_cmph16i",   IA16(28,22),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
7101 {"e_cmpl16i",   I16A(28,21),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLEUIMM}},
7102 {"e_cmplwi",    I16A(28,21),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
7103 {"e_mull2i",    I16A(28,20),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
7104 {"e_cmp16i",    IA16(28,19),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
7105 {"e_cmpwi",     IA16(28,19),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
7106 {"e_sub2is",    I16A(28,18),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLENSIMM}},
7107 {"e_add2is",    I16A(28,18),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
7108 {"e_sub2i.",    I16A(28,17),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLENSIMM}},
7109 {"e_add2i.",    I16A(28,17),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
7110 {"e_li",        LI20(28,0),     LI20_MASK,      PPCVLE, PPCNONE,        {RT, IMM20}},
7111 {"e_rlwimi",    M(29,0),        M_MASK,         PPCVLE, PPCNONE,        {RA, RS, SH, MB, ME}},
7112 {"e_rlwinm",    M(29,1),        M_MASK,         PPCVLE, PPCNONE,        {RA, RT, SH, MBE, ME}},
7113 {"e_b",         BD24(30,0,0),   BD24_MASK,      PPCVLE, PPCNONE,        {B24}},
7114 {"e_bl",        BD24(30,0,1),   BD24_MASK,      PPCVLE, PPCNONE,        {B24}},
7115 {"e_bdnz",      EBD15(30,8,BO32DNZ,0),  EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
7116 {"e_bdnzl",     EBD15(30,8,BO32DNZ,1),  EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
7117 {"e_bdz",       EBD15(30,8,BO32DZ,0),   EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
7118 {"e_bdzl",      EBD15(30,8,BO32DZ,1),   EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
7119 {"e_bge",       EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7120 {"e_bgel",      EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7121 {"e_bnl",       EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7122 {"e_bnll",      EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7123 {"e_blt",       EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7124 {"e_bltl",      EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7125 {"e_bgt",       EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7126 {"e_bgtl",      EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7127 {"e_ble",       EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7128 {"e_blel",      EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7129 {"e_bng",       EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7130 {"e_bngl",      EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7131 {"e_bne",       EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7132 {"e_bnel",      EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7133 {"e_beq",       EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7134 {"e_beql",      EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7135 {"e_bso",       EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7136 {"e_bsol",      EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7137 {"e_bun",       EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7138 {"e_bunl",      EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7139 {"e_bns",       EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7140 {"e_bnsl",      EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7141 {"e_bnu",       EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7142 {"e_bnul",      EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
7143 {"e_bc",        BD15(30,8,0),   BD15_MASK,      PPCVLE, PPCNONE,        {BO32, BI32, B15}},
7144 {"e_bcl",       BD15(30,8,1),   BD15_MASK,      PPCVLE, PPCNONE,        {BO32, BI32, B15}},
7145
7146 {"e_bf",        EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
7147 {"e_bfl",       EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
7148 {"e_bt",        EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
7149 {"e_btl",       EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
7150
7151 {"e_cmph",      X(31,14),       X_MASK,         PPCVLE, PPCNONE,        {CRD, RA, RB}},
7152 {"e_cmphl",     X(31,46),       X_MASK,         PPCVLE, PPCNONE,        {CRD, RA, RB}},
7153 {"e_crandc",    XL(31,129),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
7154 {"e_crnand",    XL(31,225),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
7155 {"e_crnot",     XL(31,33),      XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BBA}},
7156 {"e_crnor",     XL(31,33),      XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
7157 {"e_crclr",     XL(31,193),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BAT, BBA}},
7158 {"e_crxor",     XL(31,193),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
7159 {"e_mcrf",      XL(31,16),      XL_MASK,        PPCVLE, PPCNONE,        {CRD, CR}},
7160 {"e_slwi",      EX(31,112),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
7161 {"e_slwi.",     EX(31,113),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
7162
7163 {"e_crand",     XL(31,257),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
7164
7165 {"e_rlw",       EX(31,560),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, RB}},
7166 {"e_rlw.",      EX(31,561),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, RB}},
7167
7168 {"e_crset",     XL(31,289),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BAT, BBA}},
7169 {"e_creqv",     XL(31,289),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
7170
7171 {"e_rlwi",      EX(31,624),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
7172 {"e_rlwi.",     EX(31,625),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
7173
7174 {"e_crorc",     XL(31,417),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
7175
7176 {"e_crmove",    XL(31,449),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BBA}},
7177 {"e_cror",      XL(31,449),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
7178
7179 {"mtmas1",      XSPR(31,467,625), XSPR_MASK,    PPCVLE, PPCNONE,        {RS}},
7180
7181 {"e_srwi",      EX(31,1136),    EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
7182 {"e_srwi.",     EX(31,1137),    EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
7183
7184 {"se_lbz",      SD4(8),         SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SD, RX}},
7185
7186 {"se_stb",      SD4(9),         SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SD, RX}},
7187
7188 {"se_lhz",      SD4(10),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDH, RX}},
7189
7190 {"se_sth",      SD4(11),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDH, RX}},
7191
7192 {"se_lwz",      SD4(12),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDW, RX}},
7193
7194 {"se_stw",      SD4(13),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDW, RX}},
7195
7196 {"se_bge",      EBD8IO(28,0,0), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
7197 {"se_bnl",      EBD8IO(28,0,0), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
7198 {"se_ble",      EBD8IO(28,0,1), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
7199 {"se_bng",      EBD8IO(28,0,1), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
7200 {"se_bne",      EBD8IO(28,0,2), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
7201 {"se_bns",      EBD8IO(28,0,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
7202 {"se_bnu",      EBD8IO(28,0,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
7203 {"se_bf",       EBD8IO(28,0,0), EBD8IO2_MASK,   PPCVLE, PPCNONE,        {BI16, B8}},
7204 {"se_blt",      EBD8IO(28,1,0), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
7205 {"se_bgt",      EBD8IO(28,1,1), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
7206 {"se_beq",      EBD8IO(28,1,2), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
7207 {"se_bso",      EBD8IO(28,1,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
7208 {"se_bun",      EBD8IO(28,1,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
7209 {"se_bt",       EBD8IO(28,1,0), EBD8IO2_MASK,   PPCVLE, PPCNONE,        {BI16, B8}},
7210 {"se_bc",       BD8IO(28),      BD8IO_MASK,     PPCVLE, PPCNONE,        {BO16, BI16, B8}},
7211 {"se_b",        BD8(58,0,0),    BD8_MASK,       PPCVLE, PPCNONE,        {B8}},
7212 {"se_bl",       BD8(58,0,1),    BD8_MASK,       PPCVLE, PPCNONE,        {B8}},
7213 };
7214
7215 const int vle_num_opcodes =
7216   sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);
7217 \f
7218 /* The macro table.  This is only used by the assembler.  */
7219
7220 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
7221    when x=0; 32-x when x is between 1 and 31; are negative if x is
7222    negative; and are 32 or more otherwise.  This is what you want
7223    when, for instance, you are emulating a right shift by a
7224    rotate-left-and-mask, because the underlying instructions support
7225    shifts of size 0 but not shifts of size 32.  By comparison, when
7226    extracting x bits from some word you want to use just 32-x, because
7227    the underlying instructions don't support extracting 0 bits but do
7228    support extracting the whole word (32 bits in this case).  */
7229
7230 const struct powerpc_macro powerpc_macros[] = {
7231 {"extldi",   4, PPC64,  "rldicr %0,%1,%3,(%2)-1"},
7232 {"extldi.",  4, PPC64,  "rldicr. %0,%1,%3,(%2)-1"},
7233 {"extrdi",   4, PPC64,  "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
7234 {"extrdi.",  4, PPC64,  "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
7235 {"insrdi",   4, PPC64,  "rldimi %0,%1,64-((%2)+(%3)),%3"},
7236 {"insrdi.",  4, PPC64,  "rldimi. %0,%1,64-((%2)+(%3)),%3"},
7237 {"rotrdi",   3, PPC64,  "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
7238 {"rotrdi.",  3, PPC64,  "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
7239 {"sldi",     3, PPC64,  "rldicr %0,%1,%2,63-(%2)"},
7240 {"sldi.",    3, PPC64,  "rldicr. %0,%1,%2,63-(%2)"},
7241 {"srdi",     3, PPC64,  "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
7242 {"srdi.",    3, PPC64,  "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
7243 {"clrrdi",   3, PPC64,  "rldicr %0,%1,0,63-(%2)"},
7244 {"clrrdi.",  3, PPC64,  "rldicr. %0,%1,0,63-(%2)"},
7245 {"clrlsldi", 4, PPC64,  "rldic %0,%1,%3,(%2)-(%3)"},
7246 {"clrlsldi.",4, PPC64,  "rldic. %0,%1,%3,(%2)-(%3)"},
7247
7248 {"extlwi",   4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
7249 {"extlwi.",  4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
7250 {"extrwi",   4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7251 {"extrwi.",  4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7252 {"inslwi",   4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7253 {"inslwi.",  4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7254 {"insrwi",   4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7255 {"insrwi.",  4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7256 {"rotrwi",   3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7257 {"rotrwi.",  3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7258 {"slwi",     3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
7259 {"sli",      3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
7260 {"slwi.",    3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
7261 {"sli.",     3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
7262 {"srwi",     3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7263 {"sri",      3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7264 {"srwi.",    3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7265 {"sri.",     3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7266 {"clrrwi",   3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
7267 {"clrrwi.",  3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
7268 {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
7269 {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
7270
7271 {"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
7272 {"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7273 {"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7274 {"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7275 {"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
7276 {"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7277 {"e_slwi",   3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
7278 {"e_srwi",   3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7279 {"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
7280 {"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
7281 {"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
7282 };
7283
7284 const int powerpc_num_macros =
7285   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);