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* sparc-opc.c (sparc_opcodes, prefetcha insn): Fix.
[thirdparty/binutils-gdb.git] / opcodes / sparc-dis.c
1 /* Print SPARC instructions.
2 Copyright 1989, 1991, 1992, 1993, 1995 Free Software Foundation, Inc.
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17
18 #include "ansidecl.h"
19 #include "opcode/sparc.h"
20 #include "dis-asm.h"
21 #include "libiberty.h"
22 #include <string.h>
23
24 /* For faster lookup, after insns are sorted they are hashed. */
25 /* ??? I think there is room for even more improvement. */
26
27 #define HASH_SIZE 256
28 /* It is important that we only look at insn code bits as that is how the
29 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
30 of the main types (0,1,2,3). */
31 static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
32 #define HASH_INSN(INSN) \
33 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
34 struct opcode_hash {
35 struct opcode_hash *next;
36 struct sparc_opcode *opcode;
37 };
38 static struct opcode_hash *opcode_hash_table[HASH_SIZE];
39 static void build_hash_table ();
40
41 /* Sign-extend a value which is N bits long. */
42 #define SEX(value, bits) \
43 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
44 >> ((8 * sizeof (int)) - bits) )
45
46 static char *reg_names[] =
47 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
48 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
49 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
50 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
51 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
52 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
53 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
54 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
55 #ifndef NO_V9
56 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
57 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
58 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
59 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
60 /* psr, wim, tbr, fpsr, cpsr are v8 only. */
61 #endif
62 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
63 };
64
65 #define freg_names (&reg_names[4 * 8])
66
67 #ifndef NO_V9
68 /* These are ordered according to there register number in
69 rdpr and wrpr insns. */
70 static char *v9_priv_reg_names[] =
71 {
72 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
73 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
74 "wstate", "fq"
75 /* "ver" - special cased */
76 };
77 #endif
78
79 /* Macros used to extract instruction fields. Not all fields have
80 macros defined here, only those which are actually used. */
81
82 #define X_RD(i) (((i) >> 25) & 0x1f)
83 #define X_RS1(i) (((i) >> 14) & 0x1f)
84 #define X_LDST_I(i) (((i) >> 13) & 1)
85 #define X_ASI(i) (((i) >> 5) & 0xff)
86 #define X_RS2(i) (((i) >> 0) & 0x1f)
87 #define X_IMM13(i) (((i) >> 0) & 0x1fff)
88 #define X_DISP22(i) (((i) >> 0) & 0x3fffff)
89 #define X_IMM22(i) X_DISP22 (i)
90 #define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
91
92 #ifndef NO_V9
93 #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
94 #define X_MEMBAR(i) ((i) & 0x7f)
95 #endif
96
97 /* Here is the union which was used to extract instruction fields
98 before the shift and mask macros were written.
99
100 union sparc_insn
101 {
102 unsigned long int code;
103 struct
104 {
105 unsigned int anop:2;
106 #define op ldst.anop
107 unsigned int anrd:5;
108 #define rd ldst.anrd
109 unsigned int op3:6;
110 unsigned int anrs1:5;
111 #define rs1 ldst.anrs1
112 unsigned int i:1;
113 unsigned int anasi:8;
114 #define asi ldst.anasi
115 unsigned int anrs2:5;
116 #define rs2 ldst.anrs2
117 #define shcnt rs2
118 } ldst;
119 struct
120 {
121 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
122 unsigned int IMM13:13;
123 #define imm13 IMM13.IMM13
124 } IMM13;
125 struct
126 {
127 unsigned int anop:2;
128 unsigned int a:1;
129 unsigned int cond:4;
130 unsigned int op2:3;
131 unsigned int DISP22:22;
132 #define disp22 branch.DISP22
133 #define imm22 disp22
134 } branch;
135 #ifndef NO_V9
136 struct
137 {
138 unsigned int anop:2;
139 unsigned int a:1;
140 unsigned int z:1;
141 unsigned int rcond:3;
142 unsigned int op2:3;
143 unsigned int DISP16HI:2;
144 unsigned int p:1;
145 unsigned int _rs1:5;
146 unsigned int DISP16LO:14;
147 } branch16;
148 #endif
149 struct
150 {
151 unsigned int anop:2;
152 unsigned int adisp30:30;
153 #define disp30 call.adisp30
154 } call;
155 };
156
157 */
158
159 /* Nonzero if INSN is the opcode for a delayed branch. */
160 static int
161 is_delayed_branch (insn)
162 unsigned long insn;
163 {
164 struct opcode_hash *op;
165
166 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
167 {
168 CONST struct sparc_opcode *opcode = op->opcode;
169 if ((opcode->match & insn) == opcode->match
170 && (opcode->lose & insn) == 0)
171 return (opcode->flags & F_DELAYED);
172 }
173 return 0;
174 }
175
176 /* Nonzero of opcode table has been initialized. */
177 static int opcodes_initialized = 0;
178
179 /* extern void qsort (); */
180 static int compare_opcodes ();
181
182 /* Print one instruction from MEMADDR on INFO->STREAM.
183
184 We suffix the instruction with a comment that gives the absolute
185 address involved, as well as its symbolic form, if the instruction
186 is preceded by a findable `sethi' and it either adds an immediate
187 displacement to that register, or it is an `add' or `or' instruction
188 on that register. */
189
190 static int
191 print_insn (memaddr, info, sparc64_p)
192 bfd_vma memaddr;
193 disassemble_info *info;
194 int sparc64_p;
195 {
196 FILE *stream = info->stream;
197 bfd_byte buffer[4];
198 unsigned long insn;
199 register unsigned int i;
200 register struct opcode_hash *op;
201
202 if (!opcodes_initialized)
203 {
204 qsort ((char *) sparc_opcodes, NUMOPCODES,
205 sizeof (sparc_opcodes[0]), compare_opcodes);
206 build_hash_table (sparc_opcodes, opcode_hash_table, NUMOPCODES);
207 opcodes_initialized = 1;
208 }
209
210 {
211 int status =
212 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
213 if (status != 0)
214 {
215 (*info->memory_error_func) (status, memaddr, info);
216 return -1;
217 }
218 }
219
220 insn = bfd_getb32 (buffer);
221
222 info->insn_info_valid = 1; /* We do return this info */
223 info->insn_type = dis_nonbranch; /* Assume non branch insn */
224 info->branch_delay_insns = 0; /* Assume no delay */
225 info->target = 0; /* Assume no target known */
226
227 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
228 {
229 CONST struct sparc_opcode *opcode = op->opcode;
230
231 /* If the current architecture isn't sparc64, skip sparc64 insns. */
232 if (!sparc64_p
233 && opcode->architecture == v9)
234 continue;
235
236 /* If the current architecture is sparc64, skip sparc32 only insns. */
237 if (sparc64_p
238 && (opcode->flags & F_NOTV9))
239 continue;
240
241 if ((opcode->match & insn) == opcode->match
242 && (opcode->lose & insn) == 0)
243 {
244 /* Nonzero means that we have found an instruction which has
245 the effect of adding or or'ing the imm13 field to rs1. */
246 int imm_added_to_rs1 = 0;
247
248 /* Nonzero means that we have found a plus sign in the args
249 field of the opcode table. */
250 int found_plus = 0;
251
252 /* Nonzero means we have an annulled branch. */
253 int is_annulled = 0;
254
255 /* Do we have an `add' or `or' instruction where rs1 is the same
256 as rsd, and which has the i bit set? */
257 if ((opcode->match == 0x80102000 || opcode->match == 0x80002000)
258 /* (or) (add) */
259 && X_RS1 (insn) == X_RD (insn))
260 imm_added_to_rs1 = 1;
261
262 if (X_RS1 (insn) != X_RD (insn)
263 && strchr (opcode->args, 'r') != 0)
264 /* Can't do simple format if source and dest are different. */
265 continue;
266
267 (*info->fprintf_func) (stream, opcode->name);
268
269 {
270 register CONST char *s;
271
272 if (opcode->args[0] != ',')
273 (*info->fprintf_func) (stream, " ");
274 for (s = opcode->args; *s != '\0'; ++s)
275 {
276 while (*s == ',')
277 {
278 (*info->fprintf_func) (stream, ",");
279 ++s;
280 switch (*s) {
281 case 'a':
282 (*info->fprintf_func) (stream, "a");
283 is_annulled = 1;
284 ++s;
285 continue;
286 #ifndef NO_V9
287 case 'N':
288 (*info->fprintf_func) (stream, "pn");
289 ++s;
290 continue;
291
292 case 'T':
293 (*info->fprintf_func) (stream, "pt");
294 ++s;
295 continue;
296 #endif /* NO_V9 */
297
298 default:
299 break;
300 } /* switch on arg */
301 } /* while there are comma started args */
302
303 (*info->fprintf_func) (stream, " ");
304
305 switch (*s)
306 {
307 case '+':
308 found_plus = 1;
309
310 /* note fall-through */
311 default:
312 (*info->fprintf_func) (stream, "%c", *s);
313 break;
314
315 case '#':
316 (*info->fprintf_func) (stream, "0");
317 break;
318
319 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
320 case '1':
321 case 'r':
322 reg (X_RS1 (insn));
323 break;
324
325 case '2':
326 reg (X_RS2 (insn));
327 break;
328
329 case 'd':
330 reg (X_RD (insn));
331 break;
332 #undef reg
333
334 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
335 #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
336 case 'e':
337 freg (X_RS1 (insn));
338 break;
339 case 'v': /* double/even */
340 case 'V': /* quad/multiple of 4 */
341 fregx (X_RS1 (insn));
342 break;
343
344 case 'f':
345 freg (X_RS2 (insn));
346 break;
347 case 'B': /* double/even */
348 case 'R': /* quad/multiple of 4 */
349 fregx (X_RS2 (insn));
350 break;
351
352 case 'g':
353 freg (X_RD (insn));
354 break;
355 case 'H': /* double/even */
356 case 'J': /* quad/multiple of 4 */
357 fregx (X_RD (insn));
358 break;
359 #undef freg
360 #undef fregx
361
362 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
363 case 'b':
364 creg (X_RS1 (insn));
365 break;
366
367 case 'c':
368 creg (X_RS2 (insn));
369 break;
370
371 case 'D':
372 creg (X_RD (insn));
373 break;
374 #undef creg
375
376 case 'h':
377 (*info->fprintf_func) (stream, "%%hi(%#x)",
378 (0xFFFFFFFF
379 & ((int) X_IMM22 (insn) << 10)));
380 break;
381
382 case 'i':
383 {
384 int imm = SEX (X_IMM13 (insn), 13);
385
386 /* Check to see whether we have a 1+i, and take
387 note of that fact.
388
389 Note: because of the way we sort the table,
390 we will be matching 1+i rather than i+1,
391 so it is OK to assume that i is after +,
392 not before it. */
393 if (found_plus)
394 imm_added_to_rs1 = 1;
395
396 if (imm <= 9)
397 (*info->fprintf_func) (stream, "%d", imm);
398 else
399 (*info->fprintf_func) (stream, "%#x", imm);
400 }
401 break;
402
403 #ifndef NO_V9
404 case 'I': /* 11 bit immediate. */
405 case 'j': /* 10 bit immediate. */
406 {
407 int imm;
408
409 if (*s == 'I')
410 imm = SEX (X_IMM13 (insn), 11);
411 else
412 imm = SEX (X_IMM13 (insn), 10);
413
414 /* Check to see whether we have a 1+i, and take
415 note of that fact.
416
417 Note: because of the way we sort the table,
418 we will be matching 1+i rather than i+1,
419 so it is OK to assume that i is after +,
420 not before it. */
421 if (found_plus)
422 imm_added_to_rs1 = 1;
423
424 if (imm <= 9)
425 (info->fprintf_func) (stream, "%d", imm);
426 else
427 (info->fprintf_func) (stream, "%#x", (unsigned) imm);
428 }
429 break;
430
431 case 'K':
432 {
433 int mask = X_MEMBAR (insn);
434 int bit = 0x40, printed_one = 0;
435 char *name;
436
437 if (mask == 0)
438 (info->fprintf_func) (stream, "0");
439 else
440 while (bit)
441 {
442 if (mask & bit)
443 {
444 if (printed_one)
445 (info->fprintf_func) (stream, "|");
446 name = sparc_decode_membar (bit);
447 (info->fprintf_func) (stream, "%s", name);
448 printed_one = 1;
449 }
450 bit >>= 1;
451 }
452 break;
453 }
454
455 case 'k':
456 info->target = memaddr + (SEX (X_DISP16 (insn), 16)) * 4;
457 (*info->print_address_func) (info->target, info);
458 break;
459
460 case 'G':
461 info->target = memaddr + (SEX (X_DISP22 (insn), 19)) * 4;
462 (*info->print_address_func) (info->target, info);
463 break;
464
465 case '6':
466 case '7':
467 case '8':
468 case '9':
469 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
470 break;
471
472 case 'z':
473 (*info->fprintf_func) (stream, "%%icc");
474 break;
475
476 case 'Z':
477 (*info->fprintf_func) (stream, "%%xcc");
478 break;
479
480 case 'E':
481 (*info->fprintf_func) (stream, "%%ccr");
482 break;
483
484 case 's':
485 (*info->fprintf_func) (stream, "%%fprs");
486 break;
487
488 case 'o':
489 (*info->fprintf_func) (stream, "%%asi");
490 break;
491
492 case 'W':
493 (*info->fprintf_func) (stream, "%%tick");
494 break;
495
496 case 'P':
497 (*info->fprintf_func) (stream, "%%pc");
498 break;
499
500 case '?':
501 if (X_RS1 (insn) == 31)
502 (*info->fprintf_func) (stream, "%%ver");
503 else if ((unsigned) X_RS1 (insn) < 16)
504 (*info->fprintf_func) (stream, "%%%s",
505 v9_priv_reg_names[X_RS1 (insn)]);
506 else
507 (*info->fprintf_func) (stream, "%%reserved");
508 break;
509
510 case '!':
511 if ((unsigned) X_RD (insn) < 15)
512 (*info->fprintf_func) (stream, "%%%s",
513 v9_priv_reg_names[X_RD (insn)]);
514 else
515 (*info->fprintf_func) (stream, "%%reserved");
516 break;
517
518 case '*':
519 {
520 char *name = sparc_decode_prefetch (X_RD (insn));
521
522 if (name)
523 (*info->fprintf_func) (stream, "%s", name);
524 else
525 (*info->fprintf_func) (stream, "%d", X_RD (insn));
526 break;
527 }
528 #endif /* NO_V9 */
529
530 case 'M':
531 (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn));
532 break;
533
534 case 'm':
535 (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn));
536 break;
537
538 case 'L':
539 info->target = memaddr + X_DISP30 (insn) * 4;
540 (*info->print_address_func) (info->target, info);
541 break;
542
543 case 'n':
544 (*info->fprintf_func)
545 (stream, "%#x", (SEX (X_DISP22 (insn), 22)));
546 break;
547
548 case 'l':
549 info->target = memaddr + (SEX (X_DISP22 (insn), 22)) * 4;
550 (*info->print_address_func) (info->target, info);
551 break;
552
553 case 'A':
554 {
555 char *name = sparc_decode_asi (X_ASI (insn));
556
557 if (name)
558 (*info->fprintf_func) (stream, "%s", name);
559 else
560 (*info->fprintf_func) (stream, "(%d)", X_ASI (insn));
561 break;
562 }
563
564 case 'C':
565 (*info->fprintf_func) (stream, "%%csr");
566 break;
567
568 case 'F':
569 (*info->fprintf_func) (stream, "%%fsr");
570 break;
571
572 case 'p':
573 (*info->fprintf_func) (stream, "%%psr");
574 break;
575
576 case 'q':
577 (*info->fprintf_func) (stream, "%%fq");
578 break;
579
580 case 'Q':
581 (*info->fprintf_func) (stream, "%%cq");
582 break;
583
584 case 't':
585 (*info->fprintf_func) (stream, "%%tbr");
586 break;
587
588 case 'w':
589 (*info->fprintf_func) (stream, "%%wim");
590 break;
591
592 case 'x':
593 (*info->fprintf_func) (stream, "%d",
594 ((X_LDST_I (insn) << 8)
595 + X_ASI (insn)));
596 break;
597
598 case 'y':
599 (*info->fprintf_func) (stream, "%%y");
600 break;
601 }
602 }
603 }
604
605 /* If we are adding or or'ing something to rs1, then
606 check to see whether the previous instruction was
607 a sethi to the same register as in the sethi.
608 If so, attempt to print the result of the add or
609 or (in this context add and or do the same thing)
610 and its symbolic value. */
611 if (imm_added_to_rs1)
612 {
613 unsigned long prev_insn;
614 int errcode;
615
616 errcode =
617 (*info->read_memory_func)
618 (memaddr - 4, buffer, sizeof (buffer), info);
619 prev_insn = bfd_getb32 (buffer);
620
621 if (errcode == 0)
622 {
623 /* If it is a delayed branch, we need to look at the
624 instruction before the delayed branch. This handles
625 sequences such as
626
627 sethi %o1, %hi(_foo), %o1
628 call _printf
629 or %o1, %lo(_foo), %o1
630 */
631
632 if (is_delayed_branch (prev_insn))
633 {
634 errcode = (*info->read_memory_func)
635 (memaddr - 8, buffer, sizeof (buffer), info);
636 prev_insn = bfd_getb32 (buffer);
637 }
638 }
639
640 /* If there was a problem reading memory, then assume
641 the previous instruction was not sethi. */
642 if (errcode == 0)
643 {
644 /* Is it sethi to the same register? */
645 if ((prev_insn & 0xc1c00000) == 0x01000000
646 && X_RD (prev_insn) == X_RS1 (insn))
647 {
648 (*info->fprintf_func) (stream, "\t! ");
649 info->target =
650 (0xFFFFFFFF & (int) X_IMM22 (prev_insn) << 10)
651 | SEX (X_IMM13 (insn), 13);
652 (*info->print_address_func) (info->target, info);
653 info->insn_type = dis_dref;
654 info->data_size = 4; /* FIXME!!! */
655 }
656 }
657 }
658
659 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
660 {
661 /* FIXME -- check is_annulled flag */
662 if (opcode->flags & F_UNBR)
663 info->insn_type = dis_branch;
664 if (opcode->flags & F_CONDBR)
665 info->insn_type = dis_condbranch;
666 if (opcode->flags & F_JSR)
667 info->insn_type = dis_jsr;
668 if (opcode->flags & F_DELAYED)
669 info->branch_delay_insns = 1;
670 }
671
672 return sizeof (buffer);
673 }
674 }
675
676 info->insn_type = dis_noninsn; /* Mark as non-valid instruction */
677 (*info->fprintf_func) (stream, "%#8x", insn);
678 return sizeof (buffer);
679 }
680
681 /* Compare opcodes A and B. */
682
683 static int
684 compare_opcodes (a, b)
685 char *a, *b;
686 {
687 struct sparc_opcode *op0 = (struct sparc_opcode *) a;
688 struct sparc_opcode *op1 = (struct sparc_opcode *) b;
689 unsigned long int match0 = op0->match, match1 = op1->match;
690 unsigned long int lose0 = op0->lose, lose1 = op1->lose;
691 register unsigned int i;
692
693 /* If a bit is set in both match and lose, there is something
694 wrong with the opcode table. */
695 if (match0 & lose0)
696 {
697 fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
698 op0->name, match0, lose0);
699 op0->lose &= ~op0->match;
700 lose0 = op0->lose;
701 }
702
703 if (match1 & lose1)
704 {
705 fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
706 op1->name, match1, lose1);
707 op1->lose &= ~op1->match;
708 lose1 = op1->lose;
709 }
710
711 /* Because the bits that are variable in one opcode are constant in
712 another, it is important to order the opcodes in the right order. */
713 for (i = 0; i < 32; ++i)
714 {
715 unsigned long int x = 1 << i;
716 int x0 = (match0 & x) != 0;
717 int x1 = (match1 & x) != 0;
718
719 if (x0 != x1)
720 return x1 - x0;
721 }
722
723 for (i = 0; i < 32; ++i)
724 {
725 unsigned long int x = 1 << i;
726 int x0 = (lose0 & x) != 0;
727 int x1 = (lose1 & x) != 0;
728
729 if (x0 != x1)
730 return x1 - x0;
731 }
732
733 /* Put non-sparc64 insns ahead of sparc64 ones. */
734 if ((op0->architecture == v9) != (op1->architecture == v9))
735 return (op0->architecture == v9) - (op1->architecture == v9);
736
737 /* They are functionally equal. So as long as the opcode table is
738 valid, we can put whichever one first we want, on aesthetic grounds. */
739
740 /* Our first aesthetic ground is that aliases defer to real insns. */
741 {
742 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
743 if (alias_diff != 0)
744 /* Put the one that isn't an alias first. */
745 return alias_diff;
746 }
747
748 /* Except for aliases, two "identical" instructions had
749 better have the same opcode. This is a sanity check on the table. */
750 i = strcmp (op0->name, op1->name);
751 if (i)
752 if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
753 return i;
754 else
755 fprintf (stderr,
756 "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n",
757 op0->name, op1->name);
758
759 /* Fewer arguments are preferred. */
760 {
761 int length_diff = strlen (op0->args) - strlen (op1->args);
762 if (length_diff != 0)
763 /* Put the one with fewer arguments first. */
764 return length_diff;
765 }
766
767 /* Put 1+i before i+1. */
768 {
769 char *p0 = (char *) strchr(op0->args, '+');
770 char *p1 = (char *) strchr(op1->args, '+');
771
772 if (p0 && p1)
773 {
774 /* There is a plus in both operands. Note that a plus
775 sign cannot be the first character in args,
776 so the following [-1]'s are valid. */
777 if (p0[-1] == 'i' && p1[1] == 'i')
778 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
779 return 1;
780 if (p0[1] == 'i' && p1[-1] == 'i')
781 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
782 return -1;
783 }
784 }
785
786 /* Put 1,i before i,1. */
787 {
788 int i0 = strncmp (op0->args, "i,1", 3) == 0;
789 int i1 = strncmp (op1->args, "i,1", 3) == 0;
790
791 if (i0 ^ i1)
792 return i0 - i1;
793 }
794
795 /* They are, as far as we can tell, identical.
796 Since qsort may have rearranged the table partially, there is
797 no way to tell which one was first in the opcode table as
798 written, so just say there are equal. */
799 return 0;
800 }
801
802 /* Build a hash table from the opcode table. */
803
804 static void
805 build_hash_table (table, hash_table, num_opcodes)
806 struct sparc_opcode *table;
807 struct opcode_hash **hash_table;
808 int num_opcodes;
809 {
810 register int i;
811 int hash_count[HASH_SIZE];
812 static struct opcode_hash *hash_buf = NULL;
813
814 /* Start at the end of the table and work backwards so that each
815 chain is sorted. */
816
817 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
818 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
819 if (hash_buf != NULL)
820 free (hash_buf);
821 hash_buf = (struct opcode_hash *) xmalloc (sizeof (struct opcode_hash) * num_opcodes);
822 for (i = num_opcodes - 1; i >= 0; --i)
823 {
824 register int hash = HASH_INSN (sparc_opcodes[i].match);
825 register struct opcode_hash *h = &hash_buf[i];
826 h->next = hash_table[hash];
827 h->opcode = &sparc_opcodes[i];
828 hash_table[hash] = h;
829 ++hash_count[hash];
830 }
831
832 #if 0 /* for debugging */
833 {
834 int min_count = num_opcodes, max_count = 0;
835 int total;
836
837 for (i = 0; i < HASH_SIZE; ++i)
838 {
839 if (hash_count[i] < min_count)
840 min_count = hash_count[i];
841 if (hash_count[i] > max_count)
842 max_count = hash_count[i];
843 total += hash_count[i];
844 }
845
846 printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
847 min_count, max_count, (double) total / HASH_SIZE);
848 }
849 #endif
850 }
851
852 int
853 print_insn_sparc (memaddr, info)
854 bfd_vma memaddr;
855 disassemble_info *info;
856 {
857 return print_insn (memaddr, info, 0);
858 }
859
860 int
861 print_insn_sparc64 (memaddr, info)
862 bfd_vma memaddr;
863 disassemble_info *info;
864 {
865 return print_insn (memaddr, info, 1);
866 }
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