opcodes/sparc-dis.c

   1 /* Print SPARC instructions.
   2    Copyright (C) 1989, 91-93, 1995, 1996 Free Software Foundation, Inc.
   3
   4 This program is free software; you can redistribute it and/or modify
   5 it under the terms of the GNU General Public License as published by
   6 the Free Software Foundation; either version 2 of the License, or
   7 (at your option) any later version.
   8
   9 This program is distributed in the hope that it will be useful,
  10 but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 GNU General Public License for more details.
  13
  14 You should have received a copy of the GNU General Public License
  15 along with this program; if not, write to the Free Software
  16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  17
  18 #include "ansidecl.h"
  19 #include "opcode/sparc.h"
  20 #include "dis-asm.h"
  21 #include "libiberty.h"
  22 #include <string.h>
  23
  24 /* Bitmask of v9 architectures.  */
  25 #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
  26                  | (1 << SPARC_OPCODE_ARCH_V9A))
  27 /* 1 if INSN is for v9 only.  */
  28 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
  29 /* 1 if INSN is for v9.  */
  30 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
  31
  32 /* For faster lookup, after insns are sorted they are hashed.  */
  33 /* ??? I think there is room for even more improvement.  */
  34
  35 #define HASH_SIZE 256
  36 /* It is important that we only look at insn code bits as that is how the
  37    opcode table is hashed.  OPCODE_BITS is a table of valid bits for each
  38    of the main types (0,1,2,3).  */
  39 static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
  40 #define HASH_INSN(INSN) \
  41   ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
  42 struct opcode_hash {
  43   struct opcode_hash *next;
  44   struct sparc_opcode *opcode;
  45 };
  46 static struct opcode_hash *opcode_hash_table[HASH_SIZE];
  47 static void build_hash_table ();
  48
  49 /* Sign-extend a value which is N bits long.  */
  50 #define SEX(value, bits) \
  51         ((((int)(value)) << ((8 * sizeof (int)) - bits))        \
  52                          >> ((8 * sizeof (int)) - bits) )
  53
  54 static  char *reg_names[] =
  55 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
  56   "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
  57   "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
  58   "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
  59   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
  60   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
  61   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
  62   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
  63   "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
  64   "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
  65   "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
  66   "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
  67 /* psr, wim, tbr, fpsr, cpsr are v8 only.  */
  68   "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
  69 };
  70
  71 #define freg_names      (&reg_names[4 * 8])
  72
  73 /* These are ordered according to there register number in
  74    rdpr and wrpr insns.  */
  75 static char *v9_priv_reg_names[] =
  76 {
  77   "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
  78   "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
  79   "wstate", "fq"
  80   /* "ver" - special cased */
  81 };
  82
  83 /* Macros used to extract instruction fields.  Not all fields have
  84    macros defined here, only those which are actually used.  */
  85
  86 #define X_RD(i) (((i) >> 25) & 0x1f)
  87 #define X_RS1(i) (((i) >> 14) & 0x1f)
  88 #define X_LDST_I(i) (((i) >> 13) & 1)
  89 #define X_ASI(i) (((i) >> 5) & 0xff)
  90 #define X_RS2(i) (((i) >> 0) & 0x1f)
  91 #define X_IMM13(i) (((i) >> 0) & 0x1fff)
  92 #define X_DISP22(i) (((i) >> 0) & 0x3fffff)
  93 #define X_IMM22(i) X_DISP22 (i)
  94 #define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
  95
  96 /* These are for v9.  */
  97 #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
  98 #define X_DISP19(i) (((i) >> 0) & 0x7ffff)
  99 #define X_MEMBAR(i) ((i) & 0x7f)
 100
 101 /* Here is the union which was used to extract instruction fields
 102    before the shift and mask macros were written.
 103
 104    union sparc_insn
 105      {
 106        unsigned long int code;
 107        struct
 108          {
 109            unsigned int anop:2;
 110            #define      op      ldst.anop
 111            unsigned int anrd:5;
 112            #define      rd      ldst.anrd
 113            unsigned int op3:6;
 114            unsigned int anrs1:5;
 115            #define      rs1     ldst.anrs1
 116            unsigned int i:1;
 117            unsigned int anasi:8;
 118            #define      asi     ldst.anasi
 119            unsigned int anrs2:5;
 120            #define      rs2     ldst.anrs2
 121            #define      shcnt   rs2
 122          } ldst;
 123        struct
 124          {
 125            unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
 126            unsigned int IMM13:13;
 127            #define      imm13   IMM13.IMM13
 128          } IMM13;
 129        struct
 130          {
 131            unsigned int anop:2;
 132            unsigned int a:1;
 133            unsigned int cond:4;
 134            unsigned int op2:3;
 135            unsigned int DISP22:22;
 136            #define      disp22  branch.DISP22
 137            #define      imm22   disp22
 138          } branch;
 139        struct
 140          {
 141            unsigned int anop:2;
 142            unsigned int a:1;
 143            unsigned int z:1;
 144            unsigned int rcond:3;
 145            unsigned int op2:3;
 146            unsigned int DISP16HI:2;
 147            unsigned int p:1;
 148            unsigned int _rs1:5;
 149            unsigned int DISP16LO:14;
 150          } branch16;
 151        struct
 152          {
 153            unsigned int anop:2;
 154            unsigned int adisp30:30;
 155            #define      disp30  call.adisp30
 156          } call;
 157      };
 158
 159    */
 160
 161 /* Nonzero if INSN is the opcode for a delayed branch.  */
 162 static int
 163 is_delayed_branch (insn)
 164      unsigned long insn;
 165 {
 166   struct opcode_hash *op;
 167
 168   for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
 169     {
 170       CONST struct sparc_opcode *opcode = op->opcode;
 171       if ((opcode->match & insn) == opcode->match
 172           && (opcode->lose & insn) == 0)
 173         return (opcode->flags & F_DELAYED);
 174     }
 175   return 0;
 176 }
 177
 178 /* extern void qsort (); */
 179 static int compare_opcodes ();
 180
 181 /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
 182    to compare_opcodes.  */
 183 static unsigned int current_arch_mask;
 184 static int compute_arch_mask ();
 185
 186 /* Print one instruction from MEMADDR on INFO->STREAM.
 187
 188    We suffix the instruction with a comment that gives the absolute
 189    address involved, as well as its symbolic form, if the instruction
 190    is preceded by a findable `sethi' and it either adds an immediate
 191    displacement to that register, or it is an `add' or `or' instruction
 192    on that register.  */
 193
 194 int
 195 print_insn_sparc (memaddr, info)
 196      bfd_vma memaddr;
 197      disassemble_info *info;
 198 {
 199   FILE *stream = info->stream;
 200   bfd_byte buffer[4];
 201   unsigned long insn;
 202   register unsigned int i;
 203   register struct opcode_hash *op;
 204   /* Nonzero of opcode table has been initialized.  */
 205   static int opcodes_initialized = 0;
 206   /* bfd mach number of last call.  */
 207   static unsigned long current_mach = 0;
 208
 209   if (!opcodes_initialized
 210       || info->mach != current_mach)
 211     {
 212       current_arch_mask = compute_arch_mask (info->mach);
 213       qsort ((char *) sparc_opcodes, sparc_num_opcodes,
 214              sizeof (sparc_opcodes[0]), compare_opcodes);
 215       build_hash_table (sparc_opcodes, opcode_hash_table, sparc_num_opcodes);
 216       current_mach = info->mach;
 217       opcodes_initialized = 1;
 218     }
 219
 220   {
 221     int status =
 222       (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
 223     if (status != 0)
 224       {
 225         (*info->memory_error_func) (status, memaddr, info);
 226         return -1;
 227       }
 228   }
 229
 230   insn = bfd_getb32 (buffer);
 231
 232   info->insn_info_valid = 1;                    /* We do return this info */
 233   info->insn_type = dis_nonbranch;              /* Assume non branch insn */
 234   info->branch_delay_insns = 0;                 /* Assume no delay */
 235   info->target = 0;                             /* Assume no target known */
 236
 237   for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
 238     {
 239       CONST struct sparc_opcode *opcode = op->opcode;
 240
 241       /* If the insn isn't supported by the current architecture, skip it.  */
 242       if (! (opcode->architecture & current_arch_mask))
 243         continue;
 244
 245       if ((opcode->match & insn) == opcode->match
 246           && (opcode->lose & insn) == 0)
 247         {
 248           /* Nonzero means that we have found an instruction which has
 249              the effect of adding or or'ing the imm13 field to rs1.  */
 250           int imm_added_to_rs1 = 0;
 251
 252           /* Nonzero means that we have found a plus sign in the args
 253              field of the opcode table.  */
 254           int found_plus = 0;
 255
 256           /* Nonzero means we have an annulled branch.  */
 257           int is_annulled = 0;
 258
 259           /* Do we have an `add' or `or' instruction where rs1 is the same
 260              as rsd, and which has the i bit set?  */
 261           if ((opcode->match == 0x80102000 || opcode->match == 0x80002000)
 262           /*                      (or)                           (add)  */
 263               && X_RS1 (insn) == X_RD (insn))
 264             imm_added_to_rs1 = 1;
 265
 266           if (X_RS1 (insn) != X_RD (insn)
 267               && strchr (opcode->args, 'r') != 0)
 268               /* Can't do simple format if source and dest are different.  */
 269               continue;
 270           if (X_RS2 (insn) != X_RD (insn)
 271               && strchr (opcode->args, 'O') != 0)
 272               /* Can't do simple format if source and dest are different.  */
 273               continue;
 274
 275           (*info->fprintf_func) (stream, opcode->name);
 276
 277           {
 278             register CONST char *s;
 279
 280             if (opcode->args[0] != ',')
 281               (*info->fprintf_func) (stream, " ");
 282             for (s = opcode->args; *s != '\0'; ++s)
 283               {
 284                 while (*s == ',')
 285                   {
 286                     (*info->fprintf_func) (stream, ",");
 287                     ++s;
 288                     switch (*s) {
 289                     case 'a':
 290                       (*info->fprintf_func) (stream, "a");
 291                       is_annulled = 1;
 292                       ++s;
 293                       continue;
 294                     case 'N':
 295                       (*info->fprintf_func) (stream, "pn");
 296                       ++s;
 297                       continue;
 298
 299                     case 'T':
 300                       (*info->fprintf_func) (stream, "pt");
 301                       ++s;
 302                       continue;
 303
 304                     default:
 305                       break;
 306                     }           /* switch on arg */
 307                   }             /* while there are comma started args */
 308
 309                 (*info->fprintf_func) (stream, " ");
 310
 311                 switch (*s)
 312                   {
 313                   case '+':
 314                     found_plus = 1;
 315
 316                     /* note fall-through */
 317                   default:
 318                     (*info->fprintf_func) (stream, "%c", *s);
 319                     break;
 320
 321                   case '#':
 322                     (*info->fprintf_func) (stream, "0");
 323                     break;
 324
 325 #define reg(n)  (*info->fprintf_func) (stream, "%%%s", reg_names[n])
 326                   case '1':
 327                   case 'r':
 328                     reg (X_RS1 (insn));
 329                     break;
 330
 331                   case '2':
 332                   case 'O':
 333                     reg (X_RS2 (insn));
 334                     break;
 335
 336                   case 'd':
 337                     reg (X_RD (insn));
 338                     break;
 339 #undef  reg
 340
 341 #define freg(n)         (*info->fprintf_func) (stream, "%%%s", freg_names[n])
 342 #define fregx(n)        (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
 343                   case 'e':
 344                     freg (X_RS1 (insn));
 345                     break;
 346                   case 'v':     /* double/even */
 347                   case 'V':     /* quad/multiple of 4 */
 348                     fregx (X_RS1 (insn));
 349                     break;
 350
 351                   case 'f':
 352                     freg (X_RS2 (insn));
 353                     break;
 354                   case 'B':     /* double/even */
 355                   case 'R':     /* quad/multiple of 4 */
 356                     fregx (X_RS2 (insn));
 357                     break;
 358
 359                   case 'g':
 360                     freg (X_RD (insn));
 361                     break;
 362                   case 'H':     /* double/even */
 363                   case 'J':     /* quad/multiple of 4 */
 364                     fregx (X_RD (insn));
 365                     break;
 366 #undef  freg
 367 #undef  fregx
 368
 369 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
 370                   case 'b':
 371                     creg (X_RS1 (insn));
 372                     break;
 373
 374                   case 'c':
 375                     creg (X_RS2 (insn));
 376                     break;
 377
 378                   case 'D':
 379                     creg (X_RD (insn));
 380                     break;
 381 #undef  creg
 382
 383                   case 'h':
 384                     (*info->fprintf_func) (stream, "%%hi(%#x)",
 385                                            (0xFFFFFFFF
 386                                             & ((int) X_IMM22 (insn) << 10)));
 387                     break;
 388
 389                   case 'i':
 390                     {
 391                       int imm = SEX (X_IMM13 (insn), 13);
 392
 393                       /* Check to see whether we have a 1+i, and take
 394                          note of that fact.
 395
 396                          Note: because of the way we sort the table,
 397                          we will be matching 1+i rather than i+1,
 398                          so it is OK to assume that i is after +,
 399                          not before it.  */
 400                       if (found_plus)
 401                         imm_added_to_rs1 = 1;
 402
 403                       if (imm <= 9)
 404                         (*info->fprintf_func) (stream, "%d", imm);
 405                       else
 406                         (*info->fprintf_func) (stream, "%#x", imm);
 407                     }
 408                     break;
 409
 410                   case 'I':     /* 11 bit immediate.  */
 411                   case 'j':     /* 10 bit immediate.  */
 412                     {
 413                       int imm;
 414
 415                       if (*s == 'I')
 416                         imm = SEX (X_IMM13 (insn), 11);
 417                       else
 418                         imm = SEX (X_IMM13 (insn), 10);
 419
 420                       /* Check to see whether we have a 1+i, and take
 421                          note of that fact.
 422
 423                          Note: because of the way we sort the table,
 424                          we will be matching 1+i rather than i+1,
 425                          so it is OK to assume that i is after +,
 426                          not before it.  */
 427                       if (found_plus)
 428                         imm_added_to_rs1 = 1;
 429
 430                       if (imm <= 9)
 431                         (info->fprintf_func) (stream, "%d", imm);
 432                       else
 433                         (info->fprintf_func) (stream, "%#x", (unsigned) imm);
 434                     }
 435                     break;
 436
 437                   case 'K':
 438                     {
 439                       int mask = X_MEMBAR (insn);
 440                       int bit = 0x40, printed_one = 0;
 441                       char *name;
 442
 443                       if (mask == 0)
 444                         (info->fprintf_func) (stream, "0");
 445                       else
 446                         while (bit)
 447                           {
 448                             if (mask & bit)
 449                               {
 450                                 if (printed_one)
 451                                   (info->fprintf_func) (stream, "|");
 452                                 name = sparc_decode_membar (bit);
 453                                 (info->fprintf_func) (stream, "%s", name);
 454                                 printed_one = 1;
 455                               }
 456                             bit >>= 1;
 457                           }
 458                       break;
 459                     }
 460
 461                   case 'k':
 462                     info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
 463                     (*info->print_address_func) (info->target, info);
 464                     break;
 465
 466                   case 'G':
 467                     info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
 468                     (*info->print_address_func) (info->target, info);
 469                     break;
 470
 471                   case '6':
 472                   case '7':
 473                   case '8':
 474                   case '9':
 475                     (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
 476                     break;
 477
 478                   case 'z':
 479                     (*info->fprintf_func) (stream, "%%icc");
 480                     break;
 481
 482                   case 'Z':
 483                     (*info->fprintf_func) (stream, "%%xcc");
 484                     break;
 485
 486                   case 'E':
 487                     (*info->fprintf_func) (stream, "%%ccr");
 488                     break;
 489
 490                   case 's':
 491                     (*info->fprintf_func) (stream, "%%fprs");
 492                     break;
 493
 494                   case 'o':
 495                     (*info->fprintf_func) (stream, "%%asi");
 496                     break;
 497
 498                   case 'W':
 499                     (*info->fprintf_func) (stream, "%%tick");
 500                     break;
 501
 502                   case 'P':
 503                     (*info->fprintf_func) (stream, "%%pc");
 504                     break;
 505
 506                   case '?':
 507                     if (X_RS1 (insn) == 31)
 508                       (*info->fprintf_func) (stream, "%%ver");
 509                     else if ((unsigned) X_RS1 (insn) < 16)
 510                       (*info->fprintf_func) (stream, "%%%s",
 511                                              v9_priv_reg_names[X_RS1 (insn)]);
 512                     else
 513                       (*info->fprintf_func) (stream, "%%reserved");
 514                     break;
 515
 516                   case '!':
 517                     if ((unsigned) X_RD (insn) < 15)
 518                       (*info->fprintf_func) (stream, "%%%s",
 519                                              v9_priv_reg_names[X_RD (insn)]);
 520                     else
 521                       (*info->fprintf_func) (stream, "%%reserved");
 522                     break;
 523
 524                   case '*':
 525                     {
 526                       char *name = sparc_decode_prefetch (X_RD (insn));
 527
 528                       if (name)
 529                         (*info->fprintf_func) (stream, "%s", name);
 530                       else
 531                         (*info->fprintf_func) (stream, "%d", X_RD (insn));
 532                       break;
 533                     }
 534
 535                   case 'M':
 536                     (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn));
 537                     break;
 538
 539                   case 'm':
 540                     (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn));
 541                     break;
 542
 543                   case 'L':
 544                     info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
 545                     (*info->print_address_func) (info->target, info);
 546                     break;
 547
 548                   case 'n':
 549                     (*info->fprintf_func)
 550                       (stream, "%#x", SEX (X_DISP22 (insn), 22));
 551                     break;
 552
 553                   case 'l':
 554                     info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
 555                     (*info->print_address_func) (info->target, info);
 556                     break;
 557
 558                   case 'A':
 559                     {
 560                       char *name = sparc_decode_asi (X_ASI (insn));
 561
 562                       if (name)
 563                         (*info->fprintf_func) (stream, "%s", name);
 564                       else
 565                         (*info->fprintf_func) (stream, "(%d)", X_ASI (insn));
 566                       break;
 567                     }
 568
 569                   case 'C':
 570                     (*info->fprintf_func) (stream, "%%csr");
 571                     break;
 572
 573                   case 'F':
 574                     (*info->fprintf_func) (stream, "%%fsr");
 575                     break;
 576
 577                   case 'p':
 578                     (*info->fprintf_func) (stream, "%%psr");
 579                     break;
 580
 581                   case 'q':
 582                     (*info->fprintf_func) (stream, "%%fq");
 583                     break;
 584
 585                   case 'Q':
 586                     (*info->fprintf_func) (stream, "%%cq");
 587                     break;
 588
 589                   case 't':
 590                     (*info->fprintf_func) (stream, "%%tbr");
 591                     break;
 592
 593                   case 'w':
 594                     (*info->fprintf_func) (stream, "%%wim");
 595                     break;
 596
 597                   case 'x':
 598                     (*info->fprintf_func) (stream, "%d",
 599                                            ((X_LDST_I (insn) << 8)
 600                                             + X_ASI (insn)));
 601                     break;
 602
 603                   case 'y':
 604                     (*info->fprintf_func) (stream, "%%y");
 605                     break;
 606
 607                   case 'u':
 608                   case 'U':
 609                     {
 610                       int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
 611                       char *name = sparc_decode_sparclet_cpreg (val);
 612
 613                       if (name)
 614                         (*info->fprintf_func) (stream, "%s", name);
 615                       else
 616                         (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
 617                       break;
 618                     }
 619                   }
 620               }
 621           }
 622
 623           /* If we are adding or or'ing something to rs1, then
 624              check to see whether the previous instruction was
 625              a sethi to the same register as in the sethi.
 626              If so, attempt to print the result of the add or
 627              or (in this context add and or do the same thing)
 628              and its symbolic value.  */
 629           if (imm_added_to_rs1)
 630             {
 631               unsigned long prev_insn;
 632               int errcode;
 633
 634               errcode =
 635                 (*info->read_memory_func)
 636                   (memaddr - 4, buffer, sizeof (buffer), info);
 637               prev_insn = bfd_getb32 (buffer);
 638
 639               if (errcode == 0)
 640                 {
 641                   /* If it is a delayed branch, we need to look at the
 642                      instruction before the delayed branch.  This handles
 643                      sequences such as
 644
 645                      sethi %o1, %hi(_foo), %o1
 646                      call _printf
 647                      or %o1, %lo(_foo), %o1
 648                      */
 649
 650                   if (is_delayed_branch (prev_insn))
 651                     {
 652                       errcode = (*info->read_memory_func)
 653                         (memaddr - 8, buffer, sizeof (buffer), info);
 654                       prev_insn = bfd_getb32 (buffer);
 655                     }
 656                 }
 657
 658               /* If there was a problem reading memory, then assume
 659                  the previous instruction was not sethi.  */
 660               if (errcode == 0)
 661                 {
 662                   /* Is it sethi to the same register?  */
 663                   if ((prev_insn & 0xc1c00000) == 0x01000000
 664                       && X_RD (prev_insn) == X_RS1 (insn))
 665                     {
 666                       (*info->fprintf_func) (stream, "\t! ");
 667                       info->target =
 668                         (0xFFFFFFFF & (int) X_IMM22 (prev_insn) << 10)
 669                         | SEX (X_IMM13 (insn), 13);
 670                       (*info->print_address_func) (info->target, info);
 671                       info->insn_type = dis_dref;
 672                       info->data_size = 4;  /* FIXME!!! */
 673                     }
 674                 }
 675             }
 676
 677           if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
 678             {
 679                 /* FIXME -- check is_annulled flag */
 680               if (opcode->flags & F_UNBR)
 681                 info->insn_type = dis_branch;
 682               if (opcode->flags & F_CONDBR)
 683                 info->insn_type = dis_condbranch;
 684               if (opcode->flags & F_JSR)
 685                 info->insn_type = dis_jsr;
 686               if (opcode->flags & F_DELAYED)
 687                 info->branch_delay_insns = 1;
 688             }
 689
 690           return sizeof (buffer);
 691         }
 692     }
 693
 694   info->insn_type = dis_noninsn;        /* Mark as non-valid instruction */
 695   (*info->fprintf_func) (stream, "unknown");
 696   return sizeof (buffer);
 697 }
 698
 699 /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values.  */
 700
 701 static int
 702 compute_arch_mask (mach)
 703      unsigned long mach;
 704 {
 705   switch (mach)
 706     {
 707     case 0 :
 708     case bfd_mach_sparc :
 709       return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
 710     case bfd_mach_sparc_sparclet :
 711       return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
 712     case bfd_mach_sparc_sparclite :
 713       /* sparclites insns are recognized by default (because that's how
 714          they've always been treated, for better or worse).  Kludge this by
 715          indicating generic v8 is also selected.  */
 716       return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
 717               | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
 718     case bfd_mach_sparc_v8plus :
 719     case bfd_mach_sparc_v9 :
 720       return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
 721     case bfd_mach_sparc_v8plusa :
 722     case bfd_mach_sparc_v9a :
 723       return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
 724     }
 725   abort ();
 726 }
 727
 728 /* Compare opcodes A and B.  */
 729
 730 static int
 731 compare_opcodes (a, b)
 732      char *a, *b;
 733 {
 734   struct sparc_opcode *op0 = (struct sparc_opcode *) a;
 735   struct sparc_opcode *op1 = (struct sparc_opcode *) b;
 736   unsigned long int match0 = op0->match, match1 = op1->match;
 737   unsigned long int lose0 = op0->lose, lose1 = op1->lose;
 738   register unsigned int i;
 739
 740   /* If one (and only one) insn isn't supported by the current architecture,
 741      prefer the one that is.  If neither are supported, but they're both for
 742      the same architecture, continue processing.  Otherwise (both unsupported
 743      and for different architectures), prefer lower numbered arch's (fudged
 744      by comparing the bitmasks).  */
 745   if (op0->architecture & current_arch_mask)
 746     {
 747       if (! (op1->architecture & current_arch_mask))
 748         return -1;
 749     }
 750   else
 751     {
 752       if (op1->architecture & current_arch_mask)
 753         return 1;
 754       else if (op0->architecture != op1->architecture)
 755         return op0->architecture - op1->architecture;
 756     }
 757
 758   /* If a bit is set in both match and lose, there is something
 759      wrong with the opcode table.  */
 760   if (match0 & lose0)
 761     {
 762       fprintf (stderr, "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
 763                op0->name, match0, lose0);
 764       op0->lose &= ~op0->match;
 765       lose0 = op0->lose;
 766     }
 767
 768   if (match1 & lose1)
 769     {
 770       fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
 771                op1->name, match1, lose1);
 772       op1->lose &= ~op1->match;
 773       lose1 = op1->lose;
 774     }
 775
 776   /* Because the bits that are variable in one opcode are constant in
 777      another, it is important to order the opcodes in the right order.  */
 778   for (i = 0; i < 32; ++i)
 779     {
 780       unsigned long int x = 1 << i;
 781       int x0 = (match0 & x) != 0;
 782       int x1 = (match1 & x) != 0;
 783
 784       if (x0 != x1)
 785         return x1 - x0;
 786     }
 787
 788   for (i = 0; i < 32; ++i)
 789     {
 790       unsigned long int x = 1 << i;
 791       int x0 = (lose0 & x) != 0;
 792       int x1 = (lose1 & x) != 0;
 793
 794       if (x0 != x1)
 795         return x1 - x0;
 796     }
 797
 798   /* They are functionally equal.  So as long as the opcode table is
 799      valid, we can put whichever one first we want, on aesthetic grounds.  */
 800
 801   /* Our first aesthetic ground is that aliases defer to real insns.  */
 802   {
 803     int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
 804     if (alias_diff != 0)
 805       /* Put the one that isn't an alias first.  */
 806       return alias_diff;
 807   }
 808
 809   /* Except for aliases, two "identical" instructions had
 810      better have the same opcode.  This is a sanity check on the table.  */
 811   i = strcmp (op0->name, op1->name);
 812   if (i)
 813     {
 814       if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
 815         return i;
 816       else
 817         fprintf (stderr,
 818                  "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n",
 819                  op0->name, op1->name);
 820     }
 821
 822   /* Fewer arguments are preferred.  */
 823   {
 824     int length_diff = strlen (op0->args) - strlen (op1->args);
 825     if (length_diff != 0)
 826       /* Put the one with fewer arguments first.  */
 827       return length_diff;
 828   }
 829
 830   /* Put 1+i before i+1.  */
 831   {
 832     char *p0 = (char *) strchr(op0->args, '+');
 833     char *p1 = (char *) strchr(op1->args, '+');
 834
 835     if (p0 && p1)
 836       {
 837         /* There is a plus in both operands.  Note that a plus
 838            sign cannot be the first character in args,
 839            so the following [-1]'s are valid.  */
 840         if (p0[-1] == 'i' && p1[1] == 'i')
 841           /* op0 is i+1 and op1 is 1+i, so op1 goes first.  */
 842           return 1;
 843         if (p0[1] == 'i' && p1[-1] == 'i')
 844           /* op0 is 1+i and op1 is i+1, so op0 goes first.  */
 845           return -1;
 846       }
 847   }
 848
 849   /* Put 1,i before i,1.  */
 850   {
 851     int i0 = strncmp (op0->args, "i,1", 3) == 0;
 852     int i1 = strncmp (op1->args, "i,1", 3) == 0;
 853
 854     if (i0 ^ i1)
 855       return i0 - i1;
 856   }
 857
 858   /* They are, as far as we can tell, identical.
 859      Since qsort may have rearranged the table partially, there is
 860      no way to tell which one was first in the opcode table as
 861      written, so just say there are equal.  */
 862   return 0;
 863 }
 864
 865 /* Build a hash table from the opcode table.  */
 866
 867 static void
 868 build_hash_table (table, hash_table, num_opcodes)
 869      struct sparc_opcode *table;
 870      struct opcode_hash **hash_table;
 871      int num_opcodes;
 872 {
 873   register int i;
 874   int hash_count[HASH_SIZE];
 875   static struct opcode_hash *hash_buf = NULL;
 876
 877   /* Start at the end of the table and work backwards so that each
 878      chain is sorted.  */
 879
 880   memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
 881   memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
 882   if (hash_buf != NULL)
 883     free (hash_buf);
 884   hash_buf = (struct opcode_hash *) xmalloc (sizeof (struct opcode_hash) * num_opcodes);
 885   for (i = num_opcodes - 1; i >= 0; --i)
 886     {
 887       register int hash = HASH_INSN (sparc_opcodes[i].match);
 888       register struct opcode_hash *h = &hash_buf[i];
 889       h->next = hash_table[hash];
 890       h->opcode = &sparc_opcodes[i];
 891       hash_table[hash] = h;
 892       ++hash_count[hash];
 893     }
 894
 895 #if 0 /* for debugging */
 896   {
 897     int min_count = num_opcodes, max_count = 0;
 898     int total;
 899
 900     for (i = 0; i < HASH_SIZE; ++i)
 901       {
 902         if (hash_count[i] < min_count)
 903           min_count = hash_count[i];
 904         if (hash_count[i] > max_count)
 905           max_count = hash_count[i];
 906         total += hash_count[i];
 907       }
 908
 909     printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
 910             min_count, max_count, (double) total / HASH_SIZE);
 911   }
 912 #endif
 913 }