opcodes/tic80-opc.c

   1 /* Opcode table for TI TMS320C80 (MVP).
   2    Copyright 1996 Free Software Foundation, Inc.
   3
   4 This file is part of GDB, GAS, and the GNU binutils.
   5
   6 GDB, GAS, and the GNU binutils are free software; you can redistribute
   7 them and/or modify them under the terms of the GNU General Public
   8 License as published by the Free Software Foundation; either version
   9 1, or (at your option) any later version.
  10
  11 GDB, GAS, and the GNU binutils are distributed in the hope that they
  12 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  13 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  14 the GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this file; see the file COPYING.  If not, write to the Free
  18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20 #include <stdio.h>
  21 #include "ansidecl.h"
  22 #include "opcode/tic80.h"
  23
  24 /* This file holds the TMS320C80 (MVP) opcode table.  The table is
  25    strictly constant data, so the compiler should be able to put it in
  26    the .text section.
  27
  28    This file also holds the operand table.  All knowledge about
  29    inserting operands into instructions and vice-versa is kept in this
  30    file.  */
  31
  32 \f
  33 /* The operands table.  The fields are:
  34
  35         bits, shift, insertion function, extraction function, flags
  36  */
  37
  38 const struct tic80_operand tic80_operands[] =
  39 {
  40
  41   /* The zero index is used to indicate the end of the list of operands.  */
  42
  43 #define UNUSED (0)
  44   { 0, 0, 0, 0, 0 },
  45
  46   /* Short signed immediate value in bits 14-0. */
  47
  48 #define SSI (UNUSED + 1)
  49   { 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
  50
  51   /* Short unsigned immediate value in bits 14-0 */
  52
  53 #define SUI (SSI + 1)
  54   { 15, 0, NULL, NULL, 0 },
  55
  56   /* Short unsigned bitfield in bits 14-0.  We distinguish this
  57      from a regular unsigned immediate value only for the convenience
  58      of the disassembler and the user. */
  59
  60 #define SUBF (SUI + 1)
  61   { 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
  62
  63   /* Long signed immediate in following 32 bit word */
  64
  65 #define LSI (SUBF + 1)
  66   { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
  67
  68   /* Long unsigned immediate in following 32 bit word */
  69
  70 #define LUI (LSI + 1)
  71   { 32, 0, NULL, NULL, 0 },
  72
  73   /* Long unsigned bitfield in following 32 bit word.  We distinguish
  74      this from a regular unsigned immediate value only for the
  75      convenience of the disassembler and the user. */
  76
  77 #define LUBF (LUI + 1)
  78   { 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
  79
  80   /* Register in bits 4-0 */
  81
  82 #define REG0 (LUBF + 1)
  83   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR },
  84
  85   /* Register in bits 26-22 */
  86
  87 #define REG22 (REG0 + 1)
  88   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR },
  89
  90   /* Register in bits 31-27 */
  91
  92 #define REG27 (REG22 + 1)
  93   { 5, 27, NULL, NULL, TIC80_OPERAND_GPR },
  94
  95 };
  96
  97 const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
  98
  99 \f
 100 /* Macros used to generate entries for the opcodes table. */
 101
 102 #define FIXME 0
 103
 104 /* Short-Immediate Format Instructions */
 105 #define OP_SI(x)        (((x) & 0x7F) << 15)
 106 #define MASK_SI         OP_SI(0x7F)
 107 #define MASK_SI_M       OP_SI(0x7B)     /* Short-Immediate with embedded M bit */
 108
 109 /* Long-Immediate Format Instructions */
 110 #define OP_LI(x)        (((x) & 0x3FF) << 12)
 111 #define MASK_LI         OP_LI(0x3FF)
 112 #define MASK_LI_M       OP_LI(0x3F7)    /* Long-Immediate with embedded M bit */
 113
 114 /* Register Format Instructions */
 115 #define OP_REG(x)       OP_LI(x)        /* For readability */
 116 #define MASK_REG        MASK_LI         /* For readability */
 117 #define MASK_REG_M      MASK_LI_M       /* For readability */
 118
 119 const struct tic80_opcode tic80_opcodes[] = {
 120
 121   /* Signed integer ADD */
 122
 123   {"add",       OP_SI(0x58),    MASK_SI,        FMT_SI,         {SSI, REG22, REG27}     },
 124   {"add",       OP_LI(0x3B1),   MASK_LI,        FMT_LI,         {LSI, REG22, REG27}     },
 125   {"add",       OP_REG(0x3B0),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 126
 127   /* Unsigned integer ADD */
 128
 129   {"addu",      OP_SI(0x59),    MASK_SI,        FMT_SI,         {SSI, REG22, REG27}     },
 130   {"addu",      OP_LI(0x3B3),   MASK_LI,        FMT_LI,         {LSI, REG22, REG27}     },
 131   {"addu",      OP_REG(0x3B2),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 132
 133   /* Bitwise AND */
 134
 135   {"and",       OP_SI(0x11),    MASK_SI,        FMT_SI,         {SUBF, REG22, REG27}    },
 136   {"and",       OP_LI(0x323),   MASK_LI,        FMT_LI,         {LUBF, REG22, REG27}    },
 137   {"and",       OP_REG(0x322),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 138
 139   {"and.tt",    OP_SI(0x11),    MASK_SI,        FMT_SI,         {SUBF, REG22, REG27}    },
 140   {"and.tt",    OP_LI(0x323),   MASK_LI,        FMT_LI,         {LUBF, REG22, REG27}    },
 141   {"and.tt",    OP_REG(0x322),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 142
 143   /* Bitwise AND with ones complement of both sources */
 144
 145   {"and.ff",    OP_SI(0x18),    MASK_SI,        FMT_SI,         {SUBF, REG22, REG27}    },
 146   {"and.ff",    OP_LI(0x331),   MASK_LI,        FMT_LI,         {LUBF, REG22, REG27}    },
 147   {"and.ff",    OP_REG(0x330),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 148
 149   /* Bitwise AND with ones complement of source 1 */
 150
 151   {"and.ft",    OP_SI(0x14),    MASK_SI,        FMT_SI,         {SUBF, REG22, REG27}    },
 152   {"and.ft",    OP_LI(0x329),   MASK_LI,        FMT_LI,         {LUBF, REG22, REG27}    },
 153   {"and.ft",    OP_REG(0x328),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 154
 155   /* Bitwise AND with ones complement of source 2 */
 156
 157   {"and.tf",    OP_SI(0x12),    MASK_SI,        FMT_SI,         {SUBF, REG22, REG27}    },
 158   {"and.tf",    OP_LI(0x325),   MASK_LI,        FMT_LI,         {LUBF, REG22, REG27}    },
 159   {"and.tf",    OP_REG(0x324),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 160
 161   /* WORK IN PROGRESS BELOW THIS POINT */
 162
 163   {"brcr",      OP_LI(0x30D),   MASK_LI,        FMT_LI,         FIXME},
 164   {"brcr",      OP_REG(0x30C),  MASK_REG,       FMT_REG,        FIXME},
 165   {"brcr",      OP_SI(0x6),     MASK_SI,        FMT_SI,         FIXME},
 166   {"cmnd",      OP_LI(0x305),   MASK_LI,        FMT_LI,         FIXME},
 167   {"cmnd",      OP_REG(0x304),  MASK_REG,       FMT_REG,        FIXME},
 168   {"cmnd",      OP_SI(0x2),     MASK_SI,        FMT_SI,         FIXME},
 169   {"illop0",    OP_SI(0),       MASK_SI,        FMT_SI,         FIXME},
 170   {"ld",        OP_LI(0x345),   MASK_LI_M,      FMT_LI,         FIXME},
 171   {"ld",        OP_REG(0x344),  MASK_REG_M,     FMT_REG,        FIXME},
 172   {"ld",        OP_SI(0x22),    MASK_SI_M,      FMT_SI,         FIXME},
 173   {"ld.b",      OP_LI(0x341),   MASK_LI_M,      FMT_LI,         FIXME},
 174   {"ld.b",      OP_REG(0x340),  MASK_REG_M,     FMT_REG,        FIXME},
 175   {"ld.b",      OP_SI(0x20),    MASK_SI_M,      FMT_SI,         FIXME},
 176   {"ld.d",      OP_LI(0x347),   MASK_LI_M,      FMT_LI,         FIXME},
 177   {"ld.d",      OP_REG(0x346),  MASK_REG_M,     FMT_REG,        FIXME},
 178   {"ld.d",      OP_SI(0x23),    MASK_SI_M,      FMT_SI,         FIXME},
 179   {"ld.h",      OP_LI(0x343),   MASK_LI_M,      FMT_LI,         FIXME},
 180   {"ld.h",      OP_REG(0x342),  MASK_REG_M,     FMT_REG,        FIXME},
 181   {"ld.h",      OP_SI(0x21),    MASK_SI_M,      FMT_SI,         FIXME},
 182   {"ld.u",      OP_LI(0x355),   MASK_LI_M,      FMT_LI,         FIXME},
 183   {"ld.u",      OP_REG(0x354),  MASK_REG_M,     FMT_REG,        FIXME},
 184   {"ld.u",      OP_SI(0x2A),    MASK_SI_M,      FMT_SI,         FIXME},
 185   {"ld.ub",     OP_LI(0x351),   MASK_LI_M,      FMT_LI,         FIXME},
 186   {"ld.ub",     OP_REG(0x350),  MASK_REG_M,     FMT_REG,        FIXME},
 187   {"ld.ub",     OP_SI(0x28),    MASK_SI_M,      FMT_SI,         FIXME},
 188   {"ld.ud",     OP_LI(0x357),   MASK_LI_M,      FMT_LI,         FIXME},
 189   {"ld.ud",     OP_REG(0x356),  MASK_REG_M,     FMT_REG,        FIXME},
 190   {"ld.ud",     OP_SI(0x2B),    MASK_SI_M,      FMT_SI,         FIXME},
 191   {"ld.uh",     OP_LI(0x353),   MASK_LI_M,      FMT_LI,         FIXME},
 192   {"ld.uh",     OP_REG(0x352),  MASK_REG_M,     FMT_REG,        FIXME},
 193   {"ld.uh",     OP_SI(0x29),    MASK_SI_M,      FMT_SI,         FIXME},
 194   {"or.ff",     OP_LI(0x33D),   MASK_LI,        FMT_LI,         FIXME},
 195   {"or.ff",     OP_REG(0x33C),  MASK_REG,       FMT_REG,        FIXME},
 196   {"or.ff",     OP_SI(0x1E),    MASK_SI,        FMT_SI,         FIXME},
 197   {"or.ft",     OP_LI(0x33B),   MASK_LI,        FMT_LI,         FIXME},
 198   {"or.ft",     OP_REG(0x33A),  MASK_REG,       FMT_REG,        FIXME},
 199   {"or.ft",     OP_SI(0x1D),    MASK_SI,        FMT_SI,         FIXME},
 200   {"or.tf",     OP_LI(0x337),   MASK_LI,        FMT_LI,         FIXME},
 201   {"or.tf",     OP_REG(0x336),  MASK_REG,       FMT_REG,        FIXME},
 202   {"or.tf",     OP_SI(0x1B),    MASK_SI,        FMT_SI,         FIXME},
 203   {"or.tt",     OP_LI(0x32F),   MASK_LI,        FMT_LI,         FIXME},
 204   {"or.tt",     OP_REG(0x32E),  MASK_REG,       FMT_REG,        FIXME},
 205   {"or.tt",     OP_SI(0x17),    MASK_SI,        FMT_SI,         FIXME},
 206   {"rdcr",      OP_LI(0x309),   MASK_LI,        FMT_LI,         FIXME},
 207   {"rdcr",      OP_REG(0x308),  MASK_REG,       FMT_REG,        FIXME},
 208   {"rdcr",      OP_SI(0x4),     MASK_SI,        FMT_SI,         FIXME},
 209   {"shift.dm",  OP_REG(0x312),  MASK_REG,       FMT_REG,        FIXME},
 210   {"shift.dm",  OP_SI(0x9),     MASK_SI,        FMT_SI,         FIXME},
 211   {"shift.ds",  OP_REG(0x314),  MASK_REG,       FMT_REG,        FIXME},
 212   {"shift.ds",  OP_SI(0xA),     MASK_SI,        FMT_SI,         FIXME},
 213   {"shift.dz",  OP_REG(0x310),  MASK_REG,       FMT_REG,        FIXME},
 214   {"shift.dz",  OP_SI(0x8),     MASK_SI,        FMT_SI,         FIXME},
 215   {"shift.em",  OP_REG(0x318),  MASK_REG,       FMT_REG,        FIXME},
 216   {"shift.em",  OP_SI(0xC),     MASK_SI,        FMT_SI,         FIXME},
 217   {"shift.es",  OP_REG(0x31A),  MASK_REG,       FMT_REG,        FIXME},
 218   {"shift.es",  OP_SI(0xD),     MASK_SI,        FMT_SI,         FIXME},
 219   {"shift.ez",  OP_REG(0x316),  MASK_REG,       FMT_REG,        FIXME},
 220   {"shift.ez",  OP_SI(0xB),     MASK_SI,        FMT_SI,         FIXME},
 221   {"shift.im",  OP_REG(0x31E),  MASK_REG,       FMT_REG,        FIXME},
 222   {"shift.im",  OP_SI(0xF),     MASK_SI,        FMT_SI,         FIXME},
 223   {"shift.iz",  OP_REG(0x31C),  MASK_REG,       FMT_REG,        FIXME},
 224   {"shift.iz",  OP_SI(0xE),     MASK_SI,        FMT_SI,         FIXME},
 225   {"st",        OP_LI(0x365),   MASK_LI_M,      FMT_LI,         FIXME},
 226   {"st",        OP_REG(0x364),  MASK_REG_M,     FMT_REG,        FIXME},
 227   {"st",        OP_SI(0x32),    MASK_SI_M,      FMT_SI,         FIXME},
 228   {"st.b",      OP_LI(0x361),   MASK_LI_M,      FMT_LI,         FIXME},
 229   {"st.b",      OP_REG(0x360),  MASK_REG_M,     FMT_REG,        FIXME},
 230   {"st.b",      OP_SI(0x30),    MASK_SI_M,      FMT_SI,         FIXME},
 231   {"st.d",      OP_LI(0x367),   MASK_LI_M,      FMT_LI,         FIXME},
 232   {"st.d",      OP_REG(0x366),  MASK_REG_M,     FMT_REG,        FIXME},
 233   {"st.d",      OP_SI(0x33),    MASK_SI_M,      FMT_SI,         FIXME},
 234   {"st.h",      OP_LI(0x363),   MASK_LI_M,      FMT_LI,         FIXME},
 235   {"st.h",      OP_REG(0x362),  MASK_REG_M,     FMT_REG,        FIXME},
 236   {"st.h",      OP_SI(0x31),    MASK_SI_M,      FMT_SI,         FIXME},
 237   {"swcr",      OP_LI(0x30B),   MASK_LI,        FMT_LI,         FIXME},
 238   {"swcr",      OP_REG(0x30A),  MASK_REG,       FMT_REG,        FIXME},
 239   {"swcr",      OP_SI(0x5),     MASK_SI,        FMT_SI,         FIXME},
 240   {"trap",      OP_LI(0x303),   MASK_LI,        FMT_LI,         FIXME},
 241   {"trap",      OP_REG(0x302),  MASK_REG,       FMT_REG,        FIXME},
 242   {"trap",      OP_SI(0x1),     MASK_SI,        FMT_SI,         FIXME},
 243   {"xnor",      OP_LI(0x333),   MASK_LI,        FMT_LI,         FIXME},
 244   {"xnor",      OP_REG(0x332),  MASK_REG,       FMT_REG,        FIXME},
 245   {"xnor",      OP_SI(0x19),    MASK_SI,        FMT_SI,         FIXME},
 246   {"xor",       OP_LI(0x32D),   MASK_LI,        FMT_LI,         FIXME},
 247   {"xor",       OP_REG(0x32C),  MASK_REG,       FMT_REG,        FIXME},
 248   {"xor",       OP_SI(0x16),    MASK_SI,        FMT_SI,         FIXME},
 249
 250 };
 251
 252 const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]);
 253