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git.ipfire.org Git - people/ms/u-boot.git/blob - post/cpu/mpc8xx/ether.c
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * The Serial Communication Controllers (SCC) listed in ctlr_list array below
30 * are tested in the loopback ethernet mode.
31 * The controllers are configured accordingly and several packets
32 * are transmitted. The configurable test parameters are:
33 * MIN_PACKET_LENGTH - minimum size of packet to transmit
34 * MAX_PACKET_LENGTH - maximum size of packet to transmit
35 * TEST_NUM - number of tests
39 #if CONFIG_POST & CONFIG_SYS_POST_ETHER
40 #if defined(CONFIG_8xx)
42 #elif defined(CONFIG_MPC8260)
43 #include <asm/cpm_8260.h>
45 #error "Apparently a bad configuration, please fix."
52 DECLARE_GLOBAL_DATA_PTR
;
54 #define MIN_PACKET_LENGTH 64
55 #define MAX_PACKET_LENGTH 256
60 extern void spi_init_f (void);
61 extern void spi_init_r (void);
63 /* The list of controllers to test */
64 #if defined(CONFIG_MPC823)
65 static int ctlr_list
[][2] = { {CTLR_SCC
, 1} };
67 static int ctlr_list
[][2] = { };
70 #define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0]))
73 void (*init
) (int index
);
74 void (*halt
) (int index
);
75 int (*send
) (int index
, volatile void *packet
, int length
);
76 int (*recv
) (int index
, void *packet
, int length
);
79 static char *ctlr_name
[1] = { "SCC" };
81 /* Ethernet Transmit and Receive Buffers */
82 #define DBUF_LENGTH 1520
88 static char txbuf
[DBUF_LENGTH
];
90 static uint rxIdx
; /* index of the current RX buffer */
91 static uint txIdx
; /* index of the current TX buffer */
94 * SCC Ethernet Tx and Rx buffer descriptors allocated at the
95 * immr->udata_bd address on Dual-Port RAM
96 * Provide for Double Buffering
99 typedef volatile struct CommonBufferDescriptor
{
100 cbd_t rxbd
[PKTBUFSRX
]; /* Rx BD */
101 cbd_t txbd
[TX_BUF_CNT
]; /* Tx BD */
110 static void scc_init (int scc_index
)
115 { PROFF_SCC1
, PROFF_SCC2
, PROFF_SCC3
, PROFF_SCC4
};
116 static unsigned int cpm_cr
[] =
117 { CPM_CR_CH_SCC1
, CPM_CR_CH_SCC2
, CPM_CR_CH_SCC3
,
121 scc_enet_t
*pram_ptr
;
123 volatile immap_t
*immr
= (immap_t
*) CONFIG_SYS_IMMR
;
125 immr
->im_cpm
.cp_scc
[scc_index
].scc_gsmrl
&=
126 ~(SCC_GSMRL_ENR
| SCC_GSMRL_ENT
);
128 #if defined(CONFIG_FADS)
129 #if defined(CONFIG_MPC860T) || defined(CONFIG_MPC86xADS)
130 /* The FADS860T and MPC86xADS don't use the MODEM_EN or DATA_VOICE signals. */
131 *((uint
*) BCSR4
) &= ~BCSR4_ETHLOOP
;
132 *((uint
*) BCSR4
) |= BCSR4_TFPLDL
| BCSR4_TPSQEL
;
133 *((uint
*) BCSR1
) &= ~BCSR1_ETHEN
;
135 *((uint
*) BCSR4
) &= ~(BCSR4_ETHLOOP
| BCSR4_MODEM_EN
);
136 *((uint
*) BCSR4
) |= BCSR4_TFPLDL
| BCSR4_TPSQEL
| BCSR4_DATA_VOICE
;
137 *((uint
*) BCSR1
) &= ~BCSR1_ETHEN
;
141 pram_ptr
= (scc_enet_t
*) & (immr
->im_cpm
.cp_dparam
[proff
[scc_index
]]);
146 #ifdef CONFIG_SYS_ALLOC_DPRAM
147 rtx
= (RTXBD
*) (immr
->im_cpm
.cp_dpmem
+
148 dpram_alloc_align (sizeof (RTXBD
), 8));
150 rtx
= (RTXBD
*) (immr
->im_cpm
.cp_dpmem
+ CPM_SCC_BASE
);
155 #if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
156 /* Configure port A pins for Txd and Rxd.
158 immr
->im_ioport
.iop_papar
|= (PA_ENET_RXD
| PA_ENET_TXD
);
159 immr
->im_ioport
.iop_padir
&= ~(PA_ENET_RXD
| PA_ENET_TXD
);
160 immr
->im_ioport
.iop_paodr
&= ~PA_ENET_TXD
;
161 #elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
162 /* Configure port B pins for Txd and Rxd.
164 immr
->im_cpm
.cp_pbpar
|= (PB_ENET_RXD
| PB_ENET_TXD
);
165 immr
->im_cpm
.cp_pbdir
&= ~(PB_ENET_RXD
| PB_ENET_TXD
);
166 immr
->im_cpm
.cp_pbodr
&= ~PB_ENET_TXD
;
168 #error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
171 #if defined(PC_ENET_LBK)
172 /* Configure port C pins to disable External Loopback
174 immr
->im_ioport
.iop_pcpar
&= ~PC_ENET_LBK
;
175 immr
->im_ioport
.iop_pcdir
|= PC_ENET_LBK
;
176 immr
->im_ioport
.iop_pcso
&= ~PC_ENET_LBK
;
177 immr
->im_ioport
.iop_pcdat
&= ~PC_ENET_LBK
; /* Disable Loopback */
178 #endif /* PC_ENET_LBK */
180 /* Configure port C pins to enable CLSN and RENA.
182 immr
->im_ioport
.iop_pcpar
&= ~(PC_ENET_CLSN
| PC_ENET_RENA
);
183 immr
->im_ioport
.iop_pcdir
&= ~(PC_ENET_CLSN
| PC_ENET_RENA
);
184 immr
->im_ioport
.iop_pcso
|= (PC_ENET_CLSN
| PC_ENET_RENA
);
186 /* Configure port A for TCLK and RCLK.
188 immr
->im_ioport
.iop_papar
|= (PA_ENET_TCLK
| PA_ENET_RCLK
);
189 immr
->im_ioport
.iop_padir
&= ~(PA_ENET_TCLK
| PA_ENET_RCLK
);
192 * Configure Serial Interface clock routing -- see section 16.7.5.3
193 * First, clear all SCC bits to zero, then set the ones we want.
196 immr
->im_cpm
.cp_sicr
&= ~SICR_ENET_MASK
;
197 immr
->im_cpm
.cp_sicr
|= SICR_ENET_CLKRT
;
200 * SCC2 receive clock is BRG2
201 * SCC2 transmit clock is BRG3
203 immr
->im_cpm
.cp_brgc2
= 0x0001000C;
204 immr
->im_cpm
.cp_brgc3
= 0x0001000C;
206 immr
->im_cpm
.cp_sicr
&= ~0x00003F00;
207 immr
->im_cpm
.cp_sicr
|= 0x00000a00;
212 * Initialize SDCR -- see section 16.9.23.7
213 * SDMA configuration register
215 immr
->im_siu_conf
.sc_sdcr
= 0x01;
219 * Setup SCC Ethernet Parameter RAM
222 pram_ptr
->sen_genscc
.scc_rfcr
= 0x18; /* Normal Operation and Mot byte ordering */
223 pram_ptr
->sen_genscc
.scc_tfcr
= 0x18; /* Mot byte ordering, Normal access */
225 pram_ptr
->sen_genscc
.scc_mrblr
= DBUF_LENGTH
; /* max. ET package len 1520 */
227 pram_ptr
->sen_genscc
.scc_rbase
= (unsigned int) (&rtx
->rxbd
[0]); /* Set RXBD tbl start at Dual Port */
228 pram_ptr
->sen_genscc
.scc_tbase
= (unsigned int) (&rtx
->txbd
[0]); /* Set TXBD tbl start at Dual Port */
231 * Setup Receiver Buffer Descriptors (13.14.24.18)
236 for (i
= 0; i
< PKTBUFSRX
; i
++) {
237 rtx
->rxbd
[i
].cbd_sc
= BD_ENET_RX_EMPTY
;
238 rtx
->rxbd
[i
].cbd_datlen
= 0; /* Reset */
239 rtx
->rxbd
[i
].cbd_bufaddr
= (uint
) NetRxPackets
[i
];
242 rtx
->rxbd
[PKTBUFSRX
- 1].cbd_sc
|= BD_ENET_RX_WRAP
;
245 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
247 * Add PADs to Short FRAMES, Wrap, Last, Tx CRC
250 for (i
= 0; i
< TX_BUF_CNT
; i
++) {
251 rtx
->txbd
[i
].cbd_sc
=
252 (BD_ENET_TX_PAD
| BD_ENET_TX_LAST
| BD_ENET_TX_TC
);
253 rtx
->txbd
[i
].cbd_datlen
= 0; /* Reset */
254 rtx
->txbd
[i
].cbd_bufaddr
= (uint
) (&txbuf
[0]);
257 rtx
->txbd
[TX_BUF_CNT
- 1].cbd_sc
|= BD_ENET_TX_WRAP
;
260 * Enter Command: Initialize Rx Params for SCC
263 do { /* Spin until ready to issue command */
265 } while (immr
->im_cpm
.cp_cpcr
& CPM_CR_FLG
);
267 immr
->im_cpm
.cp_cpcr
=
268 ((CPM_CR_INIT_RX
<< 8) | (cpm_cr
[scc_index
] << 4) |
270 do { /* Spin until command processed */
272 } while (immr
->im_cpm
.cp_cpcr
& CPM_CR_FLG
);
275 * Ethernet Specific Parameter RAM
276 * see table 13-16, pg. 660,
277 * pg. 681 (example with suggested settings)
280 pram_ptr
->sen_cpres
= ~(0x0); /* Preset CRC */
281 pram_ptr
->sen_cmask
= 0xdebb20e3; /* Constant Mask for CRC */
282 pram_ptr
->sen_crcec
= 0x0; /* Error Counter CRC (unused) */
283 pram_ptr
->sen_alec
= 0x0; /* Alignment Error Counter (unused) */
284 pram_ptr
->sen_disfc
= 0x0; /* Discard Frame Counter (unused) */
285 pram_ptr
->sen_pads
= 0x8888; /* Short Frame PAD Characters */
287 pram_ptr
->sen_retlim
= 15; /* Retry Limit Threshold */
288 pram_ptr
->sen_maxflr
= 1518; /* MAX Frame Length Register */
289 pram_ptr
->sen_minflr
= 64; /* MIN Frame Length Register */
291 pram_ptr
->sen_maxd1
= DBUF_LENGTH
; /* MAX DMA1 Length Register */
292 pram_ptr
->sen_maxd2
= DBUF_LENGTH
; /* MAX DMA2 Length Register */
294 pram_ptr
->sen_gaddr1
= 0x0; /* Group Address Filter 1 (unused) */
295 pram_ptr
->sen_gaddr2
= 0x0; /* Group Address Filter 2 (unused) */
296 pram_ptr
->sen_gaddr3
= 0x0; /* Group Address Filter 3 (unused) */
297 pram_ptr
->sen_gaddr4
= 0x0; /* Group Address Filter 4 (unused) */
299 #define ea bd->bi_enetaddr
300 pram_ptr
->sen_paddrh
= (ea
[5] << 8) + ea
[4];
301 pram_ptr
->sen_paddrm
= (ea
[3] << 8) + ea
[2];
302 pram_ptr
->sen_paddrl
= (ea
[1] << 8) + ea
[0];
305 pram_ptr
->sen_pper
= 0x0; /* Persistence (unused) */
306 pram_ptr
->sen_iaddr1
= 0x0; /* Individual Address Filter 1 (unused) */
307 pram_ptr
->sen_iaddr2
= 0x0; /* Individual Address Filter 2 (unused) */
308 pram_ptr
->sen_iaddr3
= 0x0; /* Individual Address Filter 3 (unused) */
309 pram_ptr
->sen_iaddr4
= 0x0; /* Individual Address Filter 4 (unused) */
310 pram_ptr
->sen_taddrh
= 0x0; /* Tmp Address (MSB) (unused) */
311 pram_ptr
->sen_taddrm
= 0x0; /* Tmp Address (unused) */
312 pram_ptr
->sen_taddrl
= 0x0; /* Tmp Address (LSB) (unused) */
315 * Enter Command: Initialize Tx Params for SCC
318 do { /* Spin until ready to issue command */
320 } while (immr
->im_cpm
.cp_cpcr
& CPM_CR_FLG
);
322 immr
->im_cpm
.cp_cpcr
=
323 ((CPM_CR_INIT_TX
<< 8) | (cpm_cr
[scc_index
] << 4) |
325 do { /* Spin until command processed */
327 } while (immr
->im_cpm
.cp_cpcr
& CPM_CR_FLG
);
330 * Mask all Events in SCCM - we use polling mode
332 immr
->im_cpm
.cp_scc
[scc_index
].scc_sccm
= 0;
335 * Clear Events in SCCE -- Clear bits by writing 1's
338 immr
->im_cpm
.cp_scc
[scc_index
].scc_scce
= ~(0x0);
342 * Initialize GSMR High 32-Bits
343 * Settings: Normal Mode
346 immr
->im_cpm
.cp_scc
[scc_index
].scc_gsmrh
= 0;
349 * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
353 * TPP = Repeating 10's
358 immr
->im_cpm
.cp_scc
[scc_index
].scc_gsmrl
= (SCC_GSMRL_TCI
|
361 SCC_GSMRL_DIAG_LOOP
|
362 SCC_GSMRL_MODE_ENET
);
365 * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
368 immr
->im_cpm
.cp_scc
[scc_index
].scc_dsr
= 0xd555;
371 * Initialize the PSMR
374 * NIB = Begin searching for SFD 22 bits after RENA
375 * LPB = Loopback Enable (Needed when FDE is set)
377 immr
->im_cpm
.cp_scc
[scc_index
].scc_psmr
= SCC_PSMR_ENCRC
|
378 SCC_PSMR_NIB22
| SCC_PSMR_LPB
;
382 * Configure Ethernet TENA Signal
385 #if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
386 immr
->im_ioport
.iop_pcpar
|= PC_ENET_TENA
;
387 immr
->im_ioport
.iop_pcdir
&= ~PC_ENET_TENA
;
388 #elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
389 immr
->im_cpm
.cp_pbpar
|= PB_ENET_TENA
;
390 immr
->im_cpm
.cp_pbdir
|= PB_ENET_TENA
;
392 #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
395 #if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
397 * Port C is used to control the PHY,MC68160.
399 immr
->im_ioport
.iop_pcdir
|=
400 (PC_ENET_ETHLOOP
| PC_ENET_TPFLDL
| PC_ENET_TPSQEL
);
402 immr
->im_ioport
.iop_pcdat
|= PC_ENET_TPFLDL
;
403 immr
->im_ioport
.iop_pcdat
&= ~(PC_ENET_ETHLOOP
| PC_ENET_TPSQEL
);
404 *((uint
*) BCSR1
) &= ~BCSR1_ETHEN
;
405 #endif /* MPC860ADS */
407 #if defined(CONFIG_AMX860)
409 * Port B is used to control the PHY,MC68160.
411 immr
->im_cpm
.cp_pbdir
|=
412 (PB_ENET_ETHLOOP
| PB_ENET_TPFLDL
| PB_ENET_TPSQEL
);
414 immr
->im_cpm
.cp_pbdat
|= PB_ENET_TPFLDL
;
415 immr
->im_cpm
.cp_pbdat
&= ~(PB_ENET_ETHLOOP
| PB_ENET_TPSQEL
);
417 immr
->im_ioport
.iop_pddir
|= PD_ENET_ETH_EN
;
418 immr
->im_ioport
.iop_pddat
&= ~PD_ENET_ETH_EN
;
423 #ifdef CONFIG_RPXCLASSIC
424 *((uchar
*) BCSR0
) &= ~BCSR0_ETHLPBK
;
425 *((uchar
*) BCSR0
) |= (BCSR0_ETHEN
| BCSR0_COLTEST
| BCSR0_FULLDPLX
);
428 #ifdef CONFIG_RPXLITE
429 *((uchar
*) BCSR0
) |= BCSR0_ETHEN
;
437 * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
440 immr
->im_cpm
.cp_scc
[scc_index
].scc_gsmrl
|=
441 (SCC_GSMRL_ENR
| SCC_GSMRL_ENT
);
444 * Work around transmit problem with first eth packet
446 #if defined (CONFIG_FADS)
447 udelay (10000); /* wait 10 ms */
448 #elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
449 udelay (100000); /* wait 100 ms */
453 static void scc_halt (int scc_index
)
455 volatile immap_t
*immr
= (immap_t
*) CONFIG_SYS_IMMR
;
457 immr
->im_cpm
.cp_scc
[scc_index
].scc_gsmrl
&=
458 ~(SCC_GSMRL_ENR
| SCC_GSMRL_ENT
);
459 immr
->im_ioport
.iop_pcso
&= ~(PC_ENET_CLSN
| PC_ENET_RENA
);
462 static int scc_send (int index
, volatile void *packet
, int length
)
466 while ((rtx
->txbd
[txIdx
].cbd_sc
& BD_ENET_TX_READY
) && (j
< TOUT_LOOP
)) {
467 udelay (1); /* will also trigger Wd if needed */
471 printf ("TX not ready\n");
472 rtx
->txbd
[txIdx
].cbd_bufaddr
= (uint
) packet
;
473 rtx
->txbd
[txIdx
].cbd_datlen
= length
;
474 rtx
->txbd
[txIdx
].cbd_sc
|=
475 (BD_ENET_TX_READY
| BD_ENET_TX_LAST
| BD_ENET_TX_WRAP
);
476 while ((rtx
->txbd
[txIdx
].cbd_sc
& BD_ENET_TX_READY
) && (j
< TOUT_LOOP
)) {
477 udelay (1); /* will also trigger Wd if needed */
481 printf ("TX timeout\n");
482 i
= (rtx
->txbd
[txIdx
].
483 cbd_sc
& BD_ENET_TX_STATS
) /* return only status bits */ ;
487 static int scc_recv (int index
, void *packet
, int max_length
)
491 if (rtx
->rxbd
[rxIdx
].cbd_sc
& BD_ENET_RX_EMPTY
) {
492 goto Done
; /* nothing received */
495 if (!(rtx
->rxbd
[rxIdx
].cbd_sc
& 0x003f)) {
496 length
= rtx
->rxbd
[rxIdx
].cbd_datlen
- 4;
498 (void *) (NetRxPackets
[rxIdx
]),
499 length
< max_length
? length
: max_length
);
502 /* Give the buffer back to the SCC. */
503 rtx
->rxbd
[rxIdx
].cbd_datlen
= 0;
505 /* wrap around buffer index when necessary */
506 if ((rxIdx
+ 1) >= PKTBUFSRX
) {
507 rtx
->rxbd
[PKTBUFSRX
- 1].cbd_sc
=
508 (BD_ENET_RX_WRAP
| BD_ENET_RX_EMPTY
);
511 rtx
->rxbd
[rxIdx
].cbd_sc
= BD_ENET_RX_EMPTY
;
523 static void packet_fill (char *packet
, int length
)
525 char c
= (char) length
;
535 for (i
= 6; i
< length
; i
++) {
540 static int packet_check (char *packet
, int length
)
542 char c
= (char) length
;
545 for (i
= 6; i
< length
; i
++) {
546 if (packet
[i
] != c
++)
553 static int test_ctlr (int ctlr
, int index
)
556 char packet_send
[MAX_PACKET_LENGTH
];
557 char packet_recv
[MAX_PACKET_LENGTH
];
562 ctlr_proc
[ctlr
].init (index
);
564 for (i
= 0; i
< TEST_NUM
; i
++) {
565 for (l
= MIN_PACKET_LENGTH
; l
<= MAX_PACKET_LENGTH
; l
++) {
566 packet_fill (packet_send
, l
);
568 ctlr_proc
[ctlr
].send (index
, packet_send
, l
);
570 length
= ctlr_proc
[ctlr
].recv (index
, packet_recv
,
573 if (length
!= l
|| packet_check (packet_recv
, length
) < 0) {
583 ctlr_proc
[ctlr
].halt (index
);
586 * SCC2 Ethernet parameter RAM space overlaps
587 * the SPI parameter RAM space. So we need to restore
588 * the SPI configuration after SCC2 ethernet test.
590 #if defined(CONFIG_SPI)
591 if (ctlr
== CTLR_SCC
&& index
== 1) {
598 post_log ("ethernet %s%d test failed\n", ctlr_name
[ctlr
],
605 int ether_post_test (int flags
)
610 ctlr_proc
[CTLR_SCC
].init
= scc_init
;
611 ctlr_proc
[CTLR_SCC
].halt
= scc_halt
;
612 ctlr_proc
[CTLR_SCC
].send
= scc_send
;
613 ctlr_proc
[CTLR_SCC
].recv
= scc_recv
;
615 for (i
= 0; i
< CTRL_LIST_SIZE
; i
++) {
616 if (test_ctlr (ctlr_list
[i
][0], ctlr_list
[i
][1]) != 0) {
621 #if !defined(CONFIG_8xx_CONS_NONE)
622 serial_reinit_all ();
627 #endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */