post/cpu/mpc8xx/ether.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25
  26 /*
  27  * Ethernet test
  28  *
  29  * The Serial Communication Controllers (SCC) listed in ctlr_list array below
  30  * are tested in the loopback ethernet mode.
  31  * The controllers are configured accordingly and several packets
  32  * are transmitted. The configurable test parameters are:
  33  *   MIN_PACKET_LENGTH - minimum size of packet to transmit
  34  *   MAX_PACKET_LENGTH - maximum size of packet to transmit
  35  *   TEST_NUM - number of tests
  36  */
  37
  38 #ifdef CONFIG_POST
  39
  40 #include <post.h>
  41 #if CONFIG_POST & CFG_POST_ETHER
  42 #if defined(CONFIG_8xx)
  43 #include <commproc.h>
  44 #elif defined(CONFIG_MPC8260)
  45 #include <asm/cpm_8260.h>
  46 #else
  47 #error "Apparently a bad configuration, please fix."
  48 #endif
  49
  50 #include <command.h>
  51 #include <net.h>
  52 #include <serial.h>
  53
  54 DECLARE_GLOBAL_DATA_PTR;
  55
  56 #define MIN_PACKET_LENGTH       64
  57 #define MAX_PACKET_LENGTH       256
  58 #define TEST_NUM                1
  59
  60 #define CTLR_SCC 0
  61
  62 extern void spi_init_f (void);
  63 extern void spi_init_r (void);
  64
  65 /* The list of controllers to test */
  66 #if defined(CONFIG_MPC823)
  67 static int ctlr_list[][2] = { {CTLR_SCC, 1} };
  68 #else
  69 static int ctlr_list[][2] = { };
  70 #endif
  71
  72 #define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0]))
  73
  74 static struct {
  75         void (*init) (int index);
  76         void (*halt) (int index);
  77         int (*send) (int index, volatile void *packet, int length);
  78         int (*recv) (int index, void *packet, int length);
  79 } ctlr_proc[1];
  80
  81 static char *ctlr_name[1] = { "SCC" };
  82
  83 /* Ethernet Transmit and Receive Buffers */
  84 #define DBUF_LENGTH  1520
  85
  86 #define TX_BUF_CNT 2
  87
  88 #define TOUT_LOOP 100
  89
  90 static char txbuf[DBUF_LENGTH];
  91
  92 static uint rxIdx;              /* index of the current RX buffer */
  93 static uint txIdx;              /* index of the current TX buffer */
  94
  95 /*
  96   * SCC Ethernet Tx and Rx buffer descriptors allocated at the
  97   *  immr->udata_bd address on Dual-Port RAM
  98   * Provide for Double Buffering
  99   */
 100
 101 typedef volatile struct CommonBufferDescriptor {
 102         cbd_t rxbd[PKTBUFSRX];          /* Rx BD */
 103         cbd_t txbd[TX_BUF_CNT];         /* Tx BD */
 104 } RTXBD;
 105
 106 static RTXBD *rtx;
 107
 108   /*
 109    * SCC callbacks
 110    */
 111
 112 static void scc_init (int scc_index)
 113 {
 114         bd_t *bd = gd->bd;
 115
 116         static int proff[] =
 117                         { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };
 118         static unsigned int cpm_cr[] =
 119                         { CPM_CR_CH_SCC1, CPM_CR_CH_SCC2, CPM_CR_CH_SCC3,
 120 CPM_CR_CH_SCC4 };
 121
 122         int i;
 123         scc_enet_t *pram_ptr;
 124
 125         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 126
 127         immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
 128                         ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 129
 130 #if defined(CONFIG_FADS)
 131 #if defined(CONFIG_MPC860T) || defined(CONFIG_MPC86xADS)
 132         /* The FADS860T and MPC86xADS don't use the MODEM_EN or DATA_VOICE signals. */
 133         *((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
 134         *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
 135         *((uint *) BCSR1) &= ~BCSR1_ETHEN;
 136 #else
 137         *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
 138         *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
 139         *((uint *) BCSR1) &= ~BCSR1_ETHEN;
 140 #endif
 141 #endif
 142
 143         pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[proff[scc_index]]);
 144
 145         rxIdx = 0;
 146         txIdx = 0;
 147
 148 #ifdef CFG_ALLOC_DPRAM
 149         rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
 150                                          dpram_alloc_align (sizeof (RTXBD), 8));
 151 #else
 152         rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
 153 #endif
 154
 155 #if 0
 156
 157 #if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
 158         /* Configure port A pins for Txd and Rxd.
 159          */
 160         immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
 161         immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
 162         immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
 163 #elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
 164         /* Configure port B pins for Txd and Rxd.
 165          */
 166         immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
 167         immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
 168         immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
 169 #else
 170 #error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
 171 #endif
 172
 173 #if defined(PC_ENET_LBK)
 174         /* Configure port C pins to disable External Loopback
 175          */
 176         immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
 177         immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
 178         immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
 179         immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK;      /* Disable Loopback */
 180 #endif /* PC_ENET_LBK */
 181
 182         /* Configure port C pins to enable CLSN and RENA.
 183          */
 184         immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
 185         immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
 186         immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
 187
 188         /* Configure port A for TCLK and RCLK.
 189          */
 190         immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
 191         immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
 192
 193         /*
 194          * Configure Serial Interface clock routing -- see section 16.7.5.3
 195          * First, clear all SCC bits to zero, then set the ones we want.
 196          */
 197
 198         immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
 199         immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
 200 #else
 201         /*
 202          * SCC2 receive clock is BRG2
 203          * SCC2 transmit clock is BRG3
 204          */
 205         immr->im_cpm.cp_brgc2 = 0x0001000C;
 206         immr->im_cpm.cp_brgc3 = 0x0001000C;
 207
 208         immr->im_cpm.cp_sicr &= ~0x00003F00;
 209         immr->im_cpm.cp_sicr |=  0x00000a00;
 210 #endif /* 0 */
 211
 212
 213         /*
 214          * Initialize SDCR -- see section 16.9.23.7
 215          * SDMA configuration register
 216          */
 217         immr->im_siu_conf.sc_sdcr = 0x01;
 218
 219
 220         /*
 221          * Setup SCC Ethernet Parameter RAM
 222          */
 223
 224         pram_ptr->sen_genscc.scc_rfcr = 0x18;   /* Normal Operation and Mot byte ordering */
 225         pram_ptr->sen_genscc.scc_tfcr = 0x18;   /* Mot byte ordering, Normal access */
 226
 227         pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH;   /* max. ET package len 1520 */
 228
 229         pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]);        /* Set RXBD tbl start at Dual Port */
 230         pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]);        /* Set TXBD tbl start at Dual Port */
 231
 232         /*
 233          * Setup Receiver Buffer Descriptors (13.14.24.18)
 234          * Settings:
 235          *     Empty, Wrap
 236          */
 237
 238         for (i = 0; i < PKTBUFSRX; i++) {
 239                 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
 240                 rtx->rxbd[i].cbd_datlen = 0;    /* Reset */
 241                 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
 242         }
 243
 244         rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
 245
 246         /*
 247          * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
 248          * Settings:
 249          *    Add PADs to Short FRAMES, Wrap, Last, Tx CRC
 250          */
 251
 252         for (i = 0; i < TX_BUF_CNT; i++) {
 253                 rtx->txbd[i].cbd_sc =
 254                                 (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
 255                 rtx->txbd[i].cbd_datlen = 0;    /* Reset */
 256                 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
 257         }
 258
 259         rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
 260
 261         /*
 262          * Enter Command:  Initialize Rx Params for SCC
 263          */
 264
 265         do {                            /* Spin until ready to issue command    */
 266                 __asm__ ("eieio");
 267         } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
 268         /* Issue command */
 269         immr->im_cpm.cp_cpcr =
 270                         ((CPM_CR_INIT_RX << 8) | (cpm_cr[scc_index] << 4) |
 271                          CPM_CR_FLG);
 272         do {                            /* Spin until command processed     */
 273                 __asm__ ("eieio");
 274         } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
 275
 276         /*
 277          * Ethernet Specific Parameter RAM
 278          *     see table 13-16, pg. 660,
 279          *     pg. 681 (example with suggested settings)
 280          */
 281
 282         pram_ptr->sen_cpres = ~(0x0);   /* Preset CRC */
 283         pram_ptr->sen_cmask = 0xdebb20e3;       /* Constant Mask for CRC */
 284         pram_ptr->sen_crcec = 0x0;      /* Error Counter CRC (unused) */
 285         pram_ptr->sen_alec = 0x0;       /* Alignment Error Counter (unused) */
 286         pram_ptr->sen_disfc = 0x0;      /* Discard Frame Counter (unused) */
 287         pram_ptr->sen_pads = 0x8888;    /* Short Frame PAD Characters */
 288
 289         pram_ptr->sen_retlim = 15;      /* Retry Limit Threshold */
 290         pram_ptr->sen_maxflr = 1518;    /* MAX Frame Length Register */
 291         pram_ptr->sen_minflr = 64;      /* MIN Frame Length Register */
 292
 293         pram_ptr->sen_maxd1 = DBUF_LENGTH;      /* MAX DMA1 Length Register */
 294         pram_ptr->sen_maxd2 = DBUF_LENGTH;      /* MAX DMA2 Length Register */
 295
 296         pram_ptr->sen_gaddr1 = 0x0;     /* Group Address Filter 1 (unused) */
 297         pram_ptr->sen_gaddr2 = 0x0;     /* Group Address Filter 2 (unused) */
 298         pram_ptr->sen_gaddr3 = 0x0;     /* Group Address Filter 3 (unused) */
 299         pram_ptr->sen_gaddr4 = 0x0;     /* Group Address Filter 4 (unused) */
 300
 301 #define ea bd->bi_enetaddr
 302         pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
 303         pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
 304         pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
 305 #undef ea
 306
 307         pram_ptr->sen_pper = 0x0;       /* Persistence (unused) */
 308         pram_ptr->sen_iaddr1 = 0x0;     /* Individual Address Filter 1 (unused) */
 309         pram_ptr->sen_iaddr2 = 0x0;     /* Individual Address Filter 2 (unused) */
 310         pram_ptr->sen_iaddr3 = 0x0;     /* Individual Address Filter 3 (unused) */
 311         pram_ptr->sen_iaddr4 = 0x0;     /* Individual Address Filter 4 (unused) */
 312         pram_ptr->sen_taddrh = 0x0;     /* Tmp Address (MSB) (unused) */
 313         pram_ptr->sen_taddrm = 0x0;     /* Tmp Address (unused) */
 314         pram_ptr->sen_taddrl = 0x0;     /* Tmp Address (LSB) (unused) */
 315
 316         /*
 317          * Enter Command:  Initialize Tx Params for SCC
 318          */
 319
 320         do {                            /* Spin until ready to issue command    */
 321                 __asm__ ("eieio");
 322         } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
 323         /* Issue command */
 324         immr->im_cpm.cp_cpcr =
 325                         ((CPM_CR_INIT_TX << 8) | (cpm_cr[scc_index] << 4) |
 326                          CPM_CR_FLG);
 327         do {                            /* Spin until command processed     */
 328                 __asm__ ("eieio");
 329         } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
 330
 331         /*
 332          * Mask all Events in SCCM - we use polling mode
 333          */
 334         immr->im_cpm.cp_scc[scc_index].scc_sccm = 0;
 335
 336         /*
 337          * Clear Events in SCCE -- Clear bits by writing 1's
 338          */
 339
 340         immr->im_cpm.cp_scc[scc_index].scc_scce = ~(0x0);
 341
 342
 343         /*
 344          * Initialize GSMR High 32-Bits
 345          * Settings:  Normal Mode
 346          */
 347
 348         immr->im_cpm.cp_scc[scc_index].scc_gsmrh = 0;
 349
 350         /*
 351          * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
 352          * Settings:
 353          *     TCI = Invert
 354          *     TPL =  48 bits
 355          *     TPP = Repeating 10's
 356          *     LOOP = Loopback
 357          *     MODE = Ethernet
 358          */
 359
 360         immr->im_cpm.cp_scc[scc_index].scc_gsmrl = (SCC_GSMRL_TCI |
 361                                                     SCC_GSMRL_TPL_48 |
 362                                                     SCC_GSMRL_TPP_10 |
 363                                                     SCC_GSMRL_DIAG_LOOP |
 364                                                     SCC_GSMRL_MODE_ENET);
 365
 366         /*
 367          * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
 368          */
 369
 370         immr->im_cpm.cp_scc[scc_index].scc_dsr = 0xd555;
 371
 372         /*
 373          * Initialize the PSMR
 374          * Settings:
 375          *  CRC = 32-Bit CCITT
 376          *  NIB = Begin searching for SFD 22 bits after RENA
 377          *  LPB = Loopback Enable (Needed when FDE is set)
 378          */
 379         immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC |
 380                         SCC_PSMR_NIB22 | SCC_PSMR_LPB;
 381
 382 #if 0
 383         /*
 384          * Configure Ethernet TENA Signal
 385          */
 386
 387 #if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
 388         immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
 389         immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
 390 #elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
 391         immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
 392         immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
 393 #else
 394 #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
 395 #endif
 396
 397 #if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
 398         /*
 399          * Port C is used to control the PHY,MC68160.
 400          */
 401         immr->im_ioport.iop_pcdir |=
 402                         (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);
 403
 404         immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
 405         immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
 406         *((uint *) BCSR1) &= ~BCSR1_ETHEN;
 407 #endif /* MPC860ADS */
 408
 409 #if defined(CONFIG_AMX860)
 410         /*
 411          * Port B is used to control the PHY,MC68160.
 412          */
 413         immr->im_cpm.cp_pbdir |=
 414                         (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
 415
 416         immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
 417         immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
 418
 419         immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
 420         immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
 421 #endif /* AMX860 */
 422
 423 #endif /* 0 */
 424
 425 #ifdef CONFIG_RPXCLASSIC
 426         *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
 427         *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
 428 #endif
 429
 430 #ifdef CONFIG_RPXLITE
 431         *((uchar *) BCSR0) |= BCSR0_ETHEN;
 432 #endif
 433
 434 #ifdef CONFIG_MBX
 435         board_ether_init ();
 436 #endif
 437
 438         /*
 439          * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
 440          */
 441
 442         immr->im_cpm.cp_scc[scc_index].scc_gsmrl |=
 443                         (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 444
 445         /*
 446          * Work around transmit problem with first eth packet
 447          */
 448 #if defined (CONFIG_FADS)
 449         udelay (10000);                         /* wait 10 ms */
 450 #elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
 451         udelay (100000);                        /* wait 100 ms */
 452 #endif
 453 }
 454
 455 static void scc_halt (int scc_index)
 456 {
 457         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 458
 459         immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
 460                         ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 461         immr->im_ioport.iop_pcso  &=  ~(PC_ENET_CLSN | PC_ENET_RENA);
 462 }
 463
 464 static int scc_send (int index, volatile void *packet, int length)
 465 {
 466         int i, j = 0;
 467
 468         while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
 469                 udelay (1);             /* will also trigger Wd if needed */
 470                 j++;
 471         }
 472         if (j >= TOUT_LOOP)
 473                 printf ("TX not ready\n");
 474         rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
 475         rtx->txbd[txIdx].cbd_datlen = length;
 476         rtx->txbd[txIdx].cbd_sc |=
 477                         (BD_ENET_TX_READY | BD_ENET_TX_LAST | BD_ENET_TX_WRAP);
 478         while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
 479                 udelay (1);             /* will also trigger Wd if needed */
 480                 j++;
 481         }
 482         if (j >= TOUT_LOOP)
 483                 printf ("TX timeout\n");
 484         i = (rtx->txbd[txIdx].
 485                  cbd_sc & BD_ENET_TX_STATS) /* return only status bits */ ;
 486         return i;
 487 }
 488
 489 static int scc_recv (int index, void *packet, int max_length)
 490 {
 491         int length = -1;
 492
 493         if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
 494                 goto Done;              /* nothing received */
 495         }
 496
 497         if (!(rtx->rxbd[rxIdx].cbd_sc & 0x003f)) {
 498                 length = rtx->rxbd[rxIdx].cbd_datlen - 4;
 499                 memcpy (packet,
 500                                 (void *) (NetRxPackets[rxIdx]),
 501                                 length < max_length ? length : max_length);
 502         }
 503
 504         /* Give the buffer back to the SCC. */
 505         rtx->rxbd[rxIdx].cbd_datlen = 0;
 506
 507         /* wrap around buffer index when necessary */
 508         if ((rxIdx + 1) >= PKTBUFSRX) {
 509                 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
 510                                 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
 511                 rxIdx = 0;
 512         } else {
 513                 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
 514                 rxIdx++;
 515         }
 516
 517 Done:
 518         return length;
 519 }
 520
 521   /*
 522    * Test routines
 523    */
 524
 525 static void packet_fill (char *packet, int length)
 526 {
 527         char c = (char) length;
 528         int i;
 529
 530         packet[0] = 0xFF;
 531         packet[1] = 0xFF;
 532         packet[2] = 0xFF;
 533         packet[3] = 0xFF;
 534         packet[4] = 0xFF;
 535         packet[5] = 0xFF;
 536
 537         for (i = 6; i < length; i++) {
 538                 packet[i] = c++;
 539         }
 540 }
 541
 542 static int packet_check (char *packet, int length)
 543 {
 544         char c = (char) length;
 545         int i;
 546
 547         for (i = 6; i < length; i++) {
 548                 if (packet[i] != c++)
 549                         return -1;
 550         }
 551
 552         return 0;
 553 }
 554
 555 static int test_ctlr (int ctlr, int index)
 556 {
 557         int res = -1;
 558         char packet_send[MAX_PACKET_LENGTH];
 559         char packet_recv[MAX_PACKET_LENGTH];
 560         int length;
 561         int i;
 562         int l;
 563
 564         ctlr_proc[ctlr].init (index);
 565
 566         for (i = 0; i < TEST_NUM; i++) {
 567                 for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
 568                         packet_fill (packet_send, l);
 569
 570                         ctlr_proc[ctlr].send (index, packet_send, l);
 571
 572                         length = ctlr_proc[ctlr].recv (index, packet_recv,
 573                                                         MAX_PACKET_LENGTH);
 574
 575                         if (length != l || packet_check (packet_recv, length) < 0) {
 576                                 goto Done;
 577                         }
 578                 }
 579         }
 580
 581         res = 0;
 582
 583 Done:
 584
 585         ctlr_proc[ctlr].halt (index);
 586
 587         /*
 588          * SCC2 Ethernet parameter RAM space overlaps
 589          * the SPI parameter RAM space. So we need to restore
 590          * the SPI configuration after SCC2 ethernet test.
 591          */
 592 #if defined(CONFIG_SPI)
 593         if (ctlr == CTLR_SCC && index == 1) {
 594                 spi_init_f ();
 595                 spi_init_r ();
 596         }
 597 #endif
 598
 599         if (res != 0) {
 600                 post_log ("ethernet %s%d test failed\n", ctlr_name[ctlr],
 601                                   index + 1);
 602         }
 603
 604         return res;
 605 }
 606
 607 int ether_post_test (int flags)
 608 {
 609         int res = 0;
 610         int i;
 611
 612         ctlr_proc[CTLR_SCC].init = scc_init;
 613         ctlr_proc[CTLR_SCC].halt = scc_halt;
 614         ctlr_proc[CTLR_SCC].send = scc_send;
 615         ctlr_proc[CTLR_SCC].recv = scc_recv;
 616
 617         for (i = 0; i < CTRL_LIST_SIZE; i++) {
 618                 if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
 619                         res = -1;
 620                 }
 621         }
 622
 623 #if !defined(CONFIG_8xx_CONS_NONE)
 624         serial_reinit_all ();
 625 #endif
 626         return res;
 627 }
 628
 629 #endif /* CONFIG_POST & CFG_POST_ETHER */
 630
 631 #endif /* CONFIG_POST */