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git.ipfire.org Git - people/ms/u-boot.git/blob - post/lib_powerpc/rlwinm.c
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
12 * Shift instructions: rlwinm
14 * The test contains a pre-built table of instructions, operands and
15 * expected results. For each table entry, the test will cyclically use
16 * different sets of operand registers and result registers.
22 #if CONFIG_POST & CONFIG_SYS_POST_CPU
24 extern void cpu_post_exec_21 (ulong
*code
, ulong
*cr
, ulong
*res
, ulong op1
);
25 extern ulong
cpu_post_makecr (long v
);
27 static struct cpu_post_rlwinm_s
35 } cpu_post_rlwinm_table
[] =
46 static unsigned int cpu_post_rlwinm_size
= ARRAY_SIZE(cpu_post_rlwinm_table
);
48 int cpu_post_test_rlwinm (void)
52 int flag
= disable_interrupts();
54 for (i
= 0; i
< cpu_post_rlwinm_size
&& ret
== 0; i
++)
56 struct cpu_post_rlwinm_s
*test
= cpu_post_rlwinm_table
+ i
;
58 for (reg
= 0; reg
< 32 && ret
== 0; reg
++)
60 unsigned int reg0
= (reg
+ 0) % 32;
61 unsigned int reg1
= (reg
+ 1) % 32;
62 unsigned int stk
= reg
< 16 ? 31 : 15;
63 unsigned long code
[] =
66 ASM_ADDI(stk
, 1, -16),
68 ASM_STW(reg0
, stk
, 4),
69 ASM_STW(reg1
, stk
, 0),
70 ASM_LWZ(reg0
, stk
, 8),
71 ASM_113(test
->cmd
, reg1
, reg0
, test
->op2
, test
->mb
, test
->me
),
72 ASM_STW(reg1
, stk
, 8),
73 ASM_LWZ(reg1
, stk
, 0),
74 ASM_LWZ(reg0
, stk
, 4),
80 unsigned long codecr
[] =
83 ASM_ADDI(stk
, 1, -16),
85 ASM_STW(reg0
, stk
, 4),
86 ASM_STW(reg1
, stk
, 0),
87 ASM_LWZ(reg0
, stk
, 8),
88 ASM_113(test
->cmd
, reg1
, reg0
, test
->op2
, test
->mb
,
90 ASM_STW(reg1
, stk
, 8),
91 ASM_LWZ(reg1
, stk
, 0),
92 ASM_LWZ(reg0
, stk
, 4),
104 cpu_post_exec_21 (code
, & cr
, & res
, test
->op1
);
106 ret
= res
== test
->res
&& cr
== 0 ? 0 : -1;
110 post_log ("Error at rlwinm test %d !\n", i
);
116 cpu_post_exec_21 (codecr
, & cr
, & res
, test
->op1
);
118 ret
= res
== test
->res
&&
119 (cr
& 0xe0000000) == cpu_post_makecr (res
) ? 0 : -1;
123 post_log ("Error at rlwinm test %d !\n", i
);