post/lib_ppc/b.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25
  26 /*
  27  * CPU test
  28  * Branch instructions:         b, bl, bc
  29  *
  30  * The first 2 instructions (b, bl) are verified by jumping
  31  * to a fixed address and checking whether control was transfered
  32  * to that very point. For the bl instruction the value of the
  33  * link register is checked as well (using mfspr).
  34  * To verify the bc instruction various combinations of the BI/BO
  35  * fields, the CTR and the condition register values are
  36  * checked. The list of such combinations is pre-built and
  37  * linked in U-Boot at build time.
  38  */
  39
  40 #ifdef CONFIG_POST
  41
  42 #include <post.h>
  43 #include "cpu_asm.h"
  44
  45 #if CONFIG_POST & CFG_POST_CPU
  46
  47 extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1);
  48 extern void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump,
  49     ulong cr);
  50
  51 static int cpu_post_test_bc (ulong cmd, ulong bo, ulong bi,
  52     int pjump, int dec, int link, ulong pctr, ulong cr)
  53 {
  54     int ret = 0;
  55     ulong lr = 0;
  56     ulong ctr = pctr;
  57     ulong jump;
  58
  59     unsigned long code[] =
  60     {
  61         ASM_MTCR(6),
  62         ASM_MFLR(6),
  63         ASM_MTCTR(3),
  64         ASM_MTLR(4),
  65         ASM_LI(5, 1),
  66         ASM_3O(cmd, bo, bi, 8),
  67         ASM_LI(5, 0),
  68         ASM_MFCTR(3),
  69         ASM_MFLR(4),
  70         ASM_MTLR(6),
  71         ASM_BLR,
  72     };
  73
  74     cpu_post_exec_31 (code, &ctr, &lr, &jump, cr);
  75
  76     if (ret == 0)
  77         ret = pjump == jump ? 0 : -1;
  78     if (ret == 0)
  79     {
  80         if (dec)
  81             ret = pctr == ctr + 1 ? 0 : -1;
  82         else
  83             ret = pctr == ctr ? 0 : -1;
  84     }
  85     if (ret == 0)
  86     {
  87         if (link)
  88             ret = lr == (ulong) code + 24 ? 0 : -1;
  89         else
  90             ret = lr == 0 ? 0 : -1;
  91     }
  92
  93     return ret;
  94 }
  95
  96 int cpu_post_test_b (void)
  97 {
  98     int ret = 0;
  99     unsigned int i;
 100
 101     if (ret == 0)
 102     {
 103         ulong code[] =
 104         {
 105            ASM_MFLR(4),
 106            ASM_MTLR(3),
 107            ASM_B(4),
 108            ASM_MFLR(3),
 109            ASM_MTLR(4),
 110            ASM_BLR,
 111         };
 112         ulong res;
 113
 114         cpu_post_exec_11 (code, &res, 0);
 115
 116         ret = res == 0 ? 0 : -1;
 117
 118         if (ret != 0)
 119         {
 120             post_log ("Error at b1 test !\n");
 121         }
 122     }
 123
 124     if (ret == 0)
 125     {
 126         ulong code[] =
 127         {
 128            ASM_MFLR(4),
 129            ASM_MTLR(3),
 130            ASM_BL(4),
 131            ASM_MFLR(3),
 132            ASM_MTLR(4),
 133            ASM_BLR,
 134         };
 135         ulong res;
 136
 137         cpu_post_exec_11 (code, &res, 0);
 138
 139         ret = res == (ulong)code + 12 ? 0 : -1;
 140
 141         if (ret != 0)
 142         {
 143             post_log ("Error at b2 test !\n");
 144         }
 145     }
 146
 147     if (ret == 0)
 148     {
 149         ulong cc, cd;
 150         int cond;
 151         ulong ctr;
 152         int link;
 153
 154         i = 0;
 155
 156         for (cc = 0; cc < 4 && ret == 0; cc++)
 157         {
 158             for (cd = 0; cd < 4 && ret == 0; cd++)
 159             {
 160                 for (link = 0; link <= 1 && ret == 0; link++)
 161                 {
 162                     for (cond = 0; cond <= 1 && ret == 0; cond++)
 163                     {
 164                         for (ctr = 1; ctr <= 2 && ret == 0; ctr++)
 165                         {
 166                             int dec = cd < 2;
 167                             int cr = cond ? 0x80000000 : 0x00000000;
 168                             int jumpc = cc >= 2 ||
 169                                         (cc == 0 && !cond) ||
 170                                         (cc == 1 && cond);
 171                             int jumpd = cd >= 2 ||
 172                                         (cd == 0 && ctr != 1) ||
 173                                         (cd == 1 && ctr == 1);
 174                             int jump = jumpc && jumpd;
 175
 176                             ret = cpu_post_test_bc (link ? OP_BCL : OP_BC,
 177                                 (cc << 3) + (cd << 1), 0, jump, dec, link,
 178                                 ctr, cr);
 179
 180                             if (ret != 0)
 181                             {
 182                                 post_log ("Error at b3 test %d !\n", i);
 183                             }
 184
 185                             i++;
 186                         }
 187                     }
 188                 }
 189             }
 190         }
 191     }
 192
 193     return ret;
 194 }
 195
 196 #endif
 197 #endif