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1 /*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25
26 /*
27 * CPU test
28 * Shift instructions: rlwinm
29 *
30 * The test contains a pre-built table of instructions, operands and
31 * expected results. For each table entry, the test will cyclically use
32 * different sets of operand registers and result registers.
33 */
34
35 #include <post.h>
36 #include "cpu_asm.h"
37
38 #if CONFIG_POST & CONFIG_SYS_POST_CPU
39
40 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
41 extern ulong cpu_post_makecr (long v);
42
43 static struct cpu_post_rlwinm_s
44 {
45 ulong cmd;
46 ulong op1;
47 uchar op2;
48 uchar mb;
49 uchar me;
50 ulong res;
51 } cpu_post_rlwinm_table[] =
52 {
53 {
54 OP_RLWINM,
55 0xffff0000,
56 24,
57 16,
58 23,
59 0x0000ff00
60 },
61 };
62 static unsigned int cpu_post_rlwinm_size =
63 sizeof (cpu_post_rlwinm_table) / sizeof (struct cpu_post_rlwinm_s);
64
65 int cpu_post_test_rlwinm (void)
66 {
67 int ret = 0;
68 unsigned int i, reg;
69 int flag = disable_interrupts();
70
71 for (i = 0; i < cpu_post_rlwinm_size && ret == 0; i++)
72 {
73 struct cpu_post_rlwinm_s *test = cpu_post_rlwinm_table + i;
74
75 for (reg = 0; reg < 32 && ret == 0; reg++)
76 {
77 unsigned int reg0 = (reg + 0) % 32;
78 unsigned int reg1 = (reg + 1) % 32;
79 unsigned int stk = reg < 16 ? 31 : 15;
80 unsigned long code[] =
81 {
82 ASM_STW(stk, 1, -4),
83 ASM_ADDI(stk, 1, -16),
84 ASM_STW(3, stk, 8),
85 ASM_STW(reg0, stk, 4),
86 ASM_STW(reg1, stk, 0),
87 ASM_LWZ(reg0, stk, 8),
88 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me),
89 ASM_STW(reg1, stk, 8),
90 ASM_LWZ(reg1, stk, 0),
91 ASM_LWZ(reg0, stk, 4),
92 ASM_LWZ(3, stk, 8),
93 ASM_ADDI(1, stk, 16),
94 ASM_LWZ(stk, 1, -4),
95 ASM_BLR,
96 };
97 unsigned long codecr[] =
98 {
99 ASM_STW(stk, 1, -4),
100 ASM_ADDI(stk, 1, -16),
101 ASM_STW(3, stk, 8),
102 ASM_STW(reg0, stk, 4),
103 ASM_STW(reg1, stk, 0),
104 ASM_LWZ(reg0, stk, 8),
105 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb,
106 test->me) | BIT_C,
107 ASM_STW(reg1, stk, 8),
108 ASM_LWZ(reg1, stk, 0),
109 ASM_LWZ(reg0, stk, 4),
110 ASM_LWZ(3, stk, 8),
111 ASM_ADDI(1, stk, 16),
112 ASM_LWZ(stk, 1, -4),
113 ASM_BLR,
114 };
115 ulong res;
116 ulong cr;
117
118 if (ret == 0)
119 {
120 cr = 0;
121 cpu_post_exec_21 (code, & cr, & res, test->op1);
122
123 ret = res == test->res && cr == 0 ? 0 : -1;
124
125 if (ret != 0)
126 {
127 post_log ("Error at rlwinm test %d !\n", i);
128 }
129 }
130
131 if (ret == 0)
132 {
133 cpu_post_exec_21 (codecr, & cr, & res, test->op1);
134
135 ret = res == test->res &&
136 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
137
138 if (ret != 0)
139 {
140 post_log ("Error at rlwinm test %d !\n", i);
141 }
142 }
143 }
144 }
145
146 if (flag)
147 enable_interrupts();
148
149 return ret;
150 }
151
152 #endif