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git.ipfire.org Git - people/ms/u-boot.git/blob - post/lib_ppc/threex.c
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * Ternary instructions instr rA,rS,rB
30 * Logic instructions: or, orc, xor, nand, nor, eqv
31 * Shift instructions: slw, srw, sraw
33 * The test contains a pre-built table of instructions, operands and
34 * expected results. For each table entry, the test will cyclically use
35 * different sets of operand registers and result registers.
41 #if CONFIG_POST & CONFIG_SYS_POST_CPU
43 extern void cpu_post_exec_22 (ulong
*code
, ulong
*cr
, ulong
*res
, ulong op1
,
45 extern ulong
cpu_post_makecr (long v
);
47 static struct cpu_post_threex_s
53 } cpu_post_threex_table
[] =
128 static unsigned int cpu_post_threex_size
=
129 sizeof (cpu_post_threex_table
) / sizeof (struct cpu_post_threex_s
);
131 int cpu_post_test_threex (void)
135 int flag
= disable_interrupts();
137 for (i
= 0; i
< cpu_post_threex_size
&& ret
== 0; i
++)
139 struct cpu_post_threex_s
*test
= cpu_post_threex_table
+ i
;
141 for (reg
= 0; reg
< 32 && ret
== 0; reg
++)
143 unsigned int reg0
= (reg
+ 0) % 32;
144 unsigned int reg1
= (reg
+ 1) % 32;
145 unsigned int reg2
= (reg
+ 2) % 32;
146 unsigned int stk
= reg
< 16 ? 31 : 15;
147 unsigned long code
[] =
150 ASM_ADDI(stk
, 1, -24),
153 ASM_STW(reg0
, stk
, 8),
154 ASM_STW(reg1
, stk
, 4),
155 ASM_STW(reg2
, stk
, 0),
156 ASM_LWZ(reg1
, stk
, 12),
157 ASM_LWZ(reg0
, stk
, 16),
158 ASM_12X(test
->cmd
, reg2
, reg1
, reg0
),
159 ASM_STW(reg2
, stk
, 12),
160 ASM_LWZ(reg2
, stk
, 0),
161 ASM_LWZ(reg1
, stk
, 4),
162 ASM_LWZ(reg0
, stk
, 8),
164 ASM_ADDI(1, stk
, 24),
168 unsigned long codecr
[] =
171 ASM_ADDI(stk
, 1, -24),
174 ASM_STW(reg0
, stk
, 8),
175 ASM_STW(reg1
, stk
, 4),
176 ASM_STW(reg2
, stk
, 0),
177 ASM_LWZ(reg1
, stk
, 12),
178 ASM_LWZ(reg0
, stk
, 16),
179 ASM_12X(test
->cmd
, reg2
, reg1
, reg0
) | BIT_C
,
180 ASM_STW(reg2
, stk
, 12),
181 ASM_LWZ(reg2
, stk
, 0),
182 ASM_LWZ(reg1
, stk
, 4),
183 ASM_LWZ(reg0
, stk
, 8),
185 ASM_ADDI(1, stk
, 24),
195 cpu_post_exec_22 (code
, & cr
, & res
, test
->op1
, test
->op2
);
197 ret
= res
== test
->res
&& cr
== 0 ? 0 : -1;
201 post_log ("Error at threex test %d !\n", i
);
207 cpu_post_exec_22 (codecr
, & cr
, & res
, test
->op1
, test
->op2
);
209 ret
= res
== test
->res
&&
210 (cr
& 0xe0000000) == cpu_post_makecr (res
) ? 0 : -1;
214 post_log ("Error at threex test %d !\n", i
);