sim/aarch64/ChangeLog

   1 2021-05-17  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
   4
   5 2021-05-17  Mike Frysinger  <vapier@gentoo.org>
   6
   7         * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
   8         (struct sim_state): Delete.
   9
  10 2021-05-16  Mike Frysinger  <vapier@gentoo.org>
  11
  12         * cpustate.c: Include defs.h.
  13         * interp.c: Replace config.h include with defs.h.
  14         * memory.c, simulator.c: Likewise.
  15         * cpustate.h, simulator.h: Delete config.h include.
  16
  17 2021-05-16  Mike Frysinger  <vapier@gentoo.org>
  18
  19         * config.in, configure: Regenerate.
  20
  21 2021-05-14  Mike Frysinger  <vapier@gentoo.org>
  22
  23         * cpustate.h: Update include path.
  24         * interp.c: Likewise.
  25
  26 2021-05-04  Mike Frysinger  <vapier@gentoo.org>
  27
  28         * configure: Regenerate.
  29
  30 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  31
  32         * config.in, configure: Regenerate.
  33
  34 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  35
  36         * cpustate.c (aarch64_set_FP_float): Change lx to PRIx64.
  37         (aarch64_set_FP_double, aarch64_set_FP_long_double,
  38         aarch64_set_vec_u64, aarch64_set_vec_s64): Likewise.
  39
  40 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  41
  42         * simulator.c (do_fcvtzu): Change UL to ULL.
  43
  44 2021-04-26  Mike Frysinger  <vapier@gentoo.org>
  45
  46         * aclocal.m4, config.in, configure: Regenerate.
  47
  48 2021-04-22  Tom Tromey  <tom@tromey.com>
  49
  50         * configure, config.in: Rebuild.
  51
  52 2021-04-22  Tom Tromey  <tom@tromey.com>
  53
  54         * configure: Rebuild.
  55
  56 2021-04-21  Mike Frysinger  <vapier@gentoo.org>
  57
  58         * aclocal.m4: Regenerate.
  59
  60 2021-04-21  Simon Marchi  <simon.marchi@polymtl.ca>
  61
  62         * configure: Regenerate.
  63
  64 2021-04-18  Mike Frysinger  <vapier@gentoo.org>
  65
  66         * configure: Regenerate.
  67
  68 2021-04-12  Mike Frysinger  <vapier@gentoo.org>
  69
  70         * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
  71
  72 2021-04-07  Jim Wilson  <jimw@sifive.com>
  73
  74         PR sim/27483
  75         * simulator.c (set_flags_for_add32): Compare uresult against
  76         itself.  Compare sresult against itself.
  77
  78 2021-04-02  Mike Frysinger  <vapier@gentoo.org>
  79
  80         * aclocal.m4, configure: Regenerate.
  81
  82 2021-02-28  Mike Frysinger  <vapier@gentoo.org>
  83
  84         * configure: Regenerate.
  85
  86 2021-02-21  Mike Frysinger  <vapier@gentoo.org>
  87
  88         * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
  89         * aclocal.m4, configure: Regenerate.
  90
  91 2021-02-13  Mike Frysinger  <vapier@gentoo.org>
  92
  93         * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
  94         * aclocal.m4, configure: Regenerate.
  95
  96 2021-02-06  Mike Frysinger  <vapier@gentoo.org>
  97
  98         * configure: Regenerate.
  99
 100 2021-01-11  Mike Frysinger  <vapier@gentoo.org>
 101
 102         * config.in, configure: Regenerate.
 103
 104 2021-01-09  Mike Frysinger  <vapier@gentoo.org>
 105
 106         * configure: Regenerate.
 107
 108 2021-01-08  Mike Frysinger  <vapier@gentoo.org>
 109
 110         * configure: Regenerate.
 111
 112 2021-01-04  Mike Frysinger  <vapier@gentoo.org>
 113
 114         * configure: Regenerate.
 115
 116 2020-02-06  Carlo Bramini  <carlo_bramini@users.sourceforge.net>
 117
 118         PR sim/25318
 119         * simulator.c (blr): Read destination register before calling
 120         aarch64_save_LR.
 121
 122 2019-03-28  Andrew Burgess  <andrew.burgess@embecosm.com>
 123
 124         * cpustate.c: Add 'libiberty.h' include.
 125         * interp.c: Add 'sim-assert.h' include.
 126
 127 2017-09-06  John Baldwin  <jhb@FreeBSD.org>
 128
 129         * configure: Regenerate.
 130
 131 2017-04-22  Jim Wilson  <jim.wilson@linaro.org>
 132
 133         * simulator.c (vec_load): Add M argument.  Rewrite to iterate over
 134         registers based on structure size.
 135         (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
 136         (LD1_1): Replace with call to vec_load.
 137         (vec_store): Add new M argument.  Rewrite to iterate over registers
 138         based on structure size.
 139         (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
 140         (ST1_1): Replace with call to vec_store.
 141
 142 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
 143
 144         * simulator.c (do_vec_FCVTL): New.
 145         (do_vec_op1): Call do_vec_FCVTL.
 146
 147         * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
 148         do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
 149         (do_scalar_vec): Add calls to new functions.
 150
 151 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
 152
 153         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
 154         flag check.
 155
 156 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
 157
 158         * simulator.c (mul64hi): Shift carry left by 32.
 159         (smulh): Change signum to negate.  If negate, invert result, and add
 160         carry bit if low part of multiply result is zero.
 161
 162 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
 163
 164         * simulator.c (do_vec_SMOV_into_scalar): New.
 165         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
 166         Rewritten.
 167         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
 168         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
 169         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
 170         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
 171
 172         * simulator.c (popcount): New.
 173         (do_vec_CNT): New.
 174         (do_vec_op1): Add do_vec_CNT call.
 175
 176 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
 177
 178         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
 179         with type set to input type size.
 180         (do_vec_xtl): Change bias from 3 to 4 for byte case.
 181
 182 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
 183
 184         * simulator.c (do_vec_MLA): Rewrite switch body.
 185
 186         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
 187         2.  Move test_false if inside loop.  Fix logic for computing result
 188         stored to vd.
 189
 190         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
 191         (do_vec_LDn_single, do_vec_STn_single): New.
 192         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
 193         loop over nregs using new var n.  Add n times size to address in loop.
 194         Add n to vd in loop.
 195         (do_vec_load_store): Add comment for instruction bit 24.  New var
 196         single to hold instruction bit 24.  Add new code to use single.  Move
 197         ldnr support inside single if statements.  Fix ldnr register counts
 198         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
 199
 200 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
 201
 202         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
 203
 204 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
 205
 206         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
 207         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
 208         case 3, call HALT_UNALLOC unconditionally.
 209         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
 210         i + 2.  Delete if on bias, change index to i + bias * X.
 211
 212 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
 213
 214         * simulator.c (do_vec_UZP): Rewrite.
 215
 216 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
 217
 218         * cpustate.c: Include math.h.
 219         (aarch64_set_FP_float): Use signbit to check for signed zero.
 220         (aarch64_set_FP_double): Likewise.
 221         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
 222         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
 223         args same size as third arg.
 224         (fmaxnm): Use isnan instead of fpclassify.
 225         (fminnm, dmaxnm, dminnm): Likewise.
 226         (do_vec_MLS): Reverse order of subtraction operands.
 227         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
 228         aarch64_get_FP_float to get source register contents.
 229         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
 230         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
 231         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
 232         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
 233         raise_exception calls.
 234
 235 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
 236
 237         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
 238         Add comment to document NaN issue.
 239         (set_flags_for_double_compare): Likewise.
 240
 241 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
 242
 243         * simulator.c (NEG, POS): Move before set_flags_for_add64.
 244         (set_flags_for_add64): Replace with a modified copy of
 245         set_flags_for_sub64.
 246
 247 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
 248
 249         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 250         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 251
 252 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 253
 254         * simulator.c (fsturs): Switch use of rn and st variables.
 255         (fsturd, fsturq): Likewise
 256
 257 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 258
 259         * interp.c: Include bfd.h.
 260         (symcount, symtab, aarch64_get_sym_value): Delete.
 261         (remove_useless_symbols): Change count type to long.
 262         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 263         and symtab local variables.
 264         (sim_create_inferior): Delete storage.  Replace symbol code
 265         with a call to trace_load_symbols.
 266         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 267         includes.
 268         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 269         trace_sym_value.
 270         * memory.h: Delete bfd.h include.
 271         (mem_add_blk): Delete unused prototype.
 272         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 273         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 274         (aarch64_get_sym_value): Delete.
 275
 276 2016-08-12  Nick Clifton  <nickc@redhat.com>
 277
 278         * simulator.c (aarch64_step): Revert pervious delta.
 279         (aarch64_run): Call sim_events_tick after each
 280         instruction is simulated, and if necessary call
 281         sim_events_process.
 282         * simulator.h: Revert previous delta.
 283
 284 2016-08-11  Nick Clifton  <nickc@redhat.com>
 285
 286         * interp.c (sim_create_inferior): Allow for being called with a
 287         NULL abfd parameter.  If a bfd is provided, initialise the sim
 288         with that start address.
 289         * simulator.c (HALT_NYI): Just print out the numeric value of the
 290         instruction when not tracing.
 291         (aarch64_step): Change from static to global.
 292         * simulator.h: Add a prototype for aarch64_step().
 293
 294 2016-07-27  Alan Modra  <amodra@gmail.com>
 295
 296         * memory.c: Don't include libbfd.h.
 297
 298 2016-07-21  Nick Clifton  <nickc@redhat.com>
 299
 300         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 301
 302 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 303
 304         * cpustate.h: Include config.h.
 305         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 306         use anonymous structs to align members.
 307         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 308         endian_le2h_4 to read instruction from pc.
 309
 310 2016-05-06  Nick Clifton  <nickc@redhat.com>
 311
 312         * simulator.c (do_FMLA_by_element): New function.
 313         (do_vec_op2): Call it.
 314
 315 2016-04-27  Nick Clifton  <nickc@redhat.com>
 316
 317         * simulator.c: Add TRACE_DECODE statements to all emulation
 318         functions.
 319
 320 2016-03-30  Nick Clifton  <nickc@redhat.com>
 321
 322         * cpustate.c (aarch64_set_reg_s32): New function.
 323         (aarch64_set_reg_u32): New function.
 324         (aarch64_get_FP_half): Place half precision value into the correct
 325         slot of the union.
 326         (aarch64_set_FP_half): Likewise.
 327         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 328         aarch64_set_reg_u32.
 329         * memory.c (FETCH_FUNC): Cast the read value to the access type
 330         before converting it to the return type.  Rename to FETCH_FUNC64.
 331         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 332         accesses.  Use for 32-bit memory access functions.
 333         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 334         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 335         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 336         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 337         (ldrh32_abs): Store 32 bit value not 64-bits.
 338         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 339         (do_vec_MOV_immediate): Fix computation of val.
 340         (do_vec_MVNI): Likewise.
 341         (DO_VEC_WIDENING_MUL): New macro.
 342         (do_vec_mull): Use new macro.
 343         (do_vec_mul): Use new macro.
 344         (do_vec_MLA): Read values before writing.
 345         (do_vec_xtl): Likewise.
 346         (do_vec_SSHL): Select correct shift value.
 347         (do_vec_USHL): Likewise.
 348         (do_scalar_UCVTF): New function.
 349         (do_scalar_vec): Call new function.
 350         (store_pair_u64): Treat reads of SP as reads of XZR.
 351
 352 2016-03-29  Nick Clifton  <nickc@redhat.com>
 353
 354         * cpustate.c: Remove space after asterisk in function parameters.
 355         * decode.h (greg): Delete unused function.
 356         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 357         * simulator.c: Use INSTR macro in more places.
 358         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 359         Remove extraneous whitespace.
 360
 361 2016-03-23  Nick Clifton  <nickc@redhat.com>
 362
 363         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 364         register as a half precision floating point number.
 365         (aarch64_set_FP_half): New function.  Similar, but for setting
 366         a half precision register.
 367         (aarch64_get_thread_id): New function.  Returns the value of the
 368         CPU's TPIDR register.
 369         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 370         floating point control register.
 371         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 372         register.
 373         * cpustate.h: Add prototypes for new functions.
 374         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 375         * memory.c: Use unaligned core access functions for all memory
 376         reads and writes.
 377         * simulator.c (HALT_NYI): Generate an error message if tracing
 378         will not tell the user why the simulator is halting.
 379         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 380         (INSTR): New time-saver macro.
 381         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 382         offset.
 383         (fldrh_abs): New function.  Likewise for 16-bit values.
 384         (do_vec_SSHL): Allow for negative shift values.
 385         (do_vec_USHL): Likewise.
 386         (do_vec_SHL): Correct computation of shift amount.
 387         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 388         shifts and computation of shift value.
 389         (clz): New function.  Counts leading zero bits.
 390         (do_vec_CLZ): New function.  Implements CLZ (vector).
 391         (do_vec_MOV_element): Call do_vec_CLZ.
 392         (dexSimpleFPCondCompare): Implement.
 393         (do_FCVT_half_to_single): New function.  Implements one of the
 394         FCVT operations.
 395         (do_FCVT_half_to_double): New function.  Likewise.
 396         (do_FCVT_single_to_half): New function.  Likewise.
 397         (do_FCVT_double_to_half): New function.  Likewise.
 398         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 399         (do_scalar_SHL): Handle negative shifts.
 400         (do_scalar_shift): Handle SSHR.
 401         (do_scalar_USHL): New function.
 402         (do_double_add): Simplify to just performing a double precision
 403         add operation.  Move remaining code into...
 404         (do_scalar_vec): ... New function.
 405         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 406         functions.
 407         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 408         registers.
 409         (system_set): New function.
 410         (do_MSR_immediate): New function.  Stub for now.
 411         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 412         instruction.
 413         (do_SYS): New function.  Stub for now,
 414         (dexSystem): Call new functions.
 415
 416 2016-03-18  Nick Clifton  <nickc@redhat.com>
 417
 418         * cpustate.c: Remove spurious spaces from TRACE strings.
 419         Print hex equivalents of floats and doubles.
 420         Check element number against array size when accessing vector
 421         registers.
 422         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 423         element index.
 424         (SET_VEC_ELEMENT): Likewise.
 425         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 426
 427         * memory.c: Trace memory reads when --trace-memory is enabled.
 428         Remove float and double load and store functions.
 429         * memory.h (aarch64_get_mem_float): Delete prototype.
 430         (aarch64_get_mem_double): Likewise.
 431         (aarch64_set_mem_float): Likewise.
 432         (aarch64_set_mem_double): Likewise.
 433         * simulator (IS_SET): Always return either 0 or 1.
 434         (IS_CLEAR): Likewise.
 435         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 436         and doubles using 64-bit memory accesses.
 437         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 438         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 439         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 440         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 441         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 442         (do_vec_MUL_by_element): New function.
 443         (do_vec_op2): Call do_vec_MUL_by_element.
 444         (do_scalar_NEG): New function.
 445         (do_double_add): Call do_scalar_NEG.
 446
 447 2016-03-03  Nick Clifton  <nickc@redhat.com>
 448
 449         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 450         (CondCompare): Swap interpretation of bit 30.
 451         (DO_ADDP): Delete macro.
 452         (do_vec_ADDP): Copy source registers before starting to update
 453         destination register.
 454         (do_vec_FADDP): Likewise.
 455         (do_vec_load_store): Fix computation of sizeof_operation.
 456         (rbit64): Fix type of constant.
 457         (aarch64_step): When displaying insn value, display all 32 bits.
 458
 459 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 460
 461         * config.in, configure: Regenerate.
 462
 463 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 464
 465         * configure: Regenerate.
 466
 467 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 468
 469         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 470         * configure: Regenerate.
 471
 472 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 473
 474         * configure: Regenerate.
 475
 476 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 477
 478         * configure: Regenerate.
 479
 480 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 481
 482         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 483         * configure: Regenerate.
 484
 485 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 486
 487         * configure: Regenerate.
 488
 489 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 490
 491         * configure: Regenerate.
 492
 493 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 494
 495         * config.in, configure: Regenerate.
 496
 497 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 498
 499         * interp.c (sim_create_inferior): Mark argv and env const.
 500         (sim_open): Mark argv const.
 501
 502 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 503
 504         * interp.c: Delete dis-asm.h include.
 505         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 506         (sim_create_inferior): Delete disassemble init logic.
 507         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 508         (sim_open): Delete sim_add_option_table call.
 509         * memory.c (mem_error): Delete disas check.
 510         * simulator.c: Delete dis-asm.h include.
 511         (disas): Delete.
 512         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 513         (HALT_NYI): Likewise.
 514         (handle_halt): Delete disas call.
 515         (aarch64_step): Replace disas logic with TRACE_DISASM.
 516         * simulator.h: Delete dis-asm.h include.
 517         (aarch64_print_insn): Delete.
 518
 519 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 520
 521         * simulator.c (MAX, MIN): Delete.
 522         (do_vec_maxv): Change MAX to max and MIN to min.
 523         (do_vec_fminmaxV): Likewise.
 524
 525 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 526
 527         * simulator.c: Remove syscall.h include.
 528
 529 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 530
 531         * configure: Regenerate.
 532
 533 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 534
 535         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 536         * configure: Regenerate.
 537
 538 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 539
 540         * configure: Regenerate.
 541
 542 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 543
 544         * interp.c (sim_dis_read): Change private_data to application_data.
 545         (sim_create_inferior): Likewise.
 546
 547 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 548
 549         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 550
 551 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 552
 553         * config.in, configure: Regenerate.
 554
 555 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 556
 557         * interp.c (sim_create_inferior): Update comment and argv check.
 558
 559 2015-12-14  Nick Clifton  <nickc@redhat.com>
 560
 561         * simulator.c (system_get): New function.  Provides read
 562         access to the dczid system register.
 563         (do_mrs): New function - implements the MRS instruction.
 564         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 565         unimplemented system instructions.
 566
 567 2015-11-24  Nick Clifton  <nickc@redhat.com>
 568
 569         * configure.ac: New configure template.
 570         * aclocal.m4: Generate.
 571         * config.in: Generate.
 572         * configure: Generate.
 573         * cpustate.c: New file - functions for accessing AArch64 registers.
 574         * cpustate.h: New header.
 575         * decode.h: New header.
 576         * interp.c: New file - interface between GDB and simulator.
 577         * Makefile.in: New makefile template.
 578         * memory.c: New file - functions for simulating aarch64 memory
 579         accesses.
 580         * memory.h: New header.
 581         * sim-main.h: New header.
 582         * simulator.c: New file - aarch64 simulator functions.
 583         * simulator.h: New header.