sim/aarch64/ChangeLog

   1 2021-01-04  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * configure: Regenerate.
   4
   5 2020-02-06  Carlo Bramini  <carlo_bramini@users.sourceforge.net>
   6
   7         PR sim/25318
   8         * simulator.c (blr): Read destination register before calling
   9         aarch64_save_LR.
  10
  11 2019-03-28  Andrew Burgess  <andrew.burgess@embecosm.com>
  12
  13         * cpustate.c: Add 'libiberty.h' include.
  14         * interp.c: Add 'sim-assert.h' include.
  15
  16 2017-09-06  John Baldwin  <jhb@FreeBSD.org>
  17
  18         * configure: Regenerate.
  19
  20 2017-04-22  Jim Wilson  <jim.wilson@linaro.org>
  21
  22         * simulator.c (vec_load): Add M argument.  Rewrite to iterate over
  23         registers based on structure size.
  24         (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
  25         (LD1_1): Replace with call to vec_load.
  26         (vec_store): Add new M argument.  Rewrite to iterate over registers
  27         based on structure size.
  28         (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
  29         (ST1_1): Replace with call to vec_store.
  30
  31 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
  32
  33         * simulator.c (do_vec_FCVTL): New.
  34         (do_vec_op1): Call do_vec_FCVTL.
  35
  36         * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
  37         do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
  38         (do_scalar_vec): Add calls to new functions.
  39
  40 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
  41
  42         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
  43         flag check.
  44
  45 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
  46
  47         * simulator.c (mul64hi): Shift carry left by 32.
  48         (smulh): Change signum to negate.  If negate, invert result, and add
  49         carry bit if low part of multiply result is zero.
  50
  51 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
  52
  53         * simulator.c (do_vec_SMOV_into_scalar): New.
  54         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
  55         Rewritten.
  56         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
  57         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
  58         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
  59         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
  60
  61         * simulator.c (popcount): New.
  62         (do_vec_CNT): New.
  63         (do_vec_op1): Add do_vec_CNT call.
  64
  65 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
  66
  67         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
  68         with type set to input type size.
  69         (do_vec_xtl): Change bias from 3 to 4 for byte case.
  70
  71 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
  72
  73         * simulator.c (do_vec_MLA): Rewrite switch body.
  74
  75         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
  76         2.  Move test_false if inside loop.  Fix logic for computing result
  77         stored to vd.
  78
  79         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
  80         (do_vec_LDn_single, do_vec_STn_single): New.
  81         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
  82         loop over nregs using new var n.  Add n times size to address in loop.
  83         Add n to vd in loop.
  84         (do_vec_load_store): Add comment for instruction bit 24.  New var
  85         single to hold instruction bit 24.  Add new code to use single.  Move
  86         ldnr support inside single if statements.  Fix ldnr register counts
  87         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
  88
  89 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
  90
  91         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
  92
  93 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
  94
  95         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
  96         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
  97         case 3, call HALT_UNALLOC unconditionally.
  98         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
  99         i + 2.  Delete if on bias, change index to i + bias * X.
 100
 101 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
 102
 103         * simulator.c (do_vec_UZP): Rewrite.
 104
 105 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
 106
 107         * cpustate.c: Include math.h.
 108         (aarch64_set_FP_float): Use signbit to check for signed zero.
 109         (aarch64_set_FP_double): Likewise.
 110         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
 111         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
 112         args same size as third arg.
 113         (fmaxnm): Use isnan instead of fpclassify.
 114         (fminnm, dmaxnm, dminnm): Likewise.
 115         (do_vec_MLS): Reverse order of subtraction operands.
 116         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
 117         aarch64_get_FP_float to get source register contents.
 118         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
 119         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
 120         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
 121         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
 122         raise_exception calls.
 123
 124 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
 125
 126         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
 127         Add comment to document NaN issue.
 128         (set_flags_for_double_compare): Likewise.
 129
 130 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
 131
 132         * simulator.c (NEG, POS): Move before set_flags_for_add64.
 133         (set_flags_for_add64): Replace with a modified copy of
 134         set_flags_for_sub64.
 135
 136 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
 137
 138         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 139         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 140
 141 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 142
 143         * simulator.c (fsturs): Switch use of rn and st variables.
 144         (fsturd, fsturq): Likewise
 145
 146 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 147
 148         * interp.c: Include bfd.h.
 149         (symcount, symtab, aarch64_get_sym_value): Delete.
 150         (remove_useless_symbols): Change count type to long.
 151         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 152         and symtab local variables.
 153         (sim_create_inferior): Delete storage.  Replace symbol code
 154         with a call to trace_load_symbols.
 155         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 156         includes.
 157         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 158         trace_sym_value.
 159         * memory.h: Delete bfd.h include.
 160         (mem_add_blk): Delete unused prototype.
 161         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 162         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 163         (aarch64_get_sym_value): Delete.
 164
 165 2016-08-12  Nick Clifton  <nickc@redhat.com>
 166
 167         * simulator.c (aarch64_step): Revert pervious delta.
 168         (aarch64_run): Call sim_events_tick after each
 169         instruction is simulated, and if necessary call
 170         sim_events_process.
 171         * simulator.h: Revert previous delta.
 172
 173 2016-08-11  Nick Clifton  <nickc@redhat.com>
 174
 175         * interp.c (sim_create_inferior): Allow for being called with a
 176         NULL abfd parameter.  If a bfd is provided, initialise the sim
 177         with that start address.
 178         * simulator.c (HALT_NYI): Just print out the numeric value of the
 179         instruction when not tracing.
 180         (aarch64_step): Change from static to global.
 181         * simulator.h: Add a prototype for aarch64_step().
 182
 183 2016-07-27  Alan Modra  <amodra@gmail.com>
 184
 185         * memory.c: Don't include libbfd.h.
 186
 187 2016-07-21  Nick Clifton  <nickc@redhat.com>
 188
 189         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 190
 191 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 192
 193         * cpustate.h: Include config.h.
 194         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 195         use anonymous structs to align members.
 196         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 197         endian_le2h_4 to read instruction from pc.
 198
 199 2016-05-06  Nick Clifton  <nickc@redhat.com>
 200
 201         * simulator.c (do_FMLA_by_element): New function.
 202         (do_vec_op2): Call it.
 203
 204 2016-04-27  Nick Clifton  <nickc@redhat.com>
 205
 206         * simulator.c: Add TRACE_DECODE statements to all emulation
 207         functions.
 208
 209 2016-03-30  Nick Clifton  <nickc@redhat.com>
 210
 211         * cpustate.c (aarch64_set_reg_s32): New function.
 212         (aarch64_set_reg_u32): New function.
 213         (aarch64_get_FP_half): Place half precision value into the correct
 214         slot of the union.
 215         (aarch64_set_FP_half): Likewise.
 216         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 217         aarch64_set_reg_u32.
 218         * memory.c (FETCH_FUNC): Cast the read value to the access type
 219         before converting it to the return type.  Rename to FETCH_FUNC64.
 220         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 221         accesses.  Use for 32-bit memory access functions.
 222         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 223         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 224         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 225         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 226         (ldrh32_abs): Store 32 bit value not 64-bits.
 227         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 228         (do_vec_MOV_immediate): Fix computation of val.
 229         (do_vec_MVNI): Likewise.
 230         (DO_VEC_WIDENING_MUL): New macro.
 231         (do_vec_mull): Use new macro.
 232         (do_vec_mul): Use new macro.
 233         (do_vec_MLA): Read values before writing.
 234         (do_vec_xtl): Likewise.
 235         (do_vec_SSHL): Select correct shift value.
 236         (do_vec_USHL): Likewise.
 237         (do_scalar_UCVTF): New function.
 238         (do_scalar_vec): Call new function.
 239         (store_pair_u64): Treat reads of SP as reads of XZR.
 240
 241 2016-03-29  Nick Clifton  <nickc@redhat.com>
 242
 243         * cpustate.c: Remove space after asterisk in function parameters.
 244         * decode.h (greg): Delete unused function.
 245         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 246         * simulator.c: Use INSTR macro in more places.
 247         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 248         Remove extraneous whitespace.
 249
 250 2016-03-23  Nick Clifton  <nickc@redhat.com>
 251
 252         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 253         register as a half precision floating point number.
 254         (aarch64_set_FP_half): New function.  Similar, but for setting
 255         a half precision register.
 256         (aarch64_get_thread_id): New function.  Returns the value of the
 257         CPU's TPIDR register.
 258         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 259         floating point control register.
 260         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 261         register.
 262         * cpustate.h: Add prototypes for new functions.
 263         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 264         * memory.c: Use unaligned core access functions for all memory
 265         reads and writes.
 266         * simulator.c (HALT_NYI): Generate an error message if tracing
 267         will not tell the user why the simulator is halting.
 268         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 269         (INSTR): New time-saver macro.
 270         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 271         offset.
 272         (fldrh_abs): New function.  Likewise for 16-bit values.
 273         (do_vec_SSHL): Allow for negative shift values.
 274         (do_vec_USHL): Likewise.
 275         (do_vec_SHL): Correct computation of shift amount.
 276         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 277         shifts and computation of shift value.
 278         (clz): New function.  Counts leading zero bits.
 279         (do_vec_CLZ): New function.  Implements CLZ (vector).
 280         (do_vec_MOV_element): Call do_vec_CLZ.
 281         (dexSimpleFPCondCompare): Implement.
 282         (do_FCVT_half_to_single): New function.  Implements one of the
 283         FCVT operations.
 284         (do_FCVT_half_to_double): New function.  Likewise.
 285         (do_FCVT_single_to_half): New function.  Likewise.
 286         (do_FCVT_double_to_half): New function.  Likewise.
 287         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 288         (do_scalar_SHL): Handle negative shifts.
 289         (do_scalar_shift): Handle SSHR.
 290         (do_scalar_USHL): New function.
 291         (do_double_add): Simplify to just performing a double precision
 292         add operation.  Move remaining code into...
 293         (do_scalar_vec): ... New function.
 294         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 295         functions.
 296         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 297         registers.
 298         (system_set): New function.
 299         (do_MSR_immediate): New function.  Stub for now.
 300         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 301         instruction.
 302         (do_SYS): New function.  Stub for now,
 303         (dexSystem): Call new functions.
 304
 305 2016-03-18  Nick Clifton  <nickc@redhat.com>
 306
 307         * cpustate.c: Remove spurious spaces from TRACE strings.
 308         Print hex equivalents of floats and doubles.
 309         Check element number against array size when accessing vector
 310         registers.
 311         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 312         element index.
 313         (SET_VEC_ELEMENT): Likewise.
 314         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 315
 316         * memory.c: Trace memory reads when --trace-memory is enabled.
 317         Remove float and double load and store functions.
 318         * memory.h (aarch64_get_mem_float): Delete prototype.
 319         (aarch64_get_mem_double): Likewise.
 320         (aarch64_set_mem_float): Likewise.
 321         (aarch64_set_mem_double): Likewise.
 322         * simulator (IS_SET): Always return either 0 or 1.
 323         (IS_CLEAR): Likewise.
 324         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 325         and doubles using 64-bit memory accesses.
 326         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 327         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 328         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 329         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 330         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 331         (do_vec_MUL_by_element): New function.
 332         (do_vec_op2): Call do_vec_MUL_by_element.
 333         (do_scalar_NEG): New function.
 334         (do_double_add): Call do_scalar_NEG.
 335
 336 2016-03-03  Nick Clifton  <nickc@redhat.com>
 337
 338         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 339         (CondCompare): Swap interpretation of bit 30.
 340         (DO_ADDP): Delete macro.
 341         (do_vec_ADDP): Copy source registers before starting to update
 342         destination register.
 343         (do_vec_FADDP): Likewise.
 344         (do_vec_load_store): Fix computation of sizeof_operation.
 345         (rbit64): Fix type of constant.
 346         (aarch64_step): When displaying insn value, display all 32 bits.
 347
 348 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 349
 350         * config.in, configure: Regenerate.
 351
 352 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 353
 354         * configure: Regenerate.
 355
 356 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 357
 358         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 359         * configure: Regenerate.
 360
 361 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 362
 363         * configure: Regenerate.
 364
 365 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 366
 367         * configure: Regenerate.
 368
 369 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 370
 371         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 372         * configure: Regenerate.
 373
 374 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 375
 376         * configure: Regenerate.
 377
 378 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 379
 380         * configure: Regenerate.
 381
 382 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 383
 384         * config.in, configure: Regenerate.
 385
 386 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 387
 388         * interp.c (sim_create_inferior): Mark argv and env const.
 389         (sim_open): Mark argv const.
 390
 391 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 392
 393         * interp.c: Delete dis-asm.h include.
 394         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 395         (sim_create_inferior): Delete disassemble init logic.
 396         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 397         (sim_open): Delete sim_add_option_table call.
 398         * memory.c (mem_error): Delete disas check.
 399         * simulator.c: Delete dis-asm.h include.
 400         (disas): Delete.
 401         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 402         (HALT_NYI): Likewise.
 403         (handle_halt): Delete disas call.
 404         (aarch64_step): Replace disas logic with TRACE_DISASM.
 405         * simulator.h: Delete dis-asm.h include.
 406         (aarch64_print_insn): Delete.
 407
 408 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 409
 410         * simulator.c (MAX, MIN): Delete.
 411         (do_vec_maxv): Change MAX to max and MIN to min.
 412         (do_vec_fminmaxV): Likewise.
 413
 414 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 415
 416         * simulator.c: Remove syscall.h include.
 417
 418 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 419
 420         * configure: Regenerate.
 421
 422 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 423
 424         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 425         * configure: Regenerate.
 426
 427 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 428
 429         * configure: Regenerate.
 430
 431 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 432
 433         * interp.c (sim_dis_read): Change private_data to application_data.
 434         (sim_create_inferior): Likewise.
 435
 436 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 437
 438         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 439
 440 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 441
 442         * config.in, configure: Regenerate.
 443
 444 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 445
 446         * interp.c (sim_create_inferior): Update comment and argv check.
 447
 448 2015-12-14  Nick Clifton  <nickc@redhat.com>
 449
 450         * simulator.c (system_get): New function.  Provides read
 451         access to the dczid system register.
 452         (do_mrs): New function - implements the MRS instruction.
 453         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 454         unimplemented system instructions.
 455
 456 2015-11-24  Nick Clifton  <nickc@redhat.com>
 457
 458         * configure.ac: New configure template.
 459         * aclocal.m4: Generate.
 460         * config.in: Generate.
 461         * configure: Generate.
 462         * cpustate.c: New file - functions for accessing AArch64 registers.
 463         * cpustate.h: New header.
 464         * decode.h: New header.
 465         * interp.c: New file - interface between GDB and simulator.
 466         * Makefile.in: New makefile template.
 467         * memory.c: New file - functions for simulating aarch64 memory
 468         accesses.
 469         * memory.h: New header.
 470         * sim-main.h: New header.
 471         * simulator.c: New file - aarch64 simulator functions.
 472         * simulator.h: New header.