sim/aarch64/ChangeLog

   1 2021-02-06  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * configure: Regenerate.
   4
   5 2021-01-11  Mike Frysinger  <vapier@gentoo.org>
   6
   7         * config.in, configure: Regenerate.
   8
   9 2021-01-09  Mike Frysinger  <vapier@gentoo.org>
  10
  11         * configure: Regenerate.
  12
  13 2021-01-08  Mike Frysinger  <vapier@gentoo.org>
  14
  15         * configure: Regenerate.
  16
  17 2021-01-04  Mike Frysinger  <vapier@gentoo.org>
  18
  19         * configure: Regenerate.
  20
  21 2020-02-06  Carlo Bramini  <carlo_bramini@users.sourceforge.net>
  22
  23         PR sim/25318
  24         * simulator.c (blr): Read destination register before calling
  25         aarch64_save_LR.
  26
  27 2019-03-28  Andrew Burgess  <andrew.burgess@embecosm.com>
  28
  29         * cpustate.c: Add 'libiberty.h' include.
  30         * interp.c: Add 'sim-assert.h' include.
  31
  32 2017-09-06  John Baldwin  <jhb@FreeBSD.org>
  33
  34         * configure: Regenerate.
  35
  36 2017-04-22  Jim Wilson  <jim.wilson@linaro.org>
  37
  38         * simulator.c (vec_load): Add M argument.  Rewrite to iterate over
  39         registers based on structure size.
  40         (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
  41         (LD1_1): Replace with call to vec_load.
  42         (vec_store): Add new M argument.  Rewrite to iterate over registers
  43         based on structure size.
  44         (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
  45         (ST1_1): Replace with call to vec_store.
  46
  47 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
  48
  49         * simulator.c (do_vec_FCVTL): New.
  50         (do_vec_op1): Call do_vec_FCVTL.
  51
  52         * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
  53         do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
  54         (do_scalar_vec): Add calls to new functions.
  55
  56 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
  57
  58         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
  59         flag check.
  60
  61 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
  62
  63         * simulator.c (mul64hi): Shift carry left by 32.
  64         (smulh): Change signum to negate.  If negate, invert result, and add
  65         carry bit if low part of multiply result is zero.
  66
  67 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
  68
  69         * simulator.c (do_vec_SMOV_into_scalar): New.
  70         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
  71         Rewritten.
  72         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
  73         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
  74         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
  75         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
  76
  77         * simulator.c (popcount): New.
  78         (do_vec_CNT): New.
  79         (do_vec_op1): Add do_vec_CNT call.
  80
  81 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
  82
  83         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
  84         with type set to input type size.
  85         (do_vec_xtl): Change bias from 3 to 4 for byte case.
  86
  87 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
  88
  89         * simulator.c (do_vec_MLA): Rewrite switch body.
  90
  91         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
  92         2.  Move test_false if inside loop.  Fix logic for computing result
  93         stored to vd.
  94
  95         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
  96         (do_vec_LDn_single, do_vec_STn_single): New.
  97         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
  98         loop over nregs using new var n.  Add n times size to address in loop.
  99         Add n to vd in loop.
 100         (do_vec_load_store): Add comment for instruction bit 24.  New var
 101         single to hold instruction bit 24.  Add new code to use single.  Move
 102         ldnr support inside single if statements.  Fix ldnr register counts
 103         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
 104
 105 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
 106
 107         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
 108
 109 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
 110
 111         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
 112         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
 113         case 3, call HALT_UNALLOC unconditionally.
 114         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
 115         i + 2.  Delete if on bias, change index to i + bias * X.
 116
 117 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
 118
 119         * simulator.c (do_vec_UZP): Rewrite.
 120
 121 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
 122
 123         * cpustate.c: Include math.h.
 124         (aarch64_set_FP_float): Use signbit to check for signed zero.
 125         (aarch64_set_FP_double): Likewise.
 126         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
 127         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
 128         args same size as third arg.
 129         (fmaxnm): Use isnan instead of fpclassify.
 130         (fminnm, dmaxnm, dminnm): Likewise.
 131         (do_vec_MLS): Reverse order of subtraction operands.
 132         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
 133         aarch64_get_FP_float to get source register contents.
 134         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
 135         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
 136         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
 137         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
 138         raise_exception calls.
 139
 140 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
 141
 142         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
 143         Add comment to document NaN issue.
 144         (set_flags_for_double_compare): Likewise.
 145
 146 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
 147
 148         * simulator.c (NEG, POS): Move before set_flags_for_add64.
 149         (set_flags_for_add64): Replace with a modified copy of
 150         set_flags_for_sub64.
 151
 152 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
 153
 154         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 155         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 156
 157 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 158
 159         * simulator.c (fsturs): Switch use of rn and st variables.
 160         (fsturd, fsturq): Likewise
 161
 162 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 163
 164         * interp.c: Include bfd.h.
 165         (symcount, symtab, aarch64_get_sym_value): Delete.
 166         (remove_useless_symbols): Change count type to long.
 167         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 168         and symtab local variables.
 169         (sim_create_inferior): Delete storage.  Replace symbol code
 170         with a call to trace_load_symbols.
 171         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 172         includes.
 173         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 174         trace_sym_value.
 175         * memory.h: Delete bfd.h include.
 176         (mem_add_blk): Delete unused prototype.
 177         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 178         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 179         (aarch64_get_sym_value): Delete.
 180
 181 2016-08-12  Nick Clifton  <nickc@redhat.com>
 182
 183         * simulator.c (aarch64_step): Revert pervious delta.
 184         (aarch64_run): Call sim_events_tick after each
 185         instruction is simulated, and if necessary call
 186         sim_events_process.
 187         * simulator.h: Revert previous delta.
 188
 189 2016-08-11  Nick Clifton  <nickc@redhat.com>
 190
 191         * interp.c (sim_create_inferior): Allow for being called with a
 192         NULL abfd parameter.  If a bfd is provided, initialise the sim
 193         with that start address.
 194         * simulator.c (HALT_NYI): Just print out the numeric value of the
 195         instruction when not tracing.
 196         (aarch64_step): Change from static to global.
 197         * simulator.h: Add a prototype for aarch64_step().
 198
 199 2016-07-27  Alan Modra  <amodra@gmail.com>
 200
 201         * memory.c: Don't include libbfd.h.
 202
 203 2016-07-21  Nick Clifton  <nickc@redhat.com>
 204
 205         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 206
 207 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 208
 209         * cpustate.h: Include config.h.
 210         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 211         use anonymous structs to align members.
 212         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 213         endian_le2h_4 to read instruction from pc.
 214
 215 2016-05-06  Nick Clifton  <nickc@redhat.com>
 216
 217         * simulator.c (do_FMLA_by_element): New function.
 218         (do_vec_op2): Call it.
 219
 220 2016-04-27  Nick Clifton  <nickc@redhat.com>
 221
 222         * simulator.c: Add TRACE_DECODE statements to all emulation
 223         functions.
 224
 225 2016-03-30  Nick Clifton  <nickc@redhat.com>
 226
 227         * cpustate.c (aarch64_set_reg_s32): New function.
 228         (aarch64_set_reg_u32): New function.
 229         (aarch64_get_FP_half): Place half precision value into the correct
 230         slot of the union.
 231         (aarch64_set_FP_half): Likewise.
 232         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 233         aarch64_set_reg_u32.
 234         * memory.c (FETCH_FUNC): Cast the read value to the access type
 235         before converting it to the return type.  Rename to FETCH_FUNC64.
 236         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 237         accesses.  Use for 32-bit memory access functions.
 238         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 239         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 240         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 241         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 242         (ldrh32_abs): Store 32 bit value not 64-bits.
 243         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 244         (do_vec_MOV_immediate): Fix computation of val.
 245         (do_vec_MVNI): Likewise.
 246         (DO_VEC_WIDENING_MUL): New macro.
 247         (do_vec_mull): Use new macro.
 248         (do_vec_mul): Use new macro.
 249         (do_vec_MLA): Read values before writing.
 250         (do_vec_xtl): Likewise.
 251         (do_vec_SSHL): Select correct shift value.
 252         (do_vec_USHL): Likewise.
 253         (do_scalar_UCVTF): New function.
 254         (do_scalar_vec): Call new function.
 255         (store_pair_u64): Treat reads of SP as reads of XZR.
 256
 257 2016-03-29  Nick Clifton  <nickc@redhat.com>
 258
 259         * cpustate.c: Remove space after asterisk in function parameters.
 260         * decode.h (greg): Delete unused function.
 261         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 262         * simulator.c: Use INSTR macro in more places.
 263         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 264         Remove extraneous whitespace.
 265
 266 2016-03-23  Nick Clifton  <nickc@redhat.com>
 267
 268         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 269         register as a half precision floating point number.
 270         (aarch64_set_FP_half): New function.  Similar, but for setting
 271         a half precision register.
 272         (aarch64_get_thread_id): New function.  Returns the value of the
 273         CPU's TPIDR register.
 274         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 275         floating point control register.
 276         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 277         register.
 278         * cpustate.h: Add prototypes for new functions.
 279         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 280         * memory.c: Use unaligned core access functions for all memory
 281         reads and writes.
 282         * simulator.c (HALT_NYI): Generate an error message if tracing
 283         will not tell the user why the simulator is halting.
 284         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 285         (INSTR): New time-saver macro.
 286         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 287         offset.
 288         (fldrh_abs): New function.  Likewise for 16-bit values.
 289         (do_vec_SSHL): Allow for negative shift values.
 290         (do_vec_USHL): Likewise.
 291         (do_vec_SHL): Correct computation of shift amount.
 292         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 293         shifts and computation of shift value.
 294         (clz): New function.  Counts leading zero bits.
 295         (do_vec_CLZ): New function.  Implements CLZ (vector).
 296         (do_vec_MOV_element): Call do_vec_CLZ.
 297         (dexSimpleFPCondCompare): Implement.
 298         (do_FCVT_half_to_single): New function.  Implements one of the
 299         FCVT operations.
 300         (do_FCVT_half_to_double): New function.  Likewise.
 301         (do_FCVT_single_to_half): New function.  Likewise.
 302         (do_FCVT_double_to_half): New function.  Likewise.
 303         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 304         (do_scalar_SHL): Handle negative shifts.
 305         (do_scalar_shift): Handle SSHR.
 306         (do_scalar_USHL): New function.
 307         (do_double_add): Simplify to just performing a double precision
 308         add operation.  Move remaining code into...
 309         (do_scalar_vec): ... New function.
 310         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 311         functions.
 312         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 313         registers.
 314         (system_set): New function.
 315         (do_MSR_immediate): New function.  Stub for now.
 316         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 317         instruction.
 318         (do_SYS): New function.  Stub for now,
 319         (dexSystem): Call new functions.
 320
 321 2016-03-18  Nick Clifton  <nickc@redhat.com>
 322
 323         * cpustate.c: Remove spurious spaces from TRACE strings.
 324         Print hex equivalents of floats and doubles.
 325         Check element number against array size when accessing vector
 326         registers.
 327         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 328         element index.
 329         (SET_VEC_ELEMENT): Likewise.
 330         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 331
 332         * memory.c: Trace memory reads when --trace-memory is enabled.
 333         Remove float and double load and store functions.
 334         * memory.h (aarch64_get_mem_float): Delete prototype.
 335         (aarch64_get_mem_double): Likewise.
 336         (aarch64_set_mem_float): Likewise.
 337         (aarch64_set_mem_double): Likewise.
 338         * simulator (IS_SET): Always return either 0 or 1.
 339         (IS_CLEAR): Likewise.
 340         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 341         and doubles using 64-bit memory accesses.
 342         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 343         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 344         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 345         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 346         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 347         (do_vec_MUL_by_element): New function.
 348         (do_vec_op2): Call do_vec_MUL_by_element.
 349         (do_scalar_NEG): New function.
 350         (do_double_add): Call do_scalar_NEG.
 351
 352 2016-03-03  Nick Clifton  <nickc@redhat.com>
 353
 354         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 355         (CondCompare): Swap interpretation of bit 30.
 356         (DO_ADDP): Delete macro.
 357         (do_vec_ADDP): Copy source registers before starting to update
 358         destination register.
 359         (do_vec_FADDP): Likewise.
 360         (do_vec_load_store): Fix computation of sizeof_operation.
 361         (rbit64): Fix type of constant.
 362         (aarch64_step): When displaying insn value, display all 32 bits.
 363
 364 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 365
 366         * config.in, configure: Regenerate.
 367
 368 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 369
 370         * configure: Regenerate.
 371
 372 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 373
 374         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 375         * configure: Regenerate.
 376
 377 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 378
 379         * configure: Regenerate.
 380
 381 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 382
 383         * configure: Regenerate.
 384
 385 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 386
 387         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 388         * configure: Regenerate.
 389
 390 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 391
 392         * configure: Regenerate.
 393
 394 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 395
 396         * configure: Regenerate.
 397
 398 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 399
 400         * config.in, configure: Regenerate.
 401
 402 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 403
 404         * interp.c (sim_create_inferior): Mark argv and env const.
 405         (sim_open): Mark argv const.
 406
 407 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 408
 409         * interp.c: Delete dis-asm.h include.
 410         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 411         (sim_create_inferior): Delete disassemble init logic.
 412         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 413         (sim_open): Delete sim_add_option_table call.
 414         * memory.c (mem_error): Delete disas check.
 415         * simulator.c: Delete dis-asm.h include.
 416         (disas): Delete.
 417         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 418         (HALT_NYI): Likewise.
 419         (handle_halt): Delete disas call.
 420         (aarch64_step): Replace disas logic with TRACE_DISASM.
 421         * simulator.h: Delete dis-asm.h include.
 422         (aarch64_print_insn): Delete.
 423
 424 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 425
 426         * simulator.c (MAX, MIN): Delete.
 427         (do_vec_maxv): Change MAX to max and MIN to min.
 428         (do_vec_fminmaxV): Likewise.
 429
 430 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 431
 432         * simulator.c: Remove syscall.h include.
 433
 434 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 435
 436         * configure: Regenerate.
 437
 438 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 439
 440         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 441         * configure: Regenerate.
 442
 443 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 444
 445         * configure: Regenerate.
 446
 447 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 448
 449         * interp.c (sim_dis_read): Change private_data to application_data.
 450         (sim_create_inferior): Likewise.
 451
 452 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 453
 454         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 455
 456 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 457
 458         * config.in, configure: Regenerate.
 459
 460 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 461
 462         * interp.c (sim_create_inferior): Update comment and argv check.
 463
 464 2015-12-14  Nick Clifton  <nickc@redhat.com>
 465
 466         * simulator.c (system_get): New function.  Provides read
 467         access to the dczid system register.
 468         (do_mrs): New function - implements the MRS instruction.
 469         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 470         unimplemented system instructions.
 471
 472 2015-11-24  Nick Clifton  <nickc@redhat.com>
 473
 474         * configure.ac: New configure template.
 475         * aclocal.m4: Generate.
 476         * config.in: Generate.
 477         * configure: Generate.
 478         * cpustate.c: New file - functions for accessing AArch64 registers.
 479         * cpustate.h: New header.
 480         * decode.h: New header.
 481         * interp.c: New file - interface between GDB and simulator.
 482         * Makefile.in: New makefile template.
 483         * memory.c: New file - functions for simulating aarch64 memory
 484         accesses.
 485         * memory.h: New header.
 486         * sim-main.h: New header.
 487         * simulator.c: New file - aarch64 simulator functions.
 488         * simulator.h: New header.