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sim: bfin: fix thinko in SIC pin encoding
[thirdparty/binutils-gdb.git] / sim / bfin / dv-bfin_sic.c
1 /* Blackfin System Interrupt Controller (SIC) model.
2
3 Copyright (C) 2010-2011 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
5
6 This file is part of simulators.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21 #include "config.h"
22
23 #include "sim-main.h"
24 #include "devices.h"
25 #include "dv-bfin_sic.h"
26 #include "dv-bfin_cec.h"
27
28 struct bfin_sic
29 {
30 /* We assume first element is the base. */
31 bu32 base;
32
33 /* Order after here is important -- matches hardware MMR layout. */
34 bu16 BFIN_MMR_16(swrst);
35 bu16 BFIN_MMR_16(syscr);
36 bu16 BFIN_MMR_16(rvect); /* XXX: BF59x has a 32bit AUX_REVID here. */
37 union {
38 struct {
39 bu32 imask0;
40 bu32 iar0, iar1, iar2, iar3;
41 bu32 isr0, iwr0;
42 bu32 _pad0[9];
43 bu32 imask1;
44 bu32 iar4, iar5, iar6, iar7;
45 bu32 isr1, iwr1;
46 } bf52x;
47 struct {
48 bu32 imask;
49 bu32 iar0, iar1, iar2, iar3;
50 bu32 isr, iwr;
51 } bf537;
52 struct {
53 bu32 imask0, imask1, imask2;
54 bu32 isr0, isr1, isr2;
55 bu32 iwr0, iwr1, iwr2;
56 bu32 iar0, iar1, iar2, iar3;
57 bu32 iar4, iar5, iar6, iar7;
58 bu32 iar8, iar9, iar10, iar11;
59 } bf54x;
60 struct {
61 bu32 imask0, imask1;
62 bu32 iar0, iar1, iar2, iar3;
63 bu32 iar4, iar5, iar6, iar7;
64 bu32 isr0, isr1;
65 bu32 iwr0, iwr1;
66 } bf561;
67 };
68 };
69 #define mmr_base() offsetof(struct bfin_sic, swrst)
70 #define mmr_offset(mmr) (offsetof(struct bfin_sic, mmr) - mmr_base())
71 #define mmr_idx(mmr) (mmr_offset (mmr) / 4)
72
73 static const char * const bf52x_mmr_names[] =
74 {
75 "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK0", "SIC_IAR0", "SIC_IAR1",
76 "SIC_IAR2", "SIC_IAR3", "SIC_ISR0", "SIC_IWR0",
77 [mmr_idx (bf52x.imask1)] = "SIC_IMASK1", "SIC_IAR4", "SIC_IAR5",
78 "SIC_IAR6", "SIC_IAR7", "SIC_ISR1", "SIC_IWR1",
79 };
80 static const char * const bf537_mmr_names[] =
81 {
82 "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK", "SIC_IAR0", "SIC_IAR1",
83 "SIC_IAR2", "SIC_IAR3", "SIC_ISR", "SIC_IWR",
84 };
85 static const char * const bf54x_mmr_names[] =
86 {
87 "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK0", "SIC_IMASK1", "SIC_IMASK2",
88 "SIC_ISR0", "SIC_ISR1", "SIC_ISR2", "SIC_IWR0", "SIC_IWR1", "SIC_IWR2",
89 "SIC_IAR0", "SIC_IAR1", "SIC_IAR2", "SIC_IAR3",
90 "SIC_IAR4", "SIC_IAR5", "SIC_IAR6", "SIC_IAR7",
91 "SIC_IAR8", "SIC_IAR9", "SIC_IAR10", "SIC_IAR11",
92 };
93 static const char * const bf561_mmr_names[] =
94 {
95 "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK0", "SIC_IMASK1",
96 "SIC_IAR0", "SIC_IAR1", "SIC_IAR2", "SIC_IAR3",
97 "SIC_IAR4", "SIC_IAR5", "SIC_IAR6", "SIC_IAR7",
98 "SIC_ISR0", "SIC_ISR1", "SIC_IWR0", "SIC_IWR1",
99 };
100 static const char * const *mmr_names;
101 #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
102
103 static void
104 bfin_sic_forward_interrupts (struct hw *me, bu32 *isr, bu32 *imask, bu32 *iar)
105 {
106 int my_port;
107 bu32 ipend;
108
109 /* Process pending and unmasked interrupts. */
110 ipend = *isr & *imask;
111
112 /* Usually none are pending unmasked, so avoid bit twiddling. */
113 if (!ipend)
114 return;
115
116 for (my_port = 0; my_port < 32; ++my_port)
117 {
118 bu32 iar_idx, iar_off, iar_val;
119 bu32 bit = (1 << my_port);
120
121 /* This bit isn't pending, so check next one. */
122 if (!(ipend & bit))
123 continue;
124
125 /* The IAR registers map the System input to the Core output.
126 Every 4 bits in the IAR are used to map to IVG{7..15}. */
127 iar_idx = my_port / 8;
128 iar_off = (my_port % 8) * 4;
129 iar_val = (iar[iar_idx] & (0xf << iar_off)) >> iar_off;
130 hw_port_event (me, IVG7 + iar_val, 1);
131 }
132 }
133
134 static void
135 bfin_sic_52x_forward_interrupts (struct hw *me, struct bfin_sic *sic)
136 {
137 bfin_sic_forward_interrupts (me, &sic->bf52x.isr0, &sic->bf52x.imask0, &sic->bf52x.iar0);
138 bfin_sic_forward_interrupts (me, &sic->bf52x.isr1, &sic->bf52x.imask1, &sic->bf52x.iar4);
139 }
140
141 static unsigned
142 bfin_sic_52x_io_write_buffer (struct hw *me, const void *source, int space,
143 address_word addr, unsigned nr_bytes)
144 {
145 struct bfin_sic *sic = hw_data (me);
146 bu32 mmr_off;
147 bu32 value;
148 bu16 *value16p;
149 bu32 *value32p;
150 void *valuep;
151
152 if (nr_bytes == 4)
153 value = dv_load_4 (source);
154 else
155 value = dv_load_2 (source);
156
157 mmr_off = addr - sic->base;
158 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
159 value16p = valuep;
160 value32p = valuep;
161
162 HW_TRACE_WRITE ();
163
164 /* XXX: Discard all SIC writes for now. */
165 switch (mmr_off)
166 {
167 case mmr_offset(swrst):
168 /* XXX: This should trigger a software reset ... */
169 break;
170 case mmr_offset(syscr):
171 /* XXX: what to do ... */
172 break;
173 case mmr_offset(bf52x.imask0):
174 case mmr_offset(bf52x.imask1):
175 bfin_sic_52x_forward_interrupts (me, sic);
176 *value32p = value;
177 break;
178 case mmr_offset(bf52x.iar0) ... mmr_offset(bf52x.iar3):
179 case mmr_offset(bf52x.iar4) ... mmr_offset(bf52x.iar7):
180 case mmr_offset(bf52x.iwr0):
181 case mmr_offset(bf52x.iwr1):
182 *value32p = value;
183 break;
184 case mmr_offset(bf52x.isr0):
185 case mmr_offset(bf52x.isr1):
186 /* ISR is read-only. */
187 break;
188 default:
189 /* XXX: Should discard other writes. */
190 ;
191 }
192
193 return nr_bytes;
194 }
195
196 static unsigned
197 bfin_sic_52x_io_read_buffer (struct hw *me, void *dest, int space,
198 address_word addr, unsigned nr_bytes)
199 {
200 struct bfin_sic *sic = hw_data (me);
201 bu32 mmr_off;
202 bu16 *value16p;
203 bu32 *value32p;
204 void *valuep;
205
206 mmr_off = addr - sic->base;
207 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
208 value16p = valuep;
209 value32p = valuep;
210
211 HW_TRACE_READ ();
212
213 switch (mmr_off)
214 {
215 case mmr_offset(swrst):
216 case mmr_offset(syscr):
217 case mmr_offset(rvect):
218 dv_store_2 (dest, *value16p);
219 break;
220 case mmr_offset(bf52x.imask0):
221 case mmr_offset(bf52x.imask1):
222 case mmr_offset(bf52x.iar0) ... mmr_offset(bf52x.iar3):
223 case mmr_offset(bf52x.iar4) ... mmr_offset(bf52x.iar7):
224 case mmr_offset(bf52x.iwr0):
225 case mmr_offset(bf52x.iwr1):
226 case mmr_offset(bf52x.isr0):
227 case mmr_offset(bf52x.isr1):
228 dv_store_4 (dest, *value32p);
229 break;
230 default:
231 if (nr_bytes == 2)
232 dv_store_2 (dest, 0);
233 else
234 dv_store_4 (dest, 0);
235 break;
236 }
237
238 return nr_bytes;
239 }
240
241 static void
242 bfin_sic_537_forward_interrupts (struct hw *me, struct bfin_sic *sic)
243 {
244 bfin_sic_forward_interrupts (me, &sic->bf537.isr, &sic->bf537.imask, &sic->bf537.iar0);
245 }
246
247 static unsigned
248 bfin_sic_537_io_write_buffer (struct hw *me, const void *source, int space,
249 address_word addr, unsigned nr_bytes)
250 {
251 struct bfin_sic *sic = hw_data (me);
252 bu32 mmr_off;
253 bu32 value;
254 bu16 *value16p;
255 bu32 *value32p;
256 void *valuep;
257
258 if (nr_bytes == 4)
259 value = dv_load_4 (source);
260 else
261 value = dv_load_2 (source);
262
263 mmr_off = addr - sic->base;
264 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
265 value16p = valuep;
266 value32p = valuep;
267
268 HW_TRACE_WRITE ();
269
270 /* XXX: Discard all SIC writes for now. */
271 switch (mmr_off)
272 {
273 case mmr_offset(swrst):
274 /* XXX: This should trigger a software reset ... */
275 break;
276 case mmr_offset(syscr):
277 /* XXX: what to do ... */
278 break;
279 case mmr_offset(bf537.imask):
280 bfin_sic_537_forward_interrupts (me, sic);
281 *value32p = value;
282 break;
283 case mmr_offset(bf537.iar0):
284 case mmr_offset(bf537.iar1):
285 case mmr_offset(bf537.iar2):
286 case mmr_offset(bf537.iar3):
287 case mmr_offset(bf537.iwr):
288 *value32p = value;
289 break;
290 case mmr_offset(bf537.isr):
291 /* ISR is read-only. */
292 break;
293 default:
294 /* XXX: Should discard other writes. */
295 ;
296 }
297
298 return nr_bytes;
299 }
300
301 static unsigned
302 bfin_sic_537_io_read_buffer (struct hw *me, void *dest, int space,
303 address_word addr, unsigned nr_bytes)
304 {
305 struct bfin_sic *sic = hw_data (me);
306 bu32 mmr_off;
307 bu16 *value16p;
308 bu32 *value32p;
309 void *valuep;
310
311 mmr_off = addr - sic->base;
312 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
313 value16p = valuep;
314 value32p = valuep;
315
316 HW_TRACE_READ ();
317
318 switch (mmr_off)
319 {
320 case mmr_offset(swrst):
321 case mmr_offset(syscr):
322 case mmr_offset(rvect):
323 dv_store_2 (dest, *value16p);
324 break;
325 case mmr_offset(bf537.imask):
326 case mmr_offset(bf537.iar0):
327 case mmr_offset(bf537.iar1):
328 case mmr_offset(bf537.iar2):
329 case mmr_offset(bf537.iar3):
330 case mmr_offset(bf537.isr):
331 case mmr_offset(bf537.iwr):
332 dv_store_4 (dest, *value32p);
333 break;
334 default:
335 if (nr_bytes == 2)
336 dv_store_2 (dest, 0);
337 else
338 dv_store_4 (dest, 0);
339 break;
340 }
341
342 return nr_bytes;
343 }
344
345 static void
346 bfin_sic_54x_forward_interrupts (struct hw *me, struct bfin_sic *sic)
347 {
348 bfin_sic_forward_interrupts (me, &sic->bf54x.isr0, &sic->bf54x.imask0, &sic->bf54x.iar0);
349 bfin_sic_forward_interrupts (me, &sic->bf54x.isr1, &sic->bf54x.imask1, &sic->bf54x.iar4);
350 bfin_sic_forward_interrupts (me, &sic->bf54x.isr2, &sic->bf54x.imask2, &sic->bf54x.iar8);
351 }
352
353 static unsigned
354 bfin_sic_54x_io_write_buffer (struct hw *me, const void *source, int space,
355 address_word addr, unsigned nr_bytes)
356 {
357 struct bfin_sic *sic = hw_data (me);
358 bu32 mmr_off;
359 bu32 value;
360 bu16 *value16p;
361 bu32 *value32p;
362 void *valuep;
363
364 if (nr_bytes == 4)
365 value = dv_load_4 (source);
366 else
367 value = dv_load_2 (source);
368
369 mmr_off = addr - sic->base;
370 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
371 value16p = valuep;
372 value32p = valuep;
373
374 HW_TRACE_WRITE ();
375
376 /* XXX: Discard all SIC writes for now. */
377 switch (mmr_off)
378 {
379 case mmr_offset(swrst):
380 /* XXX: This should trigger a software reset ... */
381 break;
382 case mmr_offset(syscr):
383 /* XXX: what to do ... */
384 break;
385 case mmr_offset(bf54x.imask0) ... mmr_offset(bf54x.imask2):
386 bfin_sic_54x_forward_interrupts (me, sic);
387 *value32p = value;
388 break;
389 case mmr_offset(bf54x.iar0) ... mmr_offset(bf54x.iar11):
390 case mmr_offset(bf54x.iwr0) ... mmr_offset(bf54x.iwr2):
391 *value32p = value;
392 break;
393 case mmr_offset(bf54x.isr0) ... mmr_offset(bf54x.isr2):
394 /* ISR is read-only. */
395 break;
396 default:
397 /* XXX: Should discard other writes. */
398 ;
399 }
400
401 return nr_bytes;
402 }
403
404 static unsigned
405 bfin_sic_54x_io_read_buffer (struct hw *me, void *dest, int space,
406 address_word addr, unsigned nr_bytes)
407 {
408 struct bfin_sic *sic = hw_data (me);
409 bu32 mmr_off;
410 bu16 *value16p;
411 bu32 *value32p;
412 void *valuep;
413
414 mmr_off = addr - sic->base;
415 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
416 value16p = valuep;
417 value32p = valuep;
418
419 HW_TRACE_READ ();
420
421 switch (mmr_off)
422 {
423 case mmr_offset(swrst):
424 case mmr_offset(syscr):
425 case mmr_offset(rvect):
426 dv_store_2 (dest, *value16p);
427 break;
428 case mmr_offset(bf54x.imask0) ... mmr_offset(bf54x.imask2):
429 case mmr_offset(bf54x.iar0) ... mmr_offset(bf54x.iar11):
430 case mmr_offset(bf54x.iwr0) ... mmr_offset(bf54x.iwr2):
431 case mmr_offset(bf54x.isr0) ... mmr_offset(bf54x.isr2):
432 dv_store_4 (dest, *value32p);
433 break;
434 default:
435 if (nr_bytes == 2)
436 dv_store_2 (dest, 0);
437 else
438 dv_store_4 (dest, 0);
439 break;
440 }
441
442 return nr_bytes;
443 }
444
445 static void
446 bfin_sic_561_forward_interrupts (struct hw *me, struct bfin_sic *sic)
447 {
448 bfin_sic_forward_interrupts (me, &sic->bf561.isr0, &sic->bf561.imask0, &sic->bf561.iar0);
449 bfin_sic_forward_interrupts (me, &sic->bf561.isr1, &sic->bf561.imask1, &sic->bf561.iar4);
450 }
451
452 static unsigned
453 bfin_sic_561_io_write_buffer (struct hw *me, const void *source, int space,
454 address_word addr, unsigned nr_bytes)
455 {
456 struct bfin_sic *sic = hw_data (me);
457 bu32 mmr_off;
458 bu32 value;
459 bu16 *value16p;
460 bu32 *value32p;
461 void *valuep;
462
463 if (nr_bytes == 4)
464 value = dv_load_4 (source);
465 else
466 value = dv_load_2 (source);
467
468 mmr_off = addr - sic->base;
469 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
470 value16p = valuep;
471 value32p = valuep;
472
473 HW_TRACE_WRITE ();
474
475 /* XXX: Discard all SIC writes for now. */
476 switch (mmr_off)
477 {
478 case mmr_offset(swrst):
479 /* XXX: This should trigger a software reset ... */
480 break;
481 case mmr_offset(syscr):
482 /* XXX: what to do ... */
483 break;
484 case mmr_offset(bf561.imask0):
485 case mmr_offset(bf561.imask1):
486 bfin_sic_561_forward_interrupts (me, sic);
487 *value32p = value;
488 break;
489 case mmr_offset(bf561.iar0) ... mmr_offset(bf561.iar3):
490 case mmr_offset(bf561.iar4) ... mmr_offset(bf561.iar7):
491 case mmr_offset(bf561.iwr0):
492 case mmr_offset(bf561.iwr1):
493 *value32p = value;
494 break;
495 case mmr_offset(bf561.isr0):
496 case mmr_offset(bf561.isr1):
497 /* ISR is read-only. */
498 break;
499 default:
500 /* XXX: Should discard other writes. */
501 ;
502 }
503
504 return nr_bytes;
505 }
506
507 static unsigned
508 bfin_sic_561_io_read_buffer (struct hw *me, void *dest, int space,
509 address_word addr, unsigned nr_bytes)
510 {
511 struct bfin_sic *sic = hw_data (me);
512 bu32 mmr_off;
513 bu16 *value16p;
514 bu32 *value32p;
515 void *valuep;
516
517 mmr_off = addr - sic->base;
518 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
519 value16p = valuep;
520 value32p = valuep;
521
522 HW_TRACE_READ ();
523
524 switch (mmr_off)
525 {
526 case mmr_offset(swrst):
527 case mmr_offset(syscr):
528 case mmr_offset(rvect):
529 dv_store_2 (dest, *value16p);
530 break;
531 case mmr_offset(bf561.imask0):
532 case mmr_offset(bf561.imask1):
533 case mmr_offset(bf561.iar0) ... mmr_offset(bf561.iar3):
534 case mmr_offset(bf561.iar4) ... mmr_offset(bf561.iar7):
535 case mmr_offset(bf561.iwr0):
536 case mmr_offset(bf561.iwr1):
537 case mmr_offset(bf561.isr0):
538 case mmr_offset(bf561.isr1):
539 dv_store_4 (dest, *value32p);
540 break;
541 default:
542 if (nr_bytes == 2)
543 dv_store_2 (dest, 0);
544 else
545 dv_store_4 (dest, 0);
546 break;
547 }
548
549 return nr_bytes;
550 }
551
552 /* XXX: This doesn't handle DMA<->peripheral mappings. */
553 #define BFIN_SIC_TO_CEC_PORTS \
554 { "ivg7", IVG7, 0, output_port, }, \
555 { "ivg8", IVG8, 0, output_port, }, \
556 { "ivg9", IVG9, 0, output_port, }, \
557 { "ivg10", IVG10, 0, output_port, }, \
558 { "ivg11", IVG11, 0, output_port, }, \
559 { "ivg12", IVG12, 0, output_port, }, \
560 { "ivg13", IVG13, 0, output_port, }, \
561 { "ivg14", IVG14, 0, output_port, }, \
562 { "ivg15", IVG15, 0, output_port, },
563
564 /* Give each SIC its own base to make it easier to extract the pin at
565 runtime. The pin is used as its bit position in the SIC MMRs. */
566 #define ENC(sic, pin) (((sic) << 8) + (pin))
567 #define DEC_PIN(pin) ((pin) % 0x100)
568 #define DEC_SIC(pin) ((pin) >> 8)
569
570 static const struct hw_port_descriptor bfin_sic_50x_ports[] =
571 {
572 BFIN_SIC_TO_CEC_PORTS
573 /* SIC0 */
574 { "pll", ENC(0, 0), 0, input_port, },
575 { "dma_stat", ENC(0, 1), 0, input_port, },
576 { "ppi@0", ENC(0, 2), 0, input_port, },
577 { "sport@0_stat", ENC(0, 3), 0, input_port, },
578 { "sport@1_stat", ENC(0, 4), 0, input_port, },
579 { "uart2@0_stat", ENC(0, 5), 0, input_port, },
580 { "uart2@1_stat", ENC(0, 6), 0, input_port, },
581 { "spi@0", ENC(0, 7), 0, input_port, },
582 { "spi@1", ENC(0, 8), 0, input_port, },
583 { "can_stat", ENC(0, 9), 0, input_port, },
584 { "rsi_int0", ENC(0, 10), 0, input_port, },
585 /*{ "reserved", ENC(0, 11), 0, input_port, },*/
586 { "counter@0", ENC(0, 12), 0, input_port, },
587 { "counter@1", ENC(0, 13), 0, input_port, },
588 { "dma@0", ENC(0, 14), 0, input_port, },
589 { "dma@1", ENC(0, 15), 0, input_port, },
590 { "dma@2", ENC(0, 16), 0, input_port, },
591 { "dma@3", ENC(0, 17), 0, input_port, },
592 { "dma@4", ENC(0, 18), 0, input_port, },
593 { "dma@5", ENC(0, 19), 0, input_port, },
594 { "dma@6", ENC(0, 20), 0, input_port, },
595 { "dma@7", ENC(0, 21), 0, input_port, },
596 { "dma@8", ENC(0, 22), 0, input_port, },
597 { "dma@9", ENC(0, 23), 0, input_port, },
598 { "dma@10", ENC(0, 24), 0, input_port, },
599 { "dma@11", ENC(0, 25), 0, input_port, },
600 { "can_rx", ENC(0, 26), 0, input_port, },
601 { "can_tx", ENC(0, 27), 0, input_port, },
602 { "twi@0", ENC(0, 28), 0, input_port, },
603 { "portf_irq_a", ENC(0, 29), 0, input_port, },
604 { "portf_irq_b", ENC(0, 30), 0, input_port, },
605 /*{ "reserved", ENC(0, 31), 0, input_port, },*/
606 /* SIC1 */
607 { "gptimer@0", ENC(1, 0), 0, input_port, },
608 { "gptimer@1", ENC(1, 1), 0, input_port, },
609 { "gptimer@2", ENC(1, 2), 0, input_port, },
610 { "gptimer@3", ENC(1, 3), 0, input_port, },
611 { "gptimer@4", ENC(1, 4), 0, input_port, },
612 { "gptimer@5", ENC(1, 5), 0, input_port, },
613 { "gptimer@6", ENC(1, 6), 0, input_port, },
614 { "gptimer@7", ENC(1, 7), 0, input_port, },
615 { "portg_irq_a", ENC(1, 8), 0, input_port, },
616 { "portg_irq_b", ENC(1, 9), 0, input_port, },
617 { "mdma@0", ENC(1, 10), 0, input_port, },
618 { "mdma@1", ENC(1, 11), 0, input_port, },
619 { "wdog", ENC(1, 12), 0, input_port, },
620 { "porth_irq_a", ENC(1, 13), 0, input_port, },
621 { "porth_irq_b", ENC(1, 14), 0, input_port, },
622 { "acm_stat", ENC(1, 15), 0, input_port, },
623 { "acm_int", ENC(1, 16), 0, input_port, },
624 /*{ "reserved", ENC(1, 17), 0, input_port, },*/
625 /*{ "reserved", ENC(1, 18), 0, input_port, },*/
626 { "pwm@0_trip", ENC(1, 19), 0, input_port, },
627 { "pwm@0_sync", ENC(1, 20), 0, input_port, },
628 { "pwm@1_trip", ENC(1, 21), 0, input_port, },
629 { "pwm@1_sync", ENC(1, 22), 0, input_port, },
630 { "rsi_int1", ENC(1, 23), 0, input_port, },
631 { NULL, 0, 0, 0, },
632 };
633
634 static const struct hw_port_descriptor bfin_sic_51x_ports[] =
635 {
636 BFIN_SIC_TO_CEC_PORTS
637 /* SIC0 */
638 { "pll", ENC(0, 0), 0, input_port, },
639 { "dma_stat", ENC(0, 1), 0, input_port, },
640 { "dmar0_block", ENC(0, 2), 0, input_port, },
641 { "dmar1_block", ENC(0, 3), 0, input_port, },
642 { "dmar0_over", ENC(0, 4), 0, input_port, },
643 { "dmar1_over", ENC(0, 5), 0, input_port, },
644 { "ppi@0", ENC(0, 6), 0, input_port, },
645 { "emac_stat", ENC(0, 7), 0, input_port, },
646 { "sport@0_stat", ENC(0, 8), 0, input_port, },
647 { "sport@1_stat", ENC(0, 9), 0, input_port, },
648 { "ptp_err", ENC(0, 10), 0, input_port, },
649 /*{ "reserved", ENC(0, 11), 0, input_port, },*/
650 { "uart@0_stat", ENC(0, 12), 0, input_port, },
651 { "uart@1_stat", ENC(0, 13), 0, input_port, },
652 { "rtc", ENC(0, 14), 0, input_port, },
653 { "dma@0", ENC(0, 15), 0, input_port, },
654 { "dma@3", ENC(0, 16), 0, input_port, },
655 { "dma@4", ENC(0, 17), 0, input_port, },
656 { "dma@5", ENC(0, 18), 0, input_port, },
657 { "dma@6", ENC(0, 19), 0, input_port, },
658 { "twi@0", ENC(0, 20), 0, input_port, },
659 { "dma@7", ENC(0, 21), 0, input_port, },
660 { "dma@8", ENC(0, 22), 0, input_port, },
661 { "dma@9", ENC(0, 23), 0, input_port, },
662 { "dma@10", ENC(0, 24), 0, input_port, },
663 { "dma@11", ENC(0, 25), 0, input_port, },
664 { "otp", ENC(0, 26), 0, input_port, },
665 { "counter", ENC(0, 27), 0, input_port, },
666 { "dma@1", ENC(0, 28), 0, input_port, },
667 { "porth_irq_a", ENC(0, 29), 0, input_port, },
668 { "dma@2", ENC(0, 30), 0, input_port, },
669 { "porth_irq_b", ENC(0, 31), 0, input_port, },
670 /* SIC1 */
671 { "gptimer@0", ENC(1, 0), 0, input_port, },
672 { "gptimer@1", ENC(1, 1), 0, input_port, },
673 { "gptimer@2", ENC(1, 2), 0, input_port, },
674 { "gptimer@3", ENC(1, 3), 0, input_port, },
675 { "gptimer@4", ENC(1, 4), 0, input_port, },
676 { "gptimer@5", ENC(1, 5), 0, input_port, },
677 { "gptimer@6", ENC(1, 6), 0, input_port, },
678 { "gptimer@7", ENC(1, 7), 0, input_port, },
679 { "portg_irq_a", ENC(1, 8), 0, input_port, },
680 { "portg_irq_b", ENC(1, 9), 0, input_port, },
681 { "mdma@0", ENC(1, 10), 0, input_port, },
682 { "mdma@1", ENC(1, 11), 0, input_port, },
683 { "wdog", ENC(1, 12), 0, input_port, },
684 { "portf_irq_a", ENC(1, 13), 0, input_port, },
685 { "portf_irq_b", ENC(1, 14), 0, input_port, },
686 { "spi@0", ENC(1, 15), 0, input_port, },
687 { "spi@1", ENC(1, 16), 0, input_port, },
688 /*{ "reserved", ENC(1, 17), 0, input_port, },*/
689 /*{ "reserved", ENC(1, 18), 0, input_port, },*/
690 { "rsi_int0", ENC(1, 19), 0, input_port, },
691 { "rsi_int1", ENC(1, 20), 0, input_port, },
692 { "pwm_trip", ENC(1, 21), 0, input_port, },
693 { "pwm_sync", ENC(1, 22), 0, input_port, },
694 { "ptp_stat", ENC(1, 23), 0, input_port, },
695 { NULL, 0, 0, 0, },
696 };
697
698 static const struct hw_port_descriptor bfin_sic_52x_ports[] =
699 {
700 BFIN_SIC_TO_CEC_PORTS
701 /* SIC0 */
702 { "pll", ENC(0, 0), 0, input_port, },
703 { "dma_stat", ENC(0, 1), 0, input_port, },
704 { "dmar0_block", ENC(0, 2), 0, input_port, },
705 { "dmar1_block", ENC(0, 3), 0, input_port, },
706 { "dmar0_over", ENC(0, 4), 0, input_port, },
707 { "dmar1_over", ENC(0, 5), 0, input_port, },
708 { "ppi@0", ENC(0, 6), 0, input_port, },
709 { "emac_stat", ENC(0, 7), 0, input_port, },
710 { "sport@0_stat", ENC(0, 8), 0, input_port, },
711 { "sport@1_stat", ENC(0, 9), 0, input_port, },
712 /*{ "reserved", ENC(0, 10), 0, input_port, },*/
713 /*{ "reserved", ENC(0, 11), 0, input_port, },*/
714 { "uart@0_stat", ENC(0, 12), 0, input_port, },
715 { "uart@1_stat", ENC(0, 13), 0, input_port, },
716 { "rtc", ENC(0, 14), 0, input_port, },
717 { "dma@0", ENC(0, 15), 0, input_port, },
718 { "dma@3", ENC(0, 16), 0, input_port, },
719 { "dma@4", ENC(0, 17), 0, input_port, },
720 { "dma@5", ENC(0, 18), 0, input_port, },
721 { "dma@6", ENC(0, 19), 0, input_port, },
722 { "twi@0", ENC(0, 20), 0, input_port, },
723 { "dma@7", ENC(0, 21), 0, input_port, },
724 { "dma@8", ENC(0, 22), 0, input_port, },
725 { "dma@9", ENC(0, 23), 0, input_port, },
726 { "dma@10", ENC(0, 24), 0, input_port, },
727 { "dma@11", ENC(0, 25), 0, input_port, },
728 { "otp", ENC(0, 26), 0, input_port, },
729 { "counter", ENC(0, 27), 0, input_port, },
730 { "dma@1", ENC(0, 28), 0, input_port, },
731 { "porth_irq_a", ENC(0, 29), 0, input_port, },
732 { "dma@2", ENC(0, 30), 0, input_port, },
733 { "porth_irq_b", ENC(0, 31), 0, input_port, },
734 /* SIC1 */
735 { "gptimer@0", ENC(1, 0), 0, input_port, },
736 { "gptimer@1", ENC(1, 1), 0, input_port, },
737 { "gptimer@2", ENC(1, 2), 0, input_port, },
738 { "gptimer@3", ENC(1, 3), 0, input_port, },
739 { "gptimer@4", ENC(1, 4), 0, input_port, },
740 { "gptimer@5", ENC(1, 5), 0, input_port, },
741 { "gptimer@6", ENC(1, 6), 0, input_port, },
742 { "gptimer@7", ENC(1, 7), 0, input_port, },
743 { "portg_irq_a", ENC(1, 8), 0, input_port, },
744 { "portg_irq_b", ENC(1, 9), 0, input_port, },
745 { "mdma@0", ENC(1, 10), 0, input_port, },
746 { "mdma@1", ENC(1, 11), 0, input_port, },
747 { "wdog", ENC(1, 12), 0, input_port, },
748 { "portf_irq_a", ENC(1, 13), 0, input_port, },
749 { "portf_irq_b", ENC(1, 14), 0, input_port, },
750 { "spi@0", ENC(1, 15), 0, input_port, },
751 { "nfc_stat", ENC(1, 16), 0, input_port, },
752 { "hostdp_stat", ENC(1, 17), 0, input_port, },
753 { "hostdp_done", ENC(1, 18), 0, input_port, },
754 { "usb_int0", ENC(1, 20), 0, input_port, },
755 { "usb_int1", ENC(1, 21), 0, input_port, },
756 { "usb_int2", ENC(1, 22), 0, input_port, },
757 { NULL, 0, 0, 0, },
758 };
759
760 static void
761 bfin_sic_52x_port_event (struct hw *me, int my_port, struct hw *source,
762 int source_port, int level)
763 {
764 struct bfin_sic *sic = hw_data (me);
765 bu32 idx = DEC_SIC (my_port);
766 bu32 bit = 1 << DEC_PIN (my_port);
767
768 /* SIC only exists to forward interrupts from the system to the CEC. */
769 switch (idx)
770 {
771 case 0: sic->bf52x.isr0 |= bit; break;
772 case 1: sic->bf52x.isr1 |= bit; break;
773 }
774
775 /* XXX: Handle SIC wakeup source ?
776 if (sic->bf52x.iwr0 & bit)
777 What to do ?;
778 if (sic->bf52x.iwr1 & bit)
779 What to do ?;
780 */
781
782 bfin_sic_52x_forward_interrupts (me, sic);
783 }
784
785 static const struct hw_port_descriptor bfin_sic_533_ports[] =
786 {
787 BFIN_SIC_TO_CEC_PORTS
788 { "pll", ENC(0, 0), 0, input_port, },
789 { "dma_stat", ENC(0, 1), 0, input_port, },
790 { "ppi@0", ENC(0, 2), 0, input_port, },
791 { "sport@0_stat", ENC(0, 3), 0, input_port, },
792 { "sport@1_stat", ENC(0, 4), 0, input_port, },
793 { "spi@0", ENC(0, 5), 0, input_port, },
794 { "uart@0_stat", ENC(0, 6), 0, input_port, },
795 { "rtc", ENC(0, 7), 0, input_port, },
796 { "dma@0", ENC(0, 8), 0, input_port, },
797 { "dma@1", ENC(0, 9), 0, input_port, },
798 { "dma@2", ENC(0, 10), 0, input_port, },
799 { "dma@3", ENC(0, 11), 0, input_port, },
800 { "dma@4", ENC(0, 12), 0, input_port, },
801 { "dma@5", ENC(0, 13), 0, input_port, },
802 { "dma@6", ENC(0, 14), 0, input_port, },
803 { "dma@7", ENC(0, 15), 0, input_port, },
804 { "gptimer@0", ENC(0, 16), 0, input_port, },
805 { "gptimer@1", ENC(0, 17), 0, input_port, },
806 { "gptimer@2", ENC(0, 18), 0, input_port, },
807 { "portf_irq_a", ENC(0, 19), 0, input_port, },
808 { "portf_irq_b", ENC(0, 20), 0, input_port, },
809 { "mdma@0", ENC(0, 21), 0, input_port, },
810 { "mdma@1", ENC(0, 22), 0, input_port, },
811 { "wdog", ENC(0, 23), 0, input_port, },
812 { NULL, 0, 0, 0, },
813 };
814
815 /* The encoding here is uglier due to multiple sources being muxed into
816 the same interrupt line. So give each pin an arbitrary "SIC" so that
817 the resulting id is unique across all ports. */
818 static const struct hw_port_descriptor bfin_sic_537_ports[] =
819 {
820 BFIN_SIC_TO_CEC_PORTS
821 { "pll", ENC(0, 0), 0, input_port, },
822 { "dma_stat", ENC(0, 1), 0, input_port, },
823 { "dmar0_block", ENC(1, 1), 0, input_port, },
824 { "dmar1_block", ENC(2, 1), 0, input_port, },
825 { "dmar0_over", ENC(3, 1), 0, input_port, },
826 { "dmar1_over", ENC(4, 1), 0, input_port, },
827 { "can_stat", ENC(0, 2), 0, input_port, },
828 { "emac_stat", ENC(1, 2), 0, input_port, },
829 { "sport@0_stat", ENC(2, 2), 0, input_port, },
830 { "sport@1_stat", ENC(3, 2), 0, input_port, },
831 { "ppi@0", ENC(4, 2), 0, input_port, },
832 { "spi@0", ENC(5, 2), 0, input_port, },
833 { "uart@0_stat", ENC(6, 2), 0, input_port, },
834 { "uart@1_stat", ENC(7, 2), 0, input_port, },
835 { "rtc", ENC(0, 3), 0, input_port, },
836 { "dma@0", ENC(0, 4), 0, input_port, },
837 { "dma@3", ENC(0, 5), 0, input_port, },
838 { "dma@4", ENC(0, 6), 0, input_port, },
839 { "dma@5", ENC(0, 7), 0, input_port, },
840 { "dma@6", ENC(0, 8), 0, input_port, },
841 { "twi@0", ENC(0, 9), 0, input_port, },
842 { "dma@7", ENC(0, 10), 0, input_port, },
843 { "dma@8", ENC(0, 11), 0, input_port, },
844 { "dma@9", ENC(0, 12), 0, input_port, },
845 { "dma@10", ENC(0, 13), 0, input_port, },
846 { "dma@11", ENC(0, 14), 0, input_port, },
847 { "can_rx", ENC(0, 15), 0, input_port, },
848 { "can_tx", ENC(0, 16), 0, input_port, },
849 { "dma@1", ENC(0, 17), 0, input_port, },
850 { "porth_irq_a", ENC(1, 17), 0, input_port, },
851 { "dma@2", ENC(0, 18), 0, input_port, },
852 { "porth_irq_b", ENC(1, 18), 0, input_port, },
853 { "gptimer@0", ENC(0, 19), 0, input_port, },
854 { "gptimer@1", ENC(0, 20), 0, input_port, },
855 { "gptimer@2", ENC(0, 21), 0, input_port, },
856 { "gptimer@3", ENC(0, 22), 0, input_port, },
857 { "gptimer@4", ENC(0, 23), 0, input_port, },
858 { "gptimer@5", ENC(0, 24), 0, input_port, },
859 { "gptimer@6", ENC(0, 25), 0, input_port, },
860 { "gptimer@7", ENC(0, 26), 0, input_port, },
861 { "portf_irq_a", ENC(0, 27), 0, input_port, },
862 { "portg_irq_a", ENC(1, 27), 0, input_port, },
863 { "portg_irq_b", ENC(0, 28), 0, input_port, },
864 { "mdma@0", ENC(0, 29), 0, input_port, },
865 { "mdma@1", ENC(0, 30), 0, input_port, },
866 { "wdog", ENC(0, 31), 0, input_port, },
867 { "portf_irq_b", ENC(1, 31), 0, input_port, },
868 { NULL, 0, 0, 0, },
869 };
870
871 static void
872 bfin_sic_537_port_event (struct hw *me, int my_port, struct hw *source,
873 int source_port, int level)
874 {
875 struct bfin_sic *sic = hw_data (me);
876 bu32 bit = 1 << DEC_PIN (my_port);
877
878 /* SIC only exists to forward interrupts from the system to the CEC. */
879 sic->bf537.isr |= bit;
880
881 /* XXX: Handle SIC wakeup source ?
882 if (sic->bf537.iwr & bit)
883 What to do ?;
884 */
885
886 bfin_sic_537_forward_interrupts (me, sic);
887 }
888
889 static const struct hw_port_descriptor bfin_sic_538_ports[] =
890 {
891 BFIN_SIC_TO_CEC_PORTS
892 /* SIC0 */
893 { "pll", ENC(0, 0), 0, input_port, },
894 { "dmac@0_stat", ENC(0, 1), 0, input_port, },
895 { "ppi@0", ENC(0, 2), 0, input_port, },
896 { "sport@0_stat", ENC(0, 3), 0, input_port, },
897 { "sport@1_stat", ENC(0, 4), 0, input_port, },
898 { "spi@0", ENC(0, 5), 0, input_port, },
899 { "uart@0_stat", ENC(0, 6), 0, input_port, },
900 { "rtc", ENC(0, 7), 0, input_port, },
901 { "dma@0", ENC(0, 8), 0, input_port, },
902 { "dma@1", ENC(0, 9), 0, input_port, },
903 { "dma@2", ENC(0, 10), 0, input_port, },
904 { "dma@3", ENC(0, 11), 0, input_port, },
905 { "dma@4", ENC(0, 12), 0, input_port, },
906 { "dma@5", ENC(0, 13), 0, input_port, },
907 { "dma@6", ENC(0, 14), 0, input_port, },
908 { "dma@7", ENC(0, 15), 0, input_port, },
909 { "gptimer@0", ENC(0, 16), 0, input_port, },
910 { "gptimer@1", ENC(0, 17), 0, input_port, },
911 { "gptimer@2", ENC(0, 18), 0, input_port, },
912 { "portf_irq_a", ENC(0, 19), 0, input_port, },
913 { "portf_irq_b", ENC(0, 20), 0, input_port, },
914 { "mdma@0", ENC(0, 21), 0, input_port, },
915 { "mdma@1", ENC(0, 22), 0, input_port, },
916 { "wdog", ENC(0, 23), 0, input_port, },
917 { "dmac@1_stat", ENC(0, 24), 0, input_port, },
918 { "sport@2_stat", ENC(0, 25), 0, input_port, },
919 { "sport@3_stat", ENC(0, 26), 0, input_port, },
920 /*{ "reserved", ENC(0, 27), 0, input_port, },*/
921 { "spi@1", ENC(0, 28), 0, input_port, },
922 { "spi@2", ENC(0, 29), 0, input_port, },
923 { "uart@1_stat", ENC(0, 30), 0, input_port, },
924 { "uart@2_stat", ENC(0, 31), 0, input_port, },
925 /* SIC1 */
926 { "can_stat", ENC(1, 0), 0, input_port, },
927 { "dma@8", ENC(1, 1), 0, input_port, },
928 { "dma@9", ENC(1, 2), 0, input_port, },
929 { "dma@10", ENC(1, 3), 0, input_port, },
930 { "dma@11", ENC(1, 4), 0, input_port, },
931 { "dma@12", ENC(1, 5), 0, input_port, },
932 { "dma@13", ENC(1, 6), 0, input_port, },
933 { "dma@14", ENC(1, 7), 0, input_port, },
934 { "dma@15", ENC(1, 8), 0, input_port, },
935 { "dma@16", ENC(1, 9), 0, input_port, },
936 { "dma@17", ENC(1, 10), 0, input_port, },
937 { "dma@18", ENC(1, 11), 0, input_port, },
938 { "dma@19", ENC(1, 12), 0, input_port, },
939 { "twi@0", ENC(1, 13), 0, input_port, },
940 { "twi@1", ENC(1, 14), 0, input_port, },
941 { "can_rx", ENC(1, 15), 0, input_port, },
942 { "can_tx", ENC(1, 16), 0, input_port, },
943 { "mdma@2", ENC(1, 17), 0, input_port, },
944 { "mdma@3", ENC(1, 18), 0, input_port, },
945 { NULL, 0, 0, 0, },
946 };
947
948 static const struct hw_port_descriptor bfin_sic_54x_ports[] =
949 {
950 BFIN_SIC_TO_CEC_PORTS
951 /* SIC0 */
952 { "pll", ENC(0, 0), 0, input_port, },
953 { "dmac@0_stat", ENC(0, 1), 0, input_port, },
954 { "eppi@0", ENC(0, 2), 0, input_port, },
955 { "sport@0_stat", ENC(0, 3), 0, input_port, },
956 { "sport@1_stat", ENC(0, 4), 0, input_port, },
957 { "spi@0", ENC(0, 5), 0, input_port, },
958 { "uart2@0_stat", ENC(0, 6), 0, input_port, },
959 { "rtc", ENC(0, 7), 0, input_port, },
960 { "dma@12", ENC(0, 8), 0, input_port, },
961 { "dma@0", ENC(0, 9), 0, input_port, },
962 { "dma@1", ENC(0, 10), 0, input_port, },
963 { "dma@2", ENC(0, 11), 0, input_port, },
964 { "dma@3", ENC(0, 12), 0, input_port, },
965 { "dma@4", ENC(0, 13), 0, input_port, },
966 { "dma@6", ENC(0, 14), 0, input_port, },
967 { "dma@7", ENC(0, 15), 0, input_port, },
968 { "gptimer@8", ENC(0, 16), 0, input_port, },
969 { "gptimer@9", ENC(0, 17), 0, input_port, },
970 { "gptimer@10", ENC(0, 18), 0, input_port, },
971 { "pint@0", ENC(0, 19), 0, input_port, },
972 { "pint@1", ENC(0, 20), 0, input_port, },
973 { "mdma@0", ENC(0, 21), 0, input_port, },
974 { "mdma@1", ENC(0, 22), 0, input_port, },
975 { "wdog", ENC(0, 23), 0, input_port, },
976 { "dmac@1_stat", ENC(0, 24), 0, input_port, },
977 { "sport@2_stat", ENC(0, 25), 0, input_port, },
978 { "sport@3_stat", ENC(0, 26), 0, input_port, },
979 { "mxvr", ENC(0, 27), 0, input_port, },
980 { "spi@1", ENC(0, 28), 0, input_port, },
981 { "spi@2", ENC(0, 29), 0, input_port, },
982 { "uart2@1_stat", ENC(0, 30), 0, input_port, },
983 { "uart2@2_stat", ENC(0, 31), 0, input_port, },
984 /* SIC1 */
985 { "can@0_stat", ENC(1, 0), 0, input_port, },
986 { "dma@18", ENC(1, 1), 0, input_port, },
987 { "dma@19", ENC(1, 2), 0, input_port, },
988 { "dma@20", ENC(1, 3), 0, input_port, },
989 { "dma@21", ENC(1, 4), 0, input_port, },
990 { "dma@13", ENC(1, 5), 0, input_port, },
991 { "dma@14", ENC(1, 6), 0, input_port, },
992 { "dma@5", ENC(1, 7), 0, input_port, },
993 { "dma@23", ENC(1, 8), 0, input_port, },
994 { "dma@8", ENC(1, 9), 0, input_port, },
995 { "dma@9", ENC(1, 10), 0, input_port, },
996 { "dma@10", ENC(1, 11), 0, input_port, },
997 { "dma@11", ENC(1, 12), 0, input_port, },
998 { "twi@0", ENC(1, 13), 0, input_port, },
999 { "twi@1", ENC(1, 14), 0, input_port, },
1000 { "can@0_rx", ENC(1, 15), 0, input_port, },
1001 { "can@0_tx", ENC(1, 16), 0, input_port, },
1002 { "mdma@2", ENC(1, 17), 0, input_port, },
1003 { "mdma@3", ENC(1, 18), 0, input_port, },
1004 { "mxvr_stat", ENC(1, 19), 0, input_port, },
1005 { "mxvr_message", ENC(1, 20), 0, input_port, },
1006 { "mxvr_packet", ENC(1, 21), 0, input_port, },
1007 { "eppi@1", ENC(1, 22), 0, input_port, },
1008 { "eppi@2", ENC(1, 23), 0, input_port, },
1009 { "uart2@3_stat", ENC(1, 24), 0, input_port, },
1010 { "hostdp", ENC(1, 25), 0, input_port, },
1011 /*{ "reserved", ENC(1, 26), 0, input_port, },*/
1012 { "pixc_stat", ENC(1, 27), 0, input_port, },
1013 { "nfc", ENC(1, 28), 0, input_port, },
1014 { "atapi", ENC(1, 29), 0, input_port, },
1015 { "can@1_stat", ENC(1, 30), 0, input_port, },
1016 { "dmar", ENC(1, 31), 0, input_port, },
1017 /* SIC2 */
1018 { "dma@15", ENC(2, 0), 0, input_port, },
1019 { "dma@16", ENC(2, 1), 0, input_port, },
1020 { "dma@17", ENC(2, 2), 0, input_port, },
1021 { "dma@22", ENC(2, 3), 0, input_port, },
1022 { "counter", ENC(2, 4), 0, input_port, },
1023 { "key", ENC(2, 5), 0, input_port, },
1024 { "can@1_rx", ENC(2, 6), 0, input_port, },
1025 { "can@1_tx", ENC(2, 7), 0, input_port, },
1026 { "sdh_mask0", ENC(2, 8), 0, input_port, },
1027 { "sdh_mask1", ENC(2, 9), 0, input_port, },
1028 /*{ "reserved", ENC(2, 10), 0, input_port, },*/
1029 { "usb_int0", ENC(2, 11), 0, input_port, },
1030 { "usb_int1", ENC(2, 12), 0, input_port, },
1031 { "usb_int2", ENC(2, 13), 0, input_port, },
1032 { "usb_dma", ENC(2, 14), 0, input_port, },
1033 { "otpsec", ENC(2, 15), 0, input_port, },
1034 /*{ "reserved", ENC(2, 16), 0, input_port, },*/
1035 /*{ "reserved", ENC(2, 17), 0, input_port, },*/
1036 /*{ "reserved", ENC(2, 18), 0, input_port, },*/
1037 /*{ "reserved", ENC(2, 19), 0, input_port, },*/
1038 /*{ "reserved", ENC(2, 20), 0, input_port, },*/
1039 /*{ "reserved", ENC(2, 21), 0, input_port, },*/
1040 { "gptimer@0", ENC(2, 22), 0, input_port, },
1041 { "gptimer@1", ENC(2, 23), 0, input_port, },
1042 { "gptimer@2", ENC(2, 24), 0, input_port, },
1043 { "gptimer@3", ENC(2, 25), 0, input_port, },
1044 { "gptimer@4", ENC(2, 26), 0, input_port, },
1045 { "gptimer@5", ENC(2, 27), 0, input_port, },
1046 { "gptimer@6", ENC(2, 28), 0, input_port, },
1047 { "gptimer@7", ENC(2, 29), 0, input_port, },
1048 { "pint2", ENC(2, 30), 0, input_port, },
1049 { "pint3", ENC(2, 31), 0, input_port, },
1050 { NULL, 0, 0, 0, },
1051 };
1052
1053 static void
1054 bfin_sic_54x_port_event (struct hw *me, int my_port, struct hw *source,
1055 int source_port, int level)
1056 {
1057 struct bfin_sic *sic = hw_data (me);
1058 bu32 idx = DEC_SIC (my_port);
1059 bu32 bit = 1 << DEC_PIN (my_port);
1060
1061 /* SIC only exists to forward interrupts from the system to the CEC. */
1062 switch (idx)
1063 {
1064 case 0: sic->bf54x.isr0 |= bit; break;
1065 case 1: sic->bf54x.isr1 |= bit; break;
1066 case 2: sic->bf54x.isr2 |= bit; break;
1067 }
1068
1069 /* XXX: Handle SIC wakeup source ?
1070 if (sic->bf54x.iwr0 & bit)
1071 What to do ?;
1072 if (sic->bf54x.iwr1 & bit)
1073 What to do ?;
1074 if (sic->bf54x.iwr2 & bit)
1075 What to do ?;
1076 */
1077
1078 bfin_sic_54x_forward_interrupts (me, sic);
1079 }
1080
1081 static const struct hw_port_descriptor bfin_sic_561_ports[] =
1082 {
1083 BFIN_SIC_TO_CEC_PORTS
1084 /* SIC0 */
1085 { "pll", ENC(0, 0), 0, input_port, },
1086 { "dmac@0_stat", ENC(0, 1), 0, input_port, },
1087 { "dmac@1_stat", ENC(0, 2), 0, input_port, },
1088 { "imdma_stat", ENC(0, 3), 0, input_port, },
1089 { "ppi@0", ENC(0, 4), 0, input_port, },
1090 { "ppi@1", ENC(0, 5), 0, input_port, },
1091 { "sport@0_stat", ENC(0, 6), 0, input_port, },
1092 { "sport@1_stat", ENC(0, 7), 0, input_port, },
1093 { "spi@0", ENC(0, 8), 0, input_port, },
1094 { "uart@0_stat", ENC(0, 9), 0, input_port, },
1095 /*{ "reserved", ENC(0, 10), 0, input_port, },*/
1096 { "dma@12", ENC(0, 11), 0, input_port, },
1097 { "dma@13", ENC(0, 12), 0, input_port, },
1098 { "dma@14", ENC(0, 13), 0, input_port, },
1099 { "dma@15", ENC(0, 14), 0, input_port, },
1100 { "dma@16", ENC(0, 15), 0, input_port, },
1101 { "dma@17", ENC(0, 16), 0, input_port, },
1102 { "dma@18", ENC(0, 17), 0, input_port, },
1103 { "dma@19", ENC(0, 18), 0, input_port, },
1104 { "dma@20", ENC(0, 19), 0, input_port, },
1105 { "dma@21", ENC(0, 20), 0, input_port, },
1106 { "dma@22", ENC(0, 21), 0, input_port, },
1107 { "dma@23", ENC(0, 22), 0, input_port, },
1108 { "dma@0", ENC(0, 23), 0, input_port, },
1109 { "dma@1", ENC(0, 24), 0, input_port, },
1110 { "dma@2", ENC(0, 25), 0, input_port, },
1111 { "dma@3", ENC(0, 26), 0, input_port, },
1112 { "dma@4", ENC(0, 27), 0, input_port, },
1113 { "dma@5", ENC(0, 28), 0, input_port, },
1114 { "dma@6", ENC(0, 29), 0, input_port, },
1115 { "dma@7", ENC(0, 30), 0, input_port, },
1116 { "dma@8", ENC(0, 31), 0, input_port, },
1117 /* SIC1 */
1118 { "dma@9", ENC(1, 0), 0, input_port, },
1119 { "dma@10", ENC(1, 1), 0, input_port, },
1120 { "dma@11", ENC(1, 2), 0, input_port, },
1121 { "gptimer@0", ENC(1, 3), 0, input_port, },
1122 { "gptimer@1", ENC(1, 4), 0, input_port, },
1123 { "gptimer@2", ENC(1, 5), 0, input_port, },
1124 { "gptimer@3", ENC(1, 6), 0, input_port, },
1125 { "gptimer@4", ENC(1, 7), 0, input_port, },
1126 { "gptimer@5", ENC(1, 8), 0, input_port, },
1127 { "gptimer@6", ENC(1, 9), 0, input_port, },
1128 { "gptimer@7", ENC(1, 10), 0, input_port, },
1129 { "gptimer@8", ENC(1, 11), 0, input_port, },
1130 { "gptimer@9", ENC(1, 12), 0, input_port, },
1131 { "gptimer@10", ENC(1, 13), 0, input_port, },
1132 { "gptimer@11", ENC(1, 14), 0, input_port, },
1133 { "portf_irq_a", ENC(1, 15), 0, input_port, },
1134 { "portf_irq_b", ENC(1, 16), 0, input_port, },
1135 { "portg_irq_a", ENC(1, 17), 0, input_port, },
1136 { "portg_irq_b", ENC(1, 18), 0, input_port, },
1137 { "porth_irq_a", ENC(1, 19), 0, input_port, },
1138 { "porth_irq_b", ENC(1, 20), 0, input_port, },
1139 { "mdma@0", ENC(1, 21), 0, input_port, },
1140 { "mdma@1", ENC(1, 22), 0, input_port, },
1141 { "mdma@2", ENC(1, 23), 0, input_port, },
1142 { "mdma@3", ENC(1, 24), 0, input_port, },
1143 { "imdma@0", ENC(1, 25), 0, input_port, },
1144 { "imdma@1", ENC(1, 26), 0, input_port, },
1145 { "wdog", ENC(1, 27), 0, input_port, },
1146 /*{ "reserved", ENC(1, 28), 0, input_port, },*/
1147 /*{ "reserved", ENC(1, 29), 0, input_port, },*/
1148 { "sup_irq_0", ENC(1, 30), 0, input_port, },
1149 { "sup_irq_1", ENC(1, 31), 0, input_port, },
1150 { NULL, 0, 0, 0, },
1151 };
1152
1153 static void
1154 bfin_sic_561_port_event (struct hw *me, int my_port, struct hw *source,
1155 int source_port, int level)
1156 {
1157 struct bfin_sic *sic = hw_data (me);
1158 bu32 idx = DEC_SIC (my_port);
1159 bu32 bit = 1 << DEC_PIN (my_port);
1160
1161 /* SIC only exists to forward interrupts from the system to the CEC. */
1162 switch (idx)
1163 {
1164 case 0: sic->bf561.isr0 |= bit; break;
1165 case 1: sic->bf561.isr1 |= bit; break;
1166 }
1167
1168 /* XXX: Handle SIC wakeup source ?
1169 if (sic->bf561.iwr0 & bit)
1170 What to do ?;
1171 if (sic->bf561.iwr1 & bit)
1172 What to do ?;
1173 */
1174
1175 bfin_sic_561_forward_interrupts (me, sic);
1176 }
1177
1178 static const struct hw_port_descriptor bfin_sic_59x_ports[] =
1179 {
1180 BFIN_SIC_TO_CEC_PORTS
1181 { "pll", ENC(0, 0), 0, input_port, },
1182 { "dma_stat", ENC(0, 1), 0, input_port, },
1183 { "ppi@0", ENC(0, 2), 0, input_port, },
1184 { "sport@0_stat", ENC(0, 3), 0, input_port, },
1185 { "sport@1_stat", ENC(0, 4), 0, input_port, },
1186 { "spi@0", ENC(0, 5), 0, input_port, },
1187 { "spi@1", ENC(0, 6), 0, input_port, },
1188 { "uart@0_stat", ENC(0, 7), 0, input_port, },
1189 { "dma@0", ENC(0, 8), 0, input_port, },
1190 { "dma@1", ENC(0, 9), 0, input_port, },
1191 { "dma@2", ENC(0, 10), 0, input_port, },
1192 { "dma@3", ENC(0, 11), 0, input_port, },
1193 { "dma@4", ENC(0, 12), 0, input_port, },
1194 { "dma@5", ENC(0, 13), 0, input_port, },
1195 { "dma@6", ENC(0, 14), 0, input_port, },
1196 { "dma@7", ENC(0, 15), 0, input_port, },
1197 { "dma@8", ENC(0, 16), 0, input_port, },
1198 { "portf_irq_a", ENC(0, 17), 0, input_port, },
1199 { "portf_irq_b", ENC(0, 18), 0, input_port, },
1200 { "gptimer@0", ENC(0, 19), 0, input_port, },
1201 { "gptimer@1", ENC(0, 20), 0, input_port, },
1202 { "gptimer@2", ENC(0, 21), 0, input_port, },
1203 { "portg_irq_a", ENC(0, 22), 0, input_port, },
1204 { "portg_irq_b", ENC(0, 23), 0, input_port, },
1205 { "twi@0", ENC(0, 24), 0, input_port, },
1206 /* XXX: 25 - 28 are supposed to be reserved; see comment in machs.c:bf592_dmac[] */
1207 { "dma@9", ENC(0, 25), 0, input_port, },
1208 { "dma@10", ENC(0, 26), 0, input_port, },
1209 { "dma@11", ENC(0, 27), 0, input_port, },
1210 { "dma@12", ENC(0, 28), 0, input_port, },
1211 /*{ "reserved", ENC(0, 25), 0, input_port, },*/
1212 /*{ "reserved", ENC(0, 26), 0, input_port, },*/
1213 /*{ "reserved", ENC(0, 27), 0, input_port, },*/
1214 /*{ "reserved", ENC(0, 28), 0, input_port, },*/
1215 { "mdma@0", ENC(0, 29), 0, input_port, },
1216 { "mdma@1", ENC(0, 30), 0, input_port, },
1217 { "wdog", ENC(0, 31), 0, input_port, },
1218 { NULL, 0, 0, 0, },
1219 };
1220
1221 static void
1222 attach_bfin_sic_regs (struct hw *me, struct bfin_sic *sic)
1223 {
1224 address_word attach_address;
1225 int attach_space;
1226 unsigned attach_size;
1227 reg_property_spec reg;
1228
1229 if (hw_find_property (me, "reg") == NULL)
1230 hw_abort (me, "Missing \"reg\" property");
1231
1232 if (!hw_find_reg_array_property (me, "reg", 0, &reg))
1233 hw_abort (me, "\"reg\" property must contain three addr/size entries");
1234
1235 hw_unit_address_to_attach_address (hw_parent (me),
1236 &reg.address,
1237 &attach_space, &attach_address, me);
1238 hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
1239
1240 if (attach_size != BFIN_MMR_SIC_SIZE)
1241 hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_SIC_SIZE);
1242
1243 hw_attach_address (hw_parent (me),
1244 0, attach_space, attach_address, attach_size, me);
1245
1246 sic->base = attach_address;
1247 }
1248
1249 static void
1250 bfin_sic_finish (struct hw *me)
1251 {
1252 struct bfin_sic *sic;
1253
1254 sic = HW_ZALLOC (me, struct bfin_sic);
1255
1256 set_hw_data (me, sic);
1257 attach_bfin_sic_regs (me, sic);
1258
1259 switch (hw_find_integer_property (me, "type"))
1260 {
1261 case 500 ... 509:
1262 set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer);
1263 set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer);
1264 set_hw_ports (me, bfin_sic_50x_ports);
1265 set_hw_port_event (me, bfin_sic_52x_port_event);
1266 mmr_names = bf52x_mmr_names;
1267
1268 /* Initialize the SIC. */
1269 sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
1270 sic->bf52x.isr0 = sic->bf52x.isr1 = 0;
1271 sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF;
1272 sic->bf52x.iar0 = 0x00000000;
1273 sic->bf52x.iar1 = 0x22111000;
1274 sic->bf52x.iar2 = 0x33332222;
1275 sic->bf52x.iar3 = 0x44444433;
1276 sic->bf52x.iar4 = 0x55555555;
1277 sic->bf52x.iar5 = 0x06666655;
1278 sic->bf52x.iar6 = 0x33333003;
1279 sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */
1280 break;
1281 case 510 ... 519:
1282 set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer);
1283 set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer);
1284 set_hw_ports (me, bfin_sic_51x_ports);
1285 set_hw_port_event (me, bfin_sic_52x_port_event);
1286 mmr_names = bf52x_mmr_names;
1287
1288 /* Initialize the SIC. */
1289 sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
1290 sic->bf52x.isr0 = sic->bf52x.isr1 = 0;
1291 sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF;
1292 sic->bf52x.iar0 = 0x00000000;
1293 sic->bf52x.iar1 = 0x11000000;
1294 sic->bf52x.iar2 = 0x33332222;
1295 sic->bf52x.iar3 = 0x44444433;
1296 sic->bf52x.iar4 = 0x55555555;
1297 sic->bf52x.iar5 = 0x06666655;
1298 sic->bf52x.iar6 = 0x33333000;
1299 sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */
1300 break;
1301 case 522 ... 527:
1302 set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer);
1303 set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer);
1304 set_hw_ports (me, bfin_sic_52x_ports);
1305 set_hw_port_event (me, bfin_sic_52x_port_event);
1306 mmr_names = bf52x_mmr_names;
1307
1308 /* Initialize the SIC. */
1309 sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
1310 sic->bf52x.isr0 = sic->bf52x.isr1 = 0;
1311 sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF;
1312 sic->bf52x.iar0 = 0x00000000;
1313 sic->bf52x.iar1 = 0x11000000;
1314 sic->bf52x.iar2 = 0x33332222;
1315 sic->bf52x.iar3 = 0x44444433;
1316 sic->bf52x.iar4 = 0x55555555;
1317 sic->bf52x.iar5 = 0x06666655;
1318 sic->bf52x.iar6 = 0x33333000;
1319 sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */
1320 break;
1321 case 531 ... 533:
1322 set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer);
1323 set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer);
1324 set_hw_ports (me, bfin_sic_533_ports);
1325 set_hw_port_event (me, bfin_sic_537_port_event);
1326 mmr_names = bf537_mmr_names;
1327
1328 /* Initialize the SIC. */
1329 sic->bf537.imask = 0;
1330 sic->bf537.isr = 0;
1331 sic->bf537.iwr = 0xFFFFFFFF;
1332 sic->bf537.iar0 = 0x10000000;
1333 sic->bf537.iar1 = 0x33322221;
1334 sic->bf537.iar2 = 0x66655444;
1335 sic->bf537.iar3 = 0; /* XXX: fix this */
1336 break;
1337 case 534:
1338 case 536:
1339 case 537:
1340 set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer);
1341 set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer);
1342 set_hw_ports (me, bfin_sic_537_ports);
1343 set_hw_port_event (me, bfin_sic_537_port_event);
1344 mmr_names = bf537_mmr_names;
1345
1346 /* Initialize the SIC. */
1347 sic->bf537.imask = 0;
1348 sic->bf537.isr = 0;
1349 sic->bf537.iwr = 0xFFFFFFFF;
1350 sic->bf537.iar0 = 0x22211000;
1351 sic->bf537.iar1 = 0x43333332;
1352 sic->bf537.iar2 = 0x55555444;
1353 sic->bf537.iar3 = 0x66655555;
1354 break;
1355 case 538 ... 539:
1356 set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer);
1357 set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer);
1358 set_hw_ports (me, bfin_sic_538_ports);
1359 set_hw_port_event (me, bfin_sic_52x_port_event);
1360 mmr_names = bf52x_mmr_names;
1361
1362 /* Initialize the SIC. */
1363 sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
1364 sic->bf52x.isr0 = sic->bf52x.isr1 = 0;
1365 sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF;
1366 sic->bf52x.iar0 = 0x10000000;
1367 sic->bf52x.iar1 = 0x33322221;
1368 sic->bf52x.iar2 = 0x66655444;
1369 sic->bf52x.iar3 = 0x00000000;
1370 sic->bf52x.iar4 = 0x32222220;
1371 sic->bf52x.iar5 = 0x44433333;
1372 sic->bf52x.iar6 = 0x00444664;
1373 sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */
1374 break;
1375 case 540 ... 549:
1376 set_hw_io_read_buffer (me, bfin_sic_54x_io_read_buffer);
1377 set_hw_io_write_buffer (me, bfin_sic_54x_io_write_buffer);
1378 set_hw_ports (me, bfin_sic_54x_ports);
1379 set_hw_port_event (me, bfin_sic_54x_port_event);
1380 mmr_names = bf54x_mmr_names;
1381
1382 /* Initialize the SIC. */
1383 sic->bf54x.imask0 = sic->bf54x.imask1 = sic->bf54x.imask2 = 0;
1384 sic->bf54x.isr0 = sic->bf54x.isr1 = sic->bf54x.isr2 = 0;
1385 sic->bf54x.iwr0 = sic->bf54x.iwr1 = sic->bf54x.iwr1 = 0xFFFFFFFF;
1386 sic->bf54x.iar0 = 0x10000000;
1387 sic->bf54x.iar1 = 0x33322221;
1388 sic->bf54x.iar2 = 0x66655444;
1389 sic->bf54x.iar3 = 0x00000000;
1390 sic->bf54x.iar4 = 0x32222220;
1391 sic->bf54x.iar5 = 0x44433333;
1392 sic->bf54x.iar6 = 0x00444664;
1393 sic->bf54x.iar7 = 0x00000000;
1394 sic->bf54x.iar8 = 0x44111111;
1395 sic->bf54x.iar9 = 0x44444444;
1396 sic->bf54x.iar10 = 0x44444444;
1397 sic->bf54x.iar11 = 0x55444444;
1398 break;
1399 case 561:
1400 set_hw_io_read_buffer (me, bfin_sic_561_io_read_buffer);
1401 set_hw_io_write_buffer (me, bfin_sic_561_io_write_buffer);
1402 set_hw_ports (me, bfin_sic_561_ports);
1403 set_hw_port_event (me, bfin_sic_561_port_event);
1404 mmr_names = bf561_mmr_names;
1405
1406 /* Initialize the SIC. */
1407 sic->bf561.imask0 = sic->bf561.imask1 = 0;
1408 sic->bf561.isr0 = sic->bf561.isr1 = 0;
1409 sic->bf561.iwr0 = sic->bf561.iwr1 = 0xFFFFFFFF;
1410 sic->bf561.iar0 = 0x00000000;
1411 sic->bf561.iar1 = 0x11111000;
1412 sic->bf561.iar2 = 0x21111111;
1413 sic->bf561.iar3 = 0x22222222;
1414 sic->bf561.iar4 = 0x33333222;
1415 sic->bf561.iar5 = 0x43333333;
1416 sic->bf561.iar6 = 0x21144444;
1417 sic->bf561.iar7 = 0x00006552;
1418 break;
1419 case 590 ... 599:
1420 set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer);
1421 set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer);
1422 set_hw_ports (me, bfin_sic_59x_ports);
1423 set_hw_port_event (me, bfin_sic_537_port_event);
1424 mmr_names = bf537_mmr_names;
1425
1426 /* Initialize the SIC. */
1427 sic->bf537.imask = 0;
1428 sic->bf537.isr = 0;
1429 sic->bf537.iwr = 0xFFFFFFFF;
1430 sic->bf537.iar0 = 0x00000000;
1431 sic->bf537.iar1 = 0x33322221;
1432 sic->bf537.iar2 = 0x55444443;
1433 sic->bf537.iar3 = 0x66600005;
1434 break;
1435 default:
1436 hw_abort (me, "no support for SIC on this Blackfin model yet");
1437 }
1438 }
1439
1440 const struct hw_descriptor dv_bfin_sic_descriptor[] =
1441 {
1442 {"bfin_sic", bfin_sic_finish,},
1443 {NULL, NULL},
1444 };
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