sim/bfin/dv-bfin_spi.c

   1 /* Blackfin Serial Peripheral Interface (SPI) model
   2
   3    Copyright (C) 2010-2011 Free Software Foundation, Inc.
   4    Contributed by Analog Devices, Inc.
   5
   6    This file is part of simulators.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "config.h"
  22
  23 #include "sim-main.h"
  24 #include "devices.h"
  25 #include "dv-bfin_spi.h"
  26
  27 /* XXX: This is merely a stub.  */
  28
  29 struct bfin_spi
  30 {
  31   /* This top portion matches common dv_bfin struct.  */
  32   bu32 base;
  33   struct hw *dma_master;
  34   bool acked;
  35
  36   struct hw_event *handler;
  37   char saved_byte;
  38   int saved_count;
  39
  40   /* Order after here is important -- matches hardware MMR layout.  */
  41   bu16 BFIN_MMR_16(ctl);
  42   bu16 BFIN_MMR_16(flg);
  43   bu16 BFIN_MMR_16(stat);
  44   bu16 BFIN_MMR_16(tdbr);
  45   bu16 BFIN_MMR_16(rdbr);
  46   bu16 BFIN_MMR_16(baud);
  47   bu16 BFIN_MMR_16(shadow);
  48 };
  49 #define mmr_base()      offsetof(struct bfin_spi, ctl)
  50 #define mmr_offset(mmr) (offsetof(struct bfin_spi, mmr) - mmr_base())
  51
  52 static const char * const mmr_names[] = {
  53   "SPI_CTL", "SPI_FLG", "SPI_STAT", "SPI_TDBR",
  54   "SPI_RDBR", "SPI_BAUD", "SPI_SHADOW",
  55 };
  56 #define mmr_name(off) mmr_names[(off) / 4]
  57
  58 static bool
  59 bfin_spi_enabled (struct bfin_spi *spi)
  60 {
  61   return (spi->ctl & SPE);
  62 }
  63
  64 static bu16
  65 bfin_spi_timod (struct bfin_spi *spi)
  66 {
  67   return (spi->ctl & TIMOD);
  68 }
  69
  70 static unsigned
  71 bfin_spi_io_write_buffer (struct hw *me, const void *source, int space,
  72                           address_word addr, unsigned nr_bytes)
  73 {
  74   struct bfin_spi *spi = hw_data (me);
  75   bu32 mmr_off;
  76   bu32 value;
  77   bu16 *valuep;
  78
  79   value = dv_load_2 (source);
  80   mmr_off = addr - spi->base;
  81   valuep = (void *)((unsigned long)spi + mmr_base() + mmr_off);
  82
  83   HW_TRACE_WRITE ();
  84
  85   dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
  86
  87   switch (mmr_off)
  88     {
  89     case mmr_offset(stat):
  90       dv_w1c_2 (valuep, value, SPIF | TXS | RXS);
  91       break;
  92     case mmr_offset(tdbr):
  93       *valuep = value;
  94       if (bfin_spi_enabled (spi) && bfin_spi_timod (spi) == TDBR_CORE)
  95         {
  96           spi->stat |= RXS;
  97           spi->stat &= ~TXS;
  98         }
  99       break;
 100     case mmr_offset(rdbr):
 101     case mmr_offset(ctl):
 102     case mmr_offset(flg):
 103     case mmr_offset(baud):
 104     case mmr_offset(shadow):
 105       *valuep = value;
 106       break;
 107     default:
 108       dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
 109       break;
 110     }
 111
 112   return nr_bytes;
 113 }
 114
 115 static unsigned
 116 bfin_spi_io_read_buffer (struct hw *me, void *dest, int space,
 117                          address_word addr, unsigned nr_bytes)
 118 {
 119   struct bfin_spi *spi = hw_data (me);
 120   bu32 mmr_off;
 121   bu16 *valuep;
 122
 123   mmr_off = addr - spi->base;
 124   valuep = (void *)((unsigned long)spi + mmr_base() + mmr_off);
 125
 126   HW_TRACE_READ ();
 127
 128   dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
 129
 130   switch (mmr_off)
 131     {
 132     case mmr_offset(rdbr):
 133       dv_store_2 (dest, *valuep);
 134       if (bfin_spi_enabled (spi) && bfin_spi_timod (spi) == RDBR_CORE)
 135         spi->stat &= ~(RXS | TXS);
 136       break;
 137     case mmr_offset(ctl):
 138     case mmr_offset(stat):
 139     case mmr_offset(flg):
 140     case mmr_offset(tdbr):
 141     case mmr_offset(baud):
 142     case mmr_offset(shadow):
 143       dv_store_2 (dest, *valuep);
 144       break;
 145     default:
 146       dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
 147       break;
 148     }
 149
 150   return nr_bytes;
 151 }
 152
 153 static unsigned
 154 bfin_spi_dma_read_buffer (struct hw *me, void *dest, int space,
 155                           unsigned_word addr, unsigned nr_bytes)
 156 {
 157   HW_TRACE_DMA_READ ();
 158   return 0;
 159 }
 160
 161 static unsigned
 162 bfin_spi_dma_write_buffer (struct hw *me, const void *source,
 163                            int space, unsigned_word addr,
 164                            unsigned nr_bytes,
 165                            int violate_read_only_section)
 166 {
 167   HW_TRACE_DMA_WRITE ();
 168   return 0;
 169 }
 170
 171 static const struct hw_port_descriptor bfin_spi_ports[] = {
 172   { "stat", 0, 0, output_port, },
 173   { NULL, 0, 0, 0, },
 174 };
 175
 176 static void
 177 attach_bfin_spi_regs (struct hw *me, struct bfin_spi *spi)
 178 {
 179   address_word attach_address;
 180   int attach_space;
 181   unsigned attach_size;
 182   reg_property_spec reg;
 183
 184   if (hw_find_property (me, "reg") == NULL)
 185     hw_abort (me, "Missing \"reg\" property");
 186
 187   if (!hw_find_reg_array_property (me, "reg", 0, &reg))
 188     hw_abort (me, "\"reg\" property must contain three addr/size entries");
 189
 190   hw_unit_address_to_attach_address (hw_parent (me),
 191                                      &reg.address,
 192                                      &attach_space, &attach_address, me);
 193   hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
 194
 195   if (attach_size != BFIN_MMR_SPI_SIZE)
 196     hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_SPI_SIZE);
 197
 198   hw_attach_address (hw_parent (me),
 199                      0, attach_space, attach_address, attach_size, me);
 200
 201   spi->base = attach_address;
 202 }
 203
 204 static void
 205 bfin_spi_finish (struct hw *me)
 206 {
 207   struct bfin_spi *spi;
 208
 209   spi = HW_ZALLOC (me, struct bfin_spi);
 210
 211   set_hw_data (me, spi);
 212   set_hw_io_read_buffer (me, bfin_spi_io_read_buffer);
 213   set_hw_io_write_buffer (me, bfin_spi_io_write_buffer);
 214   set_hw_dma_read_buffer (me, bfin_spi_dma_read_buffer);
 215   set_hw_dma_write_buffer (me, bfin_spi_dma_write_buffer);
 216   set_hw_ports (me, bfin_spi_ports);
 217
 218   attach_bfin_spi_regs (me, spi);
 219
 220   /* Initialize the SPI.  */
 221   spi->ctl  = 0x0400;
 222   spi->flg  = 0xFF00;
 223   spi->stat = 0x0001;
 224 }
 225
 226 const struct hw_descriptor dv_bfin_spi_descriptor[] = {
 227   {"bfin_spi", bfin_spi_finish,},
 228   {NULL, NULL},
 229 };