sim/common/cgen-sim.h

   1 /* Simulator header for Cpu tools GENerated simulators.
   2    Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef CGEN_SIM_H
  22 #define CGEN_SIM_H
  23
  24 /* Instruction field support macros.  */
  25
  26 #define EXTRACT_SIGNED(val, total, start, length) \
  27 (((((val) >> ((total) - ((start) + (length)))) & ((1 << (length)) - 1)) \
  28   ^ (1 << ((length) - 1))) \
  29  - (1 << ((length) - 1)))
  30
  31 #define EXTRACT_UNSIGNED(val, total, start, length) \
  32 (((val) >> ((total) - ((start) + (length)))) & ((1 << (length)) - 1))
  33
  34 /* Compute number of longs required to hold N bits.  */
  35 #define HOST_LONGS_FOR_BITS(n) \
  36   (((n) + sizeof (long) * 8 - 1) / sizeof (long) * 8)
  37 \f
  38 /* Forward decls.  Defined in the machine generated files.  */
  39
  40 /* This holds the contents of the extracted insn.
  41    There are a few common entries (e.g. pc address), and then one big
  42    union with an entry for each of the instruction formats.  */
  43 typedef struct argbuf ARGBUF;
  44
  45 /* This is one ARGBUF plus whatever else is needed for WITH_SCACHE support.
  46    At present there is nothing else, but it also provides a level of
  47    abstraction.  */
  48 typedef struct scache SCACHE;
  49
  50 /* This is a union with one entry for each instruction format.
  51    Each entry contains all of the non-constant inputs of the instruction.  */
  52 typedef struct parexec PAREXEC;
  53
  54 /* An "Instruction DESCriptor".
  55    This is the main handle on an instruction for the simulator.  */
  56 typedef struct idesc IDESC;
  57 \f
  58 /* Engine support.
  59    ??? This is here because it's needed before eng.h (built by genmloop.sh)
  60    which is needed before cgen-engine.h and cpu.h.
  61    ??? This depends on a cpu family specific type, PCADDR, but no machine
  62    generated headers will have been included yet.  sim/common currently
  63    requires the typedef of sim_cia in sim-main.h between the inclusion of
  64    sim-basics.h and sim-base.h so this is no different.  */
  65
  66 #if WITH_SCACHE
  67
  68 /* instruction address
  69    ??? This was intended to be a struct of two elements in the WITH_SCACHE_PBB
  70    case.  The first element is the PCADDR, the second element is the SCACHE *.
  71    Haven't found the time yet to make this work, but it is a nicer approach
  72    than the current br_cache stuff.  */
  73 typedef PCADDR IADDR;
  74 /* current instruction address */
  75 typedef PCADDR CIA;
  76 /* argument to semantic functions */
  77 typedef SCACHE *SEM_ARG;
  78 /* semantic code's version of pc */
  79 #if WITH_SCACHE_PBB
  80 typedef SCACHE *SEM_PC;
  81 #else
  82 typedef PCADDR SEM_PC;
  83 #endif
  84
  85 #else /* ! WITH_SCACHE */
  86
  87 /* instruction address */
  88 typedef PCADDR IADDR;
  89 /* current instruction address */
  90 typedef PCADDR CIA;
  91 /* argument to semantic functions */
  92 typedef ARGBUF *SEM_ARG;
  93 /* semantic code's version of pc */
  94 typedef PCADDR SEM_PC;
  95
  96 #endif /* ! WITH_SCACHE */
  97 \f
  98 /* Additional opcode table support.  */
  99
 100 /* Opcode table for virtual insns (only used by the simulator).  */
 101 extern const struct cgen_insn cgen_virtual_opcode_table[];
 102
 103 /* -ve of indices of virtual insns in cgen_virtual_opcode_table.  */
 104 typedef enum {
 105   VIRTUAL_INSN_X_INVALID = 0,
 106   VIRTUAL_INSN_X_BEFORE = -1, VIRTUAL_INSN_X_AFTER = -2,
 107   VIRTUAL_INSN_X_BEGIN = -3,
 108   VIRTUAL_INSN_X_CHAIN= -4, VIRTUAL_INSN_X_CTI_CHAIN = -5
 109 } CGEN_INSN_VIRTUAL_TYPE;
 110
 111 /* Return non-zero if OPCODE is a virtual insn.  */
 112 #define CGEN_INSN_VIRTUAL_P(opcode) \
 113   CGEN_INSN_ATTR ((opcode), CGEN_INSN_VIRTUAL)
 114 \f
 115 /* GNU C's "computed goto" facility is used to speed things up where
 116    possible.  These macros provide a portable way to use them.
 117    Nesting of these switch statements is done by providing an extra argument
 118    that distinguishes them.  `N' can be a number or symbol.
 119    Variable `labels_##N' must be initialized with the labels of each case.  */
 120
 121 #ifdef __GNUC__
 122 #define SWITCH(N, X) goto *X;
 123 #define CASE(N, X) case_##N##_##X
 124 #define BREAK(N) goto end_switch_##N
 125 #define DEFAULT(N) default_##N
 126 #define ENDSWITCH(N) end_switch_##N:
 127 #else
 128 #define SWITCH(N, X) switch (X)
 129 #define CASE(N, X) case X /* FIXME: old sem-switch had (@arch@_,X) here */
 130 #define BREAK(N) break
 131 #define DEFAULT(N) default
 132 #define ENDSWITCH(N)
 133 #endif
 134 \f
 135 /* Simulator state.  */
 136
 137 /* Records simulator descriptor so utilities like @cpu@_dump_regs can be
 138    called from gdb.  */
 139 extern SIM_DESC current_state;
 140
 141 /* Simulator state.  */
 142
 143 /* CGEN_STATE contains additional state information not present in
 144    sim_state_base.  */
 145
 146 typedef struct cgen_state {
 147   /* FIXME: Moved to sim_state_base.  */
 148   /* argv, env */
 149   char **argv;
 150 #define STATE_ARGV(s) ((s) -> cgen_state.argv)
 151   /* FIXME: Move to sim_state_base.  */
 152   char **envp;
 153 #define STATE_ENVP(s) ((s) -> cgen_state.envp)
 154
 155   /* Non-zero if no tracing or profiling is selected.  */
 156   int run_fast_p;
 157 #define STATE_RUN_FAST_P(sd) ((sd) -> cgen_state.run_fast_p)
 158
 159   /* Opcode table.  */
 160   CGEN_OPCODE_DESC opcode_table;
 161 #define STATE_OPCODE_TABLE(sd) ((sd) -> cgen_state.opcode_table)
 162 } CGEN_STATE;
 163 \f
 164 /* Various utilities.  */
 165
 166 /* Called after sim_post_argv_init to do any cgen initialization.  */
 167 extern void cgen_init (SIM_DESC);
 168
 169 /* Return the name of an insn.  */
 170 extern CPU_INSN_NAME_FN cgen_insn_name;
 171
 172 /* Return the maximum number of extra bytes required for a sim_cpu struct.  */
 173 /* ??? Ok, yes, this is less pretty than it should be.  Give me a better
 174    language [or suggest a better way].  */
 175 extern int cgen_cpu_max_extra_bytes (void);
 176
 177 extern void
 178 sim_disassemble_insn (SIM_CPU *, const CGEN_INSN *,
 179                       const struct argbuf *, PCADDR, char *);
 180
 181 /* Called to process an invalid instruction.  */
 182 extern void sim_engine_invalid_insn (SIM_CPU *, PCADDR);
 183
 184 #endif /* CGEN_SIM_H */