1 /* This file is part of the program psim.
3 Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 #ifndef _PSIM_CONFIG_H_
23 #define _PSIM_CONFIG_H_
26 /* endianness of the host/target:
28 If the build process is aware (at compile time) of the endianness
29 of the host/target it is able to eliminate slower generic endian
32 Possible values are 0 (unknown), LITTLE_ENDIAN, BIG_ENDIAN */
34 #ifndef WITH_HOST_BYTE_ORDER
35 #define WITH_HOST_BYTE_ORDER 0 /*unknown*/
38 #ifndef WITH_TARGET_BYTE_ORDER
39 #define WITH_TARGET_BYTE_ORDER 0 /*unknown*/
42 extern int current_host_byte_order
;
43 #define CURRENT_HOST_BYTE_ORDER (WITH_HOST_BYTE_ORDER \
44 ? WITH_HOST_BYTE_ORDER \
45 : current_host_byte_order)
46 extern int current_target_byte_order
;
47 #define CURRENT_TARGET_BYTE_ORDER (WITH_TARGET_BYTE_ORDER \
48 ? WITH_TARGET_BYTE_ORDER \
49 : current_target_byte_order)
55 In addition to the above, the simulator can support the's horrible
56 XOR endian mode (for instance implemented by the PowerPC). This
57 feature makes it possible to control the endian mode of a processor
60 /* #define WITH_XOR_ENDIAN 8 */
64 /* Intel host BSWAP support:
66 Whether to use bswap on the 486 and pentiums rather than the 386
67 sequence that uses xchgb/rorl/xchgb */
76 Sets a limit on the number of processors that can be simulated. If
77 WITH_SMP is set to zero (0), the simulator is restricted to
78 suporting only on processor (and as a consequence leaves the SMP
79 code out of the build process).
81 The actual number of processors is taken from the device
82 /options/smp@<nr-cpu> */
84 #if defined (WITH_SMP)
87 #define MAX_NR_PROCESSORS WITH_SMP
89 #define MAX_NR_PROCESSORS 1
96 /* Word size of host/target:
98 Set these according to your host and target requirements. At this
99 point in time, I've only compiled (not run) for a 64bit and never
100 built for a 64bit host. This will always remain a compile time
103 #ifndef WITH_TARGET_WORD_BITSIZE
104 #define WITH_TARGET_WORD_BITSIZE 32 /* compiled only */
107 #ifndef WITH_HOST_WORD_BITSIZE
108 #define WITH_HOST_WORD_BITSIZE 32 /* 64bit ready? */
113 /* Program environment:
115 Three environments are available - UEA (user), VEA (virtual) and
116 OEA (perating). The former two are environment that users would
117 expect to see (VEA includes things like coherency and the time
118 base) while OEA is what an operating system expects to see. By
119 setting these to specific values, the build process is able to
120 eliminate non relevent environment code
122 CURRENT_ENVIRONMENT specifies which of vea or oea is required for
123 the current runtime. */
125 #if defined (WITH_ENVIRONMENT)
127 #define USER_ENVIRONMENT 1
128 #define VIRTUAL_ENVIRONMENT 2
129 #define OPERATING_ENVIRONMENT 3
131 extern int current_environment
;
132 #define CURRENT_ENVIRONMENT (WITH_ENVIRONMENT \
134 : current_environment)
140 /* Callback/Default Memory.
142 Core includes a builtin memory type (raw_memory) that is
143 implemented using an array. raw_memory does not require any
144 additional functions etc.
146 Callback memory is where the core calls a core device for the data
149 Default memory is an extenstion of this where for addresses that do
150 not map into either a callback or core memory range a default map
153 The OEA model uses callback memory for devices and default memory
156 The VEA model uses callback memory to capture `page faults'.
158 While it may be possible to eliminate callback/default memory (and
159 hence also eliminate an additional test per memory fetch) it
160 probably is not worth the effort.
162 BTW, while raw_memory could have been implemented as a callback,
163 profiling has shown that there is a biger win (at least for the
164 x86) in eliminating a function call for the most common
165 (raw_memory) case. */
167 #ifndef WITH_CALLBACK_MEMORY
168 #define WITH_CALLBACK_MEMORY 1
175 The PowerPC may or may not handle miss aligned transfers. An
176 implementation normally handles miss aligned transfers in big
177 endian mode but generates an exception in little endian mode.
179 This model. Instead allows both little and big endian modes to
180 either take exceptions or handle miss aligned transfers.
182 If 0 is specified then for big-endian mode miss alligned accesses
183 are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the
184 processor will fault on them (STRICT_ALIGNMENT). */
186 #if defined (WITH_ALIGNMENT)
188 #define NONSTRICT_ALIGNMENT 1
189 #define STRICT_ALIGNMENT 2
191 extern int current_alignment
;
192 #define CURRENT_ALIGNMENT (WITH_ALIGNMENT \
200 /* Floating point suport:
202 Should the processor trap for all floating point instructions (as
203 if the hardware wasn't implemented) or implement the floating point
204 instructions directly. */
206 #if defined (WITH_FLOATING_POINT)
208 #define SOFT_FLOATING_POINT 1
209 #define HARD_FLOATING_POINT 2
211 extern int current_floating_point
;
212 #define CURRENT_FLOATING_POINT (WITH_FLOATING_POINT \
213 ? WITH_FLOATING_POINT \
214 : current_floating_point)
222 Control the inclusion of debugging code. */
224 /* Include the tracing code. Disabling this eliminates all tracing
232 /* include code that checks assertions scattered through out the
236 #define WITH_ASSERT 1
240 /* Whether to check instructions for reserved bits being set */
242 /* #define WITH_RESERVED_BITS 1 */
246 /* include monitoring code */
248 #define MONITOR_INSTRUCTION_ISSUE 1
249 #define MONITOR_LOAD_STORE_UNIT 2
250 /* do not define WITH_MON by default */
251 #define DEFAULT_WITH_MON (MONITOR_LOAD_STORE_UNIT \
252 | MONITOR_INSTRUCTION_ISSUE)
255 /* Current CPU model (models are in the generated models.h include file) */
260 #define CURRENT_MODEL (WITH_MODEL \
264 #ifndef WITH_DEFAULT_MODEL
265 #define WITH_DEFAULT_MODEL DEFAULT_MODEL
268 #define MODEL_ISSUE_IGNORE (-1)
269 #define MODEL_ISSUE_PROCESS 1
271 #ifndef WITH_MODEL_ISSUE
272 #define WITH_MODEL_ISSUE 0
275 extern int current_model_issue
;
276 #define CURRENT_MODEL_ISSUE (WITH_MODEL_ISSUE \
278 : current_model_issue)
282 /* Whether or not input/output just uses stdio, or uses printf_filtered for
283 output, and polling input for input. */
285 #define DONT_USE_STDIO 2
286 #define DO_USE_STDIO 1
292 extern int current_stdio
;
293 #define CURRENT_STDIO (WITH_STDIO \
299 /* Specify that configured calls pass parameters in registers when the
300 convention is that they are placed on the stack */
303 #define WITH_REGPARM 0
306 /* Specify that configured calls use an alternative calling mechanism */
309 #define WITH_STDCALL 0
313 /* complete/verify/print the simulator configuration */
316 /* For prefered_target_byte_order arugment */
318 #if defined (bfd_little_endian)
319 #define PREFERED_TARGET_BYTE_ORDER(IMAGE) ((IMAGE) == NULL \
321 : bfd_little_endian(IMAGE) \
325 #define PREFERED_TARGET_BYTE_ORDER(IMAGE) ((IMAGE) == NULL \
327 : !(IMAGE)->xvec->byteorder_big_p \
333 extern void sim_config (SIM_DESC sd
,
334 int prefered_target_byte_order
);
336 extern void print_sim_config (SIM_DESC sd
);
339 #endif /* _PSIM_CONFIG_H */