sim/common/sim-core.c

   1 /*  This file is part of the program psim.
   2
   3     Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18
  19     */
  20
  21
  22 #ifndef _SIM_CORE_C_
  23 #define _SIM_CORE_C_
  24
  25 #include "libiberty.h"
  26 #include "sim-main.h"
  27 #include "sim-assert.h"
  28
  29 /* "core" module install handler.
  30
  31    This is called via sim_module_install to install the "core" subsystem
  32    into the simulator.  */
  33
  34 static MODULE_INIT_FN sim_core_init;
  35 static MODULE_UNINSTALL_FN sim_core_uninstall;
  36
  37 #if (WITH_DEVICES)
  38 /* TODO: create sim/common/device.h */
  39 void device_error (device *me, char* message, ...);
  40 int device_io_read_buffer(device *me, void *dest, int space, address_word addr, unsigned nr_bytes, sim_cpu *processor, sim_cia cia);
  41 int device_io_write_buffer(device *me, const void *source, int space, address_word addr, unsigned nr_bytes, sim_cpu *processor, sim_cia cia);
  42 #endif
  43
  44 EXTERN_SIM_CORE\
  45 (SIM_RC)
  46 sim_core_install (SIM_DESC sd)
  47 {
  48   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
  49
  50   /* establish the other handlers */
  51   sim_module_add_uninstall_fn (sd, sim_core_uninstall);
  52   sim_module_add_init_fn (sd, sim_core_init);
  53
  54   /* establish any initial data structures - none */
  55   return SIM_RC_OK;
  56 }
  57
  58
  59 /* Uninstall the "core" subsystem from the simulator.  */
  60
  61 STATIC_SIM_CORE\
  62 (void)
  63 sim_core_uninstall (SIM_DESC sd)
  64 {
  65   sim_core *core = STATE_CORE(sd);
  66   sim_core_maps map;
  67   /* blow away any mappings */
  68   for (map = 0; map < nr_sim_core_maps; map++) {
  69     sim_core_mapping *curr = core->common.map[map].first;
  70     while (curr != NULL) {
  71       sim_core_mapping *tbd = curr;
  72       curr = curr->next;
  73       if (tbd->free_buffer != NULL) {
  74         SIM_ASSERT(tbd->buffer != NULL);
  75         zfree(tbd->free_buffer);
  76       }
  77       zfree(tbd);
  78     }
  79     core->common.map[map].first = NULL;
  80   }
  81 }
  82
  83
  84 STATIC_SIM_CORE\
  85 (SIM_RC)
  86 sim_core_init (SIM_DESC sd)
  87 {
  88   /* Nothing to do */
  89   return SIM_RC_OK;
  90 }
  91
  92
  93
  94 #ifndef SIM_CORE_SIGNAL
  95 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
  96 sim_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
  97
  98 STATIC_SIM_CORE\
  99 (void)
 100 sim_core_signal (SIM_DESC sd,
 101                  sim_cpu *cpu,
 102                  sim_cia cia,
 103                  sim_core_maps map,
 104                  int nr_bytes,
 105                  address_word addr,
 106                  transfer_type transfer,
 107                  sim_core_signals sig)
 108 {
 109   const char *copy = (transfer == read_transfer ? "read" : "write");
 110   address_word ip = CIA_ADDR (cia);
 111   switch (sig)
 112     {
 113     case sim_core_unmapped_signal:
 114       sim_io_eprintf (sd, "core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
 115                       nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);
 116       sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGSEGV);
 117       break;
 118     case sim_core_unaligned_signal:
 119       sim_io_eprintf (sd, "core: %d byte misaligned %s to address 0x%lx at 0x%lx\n",
 120                       nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);
 121       sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGBUS);
 122       break;
 123     default:
 124       sim_engine_abort (sd, cpu, cia,
 125                         "sim_core_signal - internal error - bad switch");
 126     }
 127 }
 128 #endif
 129
 130
 131 EXTERN_SIM_CORE\
 132 (const char *)
 133 sim_core_map_to_str (sim_core_maps map)
 134 {
 135   switch (map)
 136     {
 137     case sim_core_read_map: return "read";
 138     case sim_core_write_map: return "write";
 139     case sim_core_execute_map: return "exec";
 140     default: return "(invalid-map)";
 141     }
 142 }
 143
 144
 145 STATIC_SIM_CORE\
 146 (sim_core_mapping *)
 147 new_sim_core_mapping (SIM_DESC sd,
 148                       int level,
 149                       int space,
 150                       address_word addr,
 151                       address_word nr_bytes,
 152                       unsigned modulo,
 153                       device *device,
 154                       void *buffer,
 155                       void *free_buffer)
 156 {
 157   sim_core_mapping *new_mapping = ZALLOC(sim_core_mapping);
 158   /* common */
 159   new_mapping->level = level;
 160   new_mapping->space = space;
 161   new_mapping->base = addr;
 162   new_mapping->nr_bytes = nr_bytes;
 163   new_mapping->bound = addr + (nr_bytes - 1);
 164   if (modulo == 0)
 165     new_mapping->mask = (unsigned) 0 - 1;
 166   else
 167     new_mapping->mask = modulo - 1;
 168   new_mapping->buffer = buffer;
 169   new_mapping->free_buffer = free_buffer;
 170   new_mapping->device = device;
 171   return new_mapping;
 172 }
 173
 174
 175 STATIC_SIM_CORE\
 176 (void)
 177 sim_core_map_attach (SIM_DESC sd,
 178                      sim_core_map *access_map,
 179                      int level,
 180                      int space,
 181                      address_word addr,
 182                      address_word nr_bytes,
 183                      unsigned modulo,
 184                      device *client, /*callback/default*/
 185                      void *buffer, /*raw_memory*/
 186                      void *free_buffer) /*raw_memory*/
 187 {
 188   /* find the insertion point for this additional mapping and then
 189      insert */
 190   sim_core_mapping *next_mapping;
 191   sim_core_mapping **last_mapping;
 192
 193   SIM_ASSERT ((client == NULL) != (buffer == NULL));
 194   SIM_ASSERT ((client == NULL) >= (free_buffer != NULL));
 195
 196   /* actually do occasionally get a zero size map */
 197   if (nr_bytes == 0)
 198     {
 199 #if (WITH_DEVICES)
 200       device_error(client, "called on sim_core_map_attach with size zero");
 201 #else
 202       sim_io_error (sd, "called on sim_core_map_attach with size zero");
 203 #endif
 204     }
 205
 206   /* find the insertion point (between last/next) */
 207   next_mapping = access_map->first;
 208   last_mapping = &access_map->first;
 209   while(next_mapping != NULL
 210         && (next_mapping->level < level
 211             || (next_mapping->level == level
 212                 && next_mapping->bound < addr)))
 213     {
 214       /* provided levels are the same */
 215       /* assert: next_mapping->base > all bases before next_mapping */
 216       /* assert: next_mapping->bound >= all bounds before next_mapping */
 217       last_mapping = &next_mapping->next;
 218       next_mapping = next_mapping->next;
 219     }
 220
 221   /* check insertion point correct */
 222   SIM_ASSERT (next_mapping == NULL || next_mapping->level >= level);
 223   if (next_mapping != NULL && next_mapping->level == level
 224       && next_mapping->base < (addr + (nr_bytes - 1)))
 225     {
 226 #if (WITH_DEVICES)
 227       device_error (client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
 228                     space,
 229                     (long) addr,
 230                     (long) nr_bytes,
 231                     (long) (addr + (nr_bytes - 1)),
 232                     next_mapping->space,
 233                     (long) next_mapping->base,
 234                     (long) next_mapping->bound,
 235                     (long) next_mapping->nr_bytes);
 236 #else
 237       sim_io_error (sd, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
 238                     space,
 239                     (long) addr,
 240                     (long) nr_bytes,
 241                     (long) (addr + (nr_bytes - 1)),
 242                     next_mapping->space,
 243                     (long) next_mapping->base,
 244                     (long) next_mapping->bound,
 245                     (long) next_mapping->nr_bytes);
 246 #endif
 247   }
 248
 249   /* create/insert the new mapping */
 250   *last_mapping = new_sim_core_mapping(sd,
 251                                        level,
 252                                        space, addr, nr_bytes, modulo,
 253                                        client, buffer, free_buffer);
 254   (*last_mapping)->next = next_mapping;
 255 }
 256
 257
 258 EXTERN_SIM_CORE\
 259 (void)
 260 sim_core_attach (SIM_DESC sd,
 261                  sim_cpu *cpu,
 262                  int level,
 263                  access_type access,
 264                  int space,
 265                  address_word addr,
 266                  address_word nr_bytes,
 267                  unsigned modulo,
 268                  device *client,
 269                  void *optional_buffer)
 270 {
 271   sim_core *memory = STATE_CORE(sd);
 272   sim_core_maps map;
 273   void *buffer;
 274   void *free_buffer;
 275
 276   /* check for for attempt to use unimplemented per-processor core map */
 277   if (cpu != NULL)
 278     sim_io_error (sd, "sim_core_map_attach - processor specific memory map not yet supported");
 279
 280   if ((access & access_read_write_exec) == 0
 281       || (access & ~access_read_write_exec) != 0)
 282     {
 283 #if (WITH_DEVICES)
 284       device_error(client, "invalid access for core attach");
 285 #else
 286       sim_io_error (sd, "invalid access for core attach");
 287 #endif
 288     }
 289
 290   /* verify modulo memory */
 291   if (!WITH_MODULO_MEMORY && modulo != 0)
 292     {
 293 #if (WITH_DEVICES)
 294       device_error (client, "sim_core_attach - internal error - modulo memory disabled");
 295 #else
 296       sim_io_error (sd, "sim_core_attach - internal error - modulo memory disabled");
 297 #endif
 298     }
 299   if (client != NULL && modulo != 0)
 300     {
 301 #if (WITH_DEVICES)
 302       device_error (client, "sim_core_attach - internal error - modulo and callback memory conflict");
 303 #else
 304       sim_io_error (sd, "sim_core_attach - internal error - modulo and callback memory conflict");
 305 #endif
 306     }
 307   if (modulo != 0)
 308     {
 309       unsigned mask = modulo - 1;
 310       /* any zero bits */
 311       while (mask >= sizeof (unsigned64)) /* minimum modulo */
 312         {
 313           if ((mask & 1) == 0)
 314             mask = 0;
 315           else
 316             mask >>= 1;
 317         }
 318       if (mask != sizeof (unsigned64) - 1)
 319         {
 320 #if (WITH_DEVICES)
 321           device_error (client, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
 322 #else
 323           sim_io_error (sd, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
 324 #endif
 325         }
 326     }
 327
 328   /* verify consistency between device and buffer */
 329   if (client != NULL && optional_buffer != NULL)
 330     {
 331 #if (WITH_DEVICES)
 332       device_error (client, "sim_core_attach - internal error - conflicting buffer and attach arguments");
 333 #else
 334       sim_io_error (sd, "sim_core_attach - internal error - conflicting buffer and attach arguments");
 335 #endif
 336     }
 337   if (client == NULL)
 338     {
 339       if (optional_buffer == NULL)
 340         {
 341           int padding = (addr % sizeof (unsigned64));
 342           free_buffer = xmalloc ((modulo == 0 ? nr_bytes : modulo) + padding);
 343           buffer = (char*) free_buffer + padding;
 344         }
 345       else
 346         {
 347           buffer = optional_buffer;
 348           free_buffer = NULL;
 349         }
 350     }
 351   else
 352     {
 353       /* a device */
 354       buffer = NULL;
 355       free_buffer = NULL;
 356     }
 357
 358   /* attach the region to all applicable access maps */
 359   for (map = 0;
 360        map < nr_sim_core_maps;
 361        map++)
 362     {
 363       switch (map)
 364         {
 365         case sim_core_read_map:
 366           if (access & access_read)
 367             sim_core_map_attach (sd, &memory->common.map[map],
 368                                  level, space, addr, nr_bytes, modulo,
 369                                  client, buffer, free_buffer);
 370           free_buffer = NULL;
 371           break;
 372         case sim_core_write_map:
 373           if (access & access_write)
 374             sim_core_map_attach (sd, &memory->common.map[map],
 375                                  level, space, addr, nr_bytes, modulo,
 376                                  client, buffer, free_buffer);
 377           free_buffer = NULL;
 378           break;
 379         case sim_core_execute_map:
 380           if (access & access_exec)
 381             sim_core_map_attach (sd, &memory->common.map[map],
 382                                  level, space, addr, nr_bytes, modulo,
 383                                  client, buffer, free_buffer);
 384           free_buffer = NULL;
 385           break;
 386         case nr_sim_core_maps:
 387           sim_io_error (sd, "sim_core_attach - internal error - bad switch");
 388           break;
 389         }
 390     }
 391
 392   /* Just copy this map to each of the processor specific data structures.
 393      FIXME - later this will be replaced by true processor specific
 394      maps. */
 395   {
 396     int i;
 397     for (i = 0; i < MAX_NR_PROCESSORS; i++)
 398       {
 399         CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
 400       }
 401   }
 402 }
 403
 404
 405 /* Remove any memory reference related to this address */
 406 STATIC_INLINE_SIM_CORE\
 407 (void)
 408 sim_core_map_detach (SIM_DESC sd,
 409                      sim_core_map *access_map,
 410                      int level,
 411                      int space,
 412                      address_word addr)
 413 {
 414   sim_core_mapping **entry;
 415   for (entry = &access_map->first;
 416        (*entry) != NULL;
 417        entry = &(*entry)->next)
 418     {
 419       if ((*entry)->base == addr
 420           && (*entry)->level == level
 421           && (*entry)->space == space)
 422         {
 423           sim_core_mapping *dead = (*entry);
 424           (*entry) = dead->next;
 425           if (dead->free_buffer != NULL)
 426             free (dead->free_buffer);
 427           zfree (dead);
 428           return;
 429         }
 430     }
 431 }
 432
 433 EXTERN_SIM_CORE\
 434 (void)
 435 sim_core_detach (SIM_DESC sd,
 436                  sim_cpu *cpu,
 437                  int level,
 438                  int address_space,
 439                  address_word addr)
 440 {
 441   sim_core *memory = STATE_CORE (sd);
 442   sim_core_maps map;
 443   for (map = 0; map < nr_sim_core_maps; map++)
 444     {
 445       sim_core_map_detach (sd, &memory->common.map[map],
 446                            level, address_space, addr);
 447     }
 448   /* Just copy this update to each of the processor specific data
 449      structures.  FIXME - later this will be replaced by true
 450      processor specific maps. */
 451   {
 452     int i;
 453     for (i = 0; i < MAX_NR_PROCESSORS; i++)
 454       {
 455         CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
 456       }
 457   }
 458 }
 459
 460
 461 STATIC_INLINE_SIM_CORE\
 462 (sim_core_mapping *)
 463 sim_core_find_mapping(sim_core_common *core,
 464                       sim_core_maps map,
 465                       address_word addr,
 466                       unsigned nr_bytes,
 467                       transfer_type transfer,
 468                       int abort, /*either 0 or 1 - hint to inline/-O */
 469                       sim_cpu *cpu, /* abort => cpu != NULL */
 470                       sim_cia cia)
 471 {
 472   sim_core_mapping *mapping = core->map[map].first;
 473   ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */
 474   ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */
 475   ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */
 476   while (mapping != NULL)
 477     {
 478       if (addr >= mapping->base
 479           && (addr + (nr_bytes - 1)) <= mapping->bound)
 480         return mapping;
 481       mapping = mapping->next;
 482     }
 483   if (abort)
 484     {
 485       SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, nr_bytes, addr, transfer,
 486                        sim_core_unmapped_signal);
 487     }
 488   return NULL;
 489 }
 490
 491
 492 STATIC_INLINE_SIM_CORE\
 493 (void *)
 494 sim_core_translate (sim_core_mapping *mapping,
 495                     address_word addr)
 496 {
 497   if (WITH_MODULO_MEMORY)
 498     return (void *)((unsigned8 *) mapping->buffer
 499                     + ((addr - mapping->base) & mapping->mask));
 500   else
 501     return (void *)((unsigned8 *) mapping->buffer
 502                     + addr - mapping->base);
 503 }
 504
 505
 506 EXTERN_SIM_CORE\
 507 (unsigned)
 508 sim_core_read_buffer (SIM_DESC sd,
 509                       sim_cpu *cpu,
 510                       sim_core_maps map,
 511                       void *buffer,
 512                       address_word addr,
 513                       unsigned len)
 514 {
 515   sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
 516   unsigned count = 0;
 517   while (count < len) {
 518     unsigned_word raddr = addr + count;
 519     sim_core_mapping *mapping =
 520       sim_core_find_mapping(core, map,
 521                             raddr, /*nr-bytes*/1,
 522                             read_transfer,
 523                             0 /*dont-abort*/, NULL, NULL_CIA);
 524     if (mapping == NULL)
 525       break;
 526 #if (WITH_DEVICES)
 527     if (mapping->device != NULL) {
 528       int nr_bytes = len - count;
 529       if (raddr + nr_bytes - 1> mapping->bound)
 530         nr_bytes = mapping->bound - raddr + 1;
 531       if (device_io_read_buffer(mapping->device,
 532                                 (unsigned_1*)buffer + count,
 533                                 mapping->space,
 534                                 raddr,
 535                                 nr_bytes,
 536                                 cpu,
 537                                 CIA_GET(cpu)) != nr_bytes)
 538         break;
 539       count += nr_bytes;
 540     }
 541     else
 542 #endif
 543       {
 544         ((unsigned_1*)buffer)[count] =
 545           *(unsigned_1*)sim_core_translate(mapping, raddr);
 546         count += 1;
 547       }
 548   }
 549   return count;
 550 }
 551
 552
 553 EXTERN_SIM_CORE\
 554 (unsigned)
 555 sim_core_write_buffer (SIM_DESC sd,
 556                        sim_cpu *cpu,
 557                        sim_core_maps map,
 558                        const void *buffer,
 559                        address_word addr,
 560                        unsigned len)
 561 {
 562   sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
 563   unsigned count = 0;
 564   while (count < len) {
 565     unsigned_word raddr = addr + count;
 566     sim_core_mapping *mapping =
 567       sim_core_find_mapping(core, map,
 568                             raddr, /*nr-bytes*/1,
 569                             write_transfer,
 570                             0 /*dont-abort*/, NULL, NULL_CIA);
 571     if (mapping == NULL)
 572       break;
 573 #if (WITH_DEVICES)
 574     if (WITH_CALLBACK_MEMORY
 575         && mapping->device != NULL) {
 576       int nr_bytes = len - count;
 577       if (raddr + nr_bytes - 1 > mapping->bound)
 578         nr_bytes = mapping->bound - raddr + 1;
 579       if (device_io_write_buffer(mapping->device,
 580                                  (unsigned_1*)buffer + count,
 581                                  mapping->space,
 582                                  raddr,
 583                                  nr_bytes,
 584                                  cpu,
 585                                  CIA_GET(cpu)) != nr_bytes)
 586         break;
 587       count += nr_bytes;
 588     }
 589     else
 590 #endif
 591       {
 592         *(unsigned_1*)sim_core_translate(mapping, raddr) =
 593           ((unsigned_1*)buffer)[count];
 594         count += 1;
 595       }
 596   }
 597   return count;
 598 }
 599
 600
 601 EXTERN_SIM_CORE\
 602 (void)
 603 sim_core_set_xor (SIM_DESC sd,
 604                   sim_cpu *cpu,
 605                   int is_xor)
 606 {
 607   /* set up the XOR map if required. */
 608   if (WITH_XOR_ENDIAN) {
 609     {
 610       sim_core *core = STATE_CORE (sd);
 611       sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL);
 612       if (cpu_core != NULL)
 613         {
 614           int i = 1;
 615           unsigned mask;
 616           if (is_xor)
 617             mask = WITH_XOR_ENDIAN - 1;
 618           else
 619             mask = 0;
 620           while (i - 1 < WITH_XOR_ENDIAN)
 621             {
 622               cpu_core->xor[i-1] = mask;
 623               mask = (mask << 1) & (WITH_XOR_ENDIAN - 1);
 624               i = (i << 1);
 625             }
 626         }
 627       else
 628         {
 629           if (is_xor)
 630             core->byte_xor = WITH_XOR_ENDIAN - 1;
 631           else
 632             core->byte_xor = 0;
 633         }
 634     }
 635   }
 636   else {
 637     if (is_xor)
 638       sim_engine_abort (sd, cpu, NULL_CIA,
 639                         "Attempted to enable xor-endian mode when permenantly disabled.");
 640   }
 641 }
 642
 643 STATIC_INLINE_SIM_CORE\
 644 (void)
 645 reverse_n (unsigned_1 *dest,
 646            const unsigned_1 *src,
 647            int nr_bytes)
 648 {
 649   int i;
 650   for (i = 0; i < nr_bytes; i++)
 651     {
 652       dest [nr_bytes - i - 1] = src [i];
 653     }
 654 }
 655
 656
 657 EXTERN_SIM_CORE\
 658 (unsigned)
 659 sim_core_xor_read_buffer (SIM_DESC sd,
 660                           sim_cpu *cpu,
 661                           sim_core_maps map,
 662                           void *buffer,
 663                           address_word addr,
 664                           unsigned nr_bytes)
 665 {
 666   address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
 667   if (!WITH_XOR_ENDIAN || !byte_xor)
 668     return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes);
 669   else
 670     /* only break up transfers when xor-endian is both selected and enabled */
 671     {
 672       unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
 673       unsigned nr_transfered = 0;
 674       address_word start = addr;
 675       unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
 676       address_word stop;
 677       /* initial and intermediate transfers are broken when they cross
 678          an XOR endian boundary */
 679       while (nr_transfered + nr_this_transfer < nr_bytes)
 680         /* initial/intermediate transfers */
 681         {
 682           /* since xor-endian is enabled stop^xor defines the start
 683              address of the transfer */
 684           stop = start + nr_this_transfer - 1;
 685           SIM_ASSERT (start <= stop);
 686           SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
 687           if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 688               != nr_this_transfer)
 689             return nr_transfered;
 690           reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
 691           nr_transfered += nr_this_transfer;
 692           nr_this_transfer = WITH_XOR_ENDIAN;
 693           start = stop + 1;
 694         }
 695       /* final transfer */
 696       nr_this_transfer = nr_bytes - nr_transfered;
 697       stop = start + nr_this_transfer - 1;
 698       SIM_ASSERT (stop == (addr + nr_bytes - 1));
 699       if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 700           != nr_this_transfer)
 701         return nr_transfered;
 702       reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
 703       return nr_bytes;
 704     }
 705 }
 706
 707
 708 EXTERN_SIM_CORE\
 709 (unsigned)
 710 sim_core_xor_write_buffer (SIM_DESC sd,
 711                            sim_cpu *cpu,
 712                            sim_core_maps map,
 713                            const void *buffer,
 714                            address_word addr,
 715                            unsigned nr_bytes)
 716 {
 717   address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
 718   if (!WITH_XOR_ENDIAN || !byte_xor)
 719     return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes);
 720   else
 721     /* only break up transfers when xor-endian is both selected and enabled */
 722     {
 723       unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero sized array */
 724       unsigned nr_transfered = 0;
 725       address_word start = addr;
 726       unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
 727       address_word stop;
 728       /* initial and intermediate transfers are broken when they cross
 729          an XOR endian boundary */
 730       while (nr_transfered + nr_this_transfer < nr_bytes)
 731         /* initial/intermediate transfers */
 732         {
 733           /* since xor-endian is enabled stop^xor defines the start
 734              address of the transfer */
 735           stop = start + nr_this_transfer - 1;
 736           SIM_ASSERT (start <= stop);
 737           SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
 738           reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
 739           if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 740               != nr_this_transfer)
 741             return nr_transfered;
 742           nr_transfered += nr_this_transfer;
 743           nr_this_transfer = WITH_XOR_ENDIAN;
 744           start = stop + 1;
 745         }
 746       /* final transfer */
 747       nr_this_transfer = nr_bytes - nr_transfered;
 748       stop = start + nr_this_transfer - 1;
 749       SIM_ASSERT (stop == (addr + nr_bytes - 1));
 750       reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
 751       if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
 752           != nr_this_transfer)
 753         return nr_transfered;
 754       return nr_bytes;
 755     }
 756 }
 757
 758
 759
 760 /* define the read/write 1/2/4/8/16/word functions */
 761
 762 #define N 16
 763 #include "sim-n-core.h"
 764
 765 #define N 8
 766 #include "sim-n-core.h"
 767
 768 #define N 7
 769 #define M 8
 770 #include "sim-n-core.h"
 771
 772 #define N 6
 773 #define M 8
 774 #include "sim-n-core.h"
 775
 776 #define N 5
 777 #define M 8
 778 #include "sim-n-core.h"
 779
 780 #define N 4
 781 #include "sim-n-core.h"
 782
 783 #define N 3
 784 #define M 4
 785 #include "sim-n-core.h"
 786
 787 #define N 2
 788 #include "sim-n-core.h"
 789
 790 #define N 1
 791 #include "sim-n-core.h"
 792
 793 #endif