sim/common/sim-core.h

   1 /*  This file is part of the program psim.
   2
   3     Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18
  19     */
  20
  21
  22 #ifndef _SIM_CORE_H_
  23 #define _SIM_CORE_H_
  24
  25
  26 /* core signals (error conditions) */
  27
  28 typedef enum {
  29   sim_core_unmapped_signal,
  30   sim_core_unaligned_signal,
  31   nr_sim_core_signals,
  32 } sim_core_signals;
  33
  34 /* define SIM_CORE_SIGNAL to catch these signals - see sim-core.c for
  35    details */
  36
  37
  38
  39 /* basic types */
  40
  41 typedef struct _sim_core_mapping sim_core_mapping;
  42 struct _sim_core_mapping {
  43   /* common */
  44   int level;
  45   int space;
  46   unsigned_word base;
  47   unsigned_word bound;
  48   unsigned_word nr_bytes;
  49   unsigned mask;
  50   /* memory map */
  51   void *free_buffer;
  52   void *buffer;
  53   /* callback map */
  54   device *device;
  55   /* tracing */
  56   int trace;
  57   /* growth */
  58   sim_core_mapping *next;
  59 };
  60
  61 typedef struct _sim_core_map sim_core_map;
  62 struct _sim_core_map {
  63   sim_core_mapping *first;
  64 };
  65
  66 typedef enum {
  67   sim_core_read_map,
  68   sim_core_write_map,
  69   sim_core_execute_map,
  70   nr_sim_core_maps,
  71 } sim_core_maps;
  72
  73
  74 typedef struct _sim_core_common {
  75   sim_core_map map[nr_sim_core_maps];
  76 } sim_core_common;
  77
  78
  79 /* Main core structure */
  80
  81 typedef struct _sim_core sim_core;
  82 struct _sim_core {
  83   sim_core_common common;
  84   address_word byte_xor; /* apply xor universally */
  85 };
  86
  87
  88 /* Per CPU distributed component of the core.  At present this is
  89    mostly a clone of the global core data structure. */
  90
  91 typedef struct _sim_cpu_core {
  92   sim_core_common common;
  93   address_word xor[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
  94 } sim_cpu_core;
  95
  96
  97 /* Install the "core" module.  */
  98
  99 EXTERN_SIM_CORE\
 100 (SIM_RC) sim_core_install (SIM_DESC sd);
 101
 102
 103
 104 /* Create a memory space within the core.
 105
 106    CPU, when non NULL, specifes the single processor that the memory
 107    space is to be attached to. (UNIMPLEMENTED).
 108
 109    LEVEL specifies the ordering of the memory region.  Lower regions
 110    are searched first.  Within a level, memory regions can not
 111    overlap.
 112
 113    DEVICE, when non NULL, specifies a callback memory space.
 114    (UNIMPLEMENTED, see the ppc simulator for an example).
 115
 116    MODULO, when the simulator has been configured WITH_MODULO support
 117    and is greater than zero, specifies that accesses to the region
 118    [ADDR .. ADDR+NR_BYTES) should be mapped onto the sub region [ADDR
 119    .. ADDR+MODULO).  The modulo value must be a power of two.
 120
 121    OPTIONAL_BUFFER, when non NULL, specifies the buffer to use for
 122    data read & written to the region.  Normally a more efficient
 123    internal structure is used.  It is assumed that buffer is allocated
 124    such that the byte alignmed of OPTIONAL_BUFFER matches ADDR vis
 125    (OPTIONAL_BUFFER % 8) == (ADDR % 8)) */
 126
 127 EXTERN_SIM_CORE\
 128 (void) sim_core_attach
 129 (SIM_DESC sd,
 130  sim_cpu *cpu,
 131  int level,
 132  access_type access,
 133  int address_space,
 134  address_word addr,
 135  address_word nr_bytes,
 136  unsigned modulo,
 137  device *client,
 138  void *optional_buffer);
 139
 140
 141 /* Utility to return the name of a map.  */
 142
 143 EXTERN_SIM_CORE\
 144 (const char *) sim_core_map_to_str
 145 (sim_core_maps);
 146
 147
 148 /* Delete a memory space within the core.
 149
 150  */
 151
 152 EXTERN_SIM_CORE\
 153 (void) sim_core_detach
 154 (SIM_DESC sd,
 155  sim_cpu *cpu,
 156  int level,
 157  int address_space,
 158  address_word addr);
 159
 160
 161 /* Variable sized read/write
 162
 163    Transfer a variable sized block of raw data between the host and
 164    target.  Should any problems occure, the number of bytes
 165    successfully transfered is returned.
 166
 167    No host/target byte endian conversion is performed.  No xor-endian
 168    conversion is performed.
 169
 170    If CPU argument, when non NULL, specifies the processor specific
 171    address map that is to be used in the transfer. */
 172
 173
 174 EXTERN_SIM_CORE\
 175 (unsigned) sim_core_read_buffer
 176 (SIM_DESC sd,
 177  sim_cpu *cpu,
 178  sim_core_maps map,
 179  void *buffer,
 180  address_word addr,
 181  unsigned nr_bytes);
 182
 183 EXTERN_SIM_CORE\
 184 (unsigned) sim_core_write_buffer
 185 (SIM_DESC sd,
 186  sim_cpu *cpu,
 187  sim_core_maps map,
 188  const void *buffer,
 189  address_word addr,
 190  unsigned nr_bytes);
 191
 192
 193
 194 /* Configure the core's XOR endian transfer mode.  Only applicable
 195    when WITH_XOR_ENDIAN is enabled.
 196
 197    Targets suporting XOR endian, shall notify the core of any changes
 198    in state via this call.
 199
 200    The CPU argument, when non NULL, specifes the single processor that
 201    the xor-endian configuration is to be applied to. */
 202
 203 EXTERN_SIM_CORE\
 204 (void) sim_core_set_xor\
 205 (SIM_DESC sd,
 206  sim_cpu *cpu,
 207  int is_xor);
 208
 209
 210 /* XOR version of variable sized read/write.
 211
 212    Transfer a variable sized block of raw data between the host and
 213    target.  Should any problems occure, the number of bytes
 214    successfully transfered is returned.
 215
 216    No host/target byte endian conversion is performed.  If applicable
 217    (WITH_XOR_ENDIAN and xor-endian set), xor-endian conversion *is*
 218    performed.
 219
 220    If CPU argument, when non NULL, specifies the processor specific
 221    address map that is to be used in the transfer. */
 222
 223 EXTERN_SIM_CORE\
 224 (unsigned) sim_core_xor_read_buffer
 225 (SIM_DESC sd,
 226  sim_cpu *cpu,
 227  sim_core_maps map,
 228  void *buffer,
 229  address_word addr,
 230  unsigned nr_bytes);
 231
 232 EXTERN_SIM_CORE\
 233 (unsigned) sim_core_xor_write_buffer
 234 (SIM_DESC sd,
 235  sim_cpu *cpu,
 236  sim_core_maps map,
 237  const void *buffer,
 238  address_word addr,
 239  unsigned nr_bytes);
 240
 241
 242
 243 /* Fixed sized, processor oriented, read/write.
 244
 245    Transfer a fixed amout of memory between the host and target.  The
 246    data transfered is translated from/to host to/from target byte
 247    order (including xor endian).  Should the transfer fail, the
 248    operation shall abort (no return).
 249
 250    ALIGNED assumes yhat the specified ADDRESS is correctly alligned
 251    for an N byte transfer (no alignment checks are made).  Passing an
 252    incorrectly aligned ADDRESS is erroneous.
 253
 254    UNALIGNED checks/modifies the ADDRESS according to the requirements
 255    of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being
 256    taken should the check fail.
 257
 258    MISSALIGNED transfers the data regardless.
 259
 260    Misaligned xor-endian accesses are broken into a sequence of
 261    transfers each <= WITH_XOR_ENDIAN bytes */
 262
 263
 264 #define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N,M) \
 265 INLINE_SIM_CORE\
 266 (void) sim_core_write_##ALIGNMENT##_##N \
 267 (sim_cpu *cpu, \
 268  sim_cia cia, \
 269  sim_core_maps map, \
 270  address_word addr, \
 271  unsigned_##M val);
 272
 273 DECLARE_SIM_CORE_WRITE_N(aligned,1,1)
 274 DECLARE_SIM_CORE_WRITE_N(aligned,2,2)
 275 DECLARE_SIM_CORE_WRITE_N(aligned,4,4)
 276 DECLARE_SIM_CORE_WRITE_N(aligned,8,8)
 277 DECLARE_SIM_CORE_WRITE_N(aligned,16,16)
 278
 279 #define sim_core_write_unaligned_1 sim_core_write_aligned_1
 280 DECLARE_SIM_CORE_WRITE_N(unaligned,2,2)
 281 DECLARE_SIM_CORE_WRITE_N(unaligned,4,4)
 282 DECLARE_SIM_CORE_WRITE_N(unaligned,8,8)
 283 DECLARE_SIM_CORE_WRITE_N(unaligned,16,16)
 284
 285 DECLARE_SIM_CORE_WRITE_N(misaligned,3,4)
 286 DECLARE_SIM_CORE_WRITE_N(misaligned,5,8)
 287 DECLARE_SIM_CORE_WRITE_N(misaligned,6,8)
 288 DECLARE_SIM_CORE_WRITE_N(misaligned,7,8)
 289
 290 #define sim_core_write_1 sim_core_write_aligned_1
 291 #define sim_core_write_2 sim_core_write_aligned_2
 292 #define sim_core_write_4 sim_core_write_aligned_4
 293 #define sim_core_write_8 sim_core_write_aligned_8
 294 #define sim_core_write_16 sim_core_write_aligned_16
 295
 296 #define sim_core_write_unaligned_word XCONCAT2(sim_core_write_unaligned_,WITH_TARGET_WORD_BITSIZE)
 297 #define sim_core_write_aligned_word XCONCAT2(sim_core_write_aligned_,WITH_TARGET_WORD_BITSIZE)
 298 #define sim_core_write_word XCONCAT2(sim_core_write_,WITH_TARGET_WORD_BITSIZE)
 299
 300 #undef DECLARE_SIM_CORE_WRITE_N
 301
 302
 303 #define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N,M) \
 304 INLINE_SIM_CORE\
 305 (unsigned_##M) sim_core_read_##ALIGNMENT##_##N \
 306 (sim_cpu *cpu, \
 307  sim_cia cia, \
 308  sim_core_maps map, \
 309  address_word addr);
 310
 311 DECLARE_SIM_CORE_READ_N(aligned,1,1)
 312 DECLARE_SIM_CORE_READ_N(aligned,2,2)
 313 DECLARE_SIM_CORE_READ_N(aligned,4,4)
 314 DECLARE_SIM_CORE_READ_N(aligned,8,8)
 315 DECLARE_SIM_CORE_READ_N(aligned,16,16)
 316
 317 #define sim_core_read_unaligned_1 sim_core_read_aligned_1
 318 DECLARE_SIM_CORE_READ_N(unaligned,2,2)
 319 DECLARE_SIM_CORE_READ_N(unaligned,4,4)
 320 DECLARE_SIM_CORE_READ_N(unaligned,8,8)
 321 DECLARE_SIM_CORE_READ_N(unaligned,16,16)
 322
 323 DECLARE_SIM_CORE_READ_N(misaligned,3,4)
 324 DECLARE_SIM_CORE_READ_N(misaligned,5,8)
 325 DECLARE_SIM_CORE_READ_N(misaligned,6,8)
 326 DECLARE_SIM_CORE_READ_N(misaligned,7,8)
 327
 328
 329 #define sim_core_read_1 sim_core_read_aligned_1
 330 #define sim_core_read_2 sim_core_read_aligned_2
 331 #define sim_core_read_4 sim_core_read_aligned_4
 332 #define sim_core_read_8 sim_core_read_aligned_8
 333 #define sim_core_read_16 sim_core_read_aligned_16
 334
 335 #define sim_core_read_unaligned_word XCONCAT2(sim_core_read_unaligned_,WITH_TARGET_WORD_BITSIZE)
 336 #define sim_core_read_aligned_word XCONCAT2(sim_core_read_aligned_,WITH_TARGET_WORD_BITSIZE)
 337 #define sim_core_read_word XCONCAT2(sim_core_read_,WITH_TARGET_WORD_BITSIZE)
 338
 339 #undef DECLARE_SIM_CORE_READ_N
 340
 341 #endif