sim/cr16/cr16_sim.h

   1 /* Simulation code for the CR16 processor.
   2    Copyright (C) 2008 Free Software Foundation, Inc.
   3    Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
   4
   5    This file is part of GDB, the GNU debugger.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License along
  18    with this program. If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include <stdio.h>
  22 #include <ctype.h>
  23 #include <limits.h>
  24 #include "ansidecl.h"
  25 #include "gdb/callback.h"
  26 #include "opcode/cr16.h"
  27 #include "bfd.h"
  28
  29 #define DEBUG_TRACE             0x00000001
  30 #define DEBUG_VALUES            0x00000002
  31 #define DEBUG_LINE_NUMBER       0x00000004
  32 #define DEBUG_MEMSIZE           0x00000008
  33 #define DEBUG_INSTRUCTION       0x00000010
  34 #define DEBUG_TRAP              0x00000020
  35 #define DEBUG_MEMORY            0x00000040
  36
  37 #ifndef DEBUG
  38 #define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
  39 #endif
  40
  41 extern int cr16_debug;
  42
  43 #include "gdb/remote-sim.h"
  44 #include "sim-config.h"
  45 #include "sim-types.h"
  46
  47 typedef unsigned8 uint8;
  48 typedef signed8 int8;
  49 typedef unsigned16 uint16;
  50 typedef signed16 int16;
  51 typedef unsigned32 uint32;
  52 typedef signed32 int32;
  53 typedef unsigned64 uint64;
  54 typedef signed64 int64;
  55
  56 /* FIXME: CR16 defines */
  57 typedef uint16 reg_t;
  58 typedef uint32 creg_t;
  59
  60 struct simops
  61 {
  62   char mnimonic[6];
  63   int  size; // size
  64   long mask;
  65   long opcode;
  66   int format;
  67   char fname[10];
  68   void (*func)();
  69   int numops;
  70   int operands[4];
  71 };
  72
  73 enum _ins_type
  74 {
  75    INS_UNKNOWN,                 /* unknown instruction */
  76    INS_NO_TYPE_INS,
  77    INS_ARITH_INS,
  78    INS_LD_STOR_INS,
  79    INS_BRANCH_INS,
  80    INS_ARITH_BYTE_INS,
  81    INS_SHIFT_INS,
  82    INS_BRANCH_NEQ_INS,
  83    INS_STOR_IMM_INS,
  84    INS_CSTBIT_INS,
  85    INS_MAX
  86 };
  87
  88 extern unsigned long ins_type_counters[ (int)INS_MAX ];
  89
  90 enum {
  91   SP_IDX = 15,
  92 };
  93
  94 /* Write-back slots */
  95 union slot_data {
  96   unsigned_1 _1;
  97   unsigned_2 _2;
  98   unsigned_4 _4;
  99 };
 100 struct slot {
 101   void *dest;
 102   int size;
 103   union slot_data data;
 104   union slot_data mask;
 105 };
 106 enum {
 107  NR_SLOTS = 16
 108 };
 109 #define SLOT (State.slot)
 110 #define SLOT_NR (State.slot_nr)
 111 #define SLOT_PEND_MASK(DEST, MSK, VAL) \
 112   do \
 113     { \
 114       SLOT[SLOT_NR].dest = &(DEST); \
 115       SLOT[SLOT_NR].size = sizeof (DEST); \
 116       switch (sizeof (DEST)) \
 117         { \
 118         case 1: \
 119           SLOT[SLOT_NR].data._1 = (unsigned_1) (VAL); \
 120           SLOT[SLOT_NR].mask._1 = (unsigned_1) (MSK); \
 121           break; \
 122         case 2: \
 123           SLOT[SLOT_NR].data._2 = (unsigned_2) (VAL); \
 124           SLOT[SLOT_NR].mask._2 = (unsigned_2) (MSK); \
 125           break; \
 126         case 4: \
 127           SLOT[SLOT_NR].data._4 = (unsigned_4) (VAL); \
 128           SLOT[SLOT_NR].mask._4 = (unsigned_4) (MSK); \
 129           break; \
 130         } \
 131       SLOT_NR = (SLOT_NR + 1); \
 132     } \
 133   while (0)
 134 #define SLOT_PEND(DEST, VAL) SLOT_PEND_MASK(DEST, 0, VAL)
 135 #define SLOT_DISCARD() (SLOT_NR = 0)
 136 #define SLOT_FLUSH() \
 137   do \
 138     { \
 139       int i; \
 140       for (i = 0; i < SLOT_NR; i++) \
 141         { \
 142           switch (SLOT[i].size) \
 143             { \
 144             case 1: \
 145               *(unsigned_1*) SLOT[i].dest &= SLOT[i].mask._1; \
 146               *(unsigned_1*) SLOT[i].dest |= SLOT[i].data._1; \
 147               break; \
 148             case 2: \
 149               *(unsigned_2*) SLOT[i].dest &= SLOT[i].mask._2; \
 150               *(unsigned_2*) SLOT[i].dest |= SLOT[i].data._2; \
 151               break; \
 152             case 4: \
 153               *(unsigned_4*) SLOT[i].dest &= SLOT[i].mask._4; \
 154               *(unsigned_4*) SLOT[i].dest |= SLOT[i].data._4; \
 155               break; \
 156             } \
 157         } \
 158       SLOT_NR = 0; \
 159     } \
 160   while (0)
 161 #define SLOT_DUMP() \
 162   do \
 163     { \
 164       int i; \
 165       for (i = 0; i < SLOT_NR; i++) \
 166         { \
 167           switch (SLOT[i].size) \
 168             { \
 169             case 1: \
 170               printf ("SLOT %d *0x%08lx & 0x%02x | 0x%02x\n", i, \
 171                       (long) SLOT[i].dest, \
 172                       (unsigned) SLOT[i].mask._1, \
 173                       (unsigned) SLOT[i].data._1); \
 174               break; \
 175             case 2: \
 176               printf ("SLOT %d *0x%08lx & 0x%04x | 0x%04x\n", i, \
 177                       (long) SLOT[i].dest, \
 178                       (unsigned) SLOT[i].mask._2, \
 179                       (unsigned) SLOT[i].data._2); \
 180               break; \
 181             case 4: \
 182               printf ("SLOT %d *0x%08lx & 0x%08x | 0x%08x\n", i, \
 183                       (long) SLOT[i].dest, \
 184                       (unsigned) SLOT[i].mask._4, \
 185                       (unsigned) SLOT[i].data._4); \
 186               break; \
 187             case 8: \
 188               printf ("SLOT %d *0x%08lx & 0x%08x%08x | 0x%08x%08x\n", i, \
 189                       (long) SLOT[i].dest, \
 190                       (unsigned) (SLOT[i].mask._8 >> 32),  \
 191                       (unsigned) SLOT[i].mask._8, \
 192                       (unsigned) (SLOT[i].data._8 >> 32),  \
 193                       (unsigned) SLOT[i].data._8); \
 194               break; \
 195             } \
 196         } \
 197     } \
 198   while (0)
 199
 200 /* cr16 memory: There are three separate cr16 memory regions IMEM,
 201    UMEM and DMEM.  The IMEM and DMEM are further broken down into
 202    blocks (very like VM pages). */
 203
 204 enum
 205 {
 206   IMAP_BLOCK_SIZE = 0x2000000,
 207   DMAP_BLOCK_SIZE = 0x4000000
 208 };
 209
 210 /* Implement the three memory regions using sparse arrays.  Allocate
 211    memory using ``segments''.  A segment must be at least as large as
 212    a BLOCK - ensures that an access that doesn't cross a block
 213    boundary can't cross a segment boundary */
 214
 215 enum
 216 {
 217   SEGMENT_SIZE = 0x2000000, /* 128KB - MAX(IMAP_BLOCK_SIZE,DMAP_BLOCK_SIZE) */
 218   IMEM_SEGMENTS = 8, /* 1MB */
 219   DMEM_SEGMENTS = 8, /* 1MB */
 220   UMEM_SEGMENTS = 128 /* 16MB */
 221 };
 222
 223 struct cr16_memory
 224 {
 225   uint8 *insn[IMEM_SEGMENTS];
 226   uint8 *data[DMEM_SEGMENTS];
 227   uint8 *unif[UMEM_SEGMENTS];
 228   uint8 fault[16];
 229 };
 230
 231 struct _state
 232 {
 233   creg_t regs[16];              /* general-purpose registers */
 234 #define GPR(N) (State.regs[(N)] + 0)
 235 #define SET_GPR(N,VAL) (State.regs[(N)] = (VAL))
 236
 237 #define GPR32(N) \
 238      (N < 12) ? \
 239      ((((uint16) State.regs[(N) + 1]) << 16) | (uint16) State.regs[(N)]) \
 240      : GPR (N)
 241
 242 #define SET_GPR32(N,VAL) do { \
 243      if (N < 11)  \
 244        { SET_GPR (N + 1, (VAL) >> 16); SET_GPR (N, ((VAL) & 0xffff));} \
 245      else { if ( N == 11) \
 246              { SET_GPR (N + 1, ((GPR32 (12)) & 0xffff0000)|((VAL) >> 16)); \
 247                SET_GPR (N, ((VAL) & 0xffff));} \
 248             else SET_GPR (N, (VAL));} \
 249     } while (0)
 250
 251   creg_t cregs[16];             /* control registers */
 252 #define CREG(N) (State.cregs[(N)] + 0)
 253 #define SET_CREG(N,VAL) move_to_cr ((N), 0, (VAL), 0)
 254 #define SET_HW_CREG(N,VAL) move_to_cr ((N), 0, (VAL), 1)
 255
 256   reg_t sp[2];                  /* holding area for SPI(0)/SPU(1) */
 257 #define HELD_SP(N) (State.sp[(N)] + 0)
 258 #define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL))
 259
 260   /* writeback info */
 261   struct slot slot[NR_SLOTS];
 262   int slot_nr;
 263
 264   /* trace data */
 265   struct {
 266     uint16 psw;
 267   } trace;
 268
 269   uint8 exe;
 270   int   exception;
 271   int   pc_changed;
 272
 273   /* NOTE: everything below this line is not reset by
 274      sim_create_inferior() */
 275
 276   struct cr16_memory mem;
 277
 278   enum _ins_type ins_type;
 279
 280 } State;
 281
 282
 283 extern host_callback *cr16_callback;
 284 extern uint32 OP[4];
 285 extern uint32 sign_flag;
 286 extern struct simops Simops[];
 287 extern asection *text;
 288 extern bfd_vma text_start;
 289 extern bfd_vma text_end;
 290 extern bfd *prog_bfd;
 291
 292 enum
 293 {
 294   PC_CR   = 0,
 295   BDS_CR  = 1,
 296   BSR_CR  = 2,
 297   DCR_CR  = 3,
 298   CAR0_CR = 5,
 299   CAR1_CR = 7,
 300   CFG_CR  = 9,
 301   PSR_CR  = 10,
 302   INTBASE_CR = 11,
 303   ISP_CR = 13,
 304   USP_CR = 15
 305 };
 306
 307 enum
 308 {
 309   PSR_I_BIT = 0x0800,
 310   PSR_P_BIT = 0x0400,
 311   PSR_E_BIT = 0x0200,
 312   PSR_N_BIT = 0x0100,
 313   PSR_Z_BIT = 0x0040,
 314   PSR_F_BIT = 0x0020,
 315   PSR_U_BIT = 0x0010,
 316   PSR_L_BIT = 0x0004,
 317   PSR_T_BIT = 0x0002,
 318   PSR_C_BIT = 0x0001,
 319 };
 320
 321 #define PSR CREG (PSR_CR)
 322 #define SET_PSR(VAL) SET_CREG (PSR_CR, (VAL))
 323 #define SET_HW_PSR(VAL) SET_HW_CREG (PSR_CR, (VAL))
 324 #define SET_PSR_BIT(MASK,VAL) move_to_cr (PSR_CR, ~((creg_t) MASK), (VAL) ? (MASK) : 0, 1)
 325
 326 #define PSR_SM ((PSR & PSR_SM_BIT) != 0)
 327 #define SET_PSR_SM(VAL) SET_PSR_BIT (PSR_SM_BIT, (VAL))
 328
 329 #define PSR_I ((PSR & PSR_I_BIT) != 0)
 330 #define SET_PSR_I(VAL) SET_PSR_BIT (PSR_I_BIT, (VAL))
 331
 332 #define PSR_DB ((PSR & PSR_DB_BIT) != 0)
 333 #define SET_PSR_DB(VAL) SET_PSR_BIT (PSR_DB_BIT, (VAL))
 334
 335 #define PSR_P ((PSR & PSR_P_BIT) != 0)
 336 #define SET_PSR_P(VAL) SET_PSR_BIT (PSR_P_BIT, (VAL))
 337
 338 #define PSR_E ((PSR & PSR_E_BIT) != 0)
 339 #define SET_PSR_E(VAL) SET_PSR_BIT (PSR_E_BIT, (VAL))
 340
 341 #define PSR_N ((PSR & PSR_N_BIT) != 0)
 342 #define SET_PSR_N(VAL) SET_PSR_BIT (PSR_N_BIT, (VAL))
 343
 344 #define PSR_Z ((PSR & PSR_Z_BIT) != 0)
 345 #define SET_PSR_Z(VAL) SET_PSR_BIT (PSR_Z_BIT, (VAL))
 346
 347 #define PSR_F ((PSR & PSR_F_BIT) != 0)
 348 #define SET_PSR_F(VAL) SET_PSR_BIT (PSR_F_BIT, (VAL))
 349
 350 #define PSR_U ((PSR & PSR_U_BIT) != 0)
 351 #define SET_PSR_U(VAL) SET_PSR_BIT (PSR_U_BIT, (VAL))
 352
 353 #define PSR_L ((PSR & PSR_L_BIT) != 0)
 354 #define SET_PSR_L(VAL) SET_PSR_BIT (PSR_L_BIT, (VAL))
 355
 356 #define PSR_T ((PSR & PSR_T_BIT) != 0)
 357 #define SET_PSR_T(VAL) SET_PSR_BIT (PSR_T_BIT, (VAL))
 358
 359 #define PSR_C ((PSR & PSR_C_BIT) != 0)
 360 #define SET_PSR_C(VAL) SET_PSR_BIT (PSR_C_BIT, (VAL))
 361
 362 /* See simopsc.:move_to_cr() for registers that can not be read-from
 363    or assigned-to directly */
 364
 365 #define PC      CREG (PC_CR)
 366 #define SET_PC(VAL) SET_CREG (PC_CR, (VAL))
 367 //#define SET_PC(VAL) (State.cregs[PC_CR] = (VAL))
 368
 369 #define BPSR    CREG (BPSR_CR)
 370 #define SET_BPSR(VAL) SET_CREG (BPSR_CR, (VAL))
 371
 372 #define BPC     CREG (BPC_CR)
 373 #define SET_BPC(VAL) SET_CREG (BPC_CR, (VAL))
 374
 375 #define DPSR    CREG (DPSR_CR)
 376 #define SET_DPSR(VAL) SET_CREG (DPSR_CR, (VAL))
 377
 378 #define DPC     CREG (DPC_CR)
 379 #define SET_DPC(VAL) SET_CREG (DPC_CR, (VAL))
 380
 381 #define RPT_C   CREG (RPT_C_CR)
 382 #define SET_RPT_C(VAL) SET_CREG (RPT_C_CR, (VAL))
 383
 384 #define RPT_S   CREG (RPT_S_CR)
 385 #define SET_RPT_S(VAL) SET_CREG (RPT_S_CR, (VAL))
 386
 387 #define RPT_E   CREG (RPT_E_CR)
 388 #define SET_RPT_E(VAL) SET_CREG (RPT_E_CR, (VAL))
 389
 390 #define MOD_S   CREG (MOD_S_CR)
 391 #define SET_MOD_S(VAL) SET_CREG (MOD_S_CR, (VAL))
 392
 393 #define MOD_E   CREG (MOD_E_CR)
 394 #define SET_MOD_E(VAL) SET_CREG (MOD_E_CR, (VAL))
 395
 396 #define IBA     CREG (IBA_CR)
 397 #define SET_IBA(VAL) SET_CREG (IBA_CR, (VAL))
 398
 399
 400 #define SIG_CR16_STOP   -1
 401 #define SIG_CR16_EXIT   -2
 402 #define SIG_CR16_BUS    -3
 403 #define SIG_CR16_IAD    -4
 404
 405 #define SEXT3(x)        ((((x)&0x7)^(~3))+4)
 406
 407 /* sign-extend a 4-bit number */
 408 #define SEXT4(x)        ((((x)&0xf)^(~7))+8)
 409
 410 /* sign-extend an 8-bit number */
 411 #define SEXT8(x)        ((((x)&0xff)^(~0x7f))+0x80)
 412
 413 /* sign-extend a 16-bit number */
 414 #define SEXT16(x)       ((((x)&0xffff)^(~0x7fff))+0x8000)
 415
 416 /* sign-extend a 24-bit number */
 417 #define SEXT24(x)       ((((x)&0xffffff)^(~0x7fffff))+0x800000)
 418
 419 /* sign-extend a 32-bit number */
 420 #define SEXT32(x)       ((((x)&0xffffffff)^(~0x7fffffff))+0x80000000)
 421
 422 extern uint8 *dmem_addr (uint32 offset);
 423 extern uint8 *imem_addr PARAMS ((uint32));
 424 extern bfd_vma decode_pc PARAMS ((void));
 425
 426 #define RB(x)   (*(dmem_addr(x)))
 427 #define SB(addr,data)   ( RB(addr) = (data & 0xff))
 428
 429 #if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE)
 430 #define ENDIAN_INLINE static __inline__
 431 #include "endian.c"
 432 #undef ENDIAN_INLINE
 433
 434 #else
 435 extern uint32 get_longword PARAMS ((uint8 *));
 436 extern uint16 get_word PARAMS ((uint8 *));
 437 extern int64 get_longlong PARAMS ((uint8 *));
 438 extern void write_word PARAMS ((uint8 *addr, uint16 data));
 439 extern void write_longword PARAMS ((uint8 *addr, uint32 data));
 440 extern void write_longlong PARAMS ((uint8 *addr, int64 data));
 441 #endif
 442
 443 #define SW(addr,data)           write_word(dmem_addr(addr),data)
 444 #define RW(x)                   get_word(dmem_addr(x))
 445 #define SLW(addr,data)          write_longword(dmem_addr(addr),data)
 446 #define RLW(x)                  get_longword(dmem_addr(x))
 447 #define READ_16(x)              get_word(x)
 448 #define WRITE_16(addr,data)     write_word(addr,data)
 449 #define READ_64(x)              get_longlong(x)
 450 #define WRITE_64(addr,data)     write_longlong(addr,data)
 451
 452 #define JMP(x)                  do { SET_PC (x); State.pc_changed = 1; } while (0)
 453
 454 #define RIE_VECTOR_START  0xffc2
 455 #define AE_VECTOR_START   0xffc3
 456 #define TRAP_VECTOR_START 0xffc4        /* vector for trap 0 */
 457 #define DBT_VECTOR_START  0xffd4
 458 #define SDBT_VECTOR_START 0xffd5
 459
 460 #define INT_VECTOR_START   0xFFFE00 /*maskable interrupt - mapped to ICU */
 461 #define NMI_VECTOR_START   0xFFFF00 /*non-maskable interrupt;for observability*/
 462 #define ISE_VECTOR_START   0xFFFC00 /*in-system emulation trap */
 463 #define ADBG_VECTOR_START  0xFFFC02 /*alternate debug trap */
 464 #define ATRC_VECTOR_START  0xFFFC0C /*alternate trace trap */
 465 #define ABPT_VECTOR_START  0xFFFC0E /*alternate break point trap */
 466
 467
 468 /* Scedule a store of VAL into cr[CR].  MASK indicates the bits in
 469    cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) |
 470    (VAL & ~MASK)).  In addition, unless PSR_HW_P, a VAL intended for
 471    PSR is masked for zero bits. */
 472
 473 extern creg_t move_to_cr (int cr, creg_t mask, creg_t val, int psw_hw_p);