sim/cris/semcrisv32f-switch.c

   1 /* Simulator instruction semantics for crisv32f.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2004 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifdef DEFINE_LABELS
  26
  27   /* The labels have the case they have because the enum of insn types
  28      is all uppercase and in the non-stdc case the insn symbol is built
  29      into the enum name.  */
  30
  31   static struct {
  32     int index;
  33     void *label;
  34   } labels[] = {
  35     { CRISV32F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
  36     { CRISV32F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
  37     { CRISV32F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
  38     { CRISV32F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
  39     { CRISV32F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
  40     { CRISV32F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
  41     { CRISV32F_INSN_MOVE_B_R, && case_sem_INSN_MOVE_B_R },
  42     { CRISV32F_INSN_MOVE_W_R, && case_sem_INSN_MOVE_W_R },
  43     { CRISV32F_INSN_MOVE_D_R, && case_sem_INSN_MOVE_D_R },
  44     { CRISV32F_INSN_MOVEQ, && case_sem_INSN_MOVEQ },
  45     { CRISV32F_INSN_MOVS_B_R, && case_sem_INSN_MOVS_B_R },
  46     { CRISV32F_INSN_MOVS_W_R, && case_sem_INSN_MOVS_W_R },
  47     { CRISV32F_INSN_MOVU_B_R, && case_sem_INSN_MOVU_B_R },
  48     { CRISV32F_INSN_MOVU_W_R, && case_sem_INSN_MOVU_W_R },
  49     { CRISV32F_INSN_MOVECBR, && case_sem_INSN_MOVECBR },
  50     { CRISV32F_INSN_MOVECWR, && case_sem_INSN_MOVECWR },
  51     { CRISV32F_INSN_MOVECDR, && case_sem_INSN_MOVECDR },
  52     { CRISV32F_INSN_MOVSCBR, && case_sem_INSN_MOVSCBR },
  53     { CRISV32F_INSN_MOVSCWR, && case_sem_INSN_MOVSCWR },
  54     { CRISV32F_INSN_MOVUCBR, && case_sem_INSN_MOVUCBR },
  55     { CRISV32F_INSN_MOVUCWR, && case_sem_INSN_MOVUCWR },
  56     { CRISV32F_INSN_ADDQ, && case_sem_INSN_ADDQ },
  57     { CRISV32F_INSN_SUBQ, && case_sem_INSN_SUBQ },
  58     { CRISV32F_INSN_CMP_R_B_R, && case_sem_INSN_CMP_R_B_R },
  59     { CRISV32F_INSN_CMP_R_W_R, && case_sem_INSN_CMP_R_W_R },
  60     { CRISV32F_INSN_CMP_R_D_R, && case_sem_INSN_CMP_R_D_R },
  61     { CRISV32F_INSN_CMP_M_B_M, && case_sem_INSN_CMP_M_B_M },
  62     { CRISV32F_INSN_CMP_M_W_M, && case_sem_INSN_CMP_M_W_M },
  63     { CRISV32F_INSN_CMP_M_D_M, && case_sem_INSN_CMP_M_D_M },
  64     { CRISV32F_INSN_CMPCBR, && case_sem_INSN_CMPCBR },
  65     { CRISV32F_INSN_CMPCWR, && case_sem_INSN_CMPCWR },
  66     { CRISV32F_INSN_CMPCDR, && case_sem_INSN_CMPCDR },
  67     { CRISV32F_INSN_CMPQ, && case_sem_INSN_CMPQ },
  68     { CRISV32F_INSN_CMPS_M_B_M, && case_sem_INSN_CMPS_M_B_M },
  69     { CRISV32F_INSN_CMPS_M_W_M, && case_sem_INSN_CMPS_M_W_M },
  70     { CRISV32F_INSN_CMPSCBR, && case_sem_INSN_CMPSCBR },
  71     { CRISV32F_INSN_CMPSCWR, && case_sem_INSN_CMPSCWR },
  72     { CRISV32F_INSN_CMPU_M_B_M, && case_sem_INSN_CMPU_M_B_M },
  73     { CRISV32F_INSN_CMPU_M_W_M, && case_sem_INSN_CMPU_M_W_M },
  74     { CRISV32F_INSN_CMPUCBR, && case_sem_INSN_CMPUCBR },
  75     { CRISV32F_INSN_CMPUCWR, && case_sem_INSN_CMPUCWR },
  76     { CRISV32F_INSN_MOVE_M_B_M, && case_sem_INSN_MOVE_M_B_M },
  77     { CRISV32F_INSN_MOVE_M_W_M, && case_sem_INSN_MOVE_M_W_M },
  78     { CRISV32F_INSN_MOVE_M_D_M, && case_sem_INSN_MOVE_M_D_M },
  79     { CRISV32F_INSN_MOVS_M_B_M, && case_sem_INSN_MOVS_M_B_M },
  80     { CRISV32F_INSN_MOVS_M_W_M, && case_sem_INSN_MOVS_M_W_M },
  81     { CRISV32F_INSN_MOVU_M_B_M, && case_sem_INSN_MOVU_M_B_M },
  82     { CRISV32F_INSN_MOVU_M_W_M, && case_sem_INSN_MOVU_M_W_M },
  83     { CRISV32F_INSN_MOVE_R_SPRV32, && case_sem_INSN_MOVE_R_SPRV32 },
  84     { CRISV32F_INSN_MOVE_SPR_RV32, && case_sem_INSN_MOVE_SPR_RV32 },
  85     { CRISV32F_INSN_MOVE_M_SPRV32, && case_sem_INSN_MOVE_M_SPRV32 },
  86     { CRISV32F_INSN_MOVE_C_SPRV32_P0, && case_sem_INSN_MOVE_C_SPRV32_P0 },
  87     { CRISV32F_INSN_MOVE_C_SPRV32_P1, && case_sem_INSN_MOVE_C_SPRV32_P1 },
  88     { CRISV32F_INSN_MOVE_C_SPRV32_P2, && case_sem_INSN_MOVE_C_SPRV32_P2 },
  89     { CRISV32F_INSN_MOVE_C_SPRV32_P3, && case_sem_INSN_MOVE_C_SPRV32_P3 },
  90     { CRISV32F_INSN_MOVE_C_SPRV32_P4, && case_sem_INSN_MOVE_C_SPRV32_P4 },
  91     { CRISV32F_INSN_MOVE_C_SPRV32_P5, && case_sem_INSN_MOVE_C_SPRV32_P5 },
  92     { CRISV32F_INSN_MOVE_C_SPRV32_P6, && case_sem_INSN_MOVE_C_SPRV32_P6 },
  93     { CRISV32F_INSN_MOVE_C_SPRV32_P7, && case_sem_INSN_MOVE_C_SPRV32_P7 },
  94     { CRISV32F_INSN_MOVE_C_SPRV32_P8, && case_sem_INSN_MOVE_C_SPRV32_P8 },
  95     { CRISV32F_INSN_MOVE_C_SPRV32_P9, && case_sem_INSN_MOVE_C_SPRV32_P9 },
  96     { CRISV32F_INSN_MOVE_C_SPRV32_P10, && case_sem_INSN_MOVE_C_SPRV32_P10 },
  97     { CRISV32F_INSN_MOVE_C_SPRV32_P11, && case_sem_INSN_MOVE_C_SPRV32_P11 },
  98     { CRISV32F_INSN_MOVE_C_SPRV32_P12, && case_sem_INSN_MOVE_C_SPRV32_P12 },
  99     { CRISV32F_INSN_MOVE_C_SPRV32_P13, && case_sem_INSN_MOVE_C_SPRV32_P13 },
 100     { CRISV32F_INSN_MOVE_C_SPRV32_P14, && case_sem_INSN_MOVE_C_SPRV32_P14 },
 101     { CRISV32F_INSN_MOVE_C_SPRV32_P15, && case_sem_INSN_MOVE_C_SPRV32_P15 },
 102     { CRISV32F_INSN_MOVE_SPR_MV32, && case_sem_INSN_MOVE_SPR_MV32 },
 103     { CRISV32F_INSN_MOVE_SS_R, && case_sem_INSN_MOVE_SS_R },
 104     { CRISV32F_INSN_MOVE_R_SS, && case_sem_INSN_MOVE_R_SS },
 105     { CRISV32F_INSN_MOVEM_R_M_V32, && case_sem_INSN_MOVEM_R_M_V32 },
 106     { CRISV32F_INSN_MOVEM_M_R_V32, && case_sem_INSN_MOVEM_M_R_V32 },
 107     { CRISV32F_INSN_ADD_B_R, && case_sem_INSN_ADD_B_R },
 108     { CRISV32F_INSN_ADD_W_R, && case_sem_INSN_ADD_W_R },
 109     { CRISV32F_INSN_ADD_D_R, && case_sem_INSN_ADD_D_R },
 110     { CRISV32F_INSN_ADD_M_B_M, && case_sem_INSN_ADD_M_B_M },
 111     { CRISV32F_INSN_ADD_M_W_M, && case_sem_INSN_ADD_M_W_M },
 112     { CRISV32F_INSN_ADD_M_D_M, && case_sem_INSN_ADD_M_D_M },
 113     { CRISV32F_INSN_ADDCBR, && case_sem_INSN_ADDCBR },
 114     { CRISV32F_INSN_ADDCWR, && case_sem_INSN_ADDCWR },
 115     { CRISV32F_INSN_ADDCDR, && case_sem_INSN_ADDCDR },
 116     { CRISV32F_INSN_ADDS_B_R, && case_sem_INSN_ADDS_B_R },
 117     { CRISV32F_INSN_ADDS_W_R, && case_sem_INSN_ADDS_W_R },
 118     { CRISV32F_INSN_ADDS_M_B_M, && case_sem_INSN_ADDS_M_B_M },
 119     { CRISV32F_INSN_ADDS_M_W_M, && case_sem_INSN_ADDS_M_W_M },
 120     { CRISV32F_INSN_ADDSCBR, && case_sem_INSN_ADDSCBR },
 121     { CRISV32F_INSN_ADDSCWR, && case_sem_INSN_ADDSCWR },
 122     { CRISV32F_INSN_ADDU_B_R, && case_sem_INSN_ADDU_B_R },
 123     { CRISV32F_INSN_ADDU_W_R, && case_sem_INSN_ADDU_W_R },
 124     { CRISV32F_INSN_ADDU_M_B_M, && case_sem_INSN_ADDU_M_B_M },
 125     { CRISV32F_INSN_ADDU_M_W_M, && case_sem_INSN_ADDU_M_W_M },
 126     { CRISV32F_INSN_ADDUCBR, && case_sem_INSN_ADDUCBR },
 127     { CRISV32F_INSN_ADDUCWR, && case_sem_INSN_ADDUCWR },
 128     { CRISV32F_INSN_SUB_B_R, && case_sem_INSN_SUB_B_R },
 129     { CRISV32F_INSN_SUB_W_R, && case_sem_INSN_SUB_W_R },
 130     { CRISV32F_INSN_SUB_D_R, && case_sem_INSN_SUB_D_R },
 131     { CRISV32F_INSN_SUB_M_B_M, && case_sem_INSN_SUB_M_B_M },
 132     { CRISV32F_INSN_SUB_M_W_M, && case_sem_INSN_SUB_M_W_M },
 133     { CRISV32F_INSN_SUB_M_D_M, && case_sem_INSN_SUB_M_D_M },
 134     { CRISV32F_INSN_SUBCBR, && case_sem_INSN_SUBCBR },
 135     { CRISV32F_INSN_SUBCWR, && case_sem_INSN_SUBCWR },
 136     { CRISV32F_INSN_SUBCDR, && case_sem_INSN_SUBCDR },
 137     { CRISV32F_INSN_SUBS_B_R, && case_sem_INSN_SUBS_B_R },
 138     { CRISV32F_INSN_SUBS_W_R, && case_sem_INSN_SUBS_W_R },
 139     { CRISV32F_INSN_SUBS_M_B_M, && case_sem_INSN_SUBS_M_B_M },
 140     { CRISV32F_INSN_SUBS_M_W_M, && case_sem_INSN_SUBS_M_W_M },
 141     { CRISV32F_INSN_SUBSCBR, && case_sem_INSN_SUBSCBR },
 142     { CRISV32F_INSN_SUBSCWR, && case_sem_INSN_SUBSCWR },
 143     { CRISV32F_INSN_SUBU_B_R, && case_sem_INSN_SUBU_B_R },
 144     { CRISV32F_INSN_SUBU_W_R, && case_sem_INSN_SUBU_W_R },
 145     { CRISV32F_INSN_SUBU_M_B_M, && case_sem_INSN_SUBU_M_B_M },
 146     { CRISV32F_INSN_SUBU_M_W_M, && case_sem_INSN_SUBU_M_W_M },
 147     { CRISV32F_INSN_SUBUCBR, && case_sem_INSN_SUBUCBR },
 148     { CRISV32F_INSN_SUBUCWR, && case_sem_INSN_SUBUCWR },
 149     { CRISV32F_INSN_ADDC_R, && case_sem_INSN_ADDC_R },
 150     { CRISV32F_INSN_ADDC_M, && case_sem_INSN_ADDC_M },
 151     { CRISV32F_INSN_ADDC_C, && case_sem_INSN_ADDC_C },
 152     { CRISV32F_INSN_LAPC_D, && case_sem_INSN_LAPC_D },
 153     { CRISV32F_INSN_LAPCQ, && case_sem_INSN_LAPCQ },
 154     { CRISV32F_INSN_ADDI_B_R, && case_sem_INSN_ADDI_B_R },
 155     { CRISV32F_INSN_ADDI_W_R, && case_sem_INSN_ADDI_W_R },
 156     { CRISV32F_INSN_ADDI_D_R, && case_sem_INSN_ADDI_D_R },
 157     { CRISV32F_INSN_NEG_B_R, && case_sem_INSN_NEG_B_R },
 158     { CRISV32F_INSN_NEG_W_R, && case_sem_INSN_NEG_W_R },
 159     { CRISV32F_INSN_NEG_D_R, && case_sem_INSN_NEG_D_R },
 160     { CRISV32F_INSN_TEST_M_B_M, && case_sem_INSN_TEST_M_B_M },
 161     { CRISV32F_INSN_TEST_M_W_M, && case_sem_INSN_TEST_M_W_M },
 162     { CRISV32F_INSN_TEST_M_D_M, && case_sem_INSN_TEST_M_D_M },
 163     { CRISV32F_INSN_MOVE_R_M_B_M, && case_sem_INSN_MOVE_R_M_B_M },
 164     { CRISV32F_INSN_MOVE_R_M_W_M, && case_sem_INSN_MOVE_R_M_W_M },
 165     { CRISV32F_INSN_MOVE_R_M_D_M, && case_sem_INSN_MOVE_R_M_D_M },
 166     { CRISV32F_INSN_MULS_B, && case_sem_INSN_MULS_B },
 167     { CRISV32F_INSN_MULS_W, && case_sem_INSN_MULS_W },
 168     { CRISV32F_INSN_MULS_D, && case_sem_INSN_MULS_D },
 169     { CRISV32F_INSN_MULU_B, && case_sem_INSN_MULU_B },
 170     { CRISV32F_INSN_MULU_W, && case_sem_INSN_MULU_W },
 171     { CRISV32F_INSN_MULU_D, && case_sem_INSN_MULU_D },
 172     { CRISV32F_INSN_MCP, && case_sem_INSN_MCP },
 173     { CRISV32F_INSN_DSTEP, && case_sem_INSN_DSTEP },
 174     { CRISV32F_INSN_ABS, && case_sem_INSN_ABS },
 175     { CRISV32F_INSN_AND_B_R, && case_sem_INSN_AND_B_R },
 176     { CRISV32F_INSN_AND_W_R, && case_sem_INSN_AND_W_R },
 177     { CRISV32F_INSN_AND_D_R, && case_sem_INSN_AND_D_R },
 178     { CRISV32F_INSN_AND_M_B_M, && case_sem_INSN_AND_M_B_M },
 179     { CRISV32F_INSN_AND_M_W_M, && case_sem_INSN_AND_M_W_M },
 180     { CRISV32F_INSN_AND_M_D_M, && case_sem_INSN_AND_M_D_M },
 181     { CRISV32F_INSN_ANDCBR, && case_sem_INSN_ANDCBR },
 182     { CRISV32F_INSN_ANDCWR, && case_sem_INSN_ANDCWR },
 183     { CRISV32F_INSN_ANDCDR, && case_sem_INSN_ANDCDR },
 184     { CRISV32F_INSN_ANDQ, && case_sem_INSN_ANDQ },
 185     { CRISV32F_INSN_ORR_B_R, && case_sem_INSN_ORR_B_R },
 186     { CRISV32F_INSN_ORR_W_R, && case_sem_INSN_ORR_W_R },
 187     { CRISV32F_INSN_ORR_D_R, && case_sem_INSN_ORR_D_R },
 188     { CRISV32F_INSN_OR_M_B_M, && case_sem_INSN_OR_M_B_M },
 189     { CRISV32F_INSN_OR_M_W_M, && case_sem_INSN_OR_M_W_M },
 190     { CRISV32F_INSN_OR_M_D_M, && case_sem_INSN_OR_M_D_M },
 191     { CRISV32F_INSN_ORCBR, && case_sem_INSN_ORCBR },
 192     { CRISV32F_INSN_ORCWR, && case_sem_INSN_ORCWR },
 193     { CRISV32F_INSN_ORCDR, && case_sem_INSN_ORCDR },
 194     { CRISV32F_INSN_ORQ, && case_sem_INSN_ORQ },
 195     { CRISV32F_INSN_XOR, && case_sem_INSN_XOR },
 196     { CRISV32F_INSN_SWAP, && case_sem_INSN_SWAP },
 197     { CRISV32F_INSN_ASRR_B_R, && case_sem_INSN_ASRR_B_R },
 198     { CRISV32F_INSN_ASRR_W_R, && case_sem_INSN_ASRR_W_R },
 199     { CRISV32F_INSN_ASRR_D_R, && case_sem_INSN_ASRR_D_R },
 200     { CRISV32F_INSN_ASRQ, && case_sem_INSN_ASRQ },
 201     { CRISV32F_INSN_LSRR_B_R, && case_sem_INSN_LSRR_B_R },
 202     { CRISV32F_INSN_LSRR_W_R, && case_sem_INSN_LSRR_W_R },
 203     { CRISV32F_INSN_LSRR_D_R, && case_sem_INSN_LSRR_D_R },
 204     { CRISV32F_INSN_LSRQ, && case_sem_INSN_LSRQ },
 205     { CRISV32F_INSN_LSLR_B_R, && case_sem_INSN_LSLR_B_R },
 206     { CRISV32F_INSN_LSLR_W_R, && case_sem_INSN_LSLR_W_R },
 207     { CRISV32F_INSN_LSLR_D_R, && case_sem_INSN_LSLR_D_R },
 208     { CRISV32F_INSN_LSLQ, && case_sem_INSN_LSLQ },
 209     { CRISV32F_INSN_BTST, && case_sem_INSN_BTST },
 210     { CRISV32F_INSN_BTSTQ, && case_sem_INSN_BTSTQ },
 211     { CRISV32F_INSN_SETF, && case_sem_INSN_SETF },
 212     { CRISV32F_INSN_CLEARF, && case_sem_INSN_CLEARF },
 213     { CRISV32F_INSN_RFE, && case_sem_INSN_RFE },
 214     { CRISV32F_INSN_SFE, && case_sem_INSN_SFE },
 215     { CRISV32F_INSN_RFG, && case_sem_INSN_RFG },
 216     { CRISV32F_INSN_RFN, && case_sem_INSN_RFN },
 217     { CRISV32F_INSN_HALT, && case_sem_INSN_HALT },
 218     { CRISV32F_INSN_BCC_B, && case_sem_INSN_BCC_B },
 219     { CRISV32F_INSN_BA_B, && case_sem_INSN_BA_B },
 220     { CRISV32F_INSN_BCC_W, && case_sem_INSN_BCC_W },
 221     { CRISV32F_INSN_BA_W, && case_sem_INSN_BA_W },
 222     { CRISV32F_INSN_JAS_R, && case_sem_INSN_JAS_R },
 223     { CRISV32F_INSN_JAS_C, && case_sem_INSN_JAS_C },
 224     { CRISV32F_INSN_JUMP_P, && case_sem_INSN_JUMP_P },
 225     { CRISV32F_INSN_BAS_C, && case_sem_INSN_BAS_C },
 226     { CRISV32F_INSN_JASC_R, && case_sem_INSN_JASC_R },
 227     { CRISV32F_INSN_JASC_C, && case_sem_INSN_JASC_C },
 228     { CRISV32F_INSN_BASC_C, && case_sem_INSN_BASC_C },
 229     { CRISV32F_INSN_BREAK, && case_sem_INSN_BREAK },
 230     { CRISV32F_INSN_BOUND_R_B_R, && case_sem_INSN_BOUND_R_B_R },
 231     { CRISV32F_INSN_BOUND_R_W_R, && case_sem_INSN_BOUND_R_W_R },
 232     { CRISV32F_INSN_BOUND_R_D_R, && case_sem_INSN_BOUND_R_D_R },
 233     { CRISV32F_INSN_BOUND_CB, && case_sem_INSN_BOUND_CB },
 234     { CRISV32F_INSN_BOUND_CW, && case_sem_INSN_BOUND_CW },
 235     { CRISV32F_INSN_BOUND_CD, && case_sem_INSN_BOUND_CD },
 236     { CRISV32F_INSN_SCC, && case_sem_INSN_SCC },
 237     { CRISV32F_INSN_LZ, && case_sem_INSN_LZ },
 238     { CRISV32F_INSN_ADDOQ, && case_sem_INSN_ADDOQ },
 239     { CRISV32F_INSN_ADDO_M_B_M, && case_sem_INSN_ADDO_M_B_M },
 240     { CRISV32F_INSN_ADDO_M_W_M, && case_sem_INSN_ADDO_M_W_M },
 241     { CRISV32F_INSN_ADDO_M_D_M, && case_sem_INSN_ADDO_M_D_M },
 242     { CRISV32F_INSN_ADDO_CB, && case_sem_INSN_ADDO_CB },
 243     { CRISV32F_INSN_ADDO_CW, && case_sem_INSN_ADDO_CW },
 244     { CRISV32F_INSN_ADDO_CD, && case_sem_INSN_ADDO_CD },
 245     { CRISV32F_INSN_ADDI_ACR_B_R, && case_sem_INSN_ADDI_ACR_B_R },
 246     { CRISV32F_INSN_ADDI_ACR_W_R, && case_sem_INSN_ADDI_ACR_W_R },
 247     { CRISV32F_INSN_ADDI_ACR_D_R, && case_sem_INSN_ADDI_ACR_D_R },
 248     { CRISV32F_INSN_FIDXI, && case_sem_INSN_FIDXI },
 249     { CRISV32F_INSN_FTAGI, && case_sem_INSN_FTAGI },
 250     { CRISV32F_INSN_FIDXD, && case_sem_INSN_FIDXD },
 251     { CRISV32F_INSN_FTAGD, && case_sem_INSN_FTAGD },
 252     { 0, 0 }
 253   };
 254   int i;
 255
 256   for (i = 0; labels[i].label != 0; ++i)
 257     {
 258 #if FAST_P
 259       CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
 260 #else
 261       CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
 262 #endif
 263     }
 264
 265 #undef DEFINE_LABELS
 266 #endif /* DEFINE_LABELS */
 267
 268 #ifdef DEFINE_SWITCH
 269
 270 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
 271    off frills like tracing and profiling.  */
 272 /* FIXME: A better way would be to have TRACE_RESULT check for something
 273    that can cause it to be optimized out.  Another way would be to emit
 274    special handlers into the instruction "stream".  */
 275
 276 #if FAST_P
 277 #undef TRACE_RESULT
 278 #define TRACE_RESULT(cpu, abuf, name, type, val)
 279 #endif
 280
 281 #undef GET_ATTR
 282 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 283 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
 284 #else
 285 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
 286 #endif
 287
 288 {
 289
 290 #if WITH_SCACHE_PBB
 291
 292 /* Branch to next handler without going around main loop.  */
 293 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
 294 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 295
 296 #else /* ! WITH_SCACHE_PBB */
 297
 298 #define NEXT(vpc) BREAK (sem)
 299 #ifdef __GNUC__
 300 #if FAST_P
 301   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
 302 #else
 303   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
 304 #endif
 305 #else
 306   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
 307 #endif
 308
 309 #endif /* ! WITH_SCACHE_PBB */
 310
 311     {
 312
 313   CASE (sem, INSN_X_INVALID) : /* --invalid-- */
 314 {
 315   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 316   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 317 #define FLD(f) abuf->fields.fmt_empty.f
 318   int UNUSED written = 0;
 319   IADDR UNUSED pc = abuf->addr;
 320   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 321
 322   {
 323     /* Update the recorded pc in the cpu state struct.
 324        Only necessary for WITH_SCACHE case, but to avoid the
 325        conditional compilation ....  */
 326     SET_H_PC (pc);
 327     /* Virtual insns have zero size.  Overwrite vpc with address of next insn
 328        using the default-insn-bitsize spec.  When executing insns in parallel
 329        we may want to queue the fault and continue execution.  */
 330     vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 331     vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
 332   }
 333
 334 #undef FLD
 335 }
 336   NEXT (vpc);
 337
 338   CASE (sem, INSN_X_AFTER) : /* --after-- */
 339 {
 340   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 341   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 342 #define FLD(f) abuf->fields.fmt_empty.f
 343   int UNUSED written = 0;
 344   IADDR UNUSED pc = abuf->addr;
 345   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 346
 347   {
 348 #if WITH_SCACHE_PBB_CRISV32F
 349     crisv32f_pbb_after (current_cpu, sem_arg);
 350 #endif
 351   }
 352
 353 #undef FLD
 354 }
 355   NEXT (vpc);
 356
 357   CASE (sem, INSN_X_BEFORE) : /* --before-- */
 358 {
 359   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 360   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 361 #define FLD(f) abuf->fields.fmt_empty.f
 362   int UNUSED written = 0;
 363   IADDR UNUSED pc = abuf->addr;
 364   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 365
 366   {
 367 #if WITH_SCACHE_PBB_CRISV32F
 368     crisv32f_pbb_before (current_cpu, sem_arg);
 369 #endif
 370   }
 371
 372 #undef FLD
 373 }
 374   NEXT (vpc);
 375
 376   CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
 377 {
 378   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 379   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 380 #define FLD(f) abuf->fields.fmt_empty.f
 381   int UNUSED written = 0;
 382   IADDR UNUSED pc = abuf->addr;
 383   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 384
 385   {
 386 #if WITH_SCACHE_PBB_CRISV32F
 387 #ifdef DEFINE_SWITCH
 388     vpc = crisv32f_pbb_cti_chain (current_cpu, sem_arg,
 389                                pbb_br_type, pbb_br_npc);
 390     BREAK (sem);
 391 #else
 392     /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
 393     vpc = crisv32f_pbb_cti_chain (current_cpu, sem_arg,
 394                                CPU_PBB_BR_TYPE (current_cpu),
 395                                CPU_PBB_BR_NPC (current_cpu));
 396 #endif
 397 #endif
 398   }
 399
 400 #undef FLD
 401 }
 402   NEXT (vpc);
 403
 404   CASE (sem, INSN_X_CHAIN) : /* --chain-- */
 405 {
 406   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 407   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 408 #define FLD(f) abuf->fields.fmt_empty.f
 409   int UNUSED written = 0;
 410   IADDR UNUSED pc = abuf->addr;
 411   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 412
 413   {
 414 #if WITH_SCACHE_PBB_CRISV32F
 415     vpc = crisv32f_pbb_chain (current_cpu, sem_arg);
 416 #ifdef DEFINE_SWITCH
 417     BREAK (sem);
 418 #endif
 419 #endif
 420   }
 421
 422 #undef FLD
 423 }
 424   NEXT (vpc);
 425
 426   CASE (sem, INSN_X_BEGIN) : /* --begin-- */
 427 {
 428   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 429   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 430 #define FLD(f) abuf->fields.fmt_empty.f
 431   int UNUSED written = 0;
 432   IADDR UNUSED pc = abuf->addr;
 433   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 434
 435   {
 436 #if WITH_SCACHE_PBB_CRISV32F
 437 #if defined DEFINE_SWITCH || defined FAST_P
 438     /* In the switch case FAST_P is a constant, allowing several optimizations
 439        in any called inline functions.  */
 440     vpc = crisv32f_pbb_begin (current_cpu, FAST_P);
 441 #else
 442 #if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
 443     vpc = crisv32f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
 444 #else
 445     vpc = crisv32f_pbb_begin (current_cpu, 0);
 446 #endif
 447 #endif
 448 #endif
 449   }
 450
 451 #undef FLD
 452 }
 453   NEXT (vpc);
 454
 455   CASE (sem, INSN_MOVE_B_R) : /* move.b move.m ${Rs},${Rd} */
 456 {
 457   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 458   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 459 #define FLD(f) abuf->fields.sfmt_addc_m.f
 460   int UNUSED written = 0;
 461   IADDR UNUSED pc = abuf->addr;
 462   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 463
 464 {
 465   QI tmp_newval;
 466   tmp_newval = GET_H_GR (FLD (f_operand1));
 467 {
 468   SI tmp_oldregval;
 469   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
 470   {
 471     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
 472     SET_H_GR (FLD (f_operand2), opval);
 473     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 474   }
 475 }
 476 {
 477   {
 478     BI opval = LTQI (tmp_newval, 0);
 479     CPU (h_nbit) = opval;
 480     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 481   }
 482   {
 483     BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 484     CPU (h_zbit) = opval;
 485     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 486   }
 487 SET_H_CBIT_MOVE (0);
 488 SET_H_VBIT_MOVE (0);
 489 {
 490   {
 491     BI opval = 0;
 492     CPU (h_xbit) = opval;
 493     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 494   }
 495   {
 496     BI opval = 0;
 497     SET_H_INSN_PREFIXED_P (opval);
 498     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 499   }
 500 }
 501 }
 502 }
 503
 504 #undef FLD
 505 }
 506   NEXT (vpc);
 507
 508   CASE (sem, INSN_MOVE_W_R) : /* move.w move.m ${Rs},${Rd} */
 509 {
 510   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 511   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 512 #define FLD(f) abuf->fields.sfmt_addc_m.f
 513   int UNUSED written = 0;
 514   IADDR UNUSED pc = abuf->addr;
 515   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 516
 517 {
 518   HI tmp_newval;
 519   tmp_newval = GET_H_GR (FLD (f_operand1));
 520 {
 521   SI tmp_oldregval;
 522   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
 523   {
 524     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
 525     SET_H_GR (FLD (f_operand2), opval);
 526     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 527   }
 528 }
 529 {
 530   {
 531     BI opval = LTHI (tmp_newval, 0);
 532     CPU (h_nbit) = opval;
 533     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 534   }
 535   {
 536     BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 537     CPU (h_zbit) = opval;
 538     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 539   }
 540 SET_H_CBIT_MOVE (0);
 541 SET_H_VBIT_MOVE (0);
 542 {
 543   {
 544     BI opval = 0;
 545     CPU (h_xbit) = opval;
 546     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 547   }
 548   {
 549     BI opval = 0;
 550     SET_H_INSN_PREFIXED_P (opval);
 551     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 552   }
 553 }
 554 }
 555 }
 556
 557 #undef FLD
 558 }
 559   NEXT (vpc);
 560
 561   CASE (sem, INSN_MOVE_D_R) : /* move.d move.m ${Rs},${Rd} */
 562 {
 563   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 564   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 565 #define FLD(f) abuf->fields.sfmt_addc_m.f
 566   int UNUSED written = 0;
 567   IADDR UNUSED pc = abuf->addr;
 568   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 569
 570 {
 571   SI tmp_newval;
 572   tmp_newval = GET_H_GR (FLD (f_operand1));
 573   {
 574     SI opval = tmp_newval;
 575     SET_H_GR (FLD (f_operand2), opval);
 576     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 577   }
 578 {
 579   {
 580     BI opval = LTSI (tmp_newval, 0);
 581     CPU (h_nbit) = opval;
 582     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 583   }
 584   {
 585     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 586     CPU (h_zbit) = opval;
 587     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 588   }
 589 SET_H_CBIT_MOVE (0);
 590 SET_H_VBIT_MOVE (0);
 591 {
 592   {
 593     BI opval = 0;
 594     CPU (h_xbit) = opval;
 595     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 596   }
 597   {
 598     BI opval = 0;
 599     SET_H_INSN_PREFIXED_P (opval);
 600     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 601   }
 602 }
 603 }
 604 }
 605
 606 #undef FLD
 607 }
 608   NEXT (vpc);
 609
 610   CASE (sem, INSN_MOVEQ) : /* moveq $i,$Rd */
 611 {
 612   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 613   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 614 #define FLD(f) abuf->fields.sfmt_moveq.f
 615   int UNUSED written = 0;
 616   IADDR UNUSED pc = abuf->addr;
 617   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 618
 619 {
 620   SI tmp_newval;
 621   tmp_newval = FLD (f_s6);
 622   {
 623     SI opval = tmp_newval;
 624     SET_H_GR (FLD (f_operand2), opval);
 625     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 626   }
 627 {
 628 SET_H_NBIT_MOVE (LTSI (tmp_newval, 0));
 629 SET_H_ZBIT_MOVE (ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))));
 630 SET_H_CBIT_MOVE (0);
 631 SET_H_VBIT_MOVE (0);
 632 {
 633   {
 634     BI opval = 0;
 635     CPU (h_xbit) = opval;
 636     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 637   }
 638   {
 639     BI opval = 0;
 640     SET_H_INSN_PREFIXED_P (opval);
 641     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 642   }
 643 }
 644 }
 645 }
 646
 647 #undef FLD
 648 }
 649   NEXT (vpc);
 650
 651   CASE (sem, INSN_MOVS_B_R) : /* movs.b movs.m ${Rs},${Rd} */
 652 {
 653   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 654   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 655 #define FLD(f) abuf->fields.sfmt_muls_b.f
 656   int UNUSED written = 0;
 657   IADDR UNUSED pc = abuf->addr;
 658   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 659
 660 {
 661   QI tmp_newval;
 662   tmp_newval = GET_H_GR (FLD (f_operand1));
 663   {
 664     SI opval = EXTQISI (tmp_newval);
 665     SET_H_GR (FLD (f_operand2), opval);
 666     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 667   }
 668 {
 669   {
 670     BI opval = LTSI (tmp_newval, 0);
 671     CPU (h_nbit) = opval;
 672     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 673   }
 674   {
 675     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 676     CPU (h_zbit) = opval;
 677     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 678   }
 679 SET_H_CBIT_MOVE (0);
 680 SET_H_VBIT_MOVE (0);
 681 {
 682   {
 683     BI opval = 0;
 684     CPU (h_xbit) = opval;
 685     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 686   }
 687   {
 688     BI opval = 0;
 689     SET_H_INSN_PREFIXED_P (opval);
 690     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 691   }
 692 }
 693 }
 694 }
 695
 696 #undef FLD
 697 }
 698   NEXT (vpc);
 699
 700   CASE (sem, INSN_MOVS_W_R) : /* movs.w movs.m ${Rs},${Rd} */
 701 {
 702   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 703   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 704 #define FLD(f) abuf->fields.sfmt_muls_b.f
 705   int UNUSED written = 0;
 706   IADDR UNUSED pc = abuf->addr;
 707   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 708
 709 {
 710   HI tmp_newval;
 711   tmp_newval = GET_H_GR (FLD (f_operand1));
 712   {
 713     SI opval = EXTHISI (tmp_newval);
 714     SET_H_GR (FLD (f_operand2), opval);
 715     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 716   }
 717 {
 718   {
 719     BI opval = LTSI (tmp_newval, 0);
 720     CPU (h_nbit) = opval;
 721     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 722   }
 723   {
 724     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 725     CPU (h_zbit) = opval;
 726     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 727   }
 728 SET_H_CBIT_MOVE (0);
 729 SET_H_VBIT_MOVE (0);
 730 {
 731   {
 732     BI opval = 0;
 733     CPU (h_xbit) = opval;
 734     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 735   }
 736   {
 737     BI opval = 0;
 738     SET_H_INSN_PREFIXED_P (opval);
 739     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 740   }
 741 }
 742 }
 743 }
 744
 745 #undef FLD
 746 }
 747   NEXT (vpc);
 748
 749   CASE (sem, INSN_MOVU_B_R) : /* movu.b movu.m ${Rs},${Rd} */
 750 {
 751   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 752   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 753 #define FLD(f) abuf->fields.sfmt_muls_b.f
 754   int UNUSED written = 0;
 755   IADDR UNUSED pc = abuf->addr;
 756   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 757
 758 {
 759   QI tmp_newval;
 760   tmp_newval = GET_H_GR (FLD (f_operand1));
 761   {
 762     SI opval = ZEXTQISI (tmp_newval);
 763     SET_H_GR (FLD (f_operand2), opval);
 764     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 765   }
 766 {
 767   {
 768     BI opval = LTSI (tmp_newval, 0);
 769     CPU (h_nbit) = opval;
 770     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 771   }
 772   {
 773     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 774     CPU (h_zbit) = opval;
 775     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 776   }
 777 SET_H_CBIT_MOVE (0);
 778 SET_H_VBIT_MOVE (0);
 779 {
 780   {
 781     BI opval = 0;
 782     CPU (h_xbit) = opval;
 783     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 784   }
 785   {
 786     BI opval = 0;
 787     SET_H_INSN_PREFIXED_P (opval);
 788     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 789   }
 790 }
 791 }
 792 }
 793
 794 #undef FLD
 795 }
 796   NEXT (vpc);
 797
 798   CASE (sem, INSN_MOVU_W_R) : /* movu.w movu.m ${Rs},${Rd} */
 799 {
 800   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 801   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 802 #define FLD(f) abuf->fields.sfmt_muls_b.f
 803   int UNUSED written = 0;
 804   IADDR UNUSED pc = abuf->addr;
 805   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 806
 807 {
 808   HI tmp_newval;
 809   tmp_newval = GET_H_GR (FLD (f_operand1));
 810   {
 811     SI opval = ZEXTHISI (tmp_newval);
 812     SET_H_GR (FLD (f_operand2), opval);
 813     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 814   }
 815 {
 816   {
 817     BI opval = LTSI (tmp_newval, 0);
 818     CPU (h_nbit) = opval;
 819     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 820   }
 821   {
 822     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 823     CPU (h_zbit) = opval;
 824     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 825   }
 826 SET_H_CBIT_MOVE (0);
 827 SET_H_VBIT_MOVE (0);
 828 {
 829   {
 830     BI opval = 0;
 831     CPU (h_xbit) = opval;
 832     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 833   }
 834   {
 835     BI opval = 0;
 836     SET_H_INSN_PREFIXED_P (opval);
 837     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 838   }
 839 }
 840 }
 841 }
 842
 843 #undef FLD
 844 }
 845   NEXT (vpc);
 846
 847   CASE (sem, INSN_MOVECBR) : /* move.b ${sconst8},${Rd} */
 848 {
 849   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 850   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 851 #define FLD(f) abuf->fields.sfmt_addcbr.f
 852   int UNUSED written = 0;
 853   IADDR UNUSED pc = abuf->addr;
 854   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 855
 856 {
 857   QI tmp_newval;
 858   tmp_newval = FLD (f_indir_pc__byte);
 859 {
 860   SI tmp_oldregval;
 861   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
 862   {
 863     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
 864     SET_H_GR (FLD (f_operand2), opval);
 865     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 866   }
 867 }
 868 {
 869   {
 870     BI opval = LTQI (tmp_newval, 0);
 871     CPU (h_nbit) = opval;
 872     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 873   }
 874   {
 875     BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 876     CPU (h_zbit) = opval;
 877     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 878   }
 879 SET_H_CBIT_MOVE (0);
 880 SET_H_VBIT_MOVE (0);
 881 {
 882   {
 883     BI opval = 0;
 884     CPU (h_xbit) = opval;
 885     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 886   }
 887   {
 888     BI opval = 0;
 889     SET_H_INSN_PREFIXED_P (opval);
 890     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 891   }
 892 }
 893 }
 894 }
 895
 896 #undef FLD
 897 }
 898   NEXT (vpc);
 899
 900   CASE (sem, INSN_MOVECWR) : /* move.w ${sconst16},${Rd} */
 901 {
 902   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 903   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 904 #define FLD(f) abuf->fields.sfmt_addcwr.f
 905   int UNUSED written = 0;
 906   IADDR UNUSED pc = abuf->addr;
 907   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 908
 909 {
 910   HI tmp_newval;
 911   tmp_newval = FLD (f_indir_pc__word);
 912 {
 913   SI tmp_oldregval;
 914   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
 915   {
 916     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
 917     SET_H_GR (FLD (f_operand2), opval);
 918     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 919   }
 920 }
 921 {
 922   {
 923     BI opval = LTHI (tmp_newval, 0);
 924     CPU (h_nbit) = opval;
 925     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 926   }
 927   {
 928     BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 929     CPU (h_zbit) = opval;
 930     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 931   }
 932 SET_H_CBIT_MOVE (0);
 933 SET_H_VBIT_MOVE (0);
 934 {
 935   {
 936     BI opval = 0;
 937     CPU (h_xbit) = opval;
 938     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 939   }
 940   {
 941     BI opval = 0;
 942     SET_H_INSN_PREFIXED_P (opval);
 943     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 944   }
 945 }
 946 }
 947 }
 948
 949 #undef FLD
 950 }
 951   NEXT (vpc);
 952
 953   CASE (sem, INSN_MOVECDR) : /* move.d ${const32},${Rd} */
 954 {
 955   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 956   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 957 #define FLD(f) abuf->fields.sfmt_bound_cd.f
 958   int UNUSED written = 0;
 959   IADDR UNUSED pc = abuf->addr;
 960   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
 961
 962 {
 963   SI tmp_newval;
 964   tmp_newval = FLD (f_indir_pc__dword);
 965   {
 966     SI opval = tmp_newval;
 967     SET_H_GR (FLD (f_operand2), opval);
 968     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 969   }
 970 {
 971   {
 972     BI opval = LTSI (tmp_newval, 0);
 973     CPU (h_nbit) = opval;
 974     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 975   }
 976   {
 977     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 978     CPU (h_zbit) = opval;
 979     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 980   }
 981 SET_H_CBIT_MOVE (0);
 982 SET_H_VBIT_MOVE (0);
 983 {
 984   {
 985     BI opval = 0;
 986     CPU (h_xbit) = opval;
 987     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 988   }
 989   {
 990     BI opval = 0;
 991     SET_H_INSN_PREFIXED_P (opval);
 992     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 993   }
 994 }
 995 }
 996 }
 997
 998 #undef FLD
 999 }
1000   NEXT (vpc);
1001
1002   CASE (sem, INSN_MOVSCBR) : /* movs.b ${sconst8},${Rd} */
1003 {
1004   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1005   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1006 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1007   int UNUSED written = 0;
1008   IADDR UNUSED pc = abuf->addr;
1009   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1010
1011 {
1012   SI tmp_newval;
1013   tmp_newval = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
1014   {
1015     SI opval = tmp_newval;
1016     SET_H_GR (FLD (f_operand2), opval);
1017     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1018   }
1019 {
1020   {
1021     BI opval = LTSI (tmp_newval, 0);
1022     CPU (h_nbit) = opval;
1023     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1024   }
1025   {
1026     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1027     CPU (h_zbit) = opval;
1028     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1029   }
1030 SET_H_CBIT_MOVE (0);
1031 SET_H_VBIT_MOVE (0);
1032 {
1033   {
1034     BI opval = 0;
1035     CPU (h_xbit) = opval;
1036     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1037   }
1038   {
1039     BI opval = 0;
1040     SET_H_INSN_PREFIXED_P (opval);
1041     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1042   }
1043 }
1044 }
1045 }
1046
1047 #undef FLD
1048 }
1049   NEXT (vpc);
1050
1051   CASE (sem, INSN_MOVSCWR) : /* movs.w ${sconst16},${Rd} */
1052 {
1053   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1054   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1055 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1056   int UNUSED written = 0;
1057   IADDR UNUSED pc = abuf->addr;
1058   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1059
1060 {
1061   SI tmp_newval;
1062   tmp_newval = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
1063   {
1064     SI opval = tmp_newval;
1065     SET_H_GR (FLD (f_operand2), opval);
1066     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1067   }
1068 {
1069   {
1070     BI opval = LTSI (tmp_newval, 0);
1071     CPU (h_nbit) = opval;
1072     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1073   }
1074   {
1075     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1076     CPU (h_zbit) = opval;
1077     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1078   }
1079 SET_H_CBIT_MOVE (0);
1080 SET_H_VBIT_MOVE (0);
1081 {
1082   {
1083     BI opval = 0;
1084     CPU (h_xbit) = opval;
1085     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1086   }
1087   {
1088     BI opval = 0;
1089     SET_H_INSN_PREFIXED_P (opval);
1090     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1091   }
1092 }
1093 }
1094 }
1095
1096 #undef FLD
1097 }
1098   NEXT (vpc);
1099
1100   CASE (sem, INSN_MOVUCBR) : /* movu.b ${uconst8},${Rd} */
1101 {
1102   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1103   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1104 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1105   int UNUSED written = 0;
1106   IADDR UNUSED pc = abuf->addr;
1107   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1108
1109 {
1110   SI tmp_newval;
1111   tmp_newval = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
1112   {
1113     SI opval = tmp_newval;
1114     SET_H_GR (FLD (f_operand2), opval);
1115     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1116   }
1117 {
1118   {
1119     BI opval = LTSI (tmp_newval, 0);
1120     CPU (h_nbit) = opval;
1121     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1122   }
1123   {
1124     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1125     CPU (h_zbit) = opval;
1126     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1127   }
1128 SET_H_CBIT_MOVE (0);
1129 SET_H_VBIT_MOVE (0);
1130 {
1131   {
1132     BI opval = 0;
1133     CPU (h_xbit) = opval;
1134     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1135   }
1136   {
1137     BI opval = 0;
1138     SET_H_INSN_PREFIXED_P (opval);
1139     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1140   }
1141 }
1142 }
1143 }
1144
1145 #undef FLD
1146 }
1147   NEXT (vpc);
1148
1149   CASE (sem, INSN_MOVUCWR) : /* movu.w ${uconst16},${Rd} */
1150 {
1151   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1152   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1153 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1154   int UNUSED written = 0;
1155   IADDR UNUSED pc = abuf->addr;
1156   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1157
1158 {
1159   SI tmp_newval;
1160   tmp_newval = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
1161   {
1162     SI opval = tmp_newval;
1163     SET_H_GR (FLD (f_operand2), opval);
1164     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1165   }
1166 {
1167   {
1168     BI opval = LTSI (tmp_newval, 0);
1169     CPU (h_nbit) = opval;
1170     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1171   }
1172   {
1173     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1174     CPU (h_zbit) = opval;
1175     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1176   }
1177 SET_H_CBIT_MOVE (0);
1178 SET_H_VBIT_MOVE (0);
1179 {
1180   {
1181     BI opval = 0;
1182     CPU (h_xbit) = opval;
1183     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1184   }
1185   {
1186     BI opval = 0;
1187     SET_H_INSN_PREFIXED_P (opval);
1188     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1189   }
1190 }
1191 }
1192 }
1193
1194 #undef FLD
1195 }
1196   NEXT (vpc);
1197
1198   CASE (sem, INSN_ADDQ) : /* addq $j,$Rd */
1199 {
1200   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1201   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1202 #define FLD(f) abuf->fields.sfmt_addq.f
1203   int UNUSED written = 0;
1204   IADDR UNUSED pc = abuf->addr;
1205   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1206
1207 {
1208   SI tmp_tmpopd;
1209   SI tmp_tmpops;
1210   BI tmp_carry;
1211   SI tmp_newval;
1212   tmp_tmpops = FLD (f_u6);
1213   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1214   tmp_carry = CPU (h_cbit);
1215   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1216   {
1217     SI opval = tmp_newval;
1218     SET_H_GR (FLD (f_operand2), opval);
1219     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1220   }
1221 {
1222   {
1223     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
1224     CPU (h_cbit) = opval;
1225     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1226   }
1227   {
1228     BI opval = LTSI (tmp_newval, 0);
1229     CPU (h_nbit) = opval;
1230     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1231   }
1232   {
1233     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1234     CPU (h_zbit) = opval;
1235     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1236   }
1237   {
1238     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1239     CPU (h_vbit) = opval;
1240     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1241   }
1242 {
1243   {
1244     BI opval = 0;
1245     CPU (h_xbit) = opval;
1246     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1247   }
1248   {
1249     BI opval = 0;
1250     SET_H_INSN_PREFIXED_P (opval);
1251     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1252   }
1253 }
1254 }
1255 }
1256
1257 #undef FLD
1258 }
1259   NEXT (vpc);
1260
1261   CASE (sem, INSN_SUBQ) : /* subq $j,$Rd */
1262 {
1263   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1264   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1265 #define FLD(f) abuf->fields.sfmt_addq.f
1266   int UNUSED written = 0;
1267   IADDR UNUSED pc = abuf->addr;
1268   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1269
1270 {
1271   SI tmp_tmpopd;
1272   SI tmp_tmpops;
1273   BI tmp_carry;
1274   SI tmp_newval;
1275   tmp_tmpops = FLD (f_u6);
1276   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1277   tmp_carry = CPU (h_cbit);
1278   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1279   {
1280     SI opval = tmp_newval;
1281     SET_H_GR (FLD (f_operand2), opval);
1282     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1283   }
1284 {
1285   {
1286     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1287     CPU (h_cbit) = opval;
1288     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1289   }
1290   {
1291     BI opval = LTSI (tmp_newval, 0);
1292     CPU (h_nbit) = opval;
1293     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1294   }
1295   {
1296     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1297     CPU (h_zbit) = opval;
1298     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1299   }
1300   {
1301     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1302     CPU (h_vbit) = opval;
1303     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1304   }
1305 {
1306   {
1307     BI opval = 0;
1308     CPU (h_xbit) = opval;
1309     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1310   }
1311   {
1312     BI opval = 0;
1313     SET_H_INSN_PREFIXED_P (opval);
1314     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1315   }
1316 }
1317 }
1318 }
1319
1320 #undef FLD
1321 }
1322   NEXT (vpc);
1323
1324   CASE (sem, INSN_CMP_R_B_R) : /* cmp-r.b $Rs,$Rd */
1325 {
1326   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1327   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1328 #define FLD(f) abuf->fields.sfmt_muls_b.f
1329   int UNUSED written = 0;
1330   IADDR UNUSED pc = abuf->addr;
1331   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1332
1333 {
1334   QI tmp_tmpopd;
1335   QI tmp_tmpops;
1336   BI tmp_carry;
1337   QI tmp_newval;
1338   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1339   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1340   tmp_carry = CPU (h_cbit);
1341   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1342 ((void) 0); /*nop*/
1343 {
1344   {
1345     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1346     CPU (h_cbit) = opval;
1347     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1348   }
1349   {
1350     BI opval = LTQI (tmp_newval, 0);
1351     CPU (h_nbit) = opval;
1352     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1353   }
1354   {
1355     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1356     CPU (h_zbit) = opval;
1357     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1358   }
1359   {
1360     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1361     CPU (h_vbit) = opval;
1362     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1363   }
1364 {
1365   {
1366     BI opval = 0;
1367     CPU (h_xbit) = opval;
1368     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1369   }
1370   {
1371     BI opval = 0;
1372     SET_H_INSN_PREFIXED_P (opval);
1373     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1374   }
1375 }
1376 }
1377 }
1378
1379 #undef FLD
1380 }
1381   NEXT (vpc);
1382
1383   CASE (sem, INSN_CMP_R_W_R) : /* cmp-r.w $Rs,$Rd */
1384 {
1385   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1386   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1387 #define FLD(f) abuf->fields.sfmt_muls_b.f
1388   int UNUSED written = 0;
1389   IADDR UNUSED pc = abuf->addr;
1390   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1391
1392 {
1393   HI tmp_tmpopd;
1394   HI tmp_tmpops;
1395   BI tmp_carry;
1396   HI tmp_newval;
1397   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1398   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1399   tmp_carry = CPU (h_cbit);
1400   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1401 ((void) 0); /*nop*/
1402 {
1403   {
1404     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1405     CPU (h_cbit) = opval;
1406     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1407   }
1408   {
1409     BI opval = LTHI (tmp_newval, 0);
1410     CPU (h_nbit) = opval;
1411     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1412   }
1413   {
1414     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1415     CPU (h_zbit) = opval;
1416     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1417   }
1418   {
1419     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1420     CPU (h_vbit) = opval;
1421     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1422   }
1423 {
1424   {
1425     BI opval = 0;
1426     CPU (h_xbit) = opval;
1427     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1428   }
1429   {
1430     BI opval = 0;
1431     SET_H_INSN_PREFIXED_P (opval);
1432     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1433   }
1434 }
1435 }
1436 }
1437
1438 #undef FLD
1439 }
1440   NEXT (vpc);
1441
1442   CASE (sem, INSN_CMP_R_D_R) : /* cmp-r.d $Rs,$Rd */
1443 {
1444   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1445   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1446 #define FLD(f) abuf->fields.sfmt_muls_b.f
1447   int UNUSED written = 0;
1448   IADDR UNUSED pc = abuf->addr;
1449   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1450
1451 {
1452   SI tmp_tmpopd;
1453   SI tmp_tmpops;
1454   BI tmp_carry;
1455   SI tmp_newval;
1456   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1457   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1458   tmp_carry = CPU (h_cbit);
1459   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1460 ((void) 0); /*nop*/
1461 {
1462   {
1463     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1464     CPU (h_cbit) = opval;
1465     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1466   }
1467   {
1468     BI opval = LTSI (tmp_newval, 0);
1469     CPU (h_nbit) = opval;
1470     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1471   }
1472   {
1473     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1474     CPU (h_zbit) = opval;
1475     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1476   }
1477   {
1478     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1479     CPU (h_vbit) = opval;
1480     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1481   }
1482 {
1483   {
1484     BI opval = 0;
1485     CPU (h_xbit) = opval;
1486     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1487   }
1488   {
1489     BI opval = 0;
1490     SET_H_INSN_PREFIXED_P (opval);
1491     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1492   }
1493 }
1494 }
1495 }
1496
1497 #undef FLD
1498 }
1499   NEXT (vpc);
1500
1501   CASE (sem, INSN_CMP_M_B_M) : /* cmp-m.b [${Rs}${inc}],${Rd} */
1502 {
1503   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1504   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1505 #define FLD(f) abuf->fields.sfmt_addc_m.f
1506   int UNUSED written = 0;
1507   IADDR UNUSED pc = abuf->addr;
1508   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1509
1510 {
1511   QI tmp_tmpopd;
1512   QI tmp_tmpops;
1513   BI tmp_carry;
1514   QI tmp_newval;
1515   tmp_tmpops = ({   SI tmp_addr;
1516   QI tmp_tmp_mem;
1517   BI tmp_postinc;
1518   tmp_postinc = FLD (f_memmode);
1519 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
1520 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
1521 ; if (NEBI (tmp_postinc, 0)) {
1522 {
1523 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1524   tmp_addr = ADDSI (tmp_addr, 1);
1525 }
1526   {
1527     SI opval = tmp_addr;
1528     SET_H_GR (FLD (f_operand1), opval);
1529     written |= (1 << 9);
1530     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1531   }
1532 }
1533 }
1534 ; tmp_tmp_mem; });
1535   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1536   tmp_carry = CPU (h_cbit);
1537   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1538 ((void) 0); /*nop*/
1539 {
1540   {
1541     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1542     CPU (h_cbit) = opval;
1543     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1544   }
1545   {
1546     BI opval = LTQI (tmp_newval, 0);
1547     CPU (h_nbit) = opval;
1548     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1549   }
1550   {
1551     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1552     CPU (h_zbit) = opval;
1553     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1554   }
1555   {
1556     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1557     CPU (h_vbit) = opval;
1558     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1559   }
1560 {
1561   {
1562     BI opval = 0;
1563     CPU (h_xbit) = opval;
1564     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1565   }
1566   {
1567     BI opval = 0;
1568     SET_H_INSN_PREFIXED_P (opval);
1569     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1570   }
1571 }
1572 }
1573 }
1574
1575   abuf->written = written;
1576 #undef FLD
1577 }
1578   NEXT (vpc);
1579
1580   CASE (sem, INSN_CMP_M_W_M) : /* cmp-m.w [${Rs}${inc}],${Rd} */
1581 {
1582   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1583   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1584 #define FLD(f) abuf->fields.sfmt_addc_m.f
1585   int UNUSED written = 0;
1586   IADDR UNUSED pc = abuf->addr;
1587   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1588
1589 {
1590   HI tmp_tmpopd;
1591   HI tmp_tmpops;
1592   BI tmp_carry;
1593   HI tmp_newval;
1594   tmp_tmpops = ({   SI tmp_addr;
1595   HI tmp_tmp_mem;
1596   BI tmp_postinc;
1597   tmp_postinc = FLD (f_memmode);
1598 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
1599 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
1600 ; if (NEBI (tmp_postinc, 0)) {
1601 {
1602 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1603   tmp_addr = ADDSI (tmp_addr, 2);
1604 }
1605   {
1606     SI opval = tmp_addr;
1607     SET_H_GR (FLD (f_operand1), opval);
1608     written |= (1 << 9);
1609     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1610   }
1611 }
1612 }
1613 ; tmp_tmp_mem; });
1614   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1615   tmp_carry = CPU (h_cbit);
1616   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1617 ((void) 0); /*nop*/
1618 {
1619   {
1620     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1621     CPU (h_cbit) = opval;
1622     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1623   }
1624   {
1625     BI opval = LTHI (tmp_newval, 0);
1626     CPU (h_nbit) = opval;
1627     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1628   }
1629   {
1630     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1631     CPU (h_zbit) = opval;
1632     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1633   }
1634   {
1635     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1636     CPU (h_vbit) = opval;
1637     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1638   }
1639 {
1640   {
1641     BI opval = 0;
1642     CPU (h_xbit) = opval;
1643     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1644   }
1645   {
1646     BI opval = 0;
1647     SET_H_INSN_PREFIXED_P (opval);
1648     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1649   }
1650 }
1651 }
1652 }
1653
1654   abuf->written = written;
1655 #undef FLD
1656 }
1657   NEXT (vpc);
1658
1659   CASE (sem, INSN_CMP_M_D_M) : /* cmp-m.d [${Rs}${inc}],${Rd} */
1660 {
1661   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1662   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1663 #define FLD(f) abuf->fields.sfmt_addc_m.f
1664   int UNUSED written = 0;
1665   IADDR UNUSED pc = abuf->addr;
1666   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1667
1668 {
1669   SI tmp_tmpopd;
1670   SI tmp_tmpops;
1671   BI tmp_carry;
1672   SI tmp_newval;
1673   tmp_tmpops = ({   SI tmp_addr;
1674   SI tmp_tmp_mem;
1675   BI tmp_postinc;
1676   tmp_postinc = FLD (f_memmode);
1677 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
1678 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
1679 ; if (NEBI (tmp_postinc, 0)) {
1680 {
1681 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1682   tmp_addr = ADDSI (tmp_addr, 4);
1683 }
1684   {
1685     SI opval = tmp_addr;
1686     SET_H_GR (FLD (f_operand1), opval);
1687     written |= (1 << 9);
1688     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1689   }
1690 }
1691 }
1692 ; tmp_tmp_mem; });
1693   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1694   tmp_carry = CPU (h_cbit);
1695   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1696 ((void) 0); /*nop*/
1697 {
1698   {
1699     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1700     CPU (h_cbit) = opval;
1701     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1702   }
1703   {
1704     BI opval = LTSI (tmp_newval, 0);
1705     CPU (h_nbit) = opval;
1706     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1707   }
1708   {
1709     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1710     CPU (h_zbit) = opval;
1711     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1712   }
1713   {
1714     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1715     CPU (h_vbit) = opval;
1716     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1717   }
1718 {
1719   {
1720     BI opval = 0;
1721     CPU (h_xbit) = opval;
1722     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1723   }
1724   {
1725     BI opval = 0;
1726     SET_H_INSN_PREFIXED_P (opval);
1727     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1728   }
1729 }
1730 }
1731 }
1732
1733   abuf->written = written;
1734 #undef FLD
1735 }
1736   NEXT (vpc);
1737
1738   CASE (sem, INSN_CMPCBR) : /* cmp.b $sconst8,$Rd */
1739 {
1740   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1741   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1742 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1743   int UNUSED written = 0;
1744   IADDR UNUSED pc = abuf->addr;
1745   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1746
1747 {
1748   QI tmp_tmpopd;
1749   QI tmp_tmpops;
1750   BI tmp_carry;
1751   QI tmp_newval;
1752   tmp_tmpops = TRUNCSIQI (FLD (f_indir_pc__byte));
1753   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1754   tmp_carry = CPU (h_cbit);
1755   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1756 ((void) 0); /*nop*/
1757 {
1758   {
1759     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1760     CPU (h_cbit) = opval;
1761     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1762   }
1763   {
1764     BI opval = LTQI (tmp_newval, 0);
1765     CPU (h_nbit) = opval;
1766     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1767   }
1768   {
1769     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1770     CPU (h_zbit) = opval;
1771     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1772   }
1773   {
1774     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1775     CPU (h_vbit) = opval;
1776     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1777   }
1778 {
1779   {
1780     BI opval = 0;
1781     CPU (h_xbit) = opval;
1782     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1783   }
1784   {
1785     BI opval = 0;
1786     SET_H_INSN_PREFIXED_P (opval);
1787     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1788   }
1789 }
1790 }
1791 }
1792
1793 #undef FLD
1794 }
1795   NEXT (vpc);
1796
1797   CASE (sem, INSN_CMPCWR) : /* cmp.w $sconst16,$Rd */
1798 {
1799   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1800   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1801 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1802   int UNUSED written = 0;
1803   IADDR UNUSED pc = abuf->addr;
1804   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1805
1806 {
1807   HI tmp_tmpopd;
1808   HI tmp_tmpops;
1809   BI tmp_carry;
1810   HI tmp_newval;
1811   tmp_tmpops = TRUNCSIHI (FLD (f_indir_pc__word));
1812   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1813   tmp_carry = CPU (h_cbit);
1814   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1815 ((void) 0); /*nop*/
1816 {
1817   {
1818     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1819     CPU (h_cbit) = opval;
1820     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1821   }
1822   {
1823     BI opval = LTHI (tmp_newval, 0);
1824     CPU (h_nbit) = opval;
1825     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1826   }
1827   {
1828     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1829     CPU (h_zbit) = opval;
1830     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1831   }
1832   {
1833     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1834     CPU (h_vbit) = opval;
1835     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1836   }
1837 {
1838   {
1839     BI opval = 0;
1840     CPU (h_xbit) = opval;
1841     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1842   }
1843   {
1844     BI opval = 0;
1845     SET_H_INSN_PREFIXED_P (opval);
1846     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1847   }
1848 }
1849 }
1850 }
1851
1852 #undef FLD
1853 }
1854   NEXT (vpc);
1855
1856   CASE (sem, INSN_CMPCDR) : /* cmp.d $const32,$Rd */
1857 {
1858   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1859   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1860 #define FLD(f) abuf->fields.sfmt_bound_cd.f
1861   int UNUSED written = 0;
1862   IADDR UNUSED pc = abuf->addr;
1863   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
1864
1865 {
1866   SI tmp_tmpopd;
1867   SI tmp_tmpops;
1868   BI tmp_carry;
1869   SI tmp_newval;
1870   tmp_tmpops = FLD (f_indir_pc__dword);
1871   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1872   tmp_carry = CPU (h_cbit);
1873   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1874 ((void) 0); /*nop*/
1875 {
1876   {
1877     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1878     CPU (h_cbit) = opval;
1879     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1880   }
1881   {
1882     BI opval = LTSI (tmp_newval, 0);
1883     CPU (h_nbit) = opval;
1884     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1885   }
1886   {
1887     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1888     CPU (h_zbit) = opval;
1889     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1890   }
1891   {
1892     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1893     CPU (h_vbit) = opval;
1894     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1895   }
1896 {
1897   {
1898     BI opval = 0;
1899     CPU (h_xbit) = opval;
1900     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1901   }
1902   {
1903     BI opval = 0;
1904     SET_H_INSN_PREFIXED_P (opval);
1905     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1906   }
1907 }
1908 }
1909 }
1910
1911 #undef FLD
1912 }
1913   NEXT (vpc);
1914
1915   CASE (sem, INSN_CMPQ) : /* cmpq $i,$Rd */
1916 {
1917   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1918   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1919 #define FLD(f) abuf->fields.sfmt_andq.f
1920   int UNUSED written = 0;
1921   IADDR UNUSED pc = abuf->addr;
1922   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1923
1924 {
1925   SI tmp_tmpopd;
1926   SI tmp_tmpops;
1927   BI tmp_carry;
1928   SI tmp_newval;
1929   tmp_tmpops = FLD (f_s6);
1930   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1931   tmp_carry = CPU (h_cbit);
1932   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1933 ((void) 0); /*nop*/
1934 {
1935   {
1936     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1937     CPU (h_cbit) = opval;
1938     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1939   }
1940   {
1941     BI opval = LTSI (tmp_newval, 0);
1942     CPU (h_nbit) = opval;
1943     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1944   }
1945   {
1946     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1947     CPU (h_zbit) = opval;
1948     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1949   }
1950   {
1951     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1952     CPU (h_vbit) = opval;
1953     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1954   }
1955 {
1956   {
1957     BI opval = 0;
1958     CPU (h_xbit) = opval;
1959     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1960   }
1961   {
1962     BI opval = 0;
1963     SET_H_INSN_PREFIXED_P (opval);
1964     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1965   }
1966 }
1967 }
1968 }
1969
1970 #undef FLD
1971 }
1972   NEXT (vpc);
1973
1974   CASE (sem, INSN_CMPS_M_B_M) : /* cmps-m.b [${Rs}${inc}],$Rd */
1975 {
1976   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1977   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1978 #define FLD(f) abuf->fields.sfmt_addc_m.f
1979   int UNUSED written = 0;
1980   IADDR UNUSED pc = abuf->addr;
1981   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1982
1983 {
1984   SI tmp_tmpopd;
1985   SI tmp_tmpops;
1986   BI tmp_carry;
1987   SI tmp_newval;
1988   tmp_tmpops = EXTQISI (({   SI tmp_addr;
1989   QI tmp_tmp_mem;
1990   BI tmp_postinc;
1991   tmp_postinc = FLD (f_memmode);
1992 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
1993 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
1994 ; if (NEBI (tmp_postinc, 0)) {
1995 {
1996 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1997   tmp_addr = ADDSI (tmp_addr, 1);
1998 }
1999   {
2000     SI opval = tmp_addr;
2001     SET_H_GR (FLD (f_operand1), opval);
2002     written |= (1 << 9);
2003     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2004   }
2005 }
2006 }
2007 ; tmp_tmp_mem; }));
2008   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2009   tmp_carry = CPU (h_cbit);
2010   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2011 ((void) 0); /*nop*/
2012 {
2013   {
2014     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2015     CPU (h_cbit) = opval;
2016     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2017   }
2018   {
2019     BI opval = LTSI (tmp_newval, 0);
2020     CPU (h_nbit) = opval;
2021     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2022   }
2023   {
2024     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2025     CPU (h_zbit) = opval;
2026     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2027   }
2028   {
2029     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2030     CPU (h_vbit) = opval;
2031     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2032   }
2033 {
2034   {
2035     BI opval = 0;
2036     CPU (h_xbit) = opval;
2037     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2038   }
2039   {
2040     BI opval = 0;
2041     SET_H_INSN_PREFIXED_P (opval);
2042     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2043   }
2044 }
2045 }
2046 }
2047
2048   abuf->written = written;
2049 #undef FLD
2050 }
2051   NEXT (vpc);
2052
2053   CASE (sem, INSN_CMPS_M_W_M) : /* cmps-m.w [${Rs}${inc}],$Rd */
2054 {
2055   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2056   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2057 #define FLD(f) abuf->fields.sfmt_addc_m.f
2058   int UNUSED written = 0;
2059   IADDR UNUSED pc = abuf->addr;
2060   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2061
2062 {
2063   SI tmp_tmpopd;
2064   SI tmp_tmpops;
2065   BI tmp_carry;
2066   SI tmp_newval;
2067   tmp_tmpops = EXTHISI (({   SI tmp_addr;
2068   HI tmp_tmp_mem;
2069   BI tmp_postinc;
2070   tmp_postinc = FLD (f_memmode);
2071 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2072 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2073 ; if (NEBI (tmp_postinc, 0)) {
2074 {
2075 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2076   tmp_addr = ADDSI (tmp_addr, 2);
2077 }
2078   {
2079     SI opval = tmp_addr;
2080     SET_H_GR (FLD (f_operand1), opval);
2081     written |= (1 << 9);
2082     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2083   }
2084 }
2085 }
2086 ; tmp_tmp_mem; }));
2087   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2088   tmp_carry = CPU (h_cbit);
2089   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2090 ((void) 0); /*nop*/
2091 {
2092   {
2093     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2094     CPU (h_cbit) = opval;
2095     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2096   }
2097   {
2098     BI opval = LTSI (tmp_newval, 0);
2099     CPU (h_nbit) = opval;
2100     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2101   }
2102   {
2103     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2104     CPU (h_zbit) = opval;
2105     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2106   }
2107   {
2108     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2109     CPU (h_vbit) = opval;
2110     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2111   }
2112 {
2113   {
2114     BI opval = 0;
2115     CPU (h_xbit) = opval;
2116     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2117   }
2118   {
2119     BI opval = 0;
2120     SET_H_INSN_PREFIXED_P (opval);
2121     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2122   }
2123 }
2124 }
2125 }
2126
2127   abuf->written = written;
2128 #undef FLD
2129 }
2130   NEXT (vpc);
2131
2132   CASE (sem, INSN_CMPSCBR) : /* [${Rs}${inc}],$Rd */
2133 {
2134   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2135   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2136 #define FLD(f) abuf->fields.sfmt_bound_cb.f
2137   int UNUSED written = 0;
2138   IADDR UNUSED pc = abuf->addr;
2139   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2140
2141 {
2142   SI tmp_tmpopd;
2143   SI tmp_tmpops;
2144   BI tmp_carry;
2145   SI tmp_newval;
2146   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
2147   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2148   tmp_carry = CPU (h_cbit);
2149   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2150 ((void) 0); /*nop*/
2151 {
2152   {
2153     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2154     CPU (h_cbit) = opval;
2155     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2156   }
2157   {
2158     BI opval = LTSI (tmp_newval, 0);
2159     CPU (h_nbit) = opval;
2160     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2161   }
2162   {
2163     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2164     CPU (h_zbit) = opval;
2165     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2166   }
2167   {
2168     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2169     CPU (h_vbit) = opval;
2170     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2171   }
2172 {
2173   {
2174     BI opval = 0;
2175     CPU (h_xbit) = opval;
2176     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2177   }
2178   {
2179     BI opval = 0;
2180     SET_H_INSN_PREFIXED_P (opval);
2181     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2182   }
2183 }
2184 }
2185 }
2186
2187 #undef FLD
2188 }
2189   NEXT (vpc);
2190
2191   CASE (sem, INSN_CMPSCWR) : /* [${Rs}${inc}],$Rd */
2192 {
2193   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2194   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2195 #define FLD(f) abuf->fields.sfmt_bound_cw.f
2196   int UNUSED written = 0;
2197   IADDR UNUSED pc = abuf->addr;
2198   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2199
2200 {
2201   SI tmp_tmpopd;
2202   SI tmp_tmpops;
2203   BI tmp_carry;
2204   SI tmp_newval;
2205   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
2206   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2207   tmp_carry = CPU (h_cbit);
2208   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2209 ((void) 0); /*nop*/
2210 {
2211   {
2212     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2213     CPU (h_cbit) = opval;
2214     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2215   }
2216   {
2217     BI opval = LTSI (tmp_newval, 0);
2218     CPU (h_nbit) = opval;
2219     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2220   }
2221   {
2222     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2223     CPU (h_zbit) = opval;
2224     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2225   }
2226   {
2227     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2228     CPU (h_vbit) = opval;
2229     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2230   }
2231 {
2232   {
2233     BI opval = 0;
2234     CPU (h_xbit) = opval;
2235     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2236   }
2237   {
2238     BI opval = 0;
2239     SET_H_INSN_PREFIXED_P (opval);
2240     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2241   }
2242 }
2243 }
2244 }
2245
2246 #undef FLD
2247 }
2248   NEXT (vpc);
2249
2250   CASE (sem, INSN_CMPU_M_B_M) : /* cmpu-m.b [${Rs}${inc}],$Rd */
2251 {
2252   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2253   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2254 #define FLD(f) abuf->fields.sfmt_addc_m.f
2255   int UNUSED written = 0;
2256   IADDR UNUSED pc = abuf->addr;
2257   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2258
2259 {
2260   SI tmp_tmpopd;
2261   SI tmp_tmpops;
2262   BI tmp_carry;
2263   SI tmp_newval;
2264   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
2265   QI tmp_tmp_mem;
2266   BI tmp_postinc;
2267   tmp_postinc = FLD (f_memmode);
2268 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2269 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2270 ; if (NEBI (tmp_postinc, 0)) {
2271 {
2272 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2273   tmp_addr = ADDSI (tmp_addr, 1);
2274 }
2275   {
2276     SI opval = tmp_addr;
2277     SET_H_GR (FLD (f_operand1), opval);
2278     written |= (1 << 9);
2279     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2280   }
2281 }
2282 }
2283 ; tmp_tmp_mem; }));
2284   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2285   tmp_carry = CPU (h_cbit);
2286   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2287 ((void) 0); /*nop*/
2288 {
2289   {
2290     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2291     CPU (h_cbit) = opval;
2292     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2293   }
2294   {
2295     BI opval = LTSI (tmp_newval, 0);
2296     CPU (h_nbit) = opval;
2297     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2298   }
2299   {
2300     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2301     CPU (h_zbit) = opval;
2302     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2303   }
2304   {
2305     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2306     CPU (h_vbit) = opval;
2307     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2308   }
2309 {
2310   {
2311     BI opval = 0;
2312     CPU (h_xbit) = opval;
2313     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2314   }
2315   {
2316     BI opval = 0;
2317     SET_H_INSN_PREFIXED_P (opval);
2318     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2319   }
2320 }
2321 }
2322 }
2323
2324   abuf->written = written;
2325 #undef FLD
2326 }
2327   NEXT (vpc);
2328
2329   CASE (sem, INSN_CMPU_M_W_M) : /* cmpu-m.w [${Rs}${inc}],$Rd */
2330 {
2331   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2332   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2333 #define FLD(f) abuf->fields.sfmt_addc_m.f
2334   int UNUSED written = 0;
2335   IADDR UNUSED pc = abuf->addr;
2336   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2337
2338 {
2339   SI tmp_tmpopd;
2340   SI tmp_tmpops;
2341   BI tmp_carry;
2342   SI tmp_newval;
2343   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
2344   HI tmp_tmp_mem;
2345   BI tmp_postinc;
2346   tmp_postinc = FLD (f_memmode);
2347 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2348 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2349 ; if (NEBI (tmp_postinc, 0)) {
2350 {
2351 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2352   tmp_addr = ADDSI (tmp_addr, 2);
2353 }
2354   {
2355     SI opval = tmp_addr;
2356     SET_H_GR (FLD (f_operand1), opval);
2357     written |= (1 << 9);
2358     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2359   }
2360 }
2361 }
2362 ; tmp_tmp_mem; }));
2363   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2364   tmp_carry = CPU (h_cbit);
2365   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2366 ((void) 0); /*nop*/
2367 {
2368   {
2369     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2370     CPU (h_cbit) = opval;
2371     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2372   }
2373   {
2374     BI opval = LTSI (tmp_newval, 0);
2375     CPU (h_nbit) = opval;
2376     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2377   }
2378   {
2379     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2380     CPU (h_zbit) = opval;
2381     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2382   }
2383   {
2384     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2385     CPU (h_vbit) = opval;
2386     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2387   }
2388 {
2389   {
2390     BI opval = 0;
2391     CPU (h_xbit) = opval;
2392     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2393   }
2394   {
2395     BI opval = 0;
2396     SET_H_INSN_PREFIXED_P (opval);
2397     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2398   }
2399 }
2400 }
2401 }
2402
2403   abuf->written = written;
2404 #undef FLD
2405 }
2406   NEXT (vpc);
2407
2408   CASE (sem, INSN_CMPUCBR) : /* [${Rs}${inc}],$Rd */
2409 {
2410   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2411   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2412 #define FLD(f) abuf->fields.sfmt_bound_cb.f
2413   int UNUSED written = 0;
2414   IADDR UNUSED pc = abuf->addr;
2415   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2416
2417 {
2418   SI tmp_tmpopd;
2419   SI tmp_tmpops;
2420   BI tmp_carry;
2421   SI tmp_newval;
2422   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
2423   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2424   tmp_carry = CPU (h_cbit);
2425   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2426 ((void) 0); /*nop*/
2427 {
2428   {
2429     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2430     CPU (h_cbit) = opval;
2431     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2432   }
2433   {
2434     BI opval = LTSI (tmp_newval, 0);
2435     CPU (h_nbit) = opval;
2436     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2437   }
2438   {
2439     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2440     CPU (h_zbit) = opval;
2441     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2442   }
2443   {
2444     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2445     CPU (h_vbit) = opval;
2446     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2447   }
2448 {
2449   {
2450     BI opval = 0;
2451     CPU (h_xbit) = opval;
2452     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2453   }
2454   {
2455     BI opval = 0;
2456     SET_H_INSN_PREFIXED_P (opval);
2457     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2458   }
2459 }
2460 }
2461 }
2462
2463 #undef FLD
2464 }
2465   NEXT (vpc);
2466
2467   CASE (sem, INSN_CMPUCWR) : /* [${Rs}${inc}],$Rd */
2468 {
2469   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2470   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2471 #define FLD(f) abuf->fields.sfmt_bound_cw.f
2472   int UNUSED written = 0;
2473   IADDR UNUSED pc = abuf->addr;
2474   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2475
2476 {
2477   SI tmp_tmpopd;
2478   SI tmp_tmpops;
2479   BI tmp_carry;
2480   SI tmp_newval;
2481   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
2482   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2483   tmp_carry = CPU (h_cbit);
2484   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2485 ((void) 0); /*nop*/
2486 {
2487   {
2488     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2489     CPU (h_cbit) = opval;
2490     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2491   }
2492   {
2493     BI opval = LTSI (tmp_newval, 0);
2494     CPU (h_nbit) = opval;
2495     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2496   }
2497   {
2498     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2499     CPU (h_zbit) = opval;
2500     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2501   }
2502   {
2503     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2504     CPU (h_vbit) = opval;
2505     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2506   }
2507 {
2508   {
2509     BI opval = 0;
2510     CPU (h_xbit) = opval;
2511     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2512   }
2513   {
2514     BI opval = 0;
2515     SET_H_INSN_PREFIXED_P (opval);
2516     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2517   }
2518 }
2519 }
2520 }
2521
2522 #undef FLD
2523 }
2524   NEXT (vpc);
2525
2526   CASE (sem, INSN_MOVE_M_B_M) : /* move-m.b [${Rs}${inc}],${Rd} */
2527 {
2528   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2529   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2530 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2531   int UNUSED written = 0;
2532   IADDR UNUSED pc = abuf->addr;
2533   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2534
2535 {
2536   SI tmp_tmp;
2537   tmp_tmp = ({   SI tmp_addr;
2538   QI tmp_tmp_mem;
2539   BI tmp_postinc;
2540   tmp_postinc = FLD (f_memmode);
2541 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2542 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2543 ; if (NEBI (tmp_postinc, 0)) {
2544 {
2545 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2546   tmp_addr = ADDSI (tmp_addr, 1);
2547 }
2548   {
2549     SI opval = tmp_addr;
2550     SET_H_GR (FLD (f_operand1), opval);
2551     written |= (1 << 10);
2552     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2553   }
2554 }
2555 }
2556 ; tmp_tmp_mem; });
2557 {
2558   SI tmp_oldregval;
2559   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
2560   {
2561     SI opval = ORSI (ANDSI (tmp_tmp, 255), ANDSI (tmp_oldregval, 0xffffff00));
2562     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2563     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2564   }
2565 }
2566 {
2567   {
2568     BI opval = LTQI (tmp_tmp, 0);
2569     CPU (h_nbit) = opval;
2570     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2571   }
2572   {
2573     BI opval = ANDIF (EQQI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2574     CPU (h_zbit) = opval;
2575     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2576   }
2577 SET_H_CBIT_MOVE (0);
2578 SET_H_VBIT_MOVE (0);
2579 {
2580   {
2581     BI opval = 0;
2582     CPU (h_xbit) = opval;
2583     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2584   }
2585   {
2586     BI opval = 0;
2587     SET_H_INSN_PREFIXED_P (opval);
2588     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2589   }
2590 }
2591 }
2592 }
2593
2594   abuf->written = written;
2595 #undef FLD
2596 }
2597   NEXT (vpc);
2598
2599   CASE (sem, INSN_MOVE_M_W_M) : /* move-m.w [${Rs}${inc}],${Rd} */
2600 {
2601   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2602   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2603 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2604   int UNUSED written = 0;
2605   IADDR UNUSED pc = abuf->addr;
2606   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2607
2608 {
2609   SI tmp_tmp;
2610   tmp_tmp = ({   SI tmp_addr;
2611   HI tmp_tmp_mem;
2612   BI tmp_postinc;
2613   tmp_postinc = FLD (f_memmode);
2614 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2615 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2616 ; if (NEBI (tmp_postinc, 0)) {
2617 {
2618 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2619   tmp_addr = ADDSI (tmp_addr, 2);
2620 }
2621   {
2622     SI opval = tmp_addr;
2623     SET_H_GR (FLD (f_operand1), opval);
2624     written |= (1 << 10);
2625     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2626   }
2627 }
2628 }
2629 ; tmp_tmp_mem; });
2630 {
2631   SI tmp_oldregval;
2632   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
2633   {
2634     SI opval = ORSI (ANDSI (tmp_tmp, 65535), ANDSI (tmp_oldregval, 0xffff0000));
2635     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2636     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2637   }
2638 }
2639 {
2640   {
2641     BI opval = LTHI (tmp_tmp, 0);
2642     CPU (h_nbit) = opval;
2643     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2644   }
2645   {
2646     BI opval = ANDIF (EQHI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2647     CPU (h_zbit) = opval;
2648     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2649   }
2650 SET_H_CBIT_MOVE (0);
2651 SET_H_VBIT_MOVE (0);
2652 {
2653   {
2654     BI opval = 0;
2655     CPU (h_xbit) = opval;
2656     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2657   }
2658   {
2659     BI opval = 0;
2660     SET_H_INSN_PREFIXED_P (opval);
2661     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2662   }
2663 }
2664 }
2665 }
2666
2667   abuf->written = written;
2668 #undef FLD
2669 }
2670   NEXT (vpc);
2671
2672   CASE (sem, INSN_MOVE_M_D_M) : /* move-m.d [${Rs}${inc}],${Rd} */
2673 {
2674   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2675   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2676 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2677   int UNUSED written = 0;
2678   IADDR UNUSED pc = abuf->addr;
2679   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2680
2681 {
2682   SI tmp_tmp;
2683   tmp_tmp = ({   SI tmp_addr;
2684   SI tmp_tmp_mem;
2685   BI tmp_postinc;
2686   tmp_postinc = FLD (f_memmode);
2687 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2688 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
2689 ; if (NEBI (tmp_postinc, 0)) {
2690 {
2691 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2692   tmp_addr = ADDSI (tmp_addr, 4);
2693 }
2694   {
2695     SI opval = tmp_addr;
2696     SET_H_GR (FLD (f_operand1), opval);
2697     written |= (1 << 9);
2698     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2699   }
2700 }
2701 }
2702 ; tmp_tmp_mem; });
2703   {
2704     SI opval = tmp_tmp;
2705     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2706     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2707   }
2708 {
2709   {
2710     BI opval = LTSI (tmp_tmp, 0);
2711     CPU (h_nbit) = opval;
2712     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2713   }
2714   {
2715     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2716     CPU (h_zbit) = opval;
2717     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2718   }
2719 SET_H_CBIT_MOVE (0);
2720 SET_H_VBIT_MOVE (0);
2721 {
2722   {
2723     BI opval = 0;
2724     CPU (h_xbit) = opval;
2725     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2726   }
2727   {
2728     BI opval = 0;
2729     SET_H_INSN_PREFIXED_P (opval);
2730     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2731   }
2732 }
2733 }
2734 }
2735
2736   abuf->written = written;
2737 #undef FLD
2738 }
2739   NEXT (vpc);
2740
2741   CASE (sem, INSN_MOVS_M_B_M) : /* movs-m.b [${Rs}${inc}],${Rd} */
2742 {
2743   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2744   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2745 #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
2746   int UNUSED written = 0;
2747   IADDR UNUSED pc = abuf->addr;
2748   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2749
2750 {
2751   SI tmp_tmp;
2752   tmp_tmp = EXTQISI (({   SI tmp_addr;
2753   QI tmp_tmp_mem;
2754   BI tmp_postinc;
2755   tmp_postinc = FLD (f_memmode);
2756 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2757 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2758 ; if (NEBI (tmp_postinc, 0)) {
2759 {
2760 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2761   tmp_addr = ADDSI (tmp_addr, 1);
2762 }
2763   {
2764     SI opval = tmp_addr;
2765     SET_H_GR (FLD (f_operand1), opval);
2766     written |= (1 << 8);
2767     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2768   }
2769 }
2770 }
2771 ; tmp_tmp_mem; }));
2772 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2773   {
2774     SI opval = tmp_tmp;
2775     SET_H_GR (FLD (f_operand1), opval);
2776     written |= (1 << 8);
2777     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2778   }
2779 } else {
2780   {
2781     SI opval = tmp_tmp;
2782     SET_H_GR (FLD (f_operand2), opval);
2783     written |= (1 << 7);
2784     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2785   }
2786 }
2787 {
2788   {
2789     BI opval = LTSI (tmp_tmp, 0);
2790     CPU (h_nbit) = opval;
2791     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2792   }
2793   {
2794     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2795     CPU (h_zbit) = opval;
2796     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2797   }
2798 SET_H_CBIT_MOVE (0);
2799 SET_H_VBIT_MOVE (0);
2800 {
2801   {
2802     BI opval = 0;
2803     CPU (h_xbit) = opval;
2804     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2805   }
2806   {
2807     BI opval = 0;
2808     SET_H_INSN_PREFIXED_P (opval);
2809     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2810   }
2811 }
2812 }
2813 }
2814
2815   abuf->written = written;
2816 #undef FLD
2817 }
2818   NEXT (vpc);
2819
2820   CASE (sem, INSN_MOVS_M_W_M) : /* movs-m.w [${Rs}${inc}],${Rd} */
2821 {
2822   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2823   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2824 #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
2825   int UNUSED written = 0;
2826   IADDR UNUSED pc = abuf->addr;
2827   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2828
2829 {
2830   SI tmp_tmp;
2831   tmp_tmp = EXTHISI (({   SI tmp_addr;
2832   HI tmp_tmp_mem;
2833   BI tmp_postinc;
2834   tmp_postinc = FLD (f_memmode);
2835 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2836 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2837 ; if (NEBI (tmp_postinc, 0)) {
2838 {
2839 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2840   tmp_addr = ADDSI (tmp_addr, 2);
2841 }
2842   {
2843     SI opval = tmp_addr;
2844     SET_H_GR (FLD (f_operand1), opval);
2845     written |= (1 << 8);
2846     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2847   }
2848 }
2849 }
2850 ; tmp_tmp_mem; }));
2851 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2852   {
2853     SI opval = tmp_tmp;
2854     SET_H_GR (FLD (f_operand1), opval);
2855     written |= (1 << 8);
2856     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2857   }
2858 } else {
2859   {
2860     SI opval = tmp_tmp;
2861     SET_H_GR (FLD (f_operand2), opval);
2862     written |= (1 << 7);
2863     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2864   }
2865 }
2866 {
2867   {
2868     BI opval = LTSI (tmp_tmp, 0);
2869     CPU (h_nbit) = opval;
2870     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2871   }
2872   {
2873     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2874     CPU (h_zbit) = opval;
2875     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2876   }
2877 SET_H_CBIT_MOVE (0);
2878 SET_H_VBIT_MOVE (0);
2879 {
2880   {
2881     BI opval = 0;
2882     CPU (h_xbit) = opval;
2883     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2884   }
2885   {
2886     BI opval = 0;
2887     SET_H_INSN_PREFIXED_P (opval);
2888     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2889   }
2890 }
2891 }
2892 }
2893
2894   abuf->written = written;
2895 #undef FLD
2896 }
2897   NEXT (vpc);
2898
2899   CASE (sem, INSN_MOVU_M_B_M) : /* movu-m.b [${Rs}${inc}],${Rd} */
2900 {
2901   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2902   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2903 #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
2904   int UNUSED written = 0;
2905   IADDR UNUSED pc = abuf->addr;
2906   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2907
2908 {
2909   SI tmp_tmp;
2910   tmp_tmp = ZEXTQISI (({   SI tmp_addr;
2911   QI tmp_tmp_mem;
2912   BI tmp_postinc;
2913   tmp_postinc = FLD (f_memmode);
2914 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2915 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2916 ; if (NEBI (tmp_postinc, 0)) {
2917 {
2918 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2919   tmp_addr = ADDSI (tmp_addr, 1);
2920 }
2921   {
2922     SI opval = tmp_addr;
2923     SET_H_GR (FLD (f_operand1), opval);
2924     written |= (1 << 8);
2925     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2926   }
2927 }
2928 }
2929 ; tmp_tmp_mem; }));
2930 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2931   {
2932     SI opval = tmp_tmp;
2933     SET_H_GR (FLD (f_operand1), opval);
2934     written |= (1 << 8);
2935     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2936   }
2937 } else {
2938   {
2939     SI opval = tmp_tmp;
2940     SET_H_GR (FLD (f_operand2), opval);
2941     written |= (1 << 7);
2942     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2943   }
2944 }
2945 {
2946   {
2947     BI opval = LTSI (tmp_tmp, 0);
2948     CPU (h_nbit) = opval;
2949     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2950   }
2951   {
2952     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2953     CPU (h_zbit) = opval;
2954     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2955   }
2956 SET_H_CBIT_MOVE (0);
2957 SET_H_VBIT_MOVE (0);
2958 {
2959   {
2960     BI opval = 0;
2961     CPU (h_xbit) = opval;
2962     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2963   }
2964   {
2965     BI opval = 0;
2966     SET_H_INSN_PREFIXED_P (opval);
2967     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2968   }
2969 }
2970 }
2971 }
2972
2973   abuf->written = written;
2974 #undef FLD
2975 }
2976   NEXT (vpc);
2977
2978   CASE (sem, INSN_MOVU_M_W_M) : /* movu-m.w [${Rs}${inc}],${Rd} */
2979 {
2980   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2981   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2982 #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
2983   int UNUSED written = 0;
2984   IADDR UNUSED pc = abuf->addr;
2985   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2986
2987 {
2988   SI tmp_tmp;
2989   tmp_tmp = ZEXTHISI (({   SI tmp_addr;
2990   HI tmp_tmp_mem;
2991   BI tmp_postinc;
2992   tmp_postinc = FLD (f_memmode);
2993 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2994 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2995 ; if (NEBI (tmp_postinc, 0)) {
2996 {
2997 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2998   tmp_addr = ADDSI (tmp_addr, 2);
2999 }
3000   {
3001     SI opval = tmp_addr;
3002     SET_H_GR (FLD (f_operand1), opval);
3003     written |= (1 << 8);
3004     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3005   }
3006 }
3007 }
3008 ; tmp_tmp_mem; }));
3009 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
3010   {
3011     SI opval = tmp_tmp;
3012     SET_H_GR (FLD (f_operand1), opval);
3013     written |= (1 << 8);
3014     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3015   }
3016 } else {
3017   {
3018     SI opval = tmp_tmp;
3019     SET_H_GR (FLD (f_operand2), opval);
3020     written |= (1 << 7);
3021     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3022   }
3023 }
3024 {
3025   {
3026     BI opval = LTSI (tmp_tmp, 0);
3027     CPU (h_nbit) = opval;
3028     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
3029   }
3030   {
3031     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
3032     CPU (h_zbit) = opval;
3033     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
3034   }
3035 SET_H_CBIT_MOVE (0);
3036 SET_H_VBIT_MOVE (0);
3037 {
3038   {
3039     BI opval = 0;
3040     CPU (h_xbit) = opval;
3041     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3042   }
3043   {
3044     BI opval = 0;
3045     SET_H_INSN_PREFIXED_P (opval);
3046     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3047   }
3048 }
3049 }
3050 }
3051
3052   abuf->written = written;
3053 #undef FLD
3054 }
3055   NEXT (vpc);
3056
3057   CASE (sem, INSN_MOVE_R_SPRV32) : /* move ${Rs},${Pd} */
3058 {
3059   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3060   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3061 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
3062   int UNUSED written = 0;
3063   IADDR UNUSED pc = abuf->addr;
3064   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3065
3066 {
3067   SI tmp_tmp;
3068   SI tmp_rno;
3069   tmp_tmp = GET_H_GR (FLD (f_operand1));
3070   tmp_rno = FLD (f_operand2);
3071 if (ORIF (ORIF (EQSI (tmp_rno, 0), EQSI (tmp_rno, 1)), ORIF (EQSI (tmp_rno, 4), EQSI (tmp_rno, 8)))) {
3072 cgen_rtx_error (current_cpu, "move-r-spr: trying to set a read-only special register");
3073 }
3074  else {
3075   {
3076     SI opval = tmp_tmp;
3077     SET_H_SR (FLD (f_operand2), opval);
3078     written |= (1 << 2);
3079     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3080   }
3081 }
3082 {
3083   {
3084     BI opval = 0;
3085     CPU (h_xbit) = opval;
3086     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3087   }
3088   {
3089     BI opval = 0;
3090     SET_H_INSN_PREFIXED_P (opval);
3091     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3092   }
3093 }
3094 }
3095
3096   abuf->written = written;
3097 #undef FLD
3098 }
3099   NEXT (vpc);
3100
3101   CASE (sem, INSN_MOVE_SPR_RV32) : /* move ${Ps},${Rd-sfield} */
3102 {
3103   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3104   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3105 #define FLD(f) abuf->fields.sfmt_mcp.f
3106   int UNUSED written = 0;
3107   IADDR UNUSED pc = abuf->addr;
3108   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3109
3110 {
3111   SI tmp_grno;
3112   SI tmp_prno;
3113   SI tmp_newval;
3114   tmp_prno = FLD (f_operand2);
3115   tmp_newval = GET_H_SR (FLD (f_operand2));
3116 if (EQSI (tmp_prno, 0)) {
3117 {
3118   SI tmp_oldregval;
3119   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3120   {
3121     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3122     SET_H_GR (FLD (f_operand1), opval);
3123     written |= (1 << 4);
3124     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3125   }
3126 }
3127 }
3128  else if (EQSI (tmp_prno, 1)) {
3129 {
3130   SI tmp_oldregval;
3131   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3132   {
3133     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3134     SET_H_GR (FLD (f_operand1), opval);
3135     written |= (1 << 4);
3136     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3137   }
3138 }
3139 }
3140  else if (EQSI (tmp_prno, 2)) {
3141 {
3142   SI tmp_oldregval;
3143   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3144   {
3145     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3146     SET_H_GR (FLD (f_operand1), opval);
3147     written |= (1 << 4);
3148     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3149   }
3150 }
3151 }
3152  else if (EQSI (tmp_prno, 3)) {
3153 {
3154   SI tmp_oldregval;
3155   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3156   {
3157     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3158     SET_H_GR (FLD (f_operand1), opval);
3159     written |= (1 << 4);
3160     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3161   }
3162 }
3163 }
3164  else if (EQSI (tmp_prno, 4)) {
3165 {
3166   SI tmp_oldregval;
3167   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3168   {
3169     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
3170     SET_H_GR (FLD (f_operand1), opval);
3171     written |= (1 << 4);
3172     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3173   }
3174 }
3175 }
3176  else if (EQSI (tmp_prno, 5)) {
3177   {
3178     SI opval = tmp_newval;
3179     SET_H_GR (FLD (f_operand1), opval);
3180     written |= (1 << 4);
3181     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3182   }
3183 }
3184  else if (EQSI (tmp_prno, 6)) {
3185   {
3186     SI opval = tmp_newval;
3187     SET_H_GR (FLD (f_operand1), opval);
3188     written |= (1 << 4);
3189     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3190   }
3191 }
3192  else if (EQSI (tmp_prno, 7)) {
3193   {
3194     SI opval = tmp_newval;
3195     SET_H_GR (FLD (f_operand1), opval);
3196     written |= (1 << 4);
3197     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3198   }
3199 }
3200  else if (EQSI (tmp_prno, 8)) {
3201   {
3202     SI opval = tmp_newval;
3203     SET_H_GR (FLD (f_operand1), opval);
3204     written |= (1 << 4);
3205     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3206   }
3207 }
3208  else if (EQSI (tmp_prno, 9)) {
3209   {
3210     SI opval = tmp_newval;
3211     SET_H_GR (FLD (f_operand1), opval);
3212     written |= (1 << 4);
3213     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3214   }
3215 }
3216  else if (EQSI (tmp_prno, 10)) {
3217   {
3218     SI opval = tmp_newval;
3219     SET_H_GR (FLD (f_operand1), opval);
3220     written |= (1 << 4);
3221     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3222   }
3223 }
3224  else if (EQSI (tmp_prno, 11)) {
3225   {
3226     SI opval = tmp_newval;
3227     SET_H_GR (FLD (f_operand1), opval);
3228     written |= (1 << 4);
3229     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3230   }
3231 }
3232  else if (EQSI (tmp_prno, 12)) {
3233   {
3234     SI opval = tmp_newval;
3235     SET_H_GR (FLD (f_operand1), opval);
3236     written |= (1 << 4);
3237     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3238   }
3239 }
3240  else if (EQSI (tmp_prno, 13)) {
3241   {
3242     SI opval = tmp_newval;
3243     SET_H_GR (FLD (f_operand1), opval);
3244     written |= (1 << 4);
3245     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3246   }
3247 }
3248  else if (EQSI (tmp_prno, 14)) {
3249   {
3250     SI opval = tmp_newval;
3251     SET_H_GR (FLD (f_operand1), opval);
3252     written |= (1 << 4);
3253     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3254   }
3255 }
3256  else if (EQSI (tmp_prno, 15)) {
3257   {
3258     SI opval = tmp_newval;
3259     SET_H_GR (FLD (f_operand1), opval);
3260     written |= (1 << 4);
3261     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3262   }
3263 }
3264  else {
3265 cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register");
3266 }
3267 {
3268   {
3269     BI opval = 0;
3270     CPU (h_xbit) = opval;
3271     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3272   }
3273   {
3274     BI opval = 0;
3275     SET_H_INSN_PREFIXED_P (opval);
3276     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3277   }
3278 }
3279 }
3280
3281   abuf->written = written;
3282 #undef FLD
3283 }
3284   NEXT (vpc);
3285
3286   CASE (sem, INSN_MOVE_M_SPRV32) : /* move [${Rs}${inc}],${Pd} */
3287 {
3288   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3289   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3290 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
3291   int UNUSED written = 0;
3292   IADDR UNUSED pc = abuf->addr;
3293   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3294
3295 {
3296   SI tmp_rno;
3297   SI tmp_newval;
3298   tmp_rno = FLD (f_operand2);
3299 if (EQSI (tmp_rno, 0)) {
3300   tmp_newval = EXTQISI (({   SI tmp_addr;
3301   QI tmp_tmp_mem;
3302   BI tmp_postinc;
3303   tmp_postinc = FLD (f_memmode);
3304 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3305 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
3306 ; if (NEBI (tmp_postinc, 0)) {
3307 {
3308 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3309   tmp_addr = ADDSI (tmp_addr, 1);
3310 }
3311   {
3312     SI opval = tmp_addr;
3313     SET_H_GR (FLD (f_operand1), opval);
3314     written |= (1 << 9);
3315     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3316   }
3317 }
3318 }
3319 ; tmp_tmp_mem; }));
3320 }
3321  else if (EQSI (tmp_rno, 1)) {
3322   tmp_newval = EXTQISI (({   SI tmp_addr;
3323   QI tmp_tmp_mem;
3324   BI tmp_postinc;
3325   tmp_postinc = FLD (f_memmode);
3326 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3327 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
3328 ; if (NEBI (tmp_postinc, 0)) {
3329 {
3330 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3331   tmp_addr = ADDSI (tmp_addr, 1);
3332 }
3333   {
3334     SI opval = tmp_addr;
3335     SET_H_GR (FLD (f_operand1), opval);
3336     written |= (1 << 9);
3337     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3338   }
3339 }
3340 }
3341 ; tmp_tmp_mem; }));
3342 }
3343  else if (EQSI (tmp_rno, 2)) {
3344   tmp_newval = EXTQISI (({   SI tmp_addr;
3345   QI tmp_tmp_mem;
3346   BI tmp_postinc;
3347   tmp_postinc = FLD (f_memmode);
3348 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3349 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
3350 ; if (NEBI (tmp_postinc, 0)) {
3351 {
3352 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3353   tmp_addr = ADDSI (tmp_addr, 1);
3354 }
3355   {
3356     SI opval = tmp_addr;
3357     SET_H_GR (FLD (f_operand1), opval);
3358     written |= (1 << 9);
3359     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3360   }
3361 }
3362 }
3363 ; tmp_tmp_mem; }));
3364 }
3365  else if (EQSI (tmp_rno, 3)) {
3366   tmp_newval = EXTQISI (({   SI tmp_addr;
3367   QI tmp_tmp_mem;
3368   BI tmp_postinc;
3369   tmp_postinc = FLD (f_memmode);
3370 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3371 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
3372 ; if (NEBI (tmp_postinc, 0)) {
3373 {
3374 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3375   tmp_addr = ADDSI (tmp_addr, 1);
3376 }
3377   {
3378     SI opval = tmp_addr;
3379     SET_H_GR (FLD (f_operand1), opval);
3380     written |= (1 << 9);
3381     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3382   }
3383 }
3384 }
3385 ; tmp_tmp_mem; }));
3386 }
3387  else if (EQSI (tmp_rno, 4)) {
3388   tmp_newval = EXTHISI (({   SI tmp_addr;
3389   HI tmp_tmp_mem;
3390   BI tmp_postinc;
3391   tmp_postinc = FLD (f_memmode);
3392 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3393 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
3394 ; if (NEBI (tmp_postinc, 0)) {
3395 {
3396 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3397   tmp_addr = ADDSI (tmp_addr, 2);
3398 }
3399   {
3400     SI opval = tmp_addr;
3401     SET_H_GR (FLD (f_operand1), opval);
3402     written |= (1 << 9);
3403     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3404   }
3405 }
3406 }
3407 ; tmp_tmp_mem; }));
3408 }
3409  else if (EQSI (tmp_rno, 5)) {
3410   tmp_newval = ({   SI tmp_addr;
3411   SI tmp_tmp_mem;
3412   BI tmp_postinc;
3413   tmp_postinc = FLD (f_memmode);
3414 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3415 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3416 ; if (NEBI (tmp_postinc, 0)) {
3417 {
3418 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3419   tmp_addr = ADDSI (tmp_addr, 4);
3420 }
3421   {
3422     SI opval = tmp_addr;
3423     SET_H_GR (FLD (f_operand1), opval);
3424     written |= (1 << 9);
3425     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3426   }
3427 }
3428 }
3429 ; tmp_tmp_mem; });
3430 }
3431  else if (EQSI (tmp_rno, 6)) {
3432   tmp_newval = ({   SI tmp_addr;
3433   SI tmp_tmp_mem;
3434   BI tmp_postinc;
3435   tmp_postinc = FLD (f_memmode);
3436 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3437 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3438 ; if (NEBI (tmp_postinc, 0)) {
3439 {
3440 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3441   tmp_addr = ADDSI (tmp_addr, 4);
3442 }
3443   {
3444     SI opval = tmp_addr;
3445     SET_H_GR (FLD (f_operand1), opval);
3446     written |= (1 << 9);
3447     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3448   }
3449 }
3450 }
3451 ; tmp_tmp_mem; });
3452 }
3453  else if (EQSI (tmp_rno, 7)) {
3454   tmp_newval = ({   SI tmp_addr;
3455   SI tmp_tmp_mem;
3456   BI tmp_postinc;
3457   tmp_postinc = FLD (f_memmode);
3458 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3459 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3460 ; if (NEBI (tmp_postinc, 0)) {
3461 {
3462 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3463   tmp_addr = ADDSI (tmp_addr, 4);
3464 }
3465   {
3466     SI opval = tmp_addr;
3467     SET_H_GR (FLD (f_operand1), opval);
3468     written |= (1 << 9);
3469     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3470   }
3471 }
3472 }
3473 ; tmp_tmp_mem; });
3474 }
3475  else if (EQSI (tmp_rno, 8)) {
3476   tmp_newval = ({   SI tmp_addr;
3477   SI tmp_tmp_mem;
3478   BI tmp_postinc;
3479   tmp_postinc = FLD (f_memmode);
3480 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3481 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3482 ; if (NEBI (tmp_postinc, 0)) {
3483 {
3484 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3485   tmp_addr = ADDSI (tmp_addr, 4);
3486 }
3487   {
3488     SI opval = tmp_addr;
3489     SET_H_GR (FLD (f_operand1), opval);
3490     written |= (1 << 9);
3491     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3492   }
3493 }
3494 }
3495 ; tmp_tmp_mem; });
3496 }
3497  else if (EQSI (tmp_rno, 9)) {
3498   tmp_newval = ({   SI tmp_addr;
3499   SI tmp_tmp_mem;
3500   BI tmp_postinc;
3501   tmp_postinc = FLD (f_memmode);
3502 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3503 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3504 ; if (NEBI (tmp_postinc, 0)) {
3505 {
3506 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3507   tmp_addr = ADDSI (tmp_addr, 4);
3508 }
3509   {
3510     SI opval = tmp_addr;
3511     SET_H_GR (FLD (f_operand1), opval);
3512     written |= (1 << 9);
3513     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3514   }
3515 }
3516 }
3517 ; tmp_tmp_mem; });
3518 }
3519  else if (EQSI (tmp_rno, 10)) {
3520   tmp_newval = ({   SI tmp_addr;
3521   SI tmp_tmp_mem;
3522   BI tmp_postinc;
3523   tmp_postinc = FLD (f_memmode);
3524 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3525 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3526 ; if (NEBI (tmp_postinc, 0)) {
3527 {
3528 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3529   tmp_addr = ADDSI (tmp_addr, 4);
3530 }
3531   {
3532     SI opval = tmp_addr;
3533     SET_H_GR (FLD (f_operand1), opval);
3534     written |= (1 << 9);
3535     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3536   }
3537 }
3538 }
3539 ; tmp_tmp_mem; });
3540 }
3541  else if (EQSI (tmp_rno, 11)) {
3542   tmp_newval = ({   SI tmp_addr;
3543   SI tmp_tmp_mem;
3544   BI tmp_postinc;
3545   tmp_postinc = FLD (f_memmode);
3546 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3547 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3548 ; if (NEBI (tmp_postinc, 0)) {
3549 {
3550 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3551   tmp_addr = ADDSI (tmp_addr, 4);
3552 }
3553   {
3554     SI opval = tmp_addr;
3555     SET_H_GR (FLD (f_operand1), opval);
3556     written |= (1 << 9);
3557     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3558   }
3559 }
3560 }
3561 ; tmp_tmp_mem; });
3562 }
3563  else if (EQSI (tmp_rno, 12)) {
3564   tmp_newval = ({   SI tmp_addr;
3565   SI tmp_tmp_mem;
3566   BI tmp_postinc;
3567   tmp_postinc = FLD (f_memmode);
3568 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3569 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3570 ; if (NEBI (tmp_postinc, 0)) {
3571 {
3572 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3573   tmp_addr = ADDSI (tmp_addr, 4);
3574 }
3575   {
3576     SI opval = tmp_addr;
3577     SET_H_GR (FLD (f_operand1), opval);
3578     written |= (1 << 9);
3579     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3580   }
3581 }
3582 }
3583 ; tmp_tmp_mem; });
3584 }
3585  else if (EQSI (tmp_rno, 13)) {
3586   tmp_newval = ({   SI tmp_addr;
3587   SI tmp_tmp_mem;
3588   BI tmp_postinc;
3589   tmp_postinc = FLD (f_memmode);
3590 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3591 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3592 ; if (NEBI (tmp_postinc, 0)) {
3593 {
3594 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3595   tmp_addr = ADDSI (tmp_addr, 4);
3596 }
3597   {
3598     SI opval = tmp_addr;
3599     SET_H_GR (FLD (f_operand1), opval);
3600     written |= (1 << 9);
3601     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3602   }
3603 }
3604 }
3605 ; tmp_tmp_mem; });
3606 }
3607  else if (EQSI (tmp_rno, 14)) {
3608   tmp_newval = ({   SI tmp_addr;
3609   SI tmp_tmp_mem;
3610   BI tmp_postinc;
3611   tmp_postinc = FLD (f_memmode);
3612 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3613 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3614 ; if (NEBI (tmp_postinc, 0)) {
3615 {
3616 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3617   tmp_addr = ADDSI (tmp_addr, 4);
3618 }
3619   {
3620     SI opval = tmp_addr;
3621     SET_H_GR (FLD (f_operand1), opval);
3622     written |= (1 << 9);
3623     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3624   }
3625 }
3626 }
3627 ; tmp_tmp_mem; });
3628 }
3629  else if (EQSI (tmp_rno, 15)) {
3630   tmp_newval = ({   SI tmp_addr;
3631   SI tmp_tmp_mem;
3632   BI tmp_postinc;
3633   tmp_postinc = FLD (f_memmode);
3634 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3635 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3636 ; if (NEBI (tmp_postinc, 0)) {
3637 {
3638 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3639   tmp_addr = ADDSI (tmp_addr, 4);
3640 }
3641   {
3642     SI opval = tmp_addr;
3643     SET_H_GR (FLD (f_operand1), opval);
3644     written |= (1 << 9);
3645     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3646   }
3647 }
3648 }
3649 ; tmp_tmp_mem; });
3650 }
3651  else {
3652 cgen_rtx_error (current_cpu, "Trying to set unimplemented special register");
3653 }
3654   {
3655     SI opval = tmp_newval;
3656     SET_H_SR (FLD (f_operand2), opval);
3657     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3658   }
3659 {
3660   {
3661     BI opval = 0;
3662     CPU (h_xbit) = opval;
3663     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3664   }
3665   {
3666     BI opval = 0;
3667     SET_H_INSN_PREFIXED_P (opval);
3668     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3669   }
3670 }
3671 }
3672
3673   abuf->written = written;
3674 #undef FLD
3675 }
3676   NEXT (vpc);
3677
3678   CASE (sem, INSN_MOVE_C_SPRV32_P0) : /* move ${const32},${Pd} */
3679 {
3680   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3681   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3682 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
3683   int UNUSED written = 0;
3684   IADDR UNUSED pc = abuf->addr;
3685   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3686
3687 {
3688   {
3689     SI opval = FLD (f_indir_pc__dword);
3690     SET_H_SR (FLD (f_operand2), opval);
3691     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3692   }
3693 {
3694   {
3695     BI opval = 0;
3696     CPU (h_xbit) = opval;
3697     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3698   }
3699   {
3700     BI opval = 0;
3701     SET_H_INSN_PREFIXED_P (opval);
3702     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3703   }
3704 }
3705 }
3706
3707 #undef FLD
3708 }
3709   NEXT (vpc);
3710
3711   CASE (sem, INSN_MOVE_C_SPRV32_P1) : /* move ${const32},${Pd} */
3712 {
3713   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3714   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3715 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
3716   int UNUSED written = 0;
3717   IADDR UNUSED pc = abuf->addr;
3718   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3719
3720 {
3721   {
3722     SI opval = FLD (f_indir_pc__dword);
3723     SET_H_SR (FLD (f_operand2), opval);
3724     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3725   }
3726 {
3727   {
3728     BI opval = 0;
3729     CPU (h_xbit) = opval;
3730     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3731   }
3732   {
3733     BI opval = 0;
3734     SET_H_INSN_PREFIXED_P (opval);
3735     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3736   }
3737 }
3738 }
3739
3740 #undef FLD
3741 }
3742   NEXT (vpc);
3743
3744   CASE (sem, INSN_MOVE_C_SPRV32_P2) : /* move ${const32},${Pd} */
3745 {
3746   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3747   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3748 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
3749   int UNUSED written = 0;
3750   IADDR UNUSED pc = abuf->addr;
3751   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3752
3753 {
3754   {
3755     SI opval = FLD (f_indir_pc__dword);
3756     SET_H_SR (FLD (f_operand2), opval);
3757     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3758   }
3759 {
3760   {
3761     BI opval = 0;
3762     CPU (h_xbit) = opval;
3763     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3764   }
3765   {
3766     BI opval = 0;
3767     SET_H_INSN_PREFIXED_P (opval);
3768     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3769   }
3770 }
3771 }
3772
3773 #undef FLD
3774 }
3775   NEXT (vpc);
3776
3777   CASE (sem, INSN_MOVE_C_SPRV32_P3) : /* move ${const32},${Pd} */
3778 {
3779   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3780   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3781 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
3782   int UNUSED written = 0;
3783   IADDR UNUSED pc = abuf->addr;
3784   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3785
3786 {
3787   {
3788     SI opval = FLD (f_indir_pc__dword);
3789     SET_H_SR (FLD (f_operand2), opval);
3790     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3791   }
3792 {
3793   {
3794     BI opval = 0;
3795     CPU (h_xbit) = opval;
3796     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3797   }
3798   {
3799     BI opval = 0;
3800     SET_H_INSN_PREFIXED_P (opval);
3801     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3802   }
3803 }
3804 }
3805
3806 #undef FLD
3807 }
3808   NEXT (vpc);
3809
3810   CASE (sem, INSN_MOVE_C_SPRV32_P4) : /* move ${const32},${Pd} */
3811 {
3812   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3813   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3814 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
3815   int UNUSED written = 0;
3816   IADDR UNUSED pc = abuf->addr;
3817   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3818
3819 {
3820   {
3821     SI opval = FLD (f_indir_pc__dword);
3822     SET_H_SR (FLD (f_operand2), opval);
3823     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3824   }
3825 {
3826   {
3827     BI opval = 0;
3828     CPU (h_xbit) = opval;
3829     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3830   }
3831   {
3832     BI opval = 0;
3833     SET_H_INSN_PREFIXED_P (opval);
3834     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3835   }
3836 }
3837 }
3838
3839 #undef FLD
3840 }
3841   NEXT (vpc);
3842
3843   CASE (sem, INSN_MOVE_C_SPRV32_P5) : /* move ${const32},${Pd} */
3844 {
3845   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3846   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3847 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
3848   int UNUSED written = 0;
3849   IADDR UNUSED pc = abuf->addr;
3850   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3851
3852 {
3853   {
3854     SI opval = FLD (f_indir_pc__dword);
3855     SET_H_SR (FLD (f_operand2), opval);
3856     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3857   }
3858 {
3859   {
3860     BI opval = 0;
3861     CPU (h_xbit) = opval;
3862     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3863   }
3864   {
3865     BI opval = 0;
3866     SET_H_INSN_PREFIXED_P (opval);
3867     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3868   }
3869 }
3870 }
3871
3872 #undef FLD
3873 }
3874   NEXT (vpc);
3875
3876   CASE (sem, INSN_MOVE_C_SPRV32_P6) : /* move ${const32},${Pd} */
3877 {
3878   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3879   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3880 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
3881   int UNUSED written = 0;
3882   IADDR UNUSED pc = abuf->addr;
3883   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3884
3885 {
3886   {
3887     SI opval = FLD (f_indir_pc__dword);
3888     SET_H_SR (FLD (f_operand2), opval);
3889     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3890   }
3891 {
3892   {
3893     BI opval = 0;
3894     CPU (h_xbit) = opval;
3895     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3896   }
3897   {
3898     BI opval = 0;
3899     SET_H_INSN_PREFIXED_P (opval);
3900     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3901   }
3902 }
3903 }
3904
3905 #undef FLD
3906 }
3907   NEXT (vpc);
3908
3909   CASE (sem, INSN_MOVE_C_SPRV32_P7) : /* move ${const32},${Pd} */
3910 {
3911   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3912   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3913 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
3914   int UNUSED written = 0;
3915   IADDR UNUSED pc = abuf->addr;
3916   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3917
3918 {
3919   {
3920     SI opval = FLD (f_indir_pc__dword);
3921     SET_H_SR (FLD (f_operand2), opval);
3922     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3923   }
3924 {
3925   {
3926     BI opval = 0;
3927     CPU (h_xbit) = opval;
3928     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3929   }
3930   {
3931     BI opval = 0;
3932     SET_H_INSN_PREFIXED_P (opval);
3933     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3934   }
3935 }
3936 }
3937
3938 #undef FLD
3939 }
3940   NEXT (vpc);
3941
3942   CASE (sem, INSN_MOVE_C_SPRV32_P8) : /* move ${const32},${Pd} */
3943 {
3944   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3945   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3946 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
3947   int UNUSED written = 0;
3948   IADDR UNUSED pc = abuf->addr;
3949   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3950
3951 {
3952   {
3953     SI opval = FLD (f_indir_pc__dword);
3954     SET_H_SR (FLD (f_operand2), opval);
3955     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3956   }
3957 {
3958   {
3959     BI opval = 0;
3960     CPU (h_xbit) = opval;
3961     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3962   }
3963   {
3964     BI opval = 0;
3965     SET_H_INSN_PREFIXED_P (opval);
3966     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3967   }
3968 }
3969 }
3970
3971 #undef FLD
3972 }
3973   NEXT (vpc);
3974
3975   CASE (sem, INSN_MOVE_C_SPRV32_P9) : /* move ${const32},${Pd} */
3976 {
3977   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3978   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3979 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
3980   int UNUSED written = 0;
3981   IADDR UNUSED pc = abuf->addr;
3982   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3983
3984 {
3985   {
3986     SI opval = FLD (f_indir_pc__dword);
3987     SET_H_SR (FLD (f_operand2), opval);
3988     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3989   }
3990 {
3991   {
3992     BI opval = 0;
3993     CPU (h_xbit) = opval;
3994     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3995   }
3996   {
3997     BI opval = 0;
3998     SET_H_INSN_PREFIXED_P (opval);
3999     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4000   }
4001 }
4002 }
4003
4004 #undef FLD
4005 }
4006   NEXT (vpc);
4007
4008   CASE (sem, INSN_MOVE_C_SPRV32_P10) : /* move ${const32},${Pd} */
4009 {
4010   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4011   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4012 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
4013   int UNUSED written = 0;
4014   IADDR UNUSED pc = abuf->addr;
4015   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
4016
4017 {
4018   {
4019     SI opval = FLD (f_indir_pc__dword);
4020     SET_H_SR (FLD (f_operand2), opval);
4021     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
4022   }
4023 {
4024   {
4025     BI opval = 0;
4026     CPU (h_xbit) = opval;
4027     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4028   }
4029   {
4030     BI opval = 0;
4031     SET_H_INSN_PREFIXED_P (opval);
4032     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4033   }
4034 }
4035 }
4036
4037 #undef FLD
4038 }
4039   NEXT (vpc);
4040
4041   CASE (sem, INSN_MOVE_C_SPRV32_P11) : /* move ${const32},${Pd} */
4042 {
4043   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4044   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4045 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
4046   int UNUSED written = 0;
4047   IADDR UNUSED pc = abuf->addr;
4048   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
4049
4050 {
4051   {
4052     SI opval = FLD (f_indir_pc__dword);
4053     SET_H_SR (FLD (f_operand2), opval);
4054     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
4055   }
4056 {
4057   {
4058     BI opval = 0;
4059     CPU (h_xbit) = opval;
4060     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4061   }
4062   {
4063     BI opval = 0;
4064     SET_H_INSN_PREFIXED_P (opval);
4065     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4066   }
4067 }
4068 }
4069
4070 #undef FLD
4071 }
4072   NEXT (vpc);
4073
4074   CASE (sem, INSN_MOVE_C_SPRV32_P12) : /* move ${const32},${Pd} */
4075 {
4076   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4077   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4078 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
4079   int UNUSED written = 0;
4080   IADDR UNUSED pc = abuf->addr;
4081   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
4082
4083 {
4084   {
4085     SI opval = FLD (f_indir_pc__dword);
4086     SET_H_SR (FLD (f_operand2), opval);
4087     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
4088   }
4089 {
4090   {
4091     BI opval = 0;
4092     CPU (h_xbit) = opval;
4093     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4094   }
4095   {
4096     BI opval = 0;
4097     SET_H_INSN_PREFIXED_P (opval);
4098     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4099   }
4100 }
4101 }
4102
4103 #undef FLD
4104 }
4105   NEXT (vpc);
4106
4107   CASE (sem, INSN_MOVE_C_SPRV32_P13) : /* move ${const32},${Pd} */
4108 {
4109   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4110   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4111 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
4112   int UNUSED written = 0;
4113   IADDR UNUSED pc = abuf->addr;
4114   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
4115
4116 {
4117   {
4118     SI opval = FLD (f_indir_pc__dword);
4119     SET_H_SR (FLD (f_operand2), opval);
4120     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
4121   }
4122 {
4123   {
4124     BI opval = 0;
4125     CPU (h_xbit) = opval;
4126     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4127   }
4128   {
4129     BI opval = 0;
4130     SET_H_INSN_PREFIXED_P (opval);
4131     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4132   }
4133 }
4134 }
4135
4136 #undef FLD
4137 }
4138   NEXT (vpc);
4139
4140   CASE (sem, INSN_MOVE_C_SPRV32_P14) : /* move ${const32},${Pd} */
4141 {
4142   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4143   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4144 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
4145   int UNUSED written = 0;
4146   IADDR UNUSED pc = abuf->addr;
4147   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
4148
4149 {
4150   {
4151     SI opval = FLD (f_indir_pc__dword);
4152     SET_H_SR (FLD (f_operand2), opval);
4153     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
4154   }
4155 {
4156   {
4157     BI opval = 0;
4158     CPU (h_xbit) = opval;
4159     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4160   }
4161   {
4162     BI opval = 0;
4163     SET_H_INSN_PREFIXED_P (opval);
4164     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4165   }
4166 }
4167 }
4168
4169 #undef FLD
4170 }
4171   NEXT (vpc);
4172
4173   CASE (sem, INSN_MOVE_C_SPRV32_P15) : /* move ${const32},${Pd} */
4174 {
4175   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4176   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4177 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
4178   int UNUSED written = 0;
4179   IADDR UNUSED pc = abuf->addr;
4180   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
4181
4182 {
4183   {
4184     SI opval = FLD (f_indir_pc__dword);
4185     SET_H_SR (FLD (f_operand2), opval);
4186     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
4187   }
4188 {
4189   {
4190     BI opval = 0;
4191     CPU (h_xbit) = opval;
4192     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4193   }
4194   {
4195     BI opval = 0;
4196     SET_H_INSN_PREFIXED_P (opval);
4197     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4198   }
4199 }
4200 }
4201
4202 #undef FLD
4203 }
4204   NEXT (vpc);
4205
4206   CASE (sem, INSN_MOVE_SPR_MV32) : /* move ${Ps},[${Rd-sfield}${inc}] */
4207 {
4208   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4209   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4210 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
4211   int UNUSED written = 0;
4212   IADDR UNUSED pc = abuf->addr;
4213   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4214
4215 {
4216   SI tmp_rno;
4217   tmp_rno = FLD (f_operand2);
4218 if (EQSI (tmp_rno, 0)) {
4219 {
4220   SI tmp_addr;
4221   BI tmp_postinc;
4222   tmp_postinc = FLD (f_memmode);
4223   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4224 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4225 if (EQBI (CPU (h_pbit), 0)) {
4226 {
4227   {
4228     QI opval = GET_H_SR (FLD (f_operand2));
4229     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4230     written |= (1 << 12);
4231     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4232   }
4233   {
4234     BI opval = CPU (h_pbit);
4235     CPU (h_cbit) = opval;
4236     written |= (1 << 10);
4237     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4238   }
4239 }
4240 } else {
4241   {
4242     BI opval = 1;
4243     CPU (h_cbit) = opval;
4244     written |= (1 << 10);
4245     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4246   }
4247 }
4248 } else {
4249   {
4250     QI opval = GET_H_SR (FLD (f_operand2));
4251     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4252     written |= (1 << 12);
4253     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4254   }
4255 }
4256 if (NEBI (tmp_postinc, 0)) {
4257 {
4258 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4259   tmp_addr = ADDSI (tmp_addr, 1);
4260 }
4261   {
4262     SI opval = tmp_addr;
4263     SET_H_GR (FLD (f_operand1), opval);
4264     written |= (1 << 9);
4265     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4266   }
4267 }
4268 }
4269 }
4270 }
4271  else if (EQSI (tmp_rno, 1)) {
4272 {
4273   SI tmp_addr;
4274   BI tmp_postinc;
4275   tmp_postinc = FLD (f_memmode);
4276   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4277 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4278 if (EQBI (CPU (h_pbit), 0)) {
4279 {
4280   {
4281     QI opval = GET_H_SR (FLD (f_operand2));
4282     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4283     written |= (1 << 12);
4284     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4285   }
4286   {
4287     BI opval = CPU (h_pbit);
4288     CPU (h_cbit) = opval;
4289     written |= (1 << 10);
4290     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4291   }
4292 }
4293 } else {
4294   {
4295     BI opval = 1;
4296     CPU (h_cbit) = opval;
4297     written |= (1 << 10);
4298     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4299   }
4300 }
4301 } else {
4302   {
4303     QI opval = GET_H_SR (FLD (f_operand2));
4304     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4305     written |= (1 << 12);
4306     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4307   }
4308 }
4309 if (NEBI (tmp_postinc, 0)) {
4310 {
4311 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4312   tmp_addr = ADDSI (tmp_addr, 1);
4313 }
4314   {
4315     SI opval = tmp_addr;
4316     SET_H_GR (FLD (f_operand1), opval);
4317     written |= (1 << 9);
4318     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4319   }
4320 }
4321 }
4322 }
4323 }
4324  else if (EQSI (tmp_rno, 2)) {
4325 {
4326   SI tmp_addr;
4327   BI tmp_postinc;
4328   tmp_postinc = FLD (f_memmode);
4329   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4330 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4331 if (EQBI (CPU (h_pbit), 0)) {
4332 {
4333   {
4334     QI opval = GET_H_SR (FLD (f_operand2));
4335     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4336     written |= (1 << 12);
4337     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4338   }
4339   {
4340     BI opval = CPU (h_pbit);
4341     CPU (h_cbit) = opval;
4342     written |= (1 << 10);
4343     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4344   }
4345 }
4346 } else {
4347   {
4348     BI opval = 1;
4349     CPU (h_cbit) = opval;
4350     written |= (1 << 10);
4351     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4352   }
4353 }
4354 } else {
4355   {
4356     QI opval = GET_H_SR (FLD (f_operand2));
4357     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4358     written |= (1 << 12);
4359     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4360   }
4361 }
4362 if (NEBI (tmp_postinc, 0)) {
4363 {
4364 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4365   tmp_addr = ADDSI (tmp_addr, 1);
4366 }
4367   {
4368     SI opval = tmp_addr;
4369     SET_H_GR (FLD (f_operand1), opval);
4370     written |= (1 << 9);
4371     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4372   }
4373 }
4374 }
4375 }
4376 }
4377  else if (EQSI (tmp_rno, 3)) {
4378 {
4379   SI tmp_addr;
4380   BI tmp_postinc;
4381   tmp_postinc = FLD (f_memmode);
4382   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4383 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4384 if (EQBI (CPU (h_pbit), 0)) {
4385 {
4386   {
4387     QI opval = GET_H_SR (FLD (f_operand2));
4388     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4389     written |= (1 << 12);
4390     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4391   }
4392   {
4393     BI opval = CPU (h_pbit);
4394     CPU (h_cbit) = opval;
4395     written |= (1 << 10);
4396     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4397   }
4398 }
4399 } else {
4400   {
4401     BI opval = 1;
4402     CPU (h_cbit) = opval;
4403     written |= (1 << 10);
4404     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4405   }
4406 }
4407 } else {
4408   {
4409     QI opval = GET_H_SR (FLD (f_operand2));
4410     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4411     written |= (1 << 12);
4412     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4413   }
4414 }
4415 if (NEBI (tmp_postinc, 0)) {
4416 {
4417 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4418   tmp_addr = ADDSI (tmp_addr, 1);
4419 }
4420   {
4421     SI opval = tmp_addr;
4422     SET_H_GR (FLD (f_operand1), opval);
4423     written |= (1 << 9);
4424     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4425   }
4426 }
4427 }
4428 }
4429 }
4430  else if (EQSI (tmp_rno, 4)) {
4431 {
4432   SI tmp_addr;
4433   BI tmp_postinc;
4434   tmp_postinc = FLD (f_memmode);
4435   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4436 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4437 if (EQBI (CPU (h_pbit), 0)) {
4438 {
4439   {
4440     HI opval = GET_H_SR (FLD (f_operand2));
4441     SETMEMHI (current_cpu, pc, tmp_addr, opval);
4442     written |= (1 << 11);
4443     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4444   }
4445   {
4446     BI opval = CPU (h_pbit);
4447     CPU (h_cbit) = opval;
4448     written |= (1 << 10);
4449     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4450   }
4451 }
4452 } else {
4453   {
4454     BI opval = 1;
4455     CPU (h_cbit) = opval;
4456     written |= (1 << 10);
4457     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4458   }
4459 }
4460 } else {
4461   {
4462     HI opval = GET_H_SR (FLD (f_operand2));
4463     SETMEMHI (current_cpu, pc, tmp_addr, opval);
4464     written |= (1 << 11);
4465     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4466   }
4467 }
4468 if (NEBI (tmp_postinc, 0)) {
4469 {
4470 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4471   tmp_addr = ADDSI (tmp_addr, 2);
4472 }
4473   {
4474     SI opval = tmp_addr;
4475     SET_H_GR (FLD (f_operand1), opval);
4476     written |= (1 << 9);
4477     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4478   }
4479 }
4480 }
4481 }
4482 }
4483  else if (EQSI (tmp_rno, 5)) {
4484 {
4485   SI tmp_addr;
4486   BI tmp_postinc;
4487   tmp_postinc = FLD (f_memmode);
4488   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4489 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4490 if (EQBI (CPU (h_pbit), 0)) {
4491 {
4492   {
4493     SI opval = GET_H_SR (FLD (f_operand2));
4494     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4495     written |= (1 << 13);
4496     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4497   }
4498   {
4499     BI opval = CPU (h_pbit);
4500     CPU (h_cbit) = opval;
4501     written |= (1 << 10);
4502     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4503   }
4504 }
4505 } else {
4506   {
4507     BI opval = 1;
4508     CPU (h_cbit) = opval;
4509     written |= (1 << 10);
4510     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4511   }
4512 }
4513 } else {
4514   {
4515     SI opval = GET_H_SR (FLD (f_operand2));
4516     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4517     written |= (1 << 13);
4518     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4519   }
4520 }
4521 if (NEBI (tmp_postinc, 0)) {
4522 {
4523 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4524   tmp_addr = ADDSI (tmp_addr, 4);
4525 }
4526   {
4527     SI opval = tmp_addr;
4528     SET_H_GR (FLD (f_operand1), opval);
4529     written |= (1 << 9);
4530     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4531   }
4532 }
4533 }
4534 }
4535 }
4536  else if (EQSI (tmp_rno, 6)) {
4537 {
4538   SI tmp_addr;
4539   BI tmp_postinc;
4540   tmp_postinc = FLD (f_memmode);
4541   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4542 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4543 if (EQBI (CPU (h_pbit), 0)) {
4544 {
4545   {
4546     SI opval = GET_H_SR (FLD (f_operand2));
4547     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4548     written |= (1 << 13);
4549     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4550   }
4551   {
4552     BI opval = CPU (h_pbit);
4553     CPU (h_cbit) = opval;
4554     written |= (1 << 10);
4555     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4556   }
4557 }
4558 } else {
4559   {
4560     BI opval = 1;
4561     CPU (h_cbit) = opval;
4562     written |= (1 << 10);
4563     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4564   }
4565 }
4566 } else {
4567   {
4568     SI opval = GET_H_SR (FLD (f_operand2));
4569     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4570     written |= (1 << 13);
4571     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4572   }
4573 }
4574 if (NEBI (tmp_postinc, 0)) {
4575 {
4576 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4577   tmp_addr = ADDSI (tmp_addr, 4);
4578 }
4579   {
4580     SI opval = tmp_addr;
4581     SET_H_GR (FLD (f_operand1), opval);
4582     written |= (1 << 9);
4583     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4584   }
4585 }
4586 }
4587 }
4588 }
4589  else if (EQSI (tmp_rno, 7)) {
4590 {
4591   SI tmp_addr;
4592   BI tmp_postinc;
4593   tmp_postinc = FLD (f_memmode);
4594   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4595 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4596 if (EQBI (CPU (h_pbit), 0)) {
4597 {
4598   {
4599     SI opval = GET_H_SR (FLD (f_operand2));
4600     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4601     written |= (1 << 13);
4602     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4603   }
4604   {
4605     BI opval = CPU (h_pbit);
4606     CPU (h_cbit) = opval;
4607     written |= (1 << 10);
4608     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4609   }
4610 }
4611 } else {
4612   {
4613     BI opval = 1;
4614     CPU (h_cbit) = opval;
4615     written |= (1 << 10);
4616     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4617   }
4618 }
4619 } else {
4620   {
4621     SI opval = GET_H_SR (FLD (f_operand2));
4622     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4623     written |= (1 << 13);
4624     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4625   }
4626 }
4627 if (NEBI (tmp_postinc, 0)) {
4628 {
4629 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4630   tmp_addr = ADDSI (tmp_addr, 4);
4631 }
4632   {
4633     SI opval = tmp_addr;
4634     SET_H_GR (FLD (f_operand1), opval);
4635     written |= (1 << 9);
4636     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4637   }
4638 }
4639 }
4640 }
4641 }
4642  else if (EQSI (tmp_rno, 8)) {
4643 {
4644   SI tmp_addr;
4645   BI tmp_postinc;
4646   tmp_postinc = FLD (f_memmode);
4647   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4648 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4649 if (EQBI (CPU (h_pbit), 0)) {
4650 {
4651   {
4652     SI opval = GET_H_SR (FLD (f_operand2));
4653     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4654     written |= (1 << 13);
4655     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4656   }
4657   {
4658     BI opval = CPU (h_pbit);
4659     CPU (h_cbit) = opval;
4660     written |= (1 << 10);
4661     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4662   }
4663 }
4664 } else {
4665   {
4666     BI opval = 1;
4667     CPU (h_cbit) = opval;
4668     written |= (1 << 10);
4669     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4670   }
4671 }
4672 } else {
4673   {
4674     SI opval = GET_H_SR (FLD (f_operand2));
4675     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4676     written |= (1 << 13);
4677     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4678   }
4679 }
4680 if (NEBI (tmp_postinc, 0)) {
4681 {
4682 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4683   tmp_addr = ADDSI (tmp_addr, 4);
4684 }
4685   {
4686     SI opval = tmp_addr;
4687     SET_H_GR (FLD (f_operand1), opval);
4688     written |= (1 << 9);
4689     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4690   }
4691 }
4692 }
4693 }
4694 }
4695  else if (EQSI (tmp_rno, 9)) {
4696 {
4697   SI tmp_addr;
4698   BI tmp_postinc;
4699   tmp_postinc = FLD (f_memmode);
4700   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4701 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4702 if (EQBI (CPU (h_pbit), 0)) {
4703 {
4704   {
4705     SI opval = GET_H_SR (FLD (f_operand2));
4706     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4707     written |= (1 << 13);
4708     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4709   }
4710   {
4711     BI opval = CPU (h_pbit);
4712     CPU (h_cbit) = opval;
4713     written |= (1 << 10);
4714     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4715   }
4716 }
4717 } else {
4718   {
4719     BI opval = 1;
4720     CPU (h_cbit) = opval;
4721     written |= (1 << 10);
4722     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4723   }
4724 }
4725 } else {
4726   {
4727     SI opval = GET_H_SR (FLD (f_operand2));
4728     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4729     written |= (1 << 13);
4730     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4731   }
4732 }
4733 if (NEBI (tmp_postinc, 0)) {
4734 {
4735 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4736   tmp_addr = ADDSI (tmp_addr, 4);
4737 }
4738   {
4739     SI opval = tmp_addr;
4740     SET_H_GR (FLD (f_operand1), opval);
4741     written |= (1 << 9);
4742     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4743   }
4744 }
4745 }
4746 }
4747 }
4748  else if (EQSI (tmp_rno, 10)) {
4749 {
4750   SI tmp_addr;
4751   BI tmp_postinc;
4752   tmp_postinc = FLD (f_memmode);
4753   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4754 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4755 if (EQBI (CPU (h_pbit), 0)) {
4756 {
4757   {
4758     SI opval = GET_H_SR (FLD (f_operand2));
4759     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4760     written |= (1 << 13);
4761     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4762   }
4763   {
4764     BI opval = CPU (h_pbit);
4765     CPU (h_cbit) = opval;
4766     written |= (1 << 10);
4767     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4768   }
4769 }
4770 } else {
4771   {
4772     BI opval = 1;
4773     CPU (h_cbit) = opval;
4774     written |= (1 << 10);
4775     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4776   }
4777 }
4778 } else {
4779   {
4780     SI opval = GET_H_SR (FLD (f_operand2));
4781     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4782     written |= (1 << 13);
4783     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4784   }
4785 }
4786 if (NEBI (tmp_postinc, 0)) {
4787 {
4788 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4789   tmp_addr = ADDSI (tmp_addr, 4);
4790 }
4791   {
4792     SI opval = tmp_addr;
4793     SET_H_GR (FLD (f_operand1), opval);
4794     written |= (1 << 9);
4795     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4796   }
4797 }
4798 }
4799 }
4800 }
4801  else if (EQSI (tmp_rno, 11)) {
4802 {
4803   SI tmp_addr;
4804   BI tmp_postinc;
4805   tmp_postinc = FLD (f_memmode);
4806   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4807 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4808 if (EQBI (CPU (h_pbit), 0)) {
4809 {
4810   {
4811     SI opval = GET_H_SR (FLD (f_operand2));
4812     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4813     written |= (1 << 13);
4814     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4815   }
4816   {
4817     BI opval = CPU (h_pbit);
4818     CPU (h_cbit) = opval;
4819     written |= (1 << 10);
4820     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4821   }
4822 }
4823 } else {
4824   {
4825     BI opval = 1;
4826     CPU (h_cbit) = opval;
4827     written |= (1 << 10);
4828     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4829   }
4830 }
4831 } else {
4832   {
4833     SI opval = GET_H_SR (FLD (f_operand2));
4834     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4835     written |= (1 << 13);
4836     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4837   }
4838 }
4839 if (NEBI (tmp_postinc, 0)) {
4840 {
4841 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4842   tmp_addr = ADDSI (tmp_addr, 4);
4843 }
4844   {
4845     SI opval = tmp_addr;
4846     SET_H_GR (FLD (f_operand1), opval);
4847     written |= (1 << 9);
4848     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4849   }
4850 }
4851 }
4852 }
4853 }
4854  else if (EQSI (tmp_rno, 12)) {
4855 {
4856   SI tmp_addr;
4857   BI tmp_postinc;
4858   tmp_postinc = FLD (f_memmode);
4859   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4860 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4861 if (EQBI (CPU (h_pbit), 0)) {
4862 {
4863   {
4864     SI opval = GET_H_SR (FLD (f_operand2));
4865     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4866     written |= (1 << 13);
4867     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4868   }
4869   {
4870     BI opval = CPU (h_pbit);
4871     CPU (h_cbit) = opval;
4872     written |= (1 << 10);
4873     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4874   }
4875 }
4876 } else {
4877   {
4878     BI opval = 1;
4879     CPU (h_cbit) = opval;
4880     written |= (1 << 10);
4881     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4882   }
4883 }
4884 } else {
4885   {
4886     SI opval = GET_H_SR (FLD (f_operand2));
4887     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4888     written |= (1 << 13);
4889     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4890   }
4891 }
4892 if (NEBI (tmp_postinc, 0)) {
4893 {
4894 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4895   tmp_addr = ADDSI (tmp_addr, 4);
4896 }
4897   {
4898     SI opval = tmp_addr;
4899     SET_H_GR (FLD (f_operand1), opval);
4900     written |= (1 << 9);
4901     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4902   }
4903 }
4904 }
4905 }
4906 }
4907  else if (EQSI (tmp_rno, 13)) {
4908 {
4909   SI tmp_addr;
4910   BI tmp_postinc;
4911   tmp_postinc = FLD (f_memmode);
4912   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4913 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4914 if (EQBI (CPU (h_pbit), 0)) {
4915 {
4916   {
4917     SI opval = GET_H_SR (FLD (f_operand2));
4918     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4919     written |= (1 << 13);
4920     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4921   }
4922   {
4923     BI opval = CPU (h_pbit);
4924     CPU (h_cbit) = opval;
4925     written |= (1 << 10);
4926     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4927   }
4928 }
4929 } else {
4930   {
4931     BI opval = 1;
4932     CPU (h_cbit) = opval;
4933     written |= (1 << 10);
4934     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4935   }
4936 }
4937 } else {
4938   {
4939     SI opval = GET_H_SR (FLD (f_operand2));
4940     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4941     written |= (1 << 13);
4942     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4943   }
4944 }
4945 if (NEBI (tmp_postinc, 0)) {
4946 {
4947 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4948   tmp_addr = ADDSI (tmp_addr, 4);
4949 }
4950   {
4951     SI opval = tmp_addr;
4952     SET_H_GR (FLD (f_operand1), opval);
4953     written |= (1 << 9);
4954     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4955   }
4956 }
4957 }
4958 }
4959 }
4960  else if (EQSI (tmp_rno, 14)) {
4961 {
4962   SI tmp_addr;
4963   BI tmp_postinc;
4964   tmp_postinc = FLD (f_memmode);
4965   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4966 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4967 if (EQBI (CPU (h_pbit), 0)) {
4968 {
4969   {
4970     SI opval = GET_H_SR (FLD (f_operand2));
4971     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4972     written |= (1 << 13);
4973     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4974   }
4975   {
4976     BI opval = CPU (h_pbit);
4977     CPU (h_cbit) = opval;
4978     written |= (1 << 10);
4979     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4980   }
4981 }
4982 } else {
4983   {
4984     BI opval = 1;
4985     CPU (h_cbit) = opval;
4986     written |= (1 << 10);
4987     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4988   }
4989 }
4990 } else {
4991   {
4992     SI opval = GET_H_SR (FLD (f_operand2));
4993     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4994     written |= (1 << 13);
4995     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4996   }
4997 }
4998 if (NEBI (tmp_postinc, 0)) {
4999 {
5000 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5001   tmp_addr = ADDSI (tmp_addr, 4);
5002 }
5003   {
5004     SI opval = tmp_addr;
5005     SET_H_GR (FLD (f_operand1), opval);
5006     written |= (1 << 9);
5007     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5008   }
5009 }
5010 }
5011 }
5012 }
5013  else if (EQSI (tmp_rno, 15)) {
5014 {
5015   SI tmp_addr;
5016   BI tmp_postinc;
5017   tmp_postinc = FLD (f_memmode);
5018   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
5019 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
5020 if (EQBI (CPU (h_pbit), 0)) {
5021 {
5022   {
5023     SI opval = GET_H_SR (FLD (f_operand2));
5024     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5025     written |= (1 << 13);
5026     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5027   }
5028   {
5029     BI opval = CPU (h_pbit);
5030     CPU (h_cbit) = opval;
5031     written |= (1 << 10);
5032     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5033   }
5034 }
5035 } else {
5036   {
5037     BI opval = 1;
5038     CPU (h_cbit) = opval;
5039     written |= (1 << 10);
5040     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5041   }
5042 }
5043 } else {
5044   {
5045     SI opval = GET_H_SR (FLD (f_operand2));
5046     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5047     written |= (1 << 13);
5048     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5049   }
5050 }
5051 if (NEBI (tmp_postinc, 0)) {
5052 {
5053 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5054   tmp_addr = ADDSI (tmp_addr, 4);
5055 }
5056   {
5057     SI opval = tmp_addr;
5058     SET_H_GR (FLD (f_operand1), opval);
5059     written |= (1 << 9);
5060     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5061   }
5062 }
5063 }
5064 }
5065 }
5066  else {
5067 cgen_rtx_error (current_cpu, "write from unimplemented special register");
5068 }
5069 {
5070   {
5071     BI opval = 0;
5072     CPU (h_xbit) = opval;
5073     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5074   }
5075   {
5076     BI opval = 0;
5077     SET_H_INSN_PREFIXED_P (opval);
5078     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5079   }
5080 }
5081 }
5082
5083   abuf->written = written;
5084 #undef FLD
5085 }
5086   NEXT (vpc);
5087
5088   CASE (sem, INSN_MOVE_SS_R) : /* move ${Ss},${Rd-sfield} */
5089 {
5090   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5091   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5092 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
5093   int UNUSED written = 0;
5094   IADDR UNUSED pc = abuf->addr;
5095   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5096
5097 {
5098   {
5099     SI opval = GET_H_SUPR (FLD (f_operand2));
5100     SET_H_GR (FLD (f_operand1), opval);
5101     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5102   }
5103 {
5104   {
5105     BI opval = 0;
5106     CPU (h_xbit) = opval;
5107     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5108   }
5109   {
5110     BI opval = 0;
5111     SET_H_INSN_PREFIXED_P (opval);
5112     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5113   }
5114 }
5115 }
5116
5117 #undef FLD
5118 }
5119   NEXT (vpc);
5120
5121   CASE (sem, INSN_MOVE_R_SS) : /* move ${Rs},${Sd} */
5122 {
5123   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5124   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5125 #define FLD(f) abuf->fields.sfmt_mcp.f
5126   int UNUSED written = 0;
5127   IADDR UNUSED pc = abuf->addr;
5128   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5129
5130 {
5131   {
5132     SI opval = GET_H_GR (FLD (f_operand1));
5133     SET_H_SUPR (FLD (f_operand2), opval);
5134     TRACE_RESULT (current_cpu, abuf, "supr", 'x', opval);
5135   }
5136 {
5137   {
5138     BI opval = 0;
5139     CPU (h_xbit) = opval;
5140     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5141   }
5142   {
5143     BI opval = 0;
5144     SET_H_INSN_PREFIXED_P (opval);
5145     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5146   }
5147 }
5148 }
5149
5150 #undef FLD
5151 }
5152   NEXT (vpc);
5153
5154   CASE (sem, INSN_MOVEM_R_M_V32) : /* movem ${Rs-dfield},[${Rd-sfield}${inc}] */
5155 {
5156   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5157   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5158 #define FLD(f) abuf->fields.sfmt_movem_r_m_v32.f
5159   int UNUSED written = 0;
5160   IADDR UNUSED pc = abuf->addr;
5161   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5162
5163 {
5164   SI tmp_addr;
5165   BI tmp_postinc;
5166   tmp_postinc = FLD (f_memmode);
5167 {
5168   SI tmp_dummy;
5169   tmp_dummy = GET_H_GR (FLD (f_operand2));
5170 }
5171   tmp_addr = GET_H_GR (FLD (f_operand1));
5172 {
5173 if (GESI (FLD (f_operand2), 0)) {
5174 {
5175   SI tmp_tmp;
5176   tmp_tmp = GET_H_GR (((UINT) 0));
5177   {
5178     SI opval = tmp_tmp;
5179     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5180     written |= (1 << 21);
5181     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5182   }
5183   tmp_addr = ADDSI (tmp_addr, 4);
5184 }
5185 }
5186 if (GESI (FLD (f_operand2), 1)) {
5187 {
5188   SI tmp_tmp;
5189   tmp_tmp = GET_H_GR (((UINT) 1));
5190   {
5191     SI opval = tmp_tmp;
5192     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5193     written |= (1 << 21);
5194     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5195   }
5196   tmp_addr = ADDSI (tmp_addr, 4);
5197 }
5198 }
5199 if (GESI (FLD (f_operand2), 2)) {
5200 {
5201   SI tmp_tmp;
5202   tmp_tmp = GET_H_GR (((UINT) 2));
5203   {
5204     SI opval = tmp_tmp;
5205     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5206     written |= (1 << 21);
5207     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5208   }
5209   tmp_addr = ADDSI (tmp_addr, 4);
5210 }
5211 }
5212 if (GESI (FLD (f_operand2), 3)) {
5213 {
5214   SI tmp_tmp;
5215   tmp_tmp = GET_H_GR (((UINT) 3));
5216   {
5217     SI opval = tmp_tmp;
5218     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5219     written |= (1 << 21);
5220     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5221   }
5222   tmp_addr = ADDSI (tmp_addr, 4);
5223 }
5224 }
5225 if (GESI (FLD (f_operand2), 4)) {
5226 {
5227   SI tmp_tmp;
5228   tmp_tmp = GET_H_GR (((UINT) 4));
5229   {
5230     SI opval = tmp_tmp;
5231     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5232     written |= (1 << 21);
5233     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5234   }
5235   tmp_addr = ADDSI (tmp_addr, 4);
5236 }
5237 }
5238 if (GESI (FLD (f_operand2), 5)) {
5239 {
5240   SI tmp_tmp;
5241   tmp_tmp = GET_H_GR (((UINT) 5));
5242   {
5243     SI opval = tmp_tmp;
5244     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5245     written |= (1 << 21);
5246     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5247   }
5248   tmp_addr = ADDSI (tmp_addr, 4);
5249 }
5250 }
5251 if (GESI (FLD (f_operand2), 6)) {
5252 {
5253   SI tmp_tmp;
5254   tmp_tmp = GET_H_GR (((UINT) 6));
5255   {
5256     SI opval = tmp_tmp;
5257     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5258     written |= (1 << 21);
5259     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5260   }
5261   tmp_addr = ADDSI (tmp_addr, 4);
5262 }
5263 }
5264 if (GESI (FLD (f_operand2), 7)) {
5265 {
5266   SI tmp_tmp;
5267   tmp_tmp = GET_H_GR (((UINT) 7));
5268   {
5269     SI opval = tmp_tmp;
5270     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5271     written |= (1 << 21);
5272     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5273   }
5274   tmp_addr = ADDSI (tmp_addr, 4);
5275 }
5276 }
5277 if (GESI (FLD (f_operand2), 8)) {
5278 {
5279   SI tmp_tmp;
5280   tmp_tmp = GET_H_GR (((UINT) 8));
5281   {
5282     SI opval = tmp_tmp;
5283     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5284     written |= (1 << 21);
5285     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5286   }
5287   tmp_addr = ADDSI (tmp_addr, 4);
5288 }
5289 }
5290 if (GESI (FLD (f_operand2), 9)) {
5291 {
5292   SI tmp_tmp;
5293   tmp_tmp = GET_H_GR (((UINT) 9));
5294   {
5295     SI opval = tmp_tmp;
5296     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5297     written |= (1 << 21);
5298     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5299   }
5300   tmp_addr = ADDSI (tmp_addr, 4);
5301 }
5302 }
5303 if (GESI (FLD (f_operand2), 10)) {
5304 {
5305   SI tmp_tmp;
5306   tmp_tmp = GET_H_GR (((UINT) 10));
5307   {
5308     SI opval = tmp_tmp;
5309     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5310     written |= (1 << 21);
5311     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5312   }
5313   tmp_addr = ADDSI (tmp_addr, 4);
5314 }
5315 }
5316 if (GESI (FLD (f_operand2), 11)) {
5317 {
5318   SI tmp_tmp;
5319   tmp_tmp = GET_H_GR (((UINT) 11));
5320   {
5321     SI opval = tmp_tmp;
5322     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5323     written |= (1 << 21);
5324     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5325   }
5326   tmp_addr = ADDSI (tmp_addr, 4);
5327 }
5328 }
5329 if (GESI (FLD (f_operand2), 12)) {
5330 {
5331   SI tmp_tmp;
5332   tmp_tmp = GET_H_GR (((UINT) 12));
5333   {
5334     SI opval = tmp_tmp;
5335     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5336     written |= (1 << 21);
5337     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5338   }
5339   tmp_addr = ADDSI (tmp_addr, 4);
5340 }
5341 }
5342 if (GESI (FLD (f_operand2), 13)) {
5343 {
5344   SI tmp_tmp;
5345   tmp_tmp = GET_H_GR (((UINT) 13));
5346   {
5347     SI opval = tmp_tmp;
5348     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5349     written |= (1 << 21);
5350     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5351   }
5352   tmp_addr = ADDSI (tmp_addr, 4);
5353 }
5354 }
5355 if (GESI (FLD (f_operand2), 14)) {
5356 {
5357   SI tmp_tmp;
5358   tmp_tmp = GET_H_GR (((UINT) 14));
5359   {
5360     SI opval = tmp_tmp;
5361     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5362     written |= (1 << 21);
5363     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5364   }
5365   tmp_addr = ADDSI (tmp_addr, 4);
5366 }
5367 }
5368 if (GESI (FLD (f_operand2), 15)) {
5369 {
5370   SI tmp_tmp;
5371   tmp_tmp = GET_H_GR (((UINT) 15));
5372   {
5373     SI opval = tmp_tmp;
5374     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5375     written |= (1 << 21);
5376     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5377   }
5378   tmp_addr = ADDSI (tmp_addr, 4);
5379 }
5380 }
5381 }
5382 if (NEBI (tmp_postinc, 0)) {
5383   {
5384     SI opval = tmp_addr;
5385     SET_H_GR (FLD (f_operand1), opval);
5386     written |= (1 << 20);
5387     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5388   }
5389 }
5390 {
5391   {
5392     BI opval = 0;
5393     CPU (h_xbit) = opval;
5394     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5395   }
5396   {
5397     BI opval = 0;
5398     SET_H_INSN_PREFIXED_P (opval);
5399     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5400   }
5401 }
5402 }
5403
5404   abuf->written = written;
5405 #undef FLD
5406 }
5407   NEXT (vpc);
5408
5409   CASE (sem, INSN_MOVEM_M_R_V32) : /* movem [${Rs}${inc}],${Rd} */
5410 {
5411   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5412   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5413 #define FLD(f) abuf->fields.sfmt_movem_m_r_v32.f
5414   int UNUSED written = 0;
5415   IADDR UNUSED pc = abuf->addr;
5416   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5417
5418 {
5419   SI tmp_addr;
5420   BI tmp_postinc;
5421   tmp_postinc = FLD (f_memmode);
5422   tmp_addr = GET_H_GR (FLD (f_operand1));
5423 {
5424   SI tmp_dummy;
5425   tmp_dummy = GET_H_GR (FLD (f_operand2));
5426 }
5427 {
5428 if (GESI (FLD (f_operand2), 0)) {
5429 {
5430   SI tmp_tmp;
5431   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5432   {
5433     SI opval = tmp_tmp;
5434     SET_H_GR (((UINT) 0), opval);
5435     written |= (1 << 6);
5436     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5437   }
5438   tmp_addr = ADDSI (tmp_addr, 4);
5439 }
5440 }
5441 if (GESI (FLD (f_operand2), 1)) {
5442 {
5443   SI tmp_tmp;
5444   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5445   {
5446     SI opval = tmp_tmp;
5447     SET_H_GR (((UINT) 1), opval);
5448     written |= (1 << 7);
5449     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5450   }
5451   tmp_addr = ADDSI (tmp_addr, 4);
5452 }
5453 }
5454 if (GESI (FLD (f_operand2), 2)) {
5455 {
5456   SI tmp_tmp;
5457   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5458   {
5459     SI opval = tmp_tmp;
5460     SET_H_GR (((UINT) 2), opval);
5461     written |= (1 << 14);
5462     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5463   }
5464   tmp_addr = ADDSI (tmp_addr, 4);
5465 }
5466 }
5467 if (GESI (FLD (f_operand2), 3)) {
5468 {
5469   SI tmp_tmp;
5470   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5471   {
5472     SI opval = tmp_tmp;
5473     SET_H_GR (((UINT) 3), opval);
5474     written |= (1 << 15);
5475     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5476   }
5477   tmp_addr = ADDSI (tmp_addr, 4);
5478 }
5479 }
5480 if (GESI (FLD (f_operand2), 4)) {
5481 {
5482   SI tmp_tmp;
5483   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5484   {
5485     SI opval = tmp_tmp;
5486     SET_H_GR (((UINT) 4), opval);
5487     written |= (1 << 16);
5488     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5489   }
5490   tmp_addr = ADDSI (tmp_addr, 4);
5491 }
5492 }
5493 if (GESI (FLD (f_operand2), 5)) {
5494 {
5495   SI tmp_tmp;
5496   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5497   {
5498     SI opval = tmp_tmp;
5499     SET_H_GR (((UINT) 5), opval);
5500     written |= (1 << 17);
5501     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5502   }
5503   tmp_addr = ADDSI (tmp_addr, 4);
5504 }
5505 }
5506 if (GESI (FLD (f_operand2), 6)) {
5507 {
5508   SI tmp_tmp;
5509   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5510   {
5511     SI opval = tmp_tmp;
5512     SET_H_GR (((UINT) 6), opval);
5513     written |= (1 << 18);
5514     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5515   }
5516   tmp_addr = ADDSI (tmp_addr, 4);
5517 }
5518 }
5519 if (GESI (FLD (f_operand2), 7)) {
5520 {
5521   SI tmp_tmp;
5522   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5523   {
5524     SI opval = tmp_tmp;
5525     SET_H_GR (((UINT) 7), opval);
5526     written |= (1 << 19);
5527     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5528   }
5529   tmp_addr = ADDSI (tmp_addr, 4);
5530 }
5531 }
5532 if (GESI (FLD (f_operand2), 8)) {
5533 {
5534   SI tmp_tmp;
5535   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5536   {
5537     SI opval = tmp_tmp;
5538     SET_H_GR (((UINT) 8), opval);
5539     written |= (1 << 20);
5540     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5541   }
5542   tmp_addr = ADDSI (tmp_addr, 4);
5543 }
5544 }
5545 if (GESI (FLD (f_operand2), 9)) {
5546 {
5547   SI tmp_tmp;
5548   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5549   {
5550     SI opval = tmp_tmp;
5551     SET_H_GR (((UINT) 9), opval);
5552     written |= (1 << 21);
5553     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5554   }
5555   tmp_addr = ADDSI (tmp_addr, 4);
5556 }
5557 }
5558 if (GESI (FLD (f_operand2), 10)) {
5559 {
5560   SI tmp_tmp;
5561   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5562   {
5563     SI opval = tmp_tmp;
5564     SET_H_GR (((UINT) 10), opval);
5565     written |= (1 << 8);
5566     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5567   }
5568   tmp_addr = ADDSI (tmp_addr, 4);
5569 }
5570 }
5571 if (GESI (FLD (f_operand2), 11)) {
5572 {
5573   SI tmp_tmp;
5574   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5575   {
5576     SI opval = tmp_tmp;
5577     SET_H_GR (((UINT) 11), opval);
5578     written |= (1 << 9);
5579     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5580   }
5581   tmp_addr = ADDSI (tmp_addr, 4);
5582 }
5583 }
5584 if (GESI (FLD (f_operand2), 12)) {
5585 {
5586   SI tmp_tmp;
5587   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5588   {
5589     SI opval = tmp_tmp;
5590     SET_H_GR (((UINT) 12), opval);
5591     written |= (1 << 10);
5592     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5593   }
5594   tmp_addr = ADDSI (tmp_addr, 4);
5595 }
5596 }
5597 if (GESI (FLD (f_operand2), 13)) {
5598 {
5599   SI tmp_tmp;
5600   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5601   {
5602     SI opval = tmp_tmp;
5603     SET_H_GR (((UINT) 13), opval);
5604     written |= (1 << 11);
5605     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5606   }
5607   tmp_addr = ADDSI (tmp_addr, 4);
5608 }
5609 }
5610 if (GESI (FLD (f_operand2), 14)) {
5611 {
5612   SI tmp_tmp;
5613   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5614   {
5615     SI opval = tmp_tmp;
5616     SET_H_GR (((UINT) 14), opval);
5617     written |= (1 << 12);
5618     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5619   }
5620   tmp_addr = ADDSI (tmp_addr, 4);
5621 }
5622 }
5623 if (GESI (FLD (f_operand2), 15)) {
5624 {
5625   SI tmp_tmp;
5626   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5627   {
5628     SI opval = tmp_tmp;
5629     SET_H_GR (((UINT) 15), opval);
5630     written |= (1 << 13);
5631     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5632   }
5633   tmp_addr = ADDSI (tmp_addr, 4);
5634 }
5635 }
5636 }
5637 if (NEBI (tmp_postinc, 0)) {
5638   {
5639     SI opval = tmp_addr;
5640     SET_H_GR (FLD (f_operand1), opval);
5641     written |= (1 << 5);
5642     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5643   }
5644 }
5645 {
5646   {
5647     BI opval = 0;
5648     CPU (h_xbit) = opval;
5649     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5650   }
5651   {
5652     BI opval = 0;
5653     SET_H_INSN_PREFIXED_P (opval);
5654     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5655   }
5656 }
5657 }
5658
5659   abuf->written = written;
5660 #undef FLD
5661 }
5662   NEXT (vpc);
5663
5664   CASE (sem, INSN_ADD_B_R) : /* add.b $Rs,$Rd */
5665 {
5666   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5667   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5668 #define FLD(f) abuf->fields.sfmt_addc_m.f
5669   int UNUSED written = 0;
5670   IADDR UNUSED pc = abuf->addr;
5671   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5672
5673 {
5674   QI tmp_tmpopd;
5675   QI tmp_tmpops;
5676   BI tmp_carry;
5677   QI tmp_newval;
5678   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5679   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5680   tmp_carry = CPU (h_cbit);
5681   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5682 {
5683   SI tmp_oldregval;
5684   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
5685   {
5686     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5687     SET_H_GR (FLD (f_operand2), opval);
5688     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5689   }
5690 }
5691 {
5692   {
5693     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5694     CPU (h_cbit) = opval;
5695     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5696   }
5697   {
5698     BI opval = LTQI (tmp_newval, 0);
5699     CPU (h_nbit) = opval;
5700     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5701   }
5702   {
5703     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5704     CPU (h_zbit) = opval;
5705     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5706   }
5707   {
5708     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5709     CPU (h_vbit) = opval;
5710     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5711   }
5712 {
5713   {
5714     BI opval = 0;
5715     CPU (h_xbit) = opval;
5716     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5717   }
5718   {
5719     BI opval = 0;
5720     SET_H_INSN_PREFIXED_P (opval);
5721     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5722   }
5723 }
5724 }
5725 }
5726
5727 #undef FLD
5728 }
5729   NEXT (vpc);
5730
5731   CASE (sem, INSN_ADD_W_R) : /* add.w $Rs,$Rd */
5732 {
5733   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5734   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5735 #define FLD(f) abuf->fields.sfmt_addc_m.f
5736   int UNUSED written = 0;
5737   IADDR UNUSED pc = abuf->addr;
5738   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5739
5740 {
5741   HI tmp_tmpopd;
5742   HI tmp_tmpops;
5743   BI tmp_carry;
5744   HI tmp_newval;
5745   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5746   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5747   tmp_carry = CPU (h_cbit);
5748   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5749 {
5750   SI tmp_oldregval;
5751   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
5752   {
5753     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5754     SET_H_GR (FLD (f_operand2), opval);
5755     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5756   }
5757 }
5758 {
5759   {
5760     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5761     CPU (h_cbit) = opval;
5762     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5763   }
5764   {
5765     BI opval = LTHI (tmp_newval, 0);
5766     CPU (h_nbit) = opval;
5767     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5768   }
5769   {
5770     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5771     CPU (h_zbit) = opval;
5772     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5773   }
5774   {
5775     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
5776     CPU (h_vbit) = opval;
5777     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5778   }
5779 {
5780   {
5781     BI opval = 0;
5782     CPU (h_xbit) = opval;
5783     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5784   }
5785   {
5786     BI opval = 0;
5787     SET_H_INSN_PREFIXED_P (opval);
5788     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5789   }
5790 }
5791 }
5792 }
5793
5794 #undef FLD
5795 }
5796   NEXT (vpc);
5797
5798   CASE (sem, INSN_ADD_D_R) : /* add.d $Rs,$Rd */
5799 {
5800   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5801   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5802 #define FLD(f) abuf->fields.sfmt_addc_m.f
5803   int UNUSED written = 0;
5804   IADDR UNUSED pc = abuf->addr;
5805   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5806
5807 {
5808   SI tmp_tmpopd;
5809   SI tmp_tmpops;
5810   BI tmp_carry;
5811   SI tmp_newval;
5812   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5813   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5814   tmp_carry = CPU (h_cbit);
5815   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5816   {
5817     SI opval = tmp_newval;
5818     SET_H_GR (FLD (f_operand2), opval);
5819     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5820   }
5821 {
5822   {
5823     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
5824     CPU (h_cbit) = opval;
5825     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5826   }
5827   {
5828     BI opval = LTSI (tmp_newval, 0);
5829     CPU (h_nbit) = opval;
5830     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5831   }
5832   {
5833     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5834     CPU (h_zbit) = opval;
5835     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5836   }
5837   {
5838     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
5839     CPU (h_vbit) = opval;
5840     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5841   }
5842 {
5843   {
5844     BI opval = 0;
5845     CPU (h_xbit) = opval;
5846     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5847   }
5848   {
5849     BI opval = 0;
5850     SET_H_INSN_PREFIXED_P (opval);
5851     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5852   }
5853 }
5854 }
5855 }
5856
5857 #undef FLD
5858 }
5859   NEXT (vpc);
5860
5861   CASE (sem, INSN_ADD_M_B_M) : /* add-m.b [${Rs}${inc}],${Rd} */
5862 {
5863   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5864   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5865 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5866   int UNUSED written = 0;
5867   IADDR UNUSED pc = abuf->addr;
5868   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5869
5870 {
5871   QI tmp_tmpopd;
5872   QI tmp_tmpops;
5873   BI tmp_carry;
5874   QI tmp_newval;
5875   tmp_tmpops = ({   SI tmp_addr;
5876   QI tmp_tmp_mem;
5877   BI tmp_postinc;
5878   tmp_postinc = FLD (f_memmode);
5879 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
5880 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
5881 ; if (NEBI (tmp_postinc, 0)) {
5882 {
5883 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5884   tmp_addr = ADDSI (tmp_addr, 1);
5885 }
5886   {
5887     SI opval = tmp_addr;
5888     SET_H_GR (FLD (f_operand1), opval);
5889     written |= (1 << 12);
5890     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5891   }
5892 }
5893 }
5894 ; tmp_tmp_mem; });
5895   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5896   tmp_carry = CPU (h_cbit);
5897   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5898 {
5899   SI tmp_oldregval;
5900   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
5901   {
5902     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5903     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5904     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5905   }
5906 }
5907 {
5908   {
5909     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5910     CPU (h_cbit) = opval;
5911     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5912   }
5913   {
5914     BI opval = LTQI (tmp_newval, 0);
5915     CPU (h_nbit) = opval;
5916     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5917   }
5918   {
5919     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5920     CPU (h_zbit) = opval;
5921     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5922   }
5923   {
5924     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5925     CPU (h_vbit) = opval;
5926     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5927   }
5928 {
5929   {
5930     BI opval = 0;
5931     CPU (h_xbit) = opval;
5932     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5933   }
5934   {
5935     BI opval = 0;
5936     SET_H_INSN_PREFIXED_P (opval);
5937     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5938   }
5939 }
5940 }
5941 }
5942
5943   abuf->written = written;
5944 #undef FLD
5945 }
5946   NEXT (vpc);
5947
5948   CASE (sem, INSN_ADD_M_W_M) : /* add-m.w [${Rs}${inc}],${Rd} */
5949 {
5950   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5951   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5952 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5953   int UNUSED written = 0;
5954   IADDR UNUSED pc = abuf->addr;
5955   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5956
5957 {
5958   HI tmp_tmpopd;
5959   HI tmp_tmpops;
5960   BI tmp_carry;
5961   HI tmp_newval;
5962   tmp_tmpops = ({   SI tmp_addr;
5963   HI tmp_tmp_mem;
5964   BI tmp_postinc;
5965   tmp_postinc = FLD (f_memmode);
5966 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
5967 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
5968 ; if (NEBI (tmp_postinc, 0)) {
5969 {
5970 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5971   tmp_addr = ADDSI (tmp_addr, 2);
5972 }
5973   {
5974     SI opval = tmp_addr;
5975     SET_H_GR (FLD (f_operand1), opval);
5976     written |= (1 << 12);
5977     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5978   }
5979 }
5980 }
5981 ; tmp_tmp_mem; });
5982   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5983   tmp_carry = CPU (h_cbit);
5984   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5985 {
5986   SI tmp_oldregval;
5987   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
5988   {
5989     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5990     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5991     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5992   }
5993 }
5994 {
5995   {
5996     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5997     CPU (h_cbit) = opval;
5998     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5999   }
6000   {
6001     BI opval = LTHI (tmp_newval, 0);
6002     CPU (h_nbit) = opval;
6003     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6004   }
6005   {
6006     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6007     CPU (h_zbit) = opval;
6008     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6009   }
6010   {
6011     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
6012     CPU (h_vbit) = opval;
6013     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6014   }
6015 {
6016   {
6017     BI opval = 0;
6018     CPU (h_xbit) = opval;
6019     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6020   }
6021   {
6022     BI opval = 0;
6023     SET_H_INSN_PREFIXED_P (opval);
6024     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6025   }
6026 }
6027 }
6028 }
6029
6030   abuf->written = written;
6031 #undef FLD
6032 }
6033   NEXT (vpc);
6034
6035   CASE (sem, INSN_ADD_M_D_M) : /* add-m.d [${Rs}${inc}],${Rd} */
6036 {
6037   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6038   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6039 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6040   int UNUSED written = 0;
6041   IADDR UNUSED pc = abuf->addr;
6042   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6043
6044 {
6045   SI tmp_tmpopd;
6046   SI tmp_tmpops;
6047   BI tmp_carry;
6048   SI tmp_newval;
6049   tmp_tmpops = ({   SI tmp_addr;
6050   SI tmp_tmp_mem;
6051   BI tmp_postinc;
6052   tmp_postinc = FLD (f_memmode);
6053 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
6054 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
6055 ; if (NEBI (tmp_postinc, 0)) {
6056 {
6057 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6058   tmp_addr = ADDSI (tmp_addr, 4);
6059 }
6060   {
6061     SI opval = tmp_addr;
6062     SET_H_GR (FLD (f_operand1), opval);
6063     written |= (1 << 11);
6064     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6065   }
6066 }
6067 }
6068 ; tmp_tmp_mem; });
6069   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6070   tmp_carry = CPU (h_cbit);
6071   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6072   {
6073     SI opval = tmp_newval;
6074     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6075     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6076   }
6077 {
6078   {
6079     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6080     CPU (h_cbit) = opval;
6081     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6082   }
6083   {
6084     BI opval = LTSI (tmp_newval, 0);
6085     CPU (h_nbit) = opval;
6086     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6087   }
6088   {
6089     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6090     CPU (h_zbit) = opval;
6091     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6092   }
6093   {
6094     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6095     CPU (h_vbit) = opval;
6096     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6097   }
6098 {
6099   {
6100     BI opval = 0;
6101     CPU (h_xbit) = opval;
6102     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6103   }
6104   {
6105     BI opval = 0;
6106     SET_H_INSN_PREFIXED_P (opval);
6107     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6108   }
6109 }
6110 }
6111 }
6112
6113   abuf->written = written;
6114 #undef FLD
6115 }
6116   NEXT (vpc);
6117
6118   CASE (sem, INSN_ADDCBR) : /* add.b ${sconst8}],${Rd} */
6119 {
6120   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6121   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6122 #define FLD(f) abuf->fields.sfmt_addcbr.f
6123   int UNUSED written = 0;
6124   IADDR UNUSED pc = abuf->addr;
6125   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6126
6127 {
6128   QI tmp_tmpopd;
6129   QI tmp_tmpops;
6130   BI tmp_carry;
6131   QI tmp_newval;
6132   tmp_tmpops = FLD (f_indir_pc__byte);
6133   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6134   tmp_carry = CPU (h_cbit);
6135   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6136 {
6137   SI tmp_oldregval;
6138   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
6139   {
6140     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
6141     SET_H_GR (FLD (f_operand2), opval);
6142     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6143   }
6144 }
6145 {
6146   {
6147     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
6148     CPU (h_cbit) = opval;
6149     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6150   }
6151   {
6152     BI opval = LTQI (tmp_newval, 0);
6153     CPU (h_nbit) = opval;
6154     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6155   }
6156   {
6157     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6158     CPU (h_zbit) = opval;
6159     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6160   }
6161   {
6162     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
6163     CPU (h_vbit) = opval;
6164     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6165   }
6166 {
6167   {
6168     BI opval = 0;
6169     CPU (h_xbit) = opval;
6170     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6171   }
6172   {
6173     BI opval = 0;
6174     SET_H_INSN_PREFIXED_P (opval);
6175     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6176   }
6177 }
6178 }
6179 }
6180
6181 #undef FLD
6182 }
6183   NEXT (vpc);
6184
6185   CASE (sem, INSN_ADDCWR) : /* add.w ${sconst16}],${Rd} */
6186 {
6187   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6188   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6189 #define FLD(f) abuf->fields.sfmt_addcwr.f
6190   int UNUSED written = 0;
6191   IADDR UNUSED pc = abuf->addr;
6192   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6193
6194 {
6195   HI tmp_tmpopd;
6196   HI tmp_tmpops;
6197   BI tmp_carry;
6198   HI tmp_newval;
6199   tmp_tmpops = FLD (f_indir_pc__word);
6200   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6201   tmp_carry = CPU (h_cbit);
6202   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6203 {
6204   SI tmp_oldregval;
6205   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
6206   {
6207     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
6208     SET_H_GR (FLD (f_operand2), opval);
6209     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6210   }
6211 }
6212 {
6213   {
6214     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
6215     CPU (h_cbit) = opval;
6216     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6217   }
6218   {
6219     BI opval = LTHI (tmp_newval, 0);
6220     CPU (h_nbit) = opval;
6221     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6222   }
6223   {
6224     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6225     CPU (h_zbit) = opval;
6226     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6227   }
6228   {
6229     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
6230     CPU (h_vbit) = opval;
6231     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6232   }
6233 {
6234   {
6235     BI opval = 0;
6236     CPU (h_xbit) = opval;
6237     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6238   }
6239   {
6240     BI opval = 0;
6241     SET_H_INSN_PREFIXED_P (opval);
6242     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6243   }
6244 }
6245 }
6246 }
6247
6248 #undef FLD
6249 }
6250   NEXT (vpc);
6251
6252   CASE (sem, INSN_ADDCDR) : /* add.d ${const32}],${Rd} */
6253 {
6254   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6255   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6256 #define FLD(f) abuf->fields.sfmt_addcdr.f
6257   int UNUSED written = 0;
6258   IADDR UNUSED pc = abuf->addr;
6259   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
6260
6261 {
6262   SI tmp_tmpopd;
6263   SI tmp_tmpops;
6264   BI tmp_carry;
6265   SI tmp_newval;
6266   tmp_tmpops = FLD (f_indir_pc__dword);
6267   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6268   tmp_carry = CPU (h_cbit);
6269   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6270   {
6271     SI opval = tmp_newval;
6272     SET_H_GR (FLD (f_operand2), opval);
6273     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6274   }
6275 {
6276   {
6277     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6278     CPU (h_cbit) = opval;
6279     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6280   }
6281   {
6282     BI opval = LTSI (tmp_newval, 0);
6283     CPU (h_nbit) = opval;
6284     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6285   }
6286   {
6287     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6288     CPU (h_zbit) = opval;
6289     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6290   }
6291   {
6292     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6293     CPU (h_vbit) = opval;
6294     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6295   }
6296 {
6297   {
6298     BI opval = 0;
6299     CPU (h_xbit) = opval;
6300     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6301   }
6302   {
6303     BI opval = 0;
6304     SET_H_INSN_PREFIXED_P (opval);
6305     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6306   }
6307 }
6308 }
6309 }
6310
6311 #undef FLD
6312 }
6313   NEXT (vpc);
6314
6315   CASE (sem, INSN_ADDS_B_R) : /* adds.b $Rs,$Rd */
6316 {
6317   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6318   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6319 #define FLD(f) abuf->fields.sfmt_addc_m.f
6320   int UNUSED written = 0;
6321   IADDR UNUSED pc = abuf->addr;
6322   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6323
6324 {
6325   SI tmp_tmpopd;
6326   SI tmp_tmpops;
6327   BI tmp_carry;
6328   SI tmp_newval;
6329   tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
6330   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6331   tmp_carry = CPU (h_cbit);
6332   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6333   {
6334     SI opval = tmp_newval;
6335     SET_H_GR (FLD (f_operand2), opval);
6336     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6337   }
6338 {
6339   {
6340     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6341     CPU (h_cbit) = opval;
6342     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6343   }
6344   {
6345     BI opval = LTSI (tmp_newval, 0);
6346     CPU (h_nbit) = opval;
6347     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6348   }
6349   {
6350     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6351     CPU (h_zbit) = opval;
6352     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6353   }
6354   {
6355     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6356     CPU (h_vbit) = opval;
6357     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6358   }
6359 {
6360   {
6361     BI opval = 0;
6362     CPU (h_xbit) = opval;
6363     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6364   }
6365   {
6366     BI opval = 0;
6367     SET_H_INSN_PREFIXED_P (opval);
6368     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6369   }
6370 }
6371 }
6372 }
6373
6374 #undef FLD
6375 }
6376   NEXT (vpc);
6377
6378   CASE (sem, INSN_ADDS_W_R) : /* adds.w $Rs,$Rd */
6379 {
6380   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6381   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6382 #define FLD(f) abuf->fields.sfmt_addc_m.f
6383   int UNUSED written = 0;
6384   IADDR UNUSED pc = abuf->addr;
6385   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6386
6387 {
6388   SI tmp_tmpopd;
6389   SI tmp_tmpops;
6390   BI tmp_carry;
6391   SI tmp_newval;
6392   tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
6393   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6394   tmp_carry = CPU (h_cbit);
6395   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6396   {
6397     SI opval = tmp_newval;
6398     SET_H_GR (FLD (f_operand2), opval);
6399     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6400   }
6401 {
6402   {
6403     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6404     CPU (h_cbit) = opval;
6405     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6406   }
6407   {
6408     BI opval = LTSI (tmp_newval, 0);
6409     CPU (h_nbit) = opval;
6410     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6411   }
6412   {
6413     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6414     CPU (h_zbit) = opval;
6415     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6416   }
6417   {
6418     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6419     CPU (h_vbit) = opval;
6420     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6421   }
6422 {
6423   {
6424     BI opval = 0;
6425     CPU (h_xbit) = opval;
6426     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6427   }
6428   {
6429     BI opval = 0;
6430     SET_H_INSN_PREFIXED_P (opval);
6431     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6432   }
6433 }
6434 }
6435 }
6436
6437 #undef FLD
6438 }
6439   NEXT (vpc);
6440
6441   CASE (sem, INSN_ADDS_M_B_M) : /* adds-m.b [${Rs}${inc}],$Rd */
6442 {
6443   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6444   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6445 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6446   int UNUSED written = 0;
6447   IADDR UNUSED pc = abuf->addr;
6448   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6449
6450 {
6451   SI tmp_tmpopd;
6452   SI tmp_tmpops;
6453   BI tmp_carry;
6454   SI tmp_newval;
6455   tmp_tmpops = EXTQISI (({   SI tmp_addr;
6456   QI tmp_tmp_mem;
6457   BI tmp_postinc;
6458   tmp_postinc = FLD (f_memmode);
6459 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
6460 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
6461 ; if (NEBI (tmp_postinc, 0)) {
6462 {
6463 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6464   tmp_addr = ADDSI (tmp_addr, 1);
6465 }
6466   {
6467     SI opval = tmp_addr;
6468     SET_H_GR (FLD (f_operand1), opval);
6469     written |= (1 << 11);
6470     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6471   }
6472 }
6473 }
6474 ; tmp_tmp_mem; }));
6475   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6476   tmp_carry = CPU (h_cbit);
6477   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6478   {
6479     SI opval = tmp_newval;
6480     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6481     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6482   }
6483 {
6484   {
6485     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6486     CPU (h_cbit) = opval;
6487     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6488   }
6489   {
6490     BI opval = LTSI (tmp_newval, 0);
6491     CPU (h_nbit) = opval;
6492     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6493   }
6494   {
6495     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6496     CPU (h_zbit) = opval;
6497     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6498   }
6499   {
6500     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6501     CPU (h_vbit) = opval;
6502     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6503   }
6504 {
6505   {
6506     BI opval = 0;
6507     CPU (h_xbit) = opval;
6508     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6509   }
6510   {
6511     BI opval = 0;
6512     SET_H_INSN_PREFIXED_P (opval);
6513     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6514   }
6515 }
6516 }
6517 }
6518
6519   abuf->written = written;
6520 #undef FLD
6521 }
6522   NEXT (vpc);
6523
6524   CASE (sem, INSN_ADDS_M_W_M) : /* adds-m.w [${Rs}${inc}],$Rd */
6525 {
6526   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6527   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6528 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6529   int UNUSED written = 0;
6530   IADDR UNUSED pc = abuf->addr;
6531   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6532
6533 {
6534   SI tmp_tmpopd;
6535   SI tmp_tmpops;
6536   BI tmp_carry;
6537   SI tmp_newval;
6538   tmp_tmpops = EXTHISI (({   SI tmp_addr;
6539   HI tmp_tmp_mem;
6540   BI tmp_postinc;
6541   tmp_postinc = FLD (f_memmode);
6542 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
6543 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
6544 ; if (NEBI (tmp_postinc, 0)) {
6545 {
6546 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6547   tmp_addr = ADDSI (tmp_addr, 2);
6548 }
6549   {
6550     SI opval = tmp_addr;
6551     SET_H_GR (FLD (f_operand1), opval);
6552     written |= (1 << 11);
6553     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6554   }
6555 }
6556 }
6557 ; tmp_tmp_mem; }));
6558   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6559   tmp_carry = CPU (h_cbit);
6560   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6561   {
6562     SI opval = tmp_newval;
6563     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6564     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6565   }
6566 {
6567   {
6568     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6569     CPU (h_cbit) = opval;
6570     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6571   }
6572   {
6573     BI opval = LTSI (tmp_newval, 0);
6574     CPU (h_nbit) = opval;
6575     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6576   }
6577   {
6578     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6579     CPU (h_zbit) = opval;
6580     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6581   }
6582   {
6583     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6584     CPU (h_vbit) = opval;
6585     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6586   }
6587 {
6588   {
6589     BI opval = 0;
6590     CPU (h_xbit) = opval;
6591     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6592   }
6593   {
6594     BI opval = 0;
6595     SET_H_INSN_PREFIXED_P (opval);
6596     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6597   }
6598 }
6599 }
6600 }
6601
6602   abuf->written = written;
6603 #undef FLD
6604 }
6605   NEXT (vpc);
6606
6607   CASE (sem, INSN_ADDSCBR) : /* [${Rs}${inc}],$Rd */
6608 {
6609   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6610   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6611 #define FLD(f) abuf->fields.sfmt_addcbr.f
6612   int UNUSED written = 0;
6613   IADDR UNUSED pc = abuf->addr;
6614   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6615
6616 {
6617   SI tmp_tmpopd;
6618   SI tmp_tmpops;
6619   BI tmp_carry;
6620   SI tmp_newval;
6621   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
6622   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6623   tmp_carry = CPU (h_cbit);
6624   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6625   {
6626     SI opval = tmp_newval;
6627     SET_H_GR (FLD (f_operand2), opval);
6628     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6629   }
6630 {
6631   {
6632     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6633     CPU (h_cbit) = opval;
6634     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6635   }
6636   {
6637     BI opval = LTSI (tmp_newval, 0);
6638     CPU (h_nbit) = opval;
6639     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6640   }
6641   {
6642     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6643     CPU (h_zbit) = opval;
6644     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6645   }
6646   {
6647     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6648     CPU (h_vbit) = opval;
6649     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6650   }
6651 {
6652   {
6653     BI opval = 0;
6654     CPU (h_xbit) = opval;
6655     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6656   }
6657   {
6658     BI opval = 0;
6659     SET_H_INSN_PREFIXED_P (opval);
6660     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6661   }
6662 }
6663 }
6664 }
6665
6666 #undef FLD
6667 }
6668   NEXT (vpc);
6669
6670   CASE (sem, INSN_ADDSCWR) : /* [${Rs}${inc}],$Rd */
6671 {
6672   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6673   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6674 #define FLD(f) abuf->fields.sfmt_addcwr.f
6675   int UNUSED written = 0;
6676   IADDR UNUSED pc = abuf->addr;
6677   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6678
6679 {
6680   SI tmp_tmpopd;
6681   SI tmp_tmpops;
6682   BI tmp_carry;
6683   SI tmp_newval;
6684   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
6685   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6686   tmp_carry = CPU (h_cbit);
6687   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6688   {
6689     SI opval = tmp_newval;
6690     SET_H_GR (FLD (f_operand2), opval);
6691     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6692   }
6693 {
6694   {
6695     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6696     CPU (h_cbit) = opval;
6697     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6698   }
6699   {
6700     BI opval = LTSI (tmp_newval, 0);
6701     CPU (h_nbit) = opval;
6702     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6703   }
6704   {
6705     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6706     CPU (h_zbit) = opval;
6707     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6708   }
6709   {
6710     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6711     CPU (h_vbit) = opval;
6712     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6713   }
6714 {
6715   {
6716     BI opval = 0;
6717     CPU (h_xbit) = opval;
6718     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6719   }
6720   {
6721     BI opval = 0;
6722     SET_H_INSN_PREFIXED_P (opval);
6723     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6724   }
6725 }
6726 }
6727 }
6728
6729 #undef FLD
6730 }
6731   NEXT (vpc);
6732
6733   CASE (sem, INSN_ADDU_B_R) : /* addu.b $Rs,$Rd */
6734 {
6735   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6736   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6737 #define FLD(f) abuf->fields.sfmt_addc_m.f
6738   int UNUSED written = 0;
6739   IADDR UNUSED pc = abuf->addr;
6740   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6741
6742 {
6743   SI tmp_tmpopd;
6744   SI tmp_tmpops;
6745   BI tmp_carry;
6746   SI tmp_newval;
6747   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
6748   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6749   tmp_carry = CPU (h_cbit);
6750   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6751   {
6752     SI opval = tmp_newval;
6753     SET_H_GR (FLD (f_operand2), opval);
6754     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6755   }
6756 {
6757   {
6758     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6759     CPU (h_cbit) = opval;
6760     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6761   }
6762   {
6763     BI opval = LTSI (tmp_newval, 0);
6764     CPU (h_nbit) = opval;
6765     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6766   }
6767   {
6768     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6769     CPU (h_zbit) = opval;
6770     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6771   }
6772   {
6773     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6774     CPU (h_vbit) = opval;
6775     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6776   }
6777 {
6778   {
6779     BI opval = 0;
6780     CPU (h_xbit) = opval;
6781     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6782   }
6783   {
6784     BI opval = 0;
6785     SET_H_INSN_PREFIXED_P (opval);
6786     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6787   }
6788 }
6789 }
6790 }
6791
6792 #undef FLD
6793 }
6794   NEXT (vpc);
6795
6796   CASE (sem, INSN_ADDU_W_R) : /* addu.w $Rs,$Rd */
6797 {
6798   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6799   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6800 #define FLD(f) abuf->fields.sfmt_addc_m.f
6801   int UNUSED written = 0;
6802   IADDR UNUSED pc = abuf->addr;
6803   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6804
6805 {
6806   SI tmp_tmpopd;
6807   SI tmp_tmpops;
6808   BI tmp_carry;
6809   SI tmp_newval;
6810   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
6811   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6812   tmp_carry = CPU (h_cbit);
6813   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6814   {
6815     SI opval = tmp_newval;
6816     SET_H_GR (FLD (f_operand2), opval);
6817     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6818   }
6819 {
6820   {
6821     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6822     CPU (h_cbit) = opval;
6823     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6824   }
6825   {
6826     BI opval = LTSI (tmp_newval, 0);
6827     CPU (h_nbit) = opval;
6828     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6829   }
6830   {
6831     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6832     CPU (h_zbit) = opval;
6833     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6834   }
6835   {
6836     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6837     CPU (h_vbit) = opval;
6838     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6839   }
6840 {
6841   {
6842     BI opval = 0;
6843     CPU (h_xbit) = opval;
6844     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6845   }
6846   {
6847     BI opval = 0;
6848     SET_H_INSN_PREFIXED_P (opval);
6849     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6850   }
6851 }
6852 }
6853 }
6854
6855 #undef FLD
6856 }
6857   NEXT (vpc);
6858
6859   CASE (sem, INSN_ADDU_M_B_M) : /* addu-m.b [${Rs}${inc}],$Rd */
6860 {
6861   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6862   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6863 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6864   int UNUSED written = 0;
6865   IADDR UNUSED pc = abuf->addr;
6866   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6867
6868 {
6869   SI tmp_tmpopd;
6870   SI tmp_tmpops;
6871   BI tmp_carry;
6872   SI tmp_newval;
6873   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
6874   QI tmp_tmp_mem;
6875   BI tmp_postinc;
6876   tmp_postinc = FLD (f_memmode);
6877 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
6878 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
6879 ; if (NEBI (tmp_postinc, 0)) {
6880 {
6881 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6882   tmp_addr = ADDSI (tmp_addr, 1);
6883 }
6884   {
6885     SI opval = tmp_addr;
6886     SET_H_GR (FLD (f_operand1), opval);
6887     written |= (1 << 11);
6888     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6889   }
6890 }
6891 }
6892 ; tmp_tmp_mem; }));
6893   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6894   tmp_carry = CPU (h_cbit);
6895   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6896   {
6897     SI opval = tmp_newval;
6898     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6899     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6900   }
6901 {
6902   {
6903     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6904     CPU (h_cbit) = opval;
6905     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6906   }
6907   {
6908     BI opval = LTSI (tmp_newval, 0);
6909     CPU (h_nbit) = opval;
6910     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6911   }
6912   {
6913     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6914     CPU (h_zbit) = opval;
6915     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6916   }
6917   {
6918     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6919     CPU (h_vbit) = opval;
6920     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6921   }
6922 {
6923   {
6924     BI opval = 0;
6925     CPU (h_xbit) = opval;
6926     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6927   }
6928   {
6929     BI opval = 0;
6930     SET_H_INSN_PREFIXED_P (opval);
6931     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6932   }
6933 }
6934 }
6935 }
6936
6937   abuf->written = written;
6938 #undef FLD
6939 }
6940   NEXT (vpc);
6941
6942   CASE (sem, INSN_ADDU_M_W_M) : /* addu-m.w [${Rs}${inc}],$Rd */
6943 {
6944   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6945   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6946 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6947   int UNUSED written = 0;
6948   IADDR UNUSED pc = abuf->addr;
6949   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6950
6951 {
6952   SI tmp_tmpopd;
6953   SI tmp_tmpops;
6954   BI tmp_carry;
6955   SI tmp_newval;
6956   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
6957   HI tmp_tmp_mem;
6958   BI tmp_postinc;
6959   tmp_postinc = FLD (f_memmode);
6960 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
6961 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
6962 ; if (NEBI (tmp_postinc, 0)) {
6963 {
6964 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6965   tmp_addr = ADDSI (tmp_addr, 2);
6966 }
6967   {
6968     SI opval = tmp_addr;
6969     SET_H_GR (FLD (f_operand1), opval);
6970     written |= (1 << 11);
6971     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6972   }
6973 }
6974 }
6975 ; tmp_tmp_mem; }));
6976   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6977   tmp_carry = CPU (h_cbit);
6978   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6979   {
6980     SI opval = tmp_newval;
6981     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6982     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6983   }
6984 {
6985   {
6986     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6987     CPU (h_cbit) = opval;
6988     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6989   }
6990   {
6991     BI opval = LTSI (tmp_newval, 0);
6992     CPU (h_nbit) = opval;
6993     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6994   }
6995   {
6996     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6997     CPU (h_zbit) = opval;
6998     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6999   }
7000   {
7001     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7002     CPU (h_vbit) = opval;
7003     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7004   }
7005 {
7006   {
7007     BI opval = 0;
7008     CPU (h_xbit) = opval;
7009     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7010   }
7011   {
7012     BI opval = 0;
7013     SET_H_INSN_PREFIXED_P (opval);
7014     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7015   }
7016 }
7017 }
7018 }
7019
7020   abuf->written = written;
7021 #undef FLD
7022 }
7023   NEXT (vpc);
7024
7025   CASE (sem, INSN_ADDUCBR) : /* [${Rs}${inc}],$Rd */
7026 {
7027   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7028   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7029 #define FLD(f) abuf->fields.sfmt_addcbr.f
7030   int UNUSED written = 0;
7031   IADDR UNUSED pc = abuf->addr;
7032   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7033
7034 {
7035   SI tmp_tmpopd;
7036   SI tmp_tmpops;
7037   BI tmp_carry;
7038   SI tmp_newval;
7039   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
7040   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7041   tmp_carry = CPU (h_cbit);
7042   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7043   {
7044     SI opval = tmp_newval;
7045     SET_H_GR (FLD (f_operand2), opval);
7046     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7047   }
7048 {
7049   {
7050     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
7051     CPU (h_cbit) = opval;
7052     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7053   }
7054   {
7055     BI opval = LTSI (tmp_newval, 0);
7056     CPU (h_nbit) = opval;
7057     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7058   }
7059   {
7060     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7061     CPU (h_zbit) = opval;
7062     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7063   }
7064   {
7065     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7066     CPU (h_vbit) = opval;
7067     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7068   }
7069 {
7070   {
7071     BI opval = 0;
7072     CPU (h_xbit) = opval;
7073     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7074   }
7075   {
7076     BI opval = 0;
7077     SET_H_INSN_PREFIXED_P (opval);
7078     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7079   }
7080 }
7081 }
7082 }
7083
7084 #undef FLD
7085 }
7086   NEXT (vpc);
7087
7088   CASE (sem, INSN_ADDUCWR) : /* [${Rs}${inc}],$Rd */
7089 {
7090   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7091   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7092 #define FLD(f) abuf->fields.sfmt_addcwr.f
7093   int UNUSED written = 0;
7094   IADDR UNUSED pc = abuf->addr;
7095   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7096
7097 {
7098   SI tmp_tmpopd;
7099   SI tmp_tmpops;
7100   BI tmp_carry;
7101   SI tmp_newval;
7102   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
7103   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7104   tmp_carry = CPU (h_cbit);
7105   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7106   {
7107     SI opval = tmp_newval;
7108     SET_H_GR (FLD (f_operand2), opval);
7109     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7110   }
7111 {
7112   {
7113     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
7114     CPU (h_cbit) = opval;
7115     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7116   }
7117   {
7118     BI opval = LTSI (tmp_newval, 0);
7119     CPU (h_nbit) = opval;
7120     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7121   }
7122   {
7123     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7124     CPU (h_zbit) = opval;
7125     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7126   }
7127   {
7128     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7129     CPU (h_vbit) = opval;
7130     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7131   }
7132 {
7133   {
7134     BI opval = 0;
7135     CPU (h_xbit) = opval;
7136     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7137   }
7138   {
7139     BI opval = 0;
7140     SET_H_INSN_PREFIXED_P (opval);
7141     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7142   }
7143 }
7144 }
7145 }
7146
7147 #undef FLD
7148 }
7149   NEXT (vpc);
7150
7151   CASE (sem, INSN_SUB_B_R) : /* sub.b $Rs,$Rd */
7152 {
7153   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7154   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7155 #define FLD(f) abuf->fields.sfmt_addc_m.f
7156   int UNUSED written = 0;
7157   IADDR UNUSED pc = abuf->addr;
7158   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7159
7160 {
7161   QI tmp_tmpopd;
7162   QI tmp_tmpops;
7163   BI tmp_carry;
7164   QI tmp_newval;
7165   tmp_tmpops = GET_H_GR (FLD (f_operand1));
7166   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7167   tmp_carry = CPU (h_cbit);
7168   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7169 {
7170   SI tmp_oldregval;
7171   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
7172   {
7173     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
7174     SET_H_GR (FLD (f_operand2), opval);
7175     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7176   }
7177 }
7178 {
7179   {
7180     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
7181     CPU (h_cbit) = opval;
7182     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7183   }
7184   {
7185     BI opval = LTQI (tmp_newval, 0);
7186     CPU (h_nbit) = opval;
7187     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7188   }
7189   {
7190     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7191     CPU (h_zbit) = opval;
7192     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7193   }
7194   {
7195     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7196     CPU (h_vbit) = opval;
7197     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7198   }
7199 {
7200   {
7201     BI opval = 0;
7202     CPU (h_xbit) = opval;
7203     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7204   }
7205   {
7206     BI opval = 0;
7207     SET_H_INSN_PREFIXED_P (opval);
7208     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7209   }
7210 }
7211 }
7212 }
7213
7214 #undef FLD
7215 }
7216   NEXT (vpc);
7217
7218   CASE (sem, INSN_SUB_W_R) : /* sub.w $Rs,$Rd */
7219 {
7220   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7221   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7222 #define FLD(f) abuf->fields.sfmt_addc_m.f
7223   int UNUSED written = 0;
7224   IADDR UNUSED pc = abuf->addr;
7225   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7226
7227 {
7228   HI tmp_tmpopd;
7229   HI tmp_tmpops;
7230   BI tmp_carry;
7231   HI tmp_newval;
7232   tmp_tmpops = GET_H_GR (FLD (f_operand1));
7233   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7234   tmp_carry = CPU (h_cbit);
7235   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7236 {
7237   SI tmp_oldregval;
7238   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
7239   {
7240     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7241     SET_H_GR (FLD (f_operand2), opval);
7242     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7243   }
7244 }
7245 {
7246   {
7247     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7248     CPU (h_cbit) = opval;
7249     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7250   }
7251   {
7252     BI opval = LTHI (tmp_newval, 0);
7253     CPU (h_nbit) = opval;
7254     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7255   }
7256   {
7257     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7258     CPU (h_zbit) = opval;
7259     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7260   }
7261   {
7262     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7263     CPU (h_vbit) = opval;
7264     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7265   }
7266 {
7267   {
7268     BI opval = 0;
7269     CPU (h_xbit) = opval;
7270     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7271   }
7272   {
7273     BI opval = 0;
7274     SET_H_INSN_PREFIXED_P (opval);
7275     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7276   }
7277 }
7278 }
7279 }
7280
7281 #undef FLD
7282 }
7283   NEXT (vpc);
7284
7285   CASE (sem, INSN_SUB_D_R) : /* sub.d $Rs,$Rd */
7286 {
7287   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7288   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7289 #define FLD(f) abuf->fields.sfmt_addc_m.f
7290   int UNUSED written = 0;
7291   IADDR UNUSED pc = abuf->addr;
7292   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7293
7294 {
7295   SI tmp_tmpopd;
7296   SI tmp_tmpops;
7297   BI tmp_carry;
7298   SI tmp_newval;
7299   tmp_tmpops = GET_H_GR (FLD (f_operand1));
7300   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7301   tmp_carry = CPU (h_cbit);
7302   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7303   {
7304     SI opval = tmp_newval;
7305     SET_H_GR (FLD (f_operand2), opval);
7306     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7307   }
7308 {
7309   {
7310     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7311     CPU (h_cbit) = opval;
7312     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7313   }
7314   {
7315     BI opval = LTSI (tmp_newval, 0);
7316     CPU (h_nbit) = opval;
7317     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7318   }
7319   {
7320     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7321     CPU (h_zbit) = opval;
7322     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7323   }
7324   {
7325     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7326     CPU (h_vbit) = opval;
7327     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7328   }
7329 {
7330   {
7331     BI opval = 0;
7332     CPU (h_xbit) = opval;
7333     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7334   }
7335   {
7336     BI opval = 0;
7337     SET_H_INSN_PREFIXED_P (opval);
7338     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7339   }
7340 }
7341 }
7342 }
7343
7344 #undef FLD
7345 }
7346   NEXT (vpc);
7347
7348   CASE (sem, INSN_SUB_M_B_M) : /* sub-m.b [${Rs}${inc}],${Rd} */
7349 {
7350   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7351   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7352 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7353   int UNUSED written = 0;
7354   IADDR UNUSED pc = abuf->addr;
7355   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7356
7357 {
7358   QI tmp_tmpopd;
7359   QI tmp_tmpops;
7360   BI tmp_carry;
7361   QI tmp_newval;
7362   tmp_tmpops = ({   SI tmp_addr;
7363   QI tmp_tmp_mem;
7364   BI tmp_postinc;
7365   tmp_postinc = FLD (f_memmode);
7366 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7367 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
7368 ; if (NEBI (tmp_postinc, 0)) {
7369 {
7370 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7371   tmp_addr = ADDSI (tmp_addr, 1);
7372 }
7373   {
7374     SI opval = tmp_addr;
7375     SET_H_GR (FLD (f_operand1), opval);
7376     written |= (1 << 12);
7377     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7378   }
7379 }
7380 }
7381 ; tmp_tmp_mem; });
7382   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7383   tmp_carry = CPU (h_cbit);
7384   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7385 {
7386   SI tmp_oldregval;
7387   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
7388   {
7389     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
7390     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7391     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7392   }
7393 }
7394 {
7395   {
7396     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
7397     CPU (h_cbit) = opval;
7398     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7399   }
7400   {
7401     BI opval = LTQI (tmp_newval, 0);
7402     CPU (h_nbit) = opval;
7403     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7404   }
7405   {
7406     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7407     CPU (h_zbit) = opval;
7408     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7409   }
7410   {
7411     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7412     CPU (h_vbit) = opval;
7413     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7414   }
7415 {
7416   {
7417     BI opval = 0;
7418     CPU (h_xbit) = opval;
7419     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7420   }
7421   {
7422     BI opval = 0;
7423     SET_H_INSN_PREFIXED_P (opval);
7424     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7425   }
7426 }
7427 }
7428 }
7429
7430   abuf->written = written;
7431 #undef FLD
7432 }
7433   NEXT (vpc);
7434
7435   CASE (sem, INSN_SUB_M_W_M) : /* sub-m.w [${Rs}${inc}],${Rd} */
7436 {
7437   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7438   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7439 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7440   int UNUSED written = 0;
7441   IADDR UNUSED pc = abuf->addr;
7442   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7443
7444 {
7445   HI tmp_tmpopd;
7446   HI tmp_tmpops;
7447   BI tmp_carry;
7448   HI tmp_newval;
7449   tmp_tmpops = ({   SI tmp_addr;
7450   HI tmp_tmp_mem;
7451   BI tmp_postinc;
7452   tmp_postinc = FLD (f_memmode);
7453 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7454 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
7455 ; if (NEBI (tmp_postinc, 0)) {
7456 {
7457 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7458   tmp_addr = ADDSI (tmp_addr, 2);
7459 }
7460   {
7461     SI opval = tmp_addr;
7462     SET_H_GR (FLD (f_operand1), opval);
7463     written |= (1 << 12);
7464     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7465   }
7466 }
7467 }
7468 ; tmp_tmp_mem; });
7469   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7470   tmp_carry = CPU (h_cbit);
7471   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7472 {
7473   SI tmp_oldregval;
7474   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
7475   {
7476     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7477     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7478     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7479   }
7480 }
7481 {
7482   {
7483     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7484     CPU (h_cbit) = opval;
7485     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7486   }
7487   {
7488     BI opval = LTHI (tmp_newval, 0);
7489     CPU (h_nbit) = opval;
7490     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7491   }
7492   {
7493     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7494     CPU (h_zbit) = opval;
7495     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7496   }
7497   {
7498     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7499     CPU (h_vbit) = opval;
7500     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7501   }
7502 {
7503   {
7504     BI opval = 0;
7505     CPU (h_xbit) = opval;
7506     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7507   }
7508   {
7509     BI opval = 0;
7510     SET_H_INSN_PREFIXED_P (opval);
7511     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7512   }
7513 }
7514 }
7515 }
7516
7517   abuf->written = written;
7518 #undef FLD
7519 }
7520   NEXT (vpc);
7521
7522   CASE (sem, INSN_SUB_M_D_M) : /* sub-m.d [${Rs}${inc}],${Rd} */
7523 {
7524   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7525   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7526 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7527   int UNUSED written = 0;
7528   IADDR UNUSED pc = abuf->addr;
7529   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7530
7531 {
7532   SI tmp_tmpopd;
7533   SI tmp_tmpops;
7534   BI tmp_carry;
7535   SI tmp_newval;
7536   tmp_tmpops = ({   SI tmp_addr;
7537   SI tmp_tmp_mem;
7538   BI tmp_postinc;
7539   tmp_postinc = FLD (f_memmode);
7540 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7541 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
7542 ; if (NEBI (tmp_postinc, 0)) {
7543 {
7544 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7545   tmp_addr = ADDSI (tmp_addr, 4);
7546 }
7547   {
7548     SI opval = tmp_addr;
7549     SET_H_GR (FLD (f_operand1), opval);
7550     written |= (1 << 11);
7551     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7552   }
7553 }
7554 }
7555 ; tmp_tmp_mem; });
7556   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7557   tmp_carry = CPU (h_cbit);
7558   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7559   {
7560     SI opval = tmp_newval;
7561     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7562     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7563   }
7564 {
7565   {
7566     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7567     CPU (h_cbit) = opval;
7568     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7569   }
7570   {
7571     BI opval = LTSI (tmp_newval, 0);
7572     CPU (h_nbit) = opval;
7573     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7574   }
7575   {
7576     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7577     CPU (h_zbit) = opval;
7578     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7579   }
7580   {
7581     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7582     CPU (h_vbit) = opval;
7583     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7584   }
7585 {
7586   {
7587     BI opval = 0;
7588     CPU (h_xbit) = opval;
7589     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7590   }
7591   {
7592     BI opval = 0;
7593     SET_H_INSN_PREFIXED_P (opval);
7594     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7595   }
7596 }
7597 }
7598 }
7599
7600   abuf->written = written;
7601 #undef FLD
7602 }
7603   NEXT (vpc);
7604
7605   CASE (sem, INSN_SUBCBR) : /* sub.b ${sconst8}],${Rd} */
7606 {
7607   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7608   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7609 #define FLD(f) abuf->fields.sfmt_addcbr.f
7610   int UNUSED written = 0;
7611   IADDR UNUSED pc = abuf->addr;
7612   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7613
7614 {
7615   QI tmp_tmpopd;
7616   QI tmp_tmpops;
7617   BI tmp_carry;
7618   QI tmp_newval;
7619   tmp_tmpops = FLD (f_indir_pc__byte);
7620   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7621   tmp_carry = CPU (h_cbit);
7622   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7623 {
7624   SI tmp_oldregval;
7625   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
7626   {
7627     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
7628     SET_H_GR (FLD (f_operand2), opval);
7629     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7630   }
7631 }
7632 {
7633   {
7634     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
7635     CPU (h_cbit) = opval;
7636     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7637   }
7638   {
7639     BI opval = LTQI (tmp_newval, 0);
7640     CPU (h_nbit) = opval;
7641     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7642   }
7643   {
7644     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7645     CPU (h_zbit) = opval;
7646     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7647   }
7648   {
7649     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7650     CPU (h_vbit) = opval;
7651     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7652   }
7653 {
7654   {
7655     BI opval = 0;
7656     CPU (h_xbit) = opval;
7657     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7658   }
7659   {
7660     BI opval = 0;
7661     SET_H_INSN_PREFIXED_P (opval);
7662     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7663   }
7664 }
7665 }
7666 }
7667
7668 #undef FLD
7669 }
7670   NEXT (vpc);
7671
7672   CASE (sem, INSN_SUBCWR) : /* sub.w ${sconst16}],${Rd} */
7673 {
7674   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7675   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7676 #define FLD(f) abuf->fields.sfmt_addcwr.f
7677   int UNUSED written = 0;
7678   IADDR UNUSED pc = abuf->addr;
7679   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7680
7681 {
7682   HI tmp_tmpopd;
7683   HI tmp_tmpops;
7684   BI tmp_carry;
7685   HI tmp_newval;
7686   tmp_tmpops = FLD (f_indir_pc__word);
7687   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7688   tmp_carry = CPU (h_cbit);
7689   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7690 {
7691   SI tmp_oldregval;
7692   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
7693   {
7694     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7695     SET_H_GR (FLD (f_operand2), opval);
7696     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7697   }
7698 }
7699 {
7700   {
7701     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7702     CPU (h_cbit) = opval;
7703     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7704   }
7705   {
7706     BI opval = LTHI (tmp_newval, 0);
7707     CPU (h_nbit) = opval;
7708     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7709   }
7710   {
7711     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7712     CPU (h_zbit) = opval;
7713     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7714   }
7715   {
7716     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7717     CPU (h_vbit) = opval;
7718     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7719   }
7720 {
7721   {
7722     BI opval = 0;
7723     CPU (h_xbit) = opval;
7724     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7725   }
7726   {
7727     BI opval = 0;
7728     SET_H_INSN_PREFIXED_P (opval);
7729     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7730   }
7731 }
7732 }
7733 }
7734
7735 #undef FLD
7736 }
7737   NEXT (vpc);
7738
7739   CASE (sem, INSN_SUBCDR) : /* sub.d ${const32}],${Rd} */
7740 {
7741   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7742   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7743 #define FLD(f) abuf->fields.sfmt_addcdr.f
7744   int UNUSED written = 0;
7745   IADDR UNUSED pc = abuf->addr;
7746   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
7747
7748 {
7749   SI tmp_tmpopd;
7750   SI tmp_tmpops;
7751   BI tmp_carry;
7752   SI tmp_newval;
7753   tmp_tmpops = FLD (f_indir_pc__dword);
7754   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7755   tmp_carry = CPU (h_cbit);
7756   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7757   {
7758     SI opval = tmp_newval;
7759     SET_H_GR (FLD (f_operand2), opval);
7760     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7761   }
7762 {
7763   {
7764     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7765     CPU (h_cbit) = opval;
7766     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7767   }
7768   {
7769     BI opval = LTSI (tmp_newval, 0);
7770     CPU (h_nbit) = opval;
7771     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7772   }
7773   {
7774     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7775     CPU (h_zbit) = opval;
7776     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7777   }
7778   {
7779     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7780     CPU (h_vbit) = opval;
7781     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7782   }
7783 {
7784   {
7785     BI opval = 0;
7786     CPU (h_xbit) = opval;
7787     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7788   }
7789   {
7790     BI opval = 0;
7791     SET_H_INSN_PREFIXED_P (opval);
7792     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7793   }
7794 }
7795 }
7796 }
7797
7798 #undef FLD
7799 }
7800   NEXT (vpc);
7801
7802   CASE (sem, INSN_SUBS_B_R) : /* subs.b $Rs,$Rd */
7803 {
7804   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7805   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7806 #define FLD(f) abuf->fields.sfmt_addc_m.f
7807   int UNUSED written = 0;
7808   IADDR UNUSED pc = abuf->addr;
7809   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7810
7811 {
7812   SI tmp_tmpopd;
7813   SI tmp_tmpops;
7814   BI tmp_carry;
7815   SI tmp_newval;
7816   tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
7817   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7818   tmp_carry = CPU (h_cbit);
7819   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7820   {
7821     SI opval = tmp_newval;
7822     SET_H_GR (FLD (f_operand2), opval);
7823     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7824   }
7825 {
7826   {
7827     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7828     CPU (h_cbit) = opval;
7829     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7830   }
7831   {
7832     BI opval = LTSI (tmp_newval, 0);
7833     CPU (h_nbit) = opval;
7834     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7835   }
7836   {
7837     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7838     CPU (h_zbit) = opval;
7839     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7840   }
7841   {
7842     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7843     CPU (h_vbit) = opval;
7844     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7845   }
7846 {
7847   {
7848     BI opval = 0;
7849     CPU (h_xbit) = opval;
7850     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7851   }
7852   {
7853     BI opval = 0;
7854     SET_H_INSN_PREFIXED_P (opval);
7855     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7856   }
7857 }
7858 }
7859 }
7860
7861 #undef FLD
7862 }
7863   NEXT (vpc);
7864
7865   CASE (sem, INSN_SUBS_W_R) : /* subs.w $Rs,$Rd */
7866 {
7867   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7868   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7869 #define FLD(f) abuf->fields.sfmt_addc_m.f
7870   int UNUSED written = 0;
7871   IADDR UNUSED pc = abuf->addr;
7872   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7873
7874 {
7875   SI tmp_tmpopd;
7876   SI tmp_tmpops;
7877   BI tmp_carry;
7878   SI tmp_newval;
7879   tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
7880   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7881   tmp_carry = CPU (h_cbit);
7882   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7883   {
7884     SI opval = tmp_newval;
7885     SET_H_GR (FLD (f_operand2), opval);
7886     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7887   }
7888 {
7889   {
7890     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7891     CPU (h_cbit) = opval;
7892     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7893   }
7894   {
7895     BI opval = LTSI (tmp_newval, 0);
7896     CPU (h_nbit) = opval;
7897     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7898   }
7899   {
7900     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7901     CPU (h_zbit) = opval;
7902     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7903   }
7904   {
7905     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7906     CPU (h_vbit) = opval;
7907     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7908   }
7909 {
7910   {
7911     BI opval = 0;
7912     CPU (h_xbit) = opval;
7913     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7914   }
7915   {
7916     BI opval = 0;
7917     SET_H_INSN_PREFIXED_P (opval);
7918     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7919   }
7920 }
7921 }
7922 }
7923
7924 #undef FLD
7925 }
7926   NEXT (vpc);
7927
7928   CASE (sem, INSN_SUBS_M_B_M) : /* subs-m.b [${Rs}${inc}],$Rd */
7929 {
7930   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7931   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7932 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7933   int UNUSED written = 0;
7934   IADDR UNUSED pc = abuf->addr;
7935   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7936
7937 {
7938   SI tmp_tmpopd;
7939   SI tmp_tmpops;
7940   BI tmp_carry;
7941   SI tmp_newval;
7942   tmp_tmpops = EXTQISI (({   SI tmp_addr;
7943   QI tmp_tmp_mem;
7944   BI tmp_postinc;
7945   tmp_postinc = FLD (f_memmode);
7946 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7947 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
7948 ; if (NEBI (tmp_postinc, 0)) {
7949 {
7950 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7951   tmp_addr = ADDSI (tmp_addr, 1);
7952 }
7953   {
7954     SI opval = tmp_addr;
7955     SET_H_GR (FLD (f_operand1), opval);
7956     written |= (1 << 11);
7957     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7958   }
7959 }
7960 }
7961 ; tmp_tmp_mem; }));
7962   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7963   tmp_carry = CPU (h_cbit);
7964   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7965   {
7966     SI opval = tmp_newval;
7967     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7968     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7969   }
7970 {
7971   {
7972     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7973     CPU (h_cbit) = opval;
7974     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7975   }
7976   {
7977     BI opval = LTSI (tmp_newval, 0);
7978     CPU (h_nbit) = opval;
7979     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7980   }
7981   {
7982     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7983     CPU (h_zbit) = opval;
7984     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7985   }
7986   {
7987     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7988     CPU (h_vbit) = opval;
7989     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7990   }
7991 {
7992   {
7993     BI opval = 0;
7994     CPU (h_xbit) = opval;
7995     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7996   }
7997   {
7998     BI opval = 0;
7999     SET_H_INSN_PREFIXED_P (opval);
8000     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8001   }
8002 }
8003 }
8004 }
8005
8006   abuf->written = written;
8007 #undef FLD
8008 }
8009   NEXT (vpc);
8010
8011   CASE (sem, INSN_SUBS_M_W_M) : /* subs-m.w [${Rs}${inc}],$Rd */
8012 {
8013   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8014   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8015 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
8016   int UNUSED written = 0;
8017   IADDR UNUSED pc = abuf->addr;
8018   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8019
8020 {
8021   SI tmp_tmpopd;
8022   SI tmp_tmpops;
8023   BI tmp_carry;
8024   SI tmp_newval;
8025   tmp_tmpops = EXTHISI (({   SI tmp_addr;
8026   HI tmp_tmp_mem;
8027   BI tmp_postinc;
8028   tmp_postinc = FLD (f_memmode);
8029 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
8030 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
8031 ; if (NEBI (tmp_postinc, 0)) {
8032 {
8033 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8034   tmp_addr = ADDSI (tmp_addr, 2);
8035 }
8036   {
8037     SI opval = tmp_addr;
8038     SET_H_GR (FLD (f_operand1), opval);
8039     written |= (1 << 11);
8040     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8041   }
8042 }
8043 }
8044 ; tmp_tmp_mem; }));
8045   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8046   tmp_carry = CPU (h_cbit);
8047   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8048   {
8049     SI opval = tmp_newval;
8050     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
8051     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8052   }
8053 {
8054   {
8055     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8056     CPU (h_cbit) = opval;
8057     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8058   }
8059   {
8060     BI opval = LTSI (tmp_newval, 0);
8061     CPU (h_nbit) = opval;
8062     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8063   }
8064   {
8065     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8066     CPU (h_zbit) = opval;
8067     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8068   }
8069   {
8070     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8071     CPU (h_vbit) = opval;
8072     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8073   }
8074 {
8075   {
8076     BI opval = 0;
8077     CPU (h_xbit) = opval;
8078     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8079   }
8080   {
8081     BI opval = 0;
8082     SET_H_INSN_PREFIXED_P (opval);
8083     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8084   }
8085 }
8086 }
8087 }
8088
8089   abuf->written = written;
8090 #undef FLD
8091 }
8092   NEXT (vpc);
8093
8094   CASE (sem, INSN_SUBSCBR) : /* [${Rs}${inc}],$Rd */
8095 {
8096   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8097   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8098 #define FLD(f) abuf->fields.sfmt_addcbr.f
8099   int UNUSED written = 0;
8100   IADDR UNUSED pc = abuf->addr;
8101   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8102
8103 {
8104   SI tmp_tmpopd;
8105   SI tmp_tmpops;
8106   BI tmp_carry;
8107   SI tmp_newval;
8108   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
8109   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8110   tmp_carry = CPU (h_cbit);
8111   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8112   {
8113     SI opval = tmp_newval;
8114     SET_H_GR (FLD (f_operand2), opval);
8115     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8116   }
8117 {
8118   {
8119     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8120     CPU (h_cbit) = opval;
8121     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8122   }
8123   {
8124     BI opval = LTSI (tmp_newval, 0);
8125     CPU (h_nbit) = opval;
8126     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8127   }
8128   {
8129     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8130     CPU (h_zbit) = opval;
8131     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8132   }
8133   {
8134     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8135     CPU (h_vbit) = opval;
8136     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8137   }
8138 {
8139   {
8140     BI opval = 0;
8141     CPU (h_xbit) = opval;
8142     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8143   }
8144   {
8145     BI opval = 0;
8146     SET_H_INSN_PREFIXED_P (opval);
8147     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8148   }
8149 }
8150 }
8151 }
8152
8153 #undef FLD
8154 }
8155   NEXT (vpc);
8156
8157   CASE (sem, INSN_SUBSCWR) : /* [${Rs}${inc}],$Rd */
8158 {
8159   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8160   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8161 #define FLD(f) abuf->fields.sfmt_addcwr.f
8162   int UNUSED written = 0;
8163   IADDR UNUSED pc = abuf->addr;
8164   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8165
8166 {
8167   SI tmp_tmpopd;
8168   SI tmp_tmpops;
8169   BI tmp_carry;
8170   SI tmp_newval;
8171   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
8172   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8173   tmp_carry = CPU (h_cbit);
8174   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8175   {
8176     SI opval = tmp_newval;
8177     SET_H_GR (FLD (f_operand2), opval);
8178     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8179   }
8180 {
8181   {
8182     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8183     CPU (h_cbit) = opval;
8184     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8185   }
8186   {
8187     BI opval = LTSI (tmp_newval, 0);
8188     CPU (h_nbit) = opval;
8189     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8190   }
8191   {
8192     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8193     CPU (h_zbit) = opval;
8194     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8195   }
8196   {
8197     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8198     CPU (h_vbit) = opval;
8199     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8200   }
8201 {
8202   {
8203     BI opval = 0;
8204     CPU (h_xbit) = opval;
8205     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8206   }
8207   {
8208     BI opval = 0;
8209     SET_H_INSN_PREFIXED_P (opval);
8210     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8211   }
8212 }
8213 }
8214 }
8215
8216 #undef FLD
8217 }
8218   NEXT (vpc);
8219
8220   CASE (sem, INSN_SUBU_B_R) : /* subu.b $Rs,$Rd */
8221 {
8222   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8223   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8224 #define FLD(f) abuf->fields.sfmt_addc_m.f
8225   int UNUSED written = 0;
8226   IADDR UNUSED pc = abuf->addr;
8227   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8228
8229 {
8230   SI tmp_tmpopd;
8231   SI tmp_tmpops;
8232   BI tmp_carry;
8233   SI tmp_newval;
8234   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
8235   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8236   tmp_carry = CPU (h_cbit);
8237   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8238   {
8239     SI opval = tmp_newval;
8240     SET_H_GR (FLD (f_operand2), opval);
8241     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8242   }
8243 {
8244   {
8245     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8246     CPU (h_cbit) = opval;
8247     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8248   }
8249   {
8250     BI opval = LTSI (tmp_newval, 0);
8251     CPU (h_nbit) = opval;
8252     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8253   }
8254   {
8255     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8256     CPU (h_zbit) = opval;
8257     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8258   }
8259   {
8260     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8261     CPU (h_vbit) = opval;
8262     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8263   }
8264 {
8265   {
8266     BI opval = 0;
8267     CPU (h_xbit) = opval;
8268     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8269   }
8270   {
8271     BI opval = 0;
8272     SET_H_INSN_PREFIXED_P (opval);
8273     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8274   }
8275 }
8276 }
8277 }
8278
8279 #undef FLD
8280 }
8281   NEXT (vpc);
8282
8283   CASE (sem, INSN_SUBU_W_R) : /* subu.w $Rs,$Rd */
8284 {
8285   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8286   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8287 #define FLD(f) abuf->fields.sfmt_addc_m.f
8288   int UNUSED written = 0;
8289   IADDR UNUSED pc = abuf->addr;
8290   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8291
8292 {
8293   SI tmp_tmpopd;
8294   SI tmp_tmpops;
8295   BI tmp_carry;
8296   SI tmp_newval;
8297   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
8298   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8299   tmp_carry = CPU (h_cbit);
8300   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8301   {
8302     SI opval = tmp_newval;
8303     SET_H_GR (FLD (f_operand2), opval);
8304     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8305   }
8306 {
8307   {
8308     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8309     CPU (h_cbit) = opval;
8310     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8311   }
8312   {
8313     BI opval = LTSI (tmp_newval, 0);
8314     CPU (h_nbit) = opval;
8315     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8316   }
8317   {
8318     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8319     CPU (h_zbit) = opval;
8320     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8321   }
8322   {
8323     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8324     CPU (h_vbit) = opval;
8325     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8326   }
8327 {
8328   {
8329     BI opval = 0;
8330     CPU (h_xbit) = opval;
8331     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8332   }
8333   {
8334     BI opval = 0;
8335     SET_H_INSN_PREFIXED_P (opval);
8336     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8337   }
8338 }
8339 }
8340 }
8341
8342 #undef FLD
8343 }
8344   NEXT (vpc);
8345
8346   CASE (sem, INSN_SUBU_M_B_M) : /* subu-m.b [${Rs}${inc}],$Rd */
8347 {
8348   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8349   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8350 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
8351   int UNUSED written = 0;
8352   IADDR UNUSED pc = abuf->addr;
8353   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8354
8355 {
8356   SI tmp_tmpopd;
8357   SI tmp_tmpops;
8358   BI tmp_carry;
8359   SI tmp_newval;
8360   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
8361   QI tmp_tmp_mem;
8362   BI tmp_postinc;
8363   tmp_postinc = FLD (f_memmode);
8364 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
8365 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
8366 ; if (NEBI (tmp_postinc, 0)) {
8367 {
8368 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8369   tmp_addr = ADDSI (tmp_addr, 1);
8370 }
8371   {
8372     SI opval = tmp_addr;
8373     SET_H_GR (FLD (f_operand1), opval);
8374     written |= (1 << 11);
8375     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8376   }
8377 }
8378 }
8379 ; tmp_tmp_mem; }));
8380   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8381   tmp_carry = CPU (h_cbit);
8382   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8383   {
8384     SI opval = tmp_newval;
8385     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
8386     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8387   }
8388 {
8389   {
8390     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8391     CPU (h_cbit) = opval;
8392     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8393   }
8394   {
8395     BI opval = LTSI (tmp_newval, 0);
8396     CPU (h_nbit) = opval;
8397     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8398   }
8399   {
8400     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8401     CPU (h_zbit) = opval;
8402     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8403   }
8404   {
8405     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8406     CPU (h_vbit) = opval;
8407     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8408   }
8409 {
8410   {
8411     BI opval = 0;
8412     CPU (h_xbit) = opval;
8413     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8414   }
8415   {
8416     BI opval = 0;
8417     SET_H_INSN_PREFIXED_P (opval);
8418     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8419   }
8420 }
8421 }
8422 }
8423
8424   abuf->written = written;
8425 #undef FLD
8426 }
8427   NEXT (vpc);
8428
8429   CASE (sem, INSN_SUBU_M_W_M) : /* subu-m.w [${Rs}${inc}],$Rd */
8430 {
8431   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8432   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8433 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
8434   int UNUSED written = 0;
8435   IADDR UNUSED pc = abuf->addr;
8436   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8437
8438 {
8439   SI tmp_tmpopd;
8440   SI tmp_tmpops;
8441   BI tmp_carry;
8442   SI tmp_newval;
8443   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
8444   HI tmp_tmp_mem;
8445   BI tmp_postinc;
8446   tmp_postinc = FLD (f_memmode);
8447 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
8448 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
8449 ; if (NEBI (tmp_postinc, 0)) {
8450 {
8451 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8452   tmp_addr = ADDSI (tmp_addr, 2);
8453 }
8454   {
8455     SI opval = tmp_addr;
8456     SET_H_GR (FLD (f_operand1), opval);
8457     written |= (1 << 11);
8458     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8459   }
8460 }
8461 }
8462 ; tmp_tmp_mem; }));
8463   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8464   tmp_carry = CPU (h_cbit);
8465   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8466   {
8467     SI opval = tmp_newval;
8468     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
8469     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8470   }
8471 {
8472   {
8473     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8474     CPU (h_cbit) = opval;
8475     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8476   }
8477   {
8478     BI opval = LTSI (tmp_newval, 0);
8479     CPU (h_nbit) = opval;
8480     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8481   }
8482   {
8483     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8484     CPU (h_zbit) = opval;
8485     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8486   }
8487   {
8488     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8489     CPU (h_vbit) = opval;
8490     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8491   }
8492 {
8493   {
8494     BI opval = 0;
8495     CPU (h_xbit) = opval;
8496     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8497   }
8498   {
8499     BI opval = 0;
8500     SET_H_INSN_PREFIXED_P (opval);
8501     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8502   }
8503 }
8504 }
8505 }
8506
8507   abuf->written = written;
8508 #undef FLD
8509 }
8510   NEXT (vpc);
8511
8512   CASE (sem, INSN_SUBUCBR) : /* [${Rs}${inc}],$Rd */
8513 {
8514   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8515   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8516 #define FLD(f) abuf->fields.sfmt_addcbr.f
8517   int UNUSED written = 0;
8518   IADDR UNUSED pc = abuf->addr;
8519   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8520
8521 {
8522   SI tmp_tmpopd;
8523   SI tmp_tmpops;
8524   BI tmp_carry;
8525   SI tmp_newval;
8526   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
8527   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8528   tmp_carry = CPU (h_cbit);
8529   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8530   {
8531     SI opval = tmp_newval;
8532     SET_H_GR (FLD (f_operand2), opval);
8533     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8534   }
8535 {
8536   {
8537     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8538     CPU (h_cbit) = opval;
8539     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8540   }
8541   {
8542     BI opval = LTSI (tmp_newval, 0);
8543     CPU (h_nbit) = opval;
8544     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8545   }
8546   {
8547     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8548     CPU (h_zbit) = opval;
8549     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8550   }
8551   {
8552     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8553     CPU (h_vbit) = opval;
8554     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8555   }
8556 {
8557   {
8558     BI opval = 0;
8559     CPU (h_xbit) = opval;
8560     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8561   }
8562   {
8563     BI opval = 0;
8564     SET_H_INSN_PREFIXED_P (opval);
8565     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8566   }
8567 }
8568 }
8569 }
8570
8571 #undef FLD
8572 }
8573   NEXT (vpc);
8574
8575   CASE (sem, INSN_SUBUCWR) : /* [${Rs}${inc}],$Rd */
8576 {
8577   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8578   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8579 #define FLD(f) abuf->fields.sfmt_addcwr.f
8580   int UNUSED written = 0;
8581   IADDR UNUSED pc = abuf->addr;
8582   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8583
8584 {
8585   SI tmp_tmpopd;
8586   SI tmp_tmpops;
8587   BI tmp_carry;
8588   SI tmp_newval;
8589   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
8590   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8591   tmp_carry = CPU (h_cbit);
8592   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8593   {
8594     SI opval = tmp_newval;
8595     SET_H_GR (FLD (f_operand2), opval);
8596     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8597   }
8598 {
8599   {
8600     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8601     CPU (h_cbit) = opval;
8602     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8603   }
8604   {
8605     BI opval = LTSI (tmp_newval, 0);
8606     CPU (h_nbit) = opval;
8607     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8608   }
8609   {
8610     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8611     CPU (h_zbit) = opval;
8612     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8613   }
8614   {
8615     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8616     CPU (h_vbit) = opval;
8617     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8618   }
8619 {
8620   {
8621     BI opval = 0;
8622     CPU (h_xbit) = opval;
8623     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8624   }
8625   {
8626     BI opval = 0;
8627     SET_H_INSN_PREFIXED_P (opval);
8628     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8629   }
8630 }
8631 }
8632 }
8633
8634 #undef FLD
8635 }
8636   NEXT (vpc);
8637
8638   CASE (sem, INSN_ADDC_R) : /* addc $Rs,$Rd */
8639 {
8640   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8641   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8642 #define FLD(f) abuf->fields.sfmt_addc_m.f
8643   int UNUSED written = 0;
8644   IADDR UNUSED pc = abuf->addr;
8645   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8646
8647 {
8648 CPU (h_xbit) = 1;
8649 {
8650   SI tmp_tmpopd;
8651   SI tmp_tmpops;
8652   BI tmp_carry;
8653   SI tmp_newval;
8654   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8655   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8656   tmp_carry = CPU (h_cbit);
8657   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8658   {
8659     SI opval = tmp_newval;
8660     SET_H_GR (FLD (f_operand2), opval);
8661     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8662   }
8663 {
8664   {
8665     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
8666     CPU (h_cbit) = opval;
8667     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8668   }
8669   {
8670     BI opval = LTSI (tmp_newval, 0);
8671     CPU (h_nbit) = opval;
8672     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8673   }
8674   {
8675     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8676     CPU (h_zbit) = opval;
8677     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8678   }
8679   {
8680     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8681     CPU (h_vbit) = opval;
8682     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8683   }
8684 {
8685   {
8686     BI opval = 0;
8687     CPU (h_xbit) = opval;
8688     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8689   }
8690   {
8691     BI opval = 0;
8692     SET_H_INSN_PREFIXED_P (opval);
8693     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8694   }
8695 }
8696 }
8697 }
8698 }
8699
8700 #undef FLD
8701 }
8702   NEXT (vpc);
8703
8704   CASE (sem, INSN_ADDC_M) : /* addc [${Rs}${inc}],${Rd} */
8705 {
8706   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8707   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8708 #define FLD(f) abuf->fields.sfmt_addc_m.f
8709   int UNUSED written = 0;
8710   IADDR UNUSED pc = abuf->addr;
8711   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8712
8713 {
8714 CPU (h_xbit) = 1;
8715 {
8716   SI tmp_tmpopd;
8717   SI tmp_tmpops;
8718   BI tmp_carry;
8719   SI tmp_newval;
8720   tmp_tmpops = ({   SI tmp_addr;
8721   SI tmp_tmp_mem;
8722   BI tmp_postinc;
8723   tmp_postinc = FLD (f_memmode);
8724 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
8725 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
8726 ; if (NEBI (tmp_postinc, 0)) {
8727 {
8728 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8729   tmp_addr = ADDSI (tmp_addr, 4);
8730 }
8731   {
8732     SI opval = tmp_addr;
8733     SET_H_GR (FLD (f_operand1), opval);
8734     written |= (1 << 10);
8735     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8736   }
8737 }
8738 }
8739 ; tmp_tmp_mem; });
8740   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8741   tmp_carry = CPU (h_cbit);
8742   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8743   {
8744     SI opval = tmp_newval;
8745     SET_H_GR (FLD (f_operand2), opval);
8746     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8747   }
8748 {
8749   {
8750     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
8751     CPU (h_cbit) = opval;
8752     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8753   }
8754   {
8755     BI opval = LTSI (tmp_newval, 0);
8756     CPU (h_nbit) = opval;
8757     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8758   }
8759   {
8760     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8761     CPU (h_zbit) = opval;
8762     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8763   }
8764   {
8765     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8766     CPU (h_vbit) = opval;
8767     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8768   }
8769 {
8770   {
8771     BI opval = 0;
8772     CPU (h_xbit) = opval;
8773     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8774   }
8775   {
8776     BI opval = 0;
8777     SET_H_INSN_PREFIXED_P (opval);
8778     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8779   }
8780 }
8781 }
8782 }
8783 }
8784
8785   abuf->written = written;
8786 #undef FLD
8787 }
8788   NEXT (vpc);
8789
8790   CASE (sem, INSN_ADDC_C) : /* addc ${const32},${Rd} */
8791 {
8792   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8793   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8794 #define FLD(f) abuf->fields.sfmt_addcdr.f
8795   int UNUSED written = 0;
8796   IADDR UNUSED pc = abuf->addr;
8797   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
8798
8799 {
8800 CPU (h_xbit) = 1;
8801 {
8802   SI tmp_tmpopd;
8803   SI tmp_tmpops;
8804   BI tmp_carry;
8805   SI tmp_newval;
8806   tmp_tmpops = FLD (f_indir_pc__dword);
8807   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8808   tmp_carry = CPU (h_cbit);
8809   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8810   {
8811     SI opval = tmp_newval;
8812     SET_H_GR (FLD (f_operand2), opval);
8813     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8814   }
8815 {
8816   {
8817     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
8818     CPU (h_cbit) = opval;
8819     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8820   }
8821   {
8822     BI opval = LTSI (tmp_newval, 0);
8823     CPU (h_nbit) = opval;
8824     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8825   }
8826   {
8827     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8828     CPU (h_zbit) = opval;
8829     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8830   }
8831   {
8832     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8833     CPU (h_vbit) = opval;
8834     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8835   }
8836 {
8837   {
8838     BI opval = 0;
8839     CPU (h_xbit) = opval;
8840     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8841   }
8842   {
8843     BI opval = 0;
8844     SET_H_INSN_PREFIXED_P (opval);
8845     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8846   }
8847 }
8848 }
8849 }
8850 }
8851
8852 #undef FLD
8853 }
8854   NEXT (vpc);
8855
8856   CASE (sem, INSN_LAPC_D) : /* lapc.d ${const32-pcrel},${Rd} */
8857 {
8858   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8859   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8860 #define FLD(f) abuf->fields.sfmt_lapc_d.f
8861   int UNUSED written = 0;
8862   IADDR UNUSED pc = abuf->addr;
8863   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
8864
8865 {
8866   {
8867     SI opval = FLD (i_const32_pcrel);
8868     SET_H_GR (FLD (f_operand2), opval);
8869     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8870   }
8871 {
8872   {
8873     BI opval = 0;
8874     CPU (h_xbit) = opval;
8875     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8876   }
8877   {
8878     BI opval = 0;
8879     SET_H_INSN_PREFIXED_P (opval);
8880     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8881   }
8882 }
8883 }
8884
8885 #undef FLD
8886 }
8887   NEXT (vpc);
8888
8889   CASE (sem, INSN_LAPCQ) : /* lapcq ${qo},${Rd} */
8890 {
8891   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8892   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8893 #define FLD(f) abuf->fields.sfmt_lapcq.f
8894   int UNUSED written = 0;
8895   IADDR UNUSED pc = abuf->addr;
8896   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8897
8898 {
8899   {
8900     SI opval = FLD (i_qo);
8901     SET_H_GR (FLD (f_operand2), opval);
8902     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8903   }
8904 {
8905   {
8906     BI opval = 0;
8907     CPU (h_xbit) = opval;
8908     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8909   }
8910   {
8911     BI opval = 0;
8912     SET_H_INSN_PREFIXED_P (opval);
8913     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8914   }
8915 }
8916 }
8917
8918 #undef FLD
8919 }
8920   NEXT (vpc);
8921
8922   CASE (sem, INSN_ADDI_B_R) : /* addi.b ${Rs-dfield}.m,${Rd-sfield} */
8923 {
8924   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8925   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8926 #define FLD(f) abuf->fields.sfmt_addc_m.f
8927   int UNUSED written = 0;
8928   IADDR UNUSED pc = abuf->addr;
8929   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8930
8931 {
8932   {
8933     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
8934     SET_H_GR (FLD (f_operand1), opval);
8935     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8936   }
8937 {
8938   {
8939     BI opval = 0;
8940     CPU (h_xbit) = opval;
8941     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8942   }
8943   {
8944     BI opval = 0;
8945     SET_H_INSN_PREFIXED_P (opval);
8946     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8947   }
8948 }
8949 }
8950
8951 #undef FLD
8952 }
8953   NEXT (vpc);
8954
8955   CASE (sem, INSN_ADDI_W_R) : /* addi.w ${Rs-dfield}.m,${Rd-sfield} */
8956 {
8957   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8958   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8959 #define FLD(f) abuf->fields.sfmt_addc_m.f
8960   int UNUSED written = 0;
8961   IADDR UNUSED pc = abuf->addr;
8962   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8963
8964 {
8965   {
8966     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
8967     SET_H_GR (FLD (f_operand1), opval);
8968     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8969   }
8970 {
8971   {
8972     BI opval = 0;
8973     CPU (h_xbit) = opval;
8974     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8975   }
8976   {
8977     BI opval = 0;
8978     SET_H_INSN_PREFIXED_P (opval);
8979     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8980   }
8981 }
8982 }
8983
8984 #undef FLD
8985 }
8986   NEXT (vpc);
8987
8988   CASE (sem, INSN_ADDI_D_R) : /* addi.d ${Rs-dfield}.m,${Rd-sfield} */
8989 {
8990   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8991   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8992 #define FLD(f) abuf->fields.sfmt_addc_m.f
8993   int UNUSED written = 0;
8994   IADDR UNUSED pc = abuf->addr;
8995   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8996
8997 {
8998   {
8999     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
9000     SET_H_GR (FLD (f_operand1), opval);
9001     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9002   }
9003 {
9004   {
9005     BI opval = 0;
9006     CPU (h_xbit) = opval;
9007     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9008   }
9009   {
9010     BI opval = 0;
9011     SET_H_INSN_PREFIXED_P (opval);
9012     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9013   }
9014 }
9015 }
9016
9017 #undef FLD
9018 }
9019   NEXT (vpc);
9020
9021   CASE (sem, INSN_NEG_B_R) : /* neg.b $Rs,$Rd */
9022 {
9023   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9024   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9025 #define FLD(f) abuf->fields.sfmt_addc_m.f
9026   int UNUSED written = 0;
9027   IADDR UNUSED pc = abuf->addr;
9028   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9029
9030 {
9031   QI tmp_tmpopd;
9032   QI tmp_tmpops;
9033   BI tmp_carry;
9034   QI tmp_newval;
9035   tmp_tmpops = GET_H_GR (FLD (f_operand1));
9036   tmp_tmpopd = 0;
9037   tmp_carry = CPU (h_cbit);
9038   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9039 {
9040   SI tmp_oldregval;
9041   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
9042   {
9043     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
9044     SET_H_GR (FLD (f_operand2), opval);
9045     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9046   }
9047 }
9048 {
9049   {
9050     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
9051     CPU (h_cbit) = opval;
9052     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9053   }
9054   {
9055     BI opval = LTQI (tmp_newval, 0);
9056     CPU (h_nbit) = opval;
9057     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9058   }
9059   {
9060     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9061     CPU (h_zbit) = opval;
9062     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9063   }
9064   {
9065     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
9066     CPU (h_vbit) = opval;
9067     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9068   }
9069 {
9070   {
9071     BI opval = 0;
9072     CPU (h_xbit) = opval;
9073     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9074   }
9075   {
9076     BI opval = 0;
9077     SET_H_INSN_PREFIXED_P (opval);
9078     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9079   }
9080 }
9081 }
9082 }
9083
9084 #undef FLD
9085 }
9086   NEXT (vpc);
9087
9088   CASE (sem, INSN_NEG_W_R) : /* neg.w $Rs,$Rd */
9089 {
9090   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9091   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9092 #define FLD(f) abuf->fields.sfmt_addc_m.f
9093   int UNUSED written = 0;
9094   IADDR UNUSED pc = abuf->addr;
9095   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9096
9097 {
9098   HI tmp_tmpopd;
9099   HI tmp_tmpops;
9100   BI tmp_carry;
9101   HI tmp_newval;
9102   tmp_tmpops = GET_H_GR (FLD (f_operand1));
9103   tmp_tmpopd = 0;
9104   tmp_carry = CPU (h_cbit);
9105   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9106 {
9107   SI tmp_oldregval;
9108   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
9109   {
9110     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
9111     SET_H_GR (FLD (f_operand2), opval);
9112     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9113   }
9114 }
9115 {
9116   {
9117     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
9118     CPU (h_cbit) = opval;
9119     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9120   }
9121   {
9122     BI opval = LTHI (tmp_newval, 0);
9123     CPU (h_nbit) = opval;
9124     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9125   }
9126   {
9127     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9128     CPU (h_zbit) = opval;
9129     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9130   }
9131   {
9132     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
9133     CPU (h_vbit) = opval;
9134     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9135   }
9136 {
9137   {
9138     BI opval = 0;
9139     CPU (h_xbit) = opval;
9140     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9141   }
9142   {
9143     BI opval = 0;
9144     SET_H_INSN_PREFIXED_P (opval);
9145     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9146   }
9147 }
9148 }
9149 }
9150
9151 #undef FLD
9152 }
9153   NEXT (vpc);
9154
9155   CASE (sem, INSN_NEG_D_R) : /* neg.d $Rs,$Rd */
9156 {
9157   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9158   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9159 #define FLD(f) abuf->fields.sfmt_addc_m.f
9160   int UNUSED written = 0;
9161   IADDR UNUSED pc = abuf->addr;
9162   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9163
9164 {
9165   SI tmp_tmpopd;
9166   SI tmp_tmpops;
9167   BI tmp_carry;
9168   SI tmp_newval;
9169   tmp_tmpops = GET_H_GR (FLD (f_operand1));
9170   tmp_tmpopd = 0;
9171   tmp_carry = CPU (h_cbit);
9172   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9173   {
9174     SI opval = tmp_newval;
9175     SET_H_GR (FLD (f_operand2), opval);
9176     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9177   }
9178 {
9179   {
9180     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
9181     CPU (h_cbit) = opval;
9182     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9183   }
9184   {
9185     BI opval = LTSI (tmp_newval, 0);
9186     CPU (h_nbit) = opval;
9187     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9188   }
9189   {
9190     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9191     CPU (h_zbit) = opval;
9192     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9193   }
9194   {
9195     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
9196     CPU (h_vbit) = opval;
9197     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9198   }
9199 {
9200   {
9201     BI opval = 0;
9202     CPU (h_xbit) = opval;
9203     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9204   }
9205   {
9206     BI opval = 0;
9207     SET_H_INSN_PREFIXED_P (opval);
9208     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9209   }
9210 }
9211 }
9212 }
9213
9214 #undef FLD
9215 }
9216   NEXT (vpc);
9217
9218   CASE (sem, INSN_TEST_M_B_M) : /* test-m.b [${Rs}${inc}] */
9219 {
9220   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9221   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9222 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
9223   int UNUSED written = 0;
9224   IADDR UNUSED pc = abuf->addr;
9225   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9226
9227 {
9228   QI tmp_tmpd;
9229   tmp_tmpd = ({   SI tmp_addr;
9230   QI tmp_tmp_mem;
9231   BI tmp_postinc;
9232   tmp_postinc = FLD (f_memmode);
9233 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9234 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
9235 ; if (NEBI (tmp_postinc, 0)) {
9236 {
9237 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9238   tmp_addr = ADDSI (tmp_addr, 1);
9239 }
9240   {
9241     SI opval = tmp_addr;
9242     SET_H_GR (FLD (f_operand1), opval);
9243     written |= (1 << 8);
9244     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9245   }
9246 }
9247 }
9248 ; tmp_tmp_mem; });
9249 {
9250   QI tmp_tmpopd;
9251   QI tmp_tmpops;
9252   BI tmp_carry;
9253   QI tmp_newval;
9254   tmp_tmpops = 0;
9255   tmp_tmpopd = tmp_tmpd;
9256   tmp_carry = CPU (h_cbit);
9257   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9258 ((void) 0); /*nop*/
9259 {
9260   {
9261     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
9262     CPU (h_cbit) = opval;
9263     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9264   }
9265   {
9266     BI opval = LTQI (tmp_newval, 0);
9267     CPU (h_nbit) = opval;
9268     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9269   }
9270   {
9271     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9272     CPU (h_zbit) = opval;
9273     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9274   }
9275   {
9276     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
9277     CPU (h_vbit) = opval;
9278     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9279   }
9280 {
9281   {
9282     BI opval = 0;
9283     CPU (h_xbit) = opval;
9284     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9285   }
9286   {
9287     BI opval = 0;
9288     SET_H_INSN_PREFIXED_P (opval);
9289     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9290   }
9291 }
9292 }
9293 }
9294 }
9295
9296   abuf->written = written;
9297 #undef FLD
9298 }
9299   NEXT (vpc);
9300
9301   CASE (sem, INSN_TEST_M_W_M) : /* test-m.w [${Rs}${inc}] */
9302 {
9303   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9304   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9305 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
9306   int UNUSED written = 0;
9307   IADDR UNUSED pc = abuf->addr;
9308   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9309
9310 {
9311   HI tmp_tmpd;
9312   tmp_tmpd = ({   SI tmp_addr;
9313   HI tmp_tmp_mem;
9314   BI tmp_postinc;
9315   tmp_postinc = FLD (f_memmode);
9316 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9317 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
9318 ; if (NEBI (tmp_postinc, 0)) {
9319 {
9320 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9321   tmp_addr = ADDSI (tmp_addr, 2);
9322 }
9323   {
9324     SI opval = tmp_addr;
9325     SET_H_GR (FLD (f_operand1), opval);
9326     written |= (1 << 8);
9327     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9328   }
9329 }
9330 }
9331 ; tmp_tmp_mem; });
9332 {
9333   HI tmp_tmpopd;
9334   HI tmp_tmpops;
9335   BI tmp_carry;
9336   HI tmp_newval;
9337   tmp_tmpops = 0;
9338   tmp_tmpopd = tmp_tmpd;
9339   tmp_carry = CPU (h_cbit);
9340   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9341 ((void) 0); /*nop*/
9342 {
9343   {
9344     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
9345     CPU (h_cbit) = opval;
9346     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9347   }
9348   {
9349     BI opval = LTHI (tmp_newval, 0);
9350     CPU (h_nbit) = opval;
9351     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9352   }
9353   {
9354     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9355     CPU (h_zbit) = opval;
9356     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9357   }
9358   {
9359     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
9360     CPU (h_vbit) = opval;
9361     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9362   }
9363 {
9364   {
9365     BI opval = 0;
9366     CPU (h_xbit) = opval;
9367     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9368   }
9369   {
9370     BI opval = 0;
9371     SET_H_INSN_PREFIXED_P (opval);
9372     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9373   }
9374 }
9375 }
9376 }
9377 }
9378
9379   abuf->written = written;
9380 #undef FLD
9381 }
9382   NEXT (vpc);
9383
9384   CASE (sem, INSN_TEST_M_D_M) : /* test-m.d [${Rs}${inc}] */
9385 {
9386   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9387   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9388 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
9389   int UNUSED written = 0;
9390   IADDR UNUSED pc = abuf->addr;
9391   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9392
9393 {
9394   SI tmp_tmpd;
9395   tmp_tmpd = ({   SI tmp_addr;
9396   SI tmp_tmp_mem;
9397   BI tmp_postinc;
9398   tmp_postinc = FLD (f_memmode);
9399 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9400 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
9401 ; if (NEBI (tmp_postinc, 0)) {
9402 {
9403 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9404   tmp_addr = ADDSI (tmp_addr, 4);
9405 }
9406   {
9407     SI opval = tmp_addr;
9408     SET_H_GR (FLD (f_operand1), opval);
9409     written |= (1 << 8);
9410     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9411   }
9412 }
9413 }
9414 ; tmp_tmp_mem; });
9415 {
9416   SI tmp_tmpopd;
9417   SI tmp_tmpops;
9418   BI tmp_carry;
9419   SI tmp_newval;
9420   tmp_tmpops = 0;
9421   tmp_tmpopd = tmp_tmpd;
9422   tmp_carry = CPU (h_cbit);
9423   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9424 ((void) 0); /*nop*/
9425 {
9426   {
9427     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
9428     CPU (h_cbit) = opval;
9429     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9430   }
9431   {
9432     BI opval = LTSI (tmp_newval, 0);
9433     CPU (h_nbit) = opval;
9434     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9435   }
9436   {
9437     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9438     CPU (h_zbit) = opval;
9439     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9440   }
9441   {
9442     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
9443     CPU (h_vbit) = opval;
9444     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9445   }
9446 {
9447   {
9448     BI opval = 0;
9449     CPU (h_xbit) = opval;
9450     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9451   }
9452   {
9453     BI opval = 0;
9454     SET_H_INSN_PREFIXED_P (opval);
9455     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9456   }
9457 }
9458 }
9459 }
9460 }
9461
9462   abuf->written = written;
9463 #undef FLD
9464 }
9465   NEXT (vpc);
9466
9467   CASE (sem, INSN_MOVE_R_M_B_M) : /* move-r-m.b ${Rs-dfield},[${Rd-sfield}${inc}] */
9468 {
9469   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9470   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9471 #define FLD(f) abuf->fields.sfmt_addc_m.f
9472   int UNUSED written = 0;
9473   IADDR UNUSED pc = abuf->addr;
9474   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9475
9476 {
9477   QI tmp_tmpd;
9478   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9479 {
9480   SI tmp_addr;
9481   BI tmp_postinc;
9482   tmp_postinc = FLD (f_memmode);
9483   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9484 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
9485 if (EQBI (CPU (h_pbit), 0)) {
9486 {
9487   {
9488     QI opval = tmp_tmpd;
9489     SETMEMQI (current_cpu, pc, tmp_addr, opval);
9490     written |= (1 << 10);
9491     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9492   }
9493   {
9494     BI opval = CPU (h_pbit);
9495     CPU (h_cbit) = opval;
9496     written |= (1 << 9);
9497     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9498   }
9499 }
9500 } else {
9501   {
9502     BI opval = 1;
9503     CPU (h_cbit) = opval;
9504     written |= (1 << 9);
9505     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9506   }
9507 }
9508 } else {
9509   {
9510     QI opval = tmp_tmpd;
9511     SETMEMQI (current_cpu, pc, tmp_addr, opval);
9512     written |= (1 << 10);
9513     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9514   }
9515 }
9516 if (NEBI (tmp_postinc, 0)) {
9517 {
9518 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9519   tmp_addr = ADDSI (tmp_addr, 1);
9520 }
9521   {
9522     SI opval = tmp_addr;
9523     SET_H_GR (FLD (f_operand1), opval);
9524     written |= (1 << 8);
9525     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9526   }
9527 }
9528 }
9529 }
9530 {
9531   {
9532     BI opval = 0;
9533     CPU (h_xbit) = opval;
9534     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9535   }
9536   {
9537     BI opval = 0;
9538     SET_H_INSN_PREFIXED_P (opval);
9539     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9540   }
9541 }
9542 }
9543
9544   abuf->written = written;
9545 #undef FLD
9546 }
9547   NEXT (vpc);
9548
9549   CASE (sem, INSN_MOVE_R_M_W_M) : /* move-r-m.w ${Rs-dfield},[${Rd-sfield}${inc}] */
9550 {
9551   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9552   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9553 #define FLD(f) abuf->fields.sfmt_addc_m.f
9554   int UNUSED written = 0;
9555   IADDR UNUSED pc = abuf->addr;
9556   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9557
9558 {
9559   HI tmp_tmpd;
9560   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9561 {
9562   SI tmp_addr;
9563   BI tmp_postinc;
9564   tmp_postinc = FLD (f_memmode);
9565   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9566 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
9567 if (EQBI (CPU (h_pbit), 0)) {
9568 {
9569   {
9570     HI opval = tmp_tmpd;
9571     SETMEMHI (current_cpu, pc, tmp_addr, opval);
9572     written |= (1 << 10);
9573     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9574   }
9575   {
9576     BI opval = CPU (h_pbit);
9577     CPU (h_cbit) = opval;
9578     written |= (1 << 9);
9579     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9580   }
9581 }
9582 } else {
9583   {
9584     BI opval = 1;
9585     CPU (h_cbit) = opval;
9586     written |= (1 << 9);
9587     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9588   }
9589 }
9590 } else {
9591   {
9592     HI opval = tmp_tmpd;
9593     SETMEMHI (current_cpu, pc, tmp_addr, opval);
9594     written |= (1 << 10);
9595     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9596   }
9597 }
9598 if (NEBI (tmp_postinc, 0)) {
9599 {
9600 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9601   tmp_addr = ADDSI (tmp_addr, 2);
9602 }
9603   {
9604     SI opval = tmp_addr;
9605     SET_H_GR (FLD (f_operand1), opval);
9606     written |= (1 << 8);
9607     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9608   }
9609 }
9610 }
9611 }
9612 {
9613   {
9614     BI opval = 0;
9615     CPU (h_xbit) = opval;
9616     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9617   }
9618   {
9619     BI opval = 0;
9620     SET_H_INSN_PREFIXED_P (opval);
9621     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9622   }
9623 }
9624 }
9625
9626   abuf->written = written;
9627 #undef FLD
9628 }
9629   NEXT (vpc);
9630
9631   CASE (sem, INSN_MOVE_R_M_D_M) : /* move-r-m.d ${Rs-dfield},[${Rd-sfield}${inc}] */
9632 {
9633   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9634   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9635 #define FLD(f) abuf->fields.sfmt_addc_m.f
9636   int UNUSED written = 0;
9637   IADDR UNUSED pc = abuf->addr;
9638   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9639
9640 {
9641   SI tmp_tmpd;
9642   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9643 {
9644   SI tmp_addr;
9645   BI tmp_postinc;
9646   tmp_postinc = FLD (f_memmode);
9647   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9648 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
9649 if (EQBI (CPU (h_pbit), 0)) {
9650 {
9651   {
9652     SI opval = tmp_tmpd;
9653     SETMEMSI (current_cpu, pc, tmp_addr, opval);
9654     written |= (1 << 10);
9655     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9656   }
9657   {
9658     BI opval = CPU (h_pbit);
9659     CPU (h_cbit) = opval;
9660     written |= (1 << 9);
9661     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9662   }
9663 }
9664 } else {
9665   {
9666     BI opval = 1;
9667     CPU (h_cbit) = opval;
9668     written |= (1 << 9);
9669     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9670   }
9671 }
9672 } else {
9673   {
9674     SI opval = tmp_tmpd;
9675     SETMEMSI (current_cpu, pc, tmp_addr, opval);
9676     written |= (1 << 10);
9677     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9678   }
9679 }
9680 if (NEBI (tmp_postinc, 0)) {
9681 {
9682 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9683   tmp_addr = ADDSI (tmp_addr, 4);
9684 }
9685   {
9686     SI opval = tmp_addr;
9687     SET_H_GR (FLD (f_operand1), opval);
9688     written |= (1 << 8);
9689     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9690   }
9691 }
9692 }
9693 }
9694 {
9695   {
9696     BI opval = 0;
9697     CPU (h_xbit) = opval;
9698     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9699   }
9700   {
9701     BI opval = 0;
9702     SET_H_INSN_PREFIXED_P (opval);
9703     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9704   }
9705 }
9706 }
9707
9708   abuf->written = written;
9709 #undef FLD
9710 }
9711   NEXT (vpc);
9712
9713   CASE (sem, INSN_MULS_B) : /* muls.b $Rs,$Rd */
9714 {
9715   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9716   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9717 #define FLD(f) abuf->fields.sfmt_muls_b.f
9718   int UNUSED written = 0;
9719   IADDR UNUSED pc = abuf->addr;
9720   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9721
9722 {
9723   DI tmp_src1;
9724   DI tmp_src2;
9725   DI tmp_tmpr;
9726   tmp_src1 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
9727   tmp_src2 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
9728   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9729   {
9730     SI opval = TRUNCDISI (tmp_tmpr);
9731     SET_H_GR (FLD (f_operand2), opval);
9732     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9733   }
9734   {
9735     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9736     SET_H_SR (((UINT) 7), opval);
9737     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9738   }
9739 {
9740   {
9741     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9742     CPU (h_cbit) = opval;
9743     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9744   }
9745   {
9746     BI opval = LTDI (tmp_tmpr, 0);
9747     CPU (h_nbit) = opval;
9748     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9749   }
9750   {
9751     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9752     CPU (h_zbit) = opval;
9753     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9754   }
9755   {
9756     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9757     CPU (h_vbit) = opval;
9758     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9759   }
9760 {
9761   {
9762     BI opval = 0;
9763     CPU (h_xbit) = opval;
9764     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9765   }
9766   {
9767     BI opval = 0;
9768     SET_H_INSN_PREFIXED_P (opval);
9769     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9770   }
9771 }
9772 }
9773 }
9774
9775 #undef FLD
9776 }
9777   NEXT (vpc);
9778
9779   CASE (sem, INSN_MULS_W) : /* muls.w $Rs,$Rd */
9780 {
9781   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9782   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9783 #define FLD(f) abuf->fields.sfmt_muls_b.f
9784   int UNUSED written = 0;
9785   IADDR UNUSED pc = abuf->addr;
9786   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9787
9788 {
9789   DI tmp_src1;
9790   DI tmp_src2;
9791   DI tmp_tmpr;
9792   tmp_src1 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
9793   tmp_src2 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
9794   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9795   {
9796     SI opval = TRUNCDISI (tmp_tmpr);
9797     SET_H_GR (FLD (f_operand2), opval);
9798     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9799   }
9800   {
9801     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9802     SET_H_SR (((UINT) 7), opval);
9803     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9804   }
9805 {
9806   {
9807     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9808     CPU (h_cbit) = opval;
9809     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9810   }
9811   {
9812     BI opval = LTDI (tmp_tmpr, 0);
9813     CPU (h_nbit) = opval;
9814     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9815   }
9816   {
9817     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9818     CPU (h_zbit) = opval;
9819     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9820   }
9821   {
9822     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9823     CPU (h_vbit) = opval;
9824     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9825   }
9826 {
9827   {
9828     BI opval = 0;
9829     CPU (h_xbit) = opval;
9830     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9831   }
9832   {
9833     BI opval = 0;
9834     SET_H_INSN_PREFIXED_P (opval);
9835     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9836   }
9837 }
9838 }
9839 }
9840
9841 #undef FLD
9842 }
9843   NEXT (vpc);
9844
9845   CASE (sem, INSN_MULS_D) : /* muls.d $Rs,$Rd */
9846 {
9847   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9848   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9849 #define FLD(f) abuf->fields.sfmt_muls_b.f
9850   int UNUSED written = 0;
9851   IADDR UNUSED pc = abuf->addr;
9852   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9853
9854 {
9855   DI tmp_src1;
9856   DI tmp_src2;
9857   DI tmp_tmpr;
9858   tmp_src1 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
9859   tmp_src2 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
9860   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9861   {
9862     SI opval = TRUNCDISI (tmp_tmpr);
9863     SET_H_GR (FLD (f_operand2), opval);
9864     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9865   }
9866   {
9867     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9868     SET_H_SR (((UINT) 7), opval);
9869     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9870   }
9871 {
9872   {
9873     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9874     CPU (h_cbit) = opval;
9875     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9876   }
9877   {
9878     BI opval = LTDI (tmp_tmpr, 0);
9879     CPU (h_nbit) = opval;
9880     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9881   }
9882   {
9883     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9884     CPU (h_zbit) = opval;
9885     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9886   }
9887   {
9888     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9889     CPU (h_vbit) = opval;
9890     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9891   }
9892 {
9893   {
9894     BI opval = 0;
9895     CPU (h_xbit) = opval;
9896     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9897   }
9898   {
9899     BI opval = 0;
9900     SET_H_INSN_PREFIXED_P (opval);
9901     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9902   }
9903 }
9904 }
9905 }
9906
9907 #undef FLD
9908 }
9909   NEXT (vpc);
9910
9911   CASE (sem, INSN_MULU_B) : /* mulu.b $Rs,$Rd */
9912 {
9913   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9914   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9915 #define FLD(f) abuf->fields.sfmt_muls_b.f
9916   int UNUSED written = 0;
9917   IADDR UNUSED pc = abuf->addr;
9918   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9919
9920 {
9921   DI tmp_src1;
9922   DI tmp_src2;
9923   DI tmp_tmpr;
9924   tmp_src1 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
9925   tmp_src2 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
9926   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9927   {
9928     SI opval = TRUNCDISI (tmp_tmpr);
9929     SET_H_GR (FLD (f_operand2), opval);
9930     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9931   }
9932   {
9933     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9934     SET_H_SR (((UINT) 7), opval);
9935     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9936   }
9937 {
9938   {
9939     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9940     CPU (h_cbit) = opval;
9941     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9942   }
9943   {
9944     BI opval = LTDI (tmp_tmpr, 0);
9945     CPU (h_nbit) = opval;
9946     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9947   }
9948   {
9949     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9950     CPU (h_zbit) = opval;
9951     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9952   }
9953   {
9954     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9955     CPU (h_vbit) = opval;
9956     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9957   }
9958 {
9959   {
9960     BI opval = 0;
9961     CPU (h_xbit) = opval;
9962     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9963   }
9964   {
9965     BI opval = 0;
9966     SET_H_INSN_PREFIXED_P (opval);
9967     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9968   }
9969 }
9970 }
9971 }
9972
9973 #undef FLD
9974 }
9975   NEXT (vpc);
9976
9977   CASE (sem, INSN_MULU_W) : /* mulu.w $Rs,$Rd */
9978 {
9979   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9980   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9981 #define FLD(f) abuf->fields.sfmt_muls_b.f
9982   int UNUSED written = 0;
9983   IADDR UNUSED pc = abuf->addr;
9984   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9985
9986 {
9987   DI tmp_src1;
9988   DI tmp_src2;
9989   DI tmp_tmpr;
9990   tmp_src1 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
9991   tmp_src2 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
9992   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9993   {
9994     SI opval = TRUNCDISI (tmp_tmpr);
9995     SET_H_GR (FLD (f_operand2), opval);
9996     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9997   }
9998   {
9999     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
10000     SET_H_SR (((UINT) 7), opval);
10001     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
10002   }
10003 {
10004   {
10005     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
10006     CPU (h_cbit) = opval;
10007     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
10008   }
10009   {
10010     BI opval = LTDI (tmp_tmpr, 0);
10011     CPU (h_nbit) = opval;
10012     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10013   }
10014   {
10015     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
10016     CPU (h_zbit) = opval;
10017     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10018   }
10019   {
10020     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
10021     CPU (h_vbit) = opval;
10022     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
10023   }
10024 {
10025   {
10026     BI opval = 0;
10027     CPU (h_xbit) = opval;
10028     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10029   }
10030   {
10031     BI opval = 0;
10032     SET_H_INSN_PREFIXED_P (opval);
10033     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10034   }
10035 }
10036 }
10037 }
10038
10039 #undef FLD
10040 }
10041   NEXT (vpc);
10042
10043   CASE (sem, INSN_MULU_D) : /* mulu.d $Rs,$Rd */
10044 {
10045   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10046   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10047 #define FLD(f) abuf->fields.sfmt_muls_b.f
10048   int UNUSED written = 0;
10049   IADDR UNUSED pc = abuf->addr;
10050   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10051
10052 {
10053   DI tmp_src1;
10054   DI tmp_src2;
10055   DI tmp_tmpr;
10056   tmp_src1 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
10057   tmp_src2 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
10058   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
10059   {
10060     SI opval = TRUNCDISI (tmp_tmpr);
10061     SET_H_GR (FLD (f_operand2), opval);
10062     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10063   }
10064   {
10065     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
10066     SET_H_SR (((UINT) 7), opval);
10067     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
10068   }
10069 {
10070   {
10071     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
10072     CPU (h_cbit) = opval;
10073     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
10074   }
10075   {
10076     BI opval = LTDI (tmp_tmpr, 0);
10077     CPU (h_nbit) = opval;
10078     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10079   }
10080   {
10081     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
10082     CPU (h_zbit) = opval;
10083     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10084   }
10085   {
10086     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
10087     CPU (h_vbit) = opval;
10088     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
10089   }
10090 {
10091   {
10092     BI opval = 0;
10093     CPU (h_xbit) = opval;
10094     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10095   }
10096   {
10097     BI opval = 0;
10098     SET_H_INSN_PREFIXED_P (opval);
10099     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10100   }
10101 }
10102 }
10103 }
10104
10105 #undef FLD
10106 }
10107   NEXT (vpc);
10108
10109   CASE (sem, INSN_MCP) : /* mcp $Ps,$Rd */
10110 {
10111   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10112   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10113 #define FLD(f) abuf->fields.sfmt_mcp.f
10114   int UNUSED written = 0;
10115   IADDR UNUSED pc = abuf->addr;
10116   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10117
10118 {
10119 CPU (h_xbit) = 1;
10120 CPU (h_zbit) = 1;
10121 {
10122   SI tmp_tmpopd;
10123   SI tmp_tmpops;
10124   BI tmp_carry;
10125   SI tmp_newval;
10126   tmp_tmpops = GET_H_SR (FLD (f_operand2));
10127   tmp_tmpopd = GET_H_GR (FLD (f_operand1));
10128   tmp_carry = CPU (h_rbit);
10129   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
10130   {
10131     SI opval = tmp_newval;
10132     SET_H_GR (FLD (f_operand1), opval);
10133     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10134   }
10135 {
10136   {
10137     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
10138     CPU (h_rbit) = opval;
10139     TRACE_RESULT (current_cpu, abuf, "rbit", 'x', opval);
10140   }
10141   {
10142     BI opval = LTSI (tmp_newval, 0);
10143     CPU (h_nbit) = opval;
10144     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10145   }
10146   {
10147     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
10148     CPU (h_zbit) = opval;
10149     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10150   }
10151   {
10152     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
10153     CPU (h_vbit) = opval;
10154     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
10155   }
10156 {
10157   {
10158     BI opval = 0;
10159     CPU (h_xbit) = opval;
10160     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10161   }
10162   {
10163     BI opval = 0;
10164     SET_H_INSN_PREFIXED_P (opval);
10165     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10166   }
10167 }
10168 }
10169 }
10170 }
10171
10172 #undef FLD
10173 }
10174   NEXT (vpc);
10175
10176   CASE (sem, INSN_DSTEP) : /* dstep $Rs,$Rd */
10177 {
10178   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10179   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10180 #define FLD(f) abuf->fields.sfmt_muls_b.f
10181   int UNUSED written = 0;
10182   IADDR UNUSED pc = abuf->addr;
10183   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10184
10185 {
10186   SI tmp_tmp;
10187   SI tmp_tmps;
10188   SI tmp_tmpd;
10189   tmp_tmps = GET_H_GR (FLD (f_operand1));
10190   tmp_tmp = SLLSI (GET_H_GR (FLD (f_operand2)), 1);
10191   tmp_tmpd = ((GEUSI (tmp_tmp, tmp_tmps)) ? (SUBSI (tmp_tmp, tmp_tmps)) : (tmp_tmp));
10192   {
10193     SI opval = tmp_tmpd;
10194     SET_H_GR (FLD (f_operand2), opval);
10195     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10196   }
10197 {
10198   {
10199     BI opval = LTSI (tmp_tmpd, 0);
10200     CPU (h_nbit) = opval;
10201     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10202   }
10203   {
10204     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10205     CPU (h_zbit) = opval;
10206     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10207   }
10208 SET_H_CBIT_MOVE (0);
10209 SET_H_VBIT_MOVE (0);
10210 {
10211   {
10212     BI opval = 0;
10213     CPU (h_xbit) = opval;
10214     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10215   }
10216   {
10217     BI opval = 0;
10218     SET_H_INSN_PREFIXED_P (opval);
10219     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10220   }
10221 }
10222 }
10223 }
10224
10225 #undef FLD
10226 }
10227   NEXT (vpc);
10228
10229   CASE (sem, INSN_ABS) : /* abs $Rs,$Rd */
10230 {
10231   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10232   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10233 #define FLD(f) abuf->fields.sfmt_muls_b.f
10234   int UNUSED written = 0;
10235   IADDR UNUSED pc = abuf->addr;
10236   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10237
10238 {
10239   SI tmp_tmpd;
10240   tmp_tmpd = ABSSI (GET_H_GR (FLD (f_operand1)));
10241   {
10242     SI opval = tmp_tmpd;
10243     SET_H_GR (FLD (f_operand2), opval);
10244     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10245   }
10246 {
10247   {
10248     BI opval = LTSI (tmp_tmpd, 0);
10249     CPU (h_nbit) = opval;
10250     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10251   }
10252   {
10253     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10254     CPU (h_zbit) = opval;
10255     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10256   }
10257 SET_H_CBIT_MOVE (0);
10258 SET_H_VBIT_MOVE (0);
10259 {
10260   {
10261     BI opval = 0;
10262     CPU (h_xbit) = opval;
10263     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10264   }
10265   {
10266     BI opval = 0;
10267     SET_H_INSN_PREFIXED_P (opval);
10268     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10269   }
10270 }
10271 }
10272 }
10273
10274 #undef FLD
10275 }
10276   NEXT (vpc);
10277
10278   CASE (sem, INSN_AND_B_R) : /* and.b $Rs,$Rd */
10279 {
10280   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10281   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10282 #define FLD(f) abuf->fields.sfmt_addc_m.f
10283   int UNUSED written = 0;
10284   IADDR UNUSED pc = abuf->addr;
10285   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10286
10287 {
10288   QI tmp_tmpd;
10289   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10290 {
10291   SI tmp_oldregval;
10292   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10293   {
10294     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10295     SET_H_GR (FLD (f_operand2), opval);
10296     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10297   }
10298 }
10299 {
10300   {
10301     BI opval = LTQI (tmp_tmpd, 0);
10302     CPU (h_nbit) = opval;
10303     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10304   }
10305   {
10306     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10307     CPU (h_zbit) = opval;
10308     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10309   }
10310 SET_H_CBIT_MOVE (0);
10311 SET_H_VBIT_MOVE (0);
10312 {
10313   {
10314     BI opval = 0;
10315     CPU (h_xbit) = opval;
10316     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10317   }
10318   {
10319     BI opval = 0;
10320     SET_H_INSN_PREFIXED_P (opval);
10321     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10322   }
10323 }
10324 }
10325 }
10326
10327 #undef FLD
10328 }
10329   NEXT (vpc);
10330
10331   CASE (sem, INSN_AND_W_R) : /* and.w $Rs,$Rd */
10332 {
10333   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10334   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10335 #define FLD(f) abuf->fields.sfmt_addc_m.f
10336   int UNUSED written = 0;
10337   IADDR UNUSED pc = abuf->addr;
10338   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10339
10340 {
10341   HI tmp_tmpd;
10342   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10343 {
10344   SI tmp_oldregval;
10345   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10346   {
10347     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10348     SET_H_GR (FLD (f_operand2), opval);
10349     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10350   }
10351 }
10352 {
10353   {
10354     BI opval = LTHI (tmp_tmpd, 0);
10355     CPU (h_nbit) = opval;
10356     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10357   }
10358   {
10359     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10360     CPU (h_zbit) = opval;
10361     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10362   }
10363 SET_H_CBIT_MOVE (0);
10364 SET_H_VBIT_MOVE (0);
10365 {
10366   {
10367     BI opval = 0;
10368     CPU (h_xbit) = opval;
10369     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10370   }
10371   {
10372     BI opval = 0;
10373     SET_H_INSN_PREFIXED_P (opval);
10374     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10375   }
10376 }
10377 }
10378 }
10379
10380 #undef FLD
10381 }
10382   NEXT (vpc);
10383
10384   CASE (sem, INSN_AND_D_R) : /* and.d $Rs,$Rd */
10385 {
10386   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10387   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10388 #define FLD(f) abuf->fields.sfmt_addc_m.f
10389   int UNUSED written = 0;
10390   IADDR UNUSED pc = abuf->addr;
10391   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10392
10393 {
10394   SI tmp_tmpd;
10395   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10396   {
10397     SI opval = tmp_tmpd;
10398     SET_H_GR (FLD (f_operand2), opval);
10399     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10400   }
10401 {
10402   {
10403     BI opval = LTSI (tmp_tmpd, 0);
10404     CPU (h_nbit) = opval;
10405     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10406   }
10407   {
10408     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10409     CPU (h_zbit) = opval;
10410     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10411   }
10412 SET_H_CBIT_MOVE (0);
10413 SET_H_VBIT_MOVE (0);
10414 {
10415   {
10416     BI opval = 0;
10417     CPU (h_xbit) = opval;
10418     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10419   }
10420   {
10421     BI opval = 0;
10422     SET_H_INSN_PREFIXED_P (opval);
10423     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10424   }
10425 }
10426 }
10427 }
10428
10429 #undef FLD
10430 }
10431   NEXT (vpc);
10432
10433   CASE (sem, INSN_AND_M_B_M) : /* and-m.b [${Rs}${inc}],${Rd} */
10434 {
10435   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10436   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10437 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10438   int UNUSED written = 0;
10439   IADDR UNUSED pc = abuf->addr;
10440   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10441
10442 {
10443   QI tmp_tmpd;
10444   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10445   QI tmp_tmp_mem;
10446   BI tmp_postinc;
10447   tmp_postinc = FLD (f_memmode);
10448 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10449 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
10450 ; if (NEBI (tmp_postinc, 0)) {
10451 {
10452 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10453   tmp_addr = ADDSI (tmp_addr, 1);
10454 }
10455   {
10456     SI opval = tmp_addr;
10457     SET_H_GR (FLD (f_operand1), opval);
10458     written |= (1 << 11);
10459     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10460   }
10461 }
10462 }
10463 ; tmp_tmp_mem; }));
10464 {
10465   SI tmp_oldregval;
10466   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10467   {
10468     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10469     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10470     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10471   }
10472 }
10473 {
10474   {
10475     BI opval = LTQI (tmp_tmpd, 0);
10476     CPU (h_nbit) = opval;
10477     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10478   }
10479   {
10480     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10481     CPU (h_zbit) = opval;
10482     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10483   }
10484 SET_H_CBIT_MOVE (0);
10485 SET_H_VBIT_MOVE (0);
10486 {
10487   {
10488     BI opval = 0;
10489     CPU (h_xbit) = opval;
10490     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10491   }
10492   {
10493     BI opval = 0;
10494     SET_H_INSN_PREFIXED_P (opval);
10495     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10496   }
10497 }
10498 }
10499 }
10500
10501   abuf->written = written;
10502 #undef FLD
10503 }
10504   NEXT (vpc);
10505
10506   CASE (sem, INSN_AND_M_W_M) : /* and-m.w [${Rs}${inc}],${Rd} */
10507 {
10508   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10509   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10510 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10511   int UNUSED written = 0;
10512   IADDR UNUSED pc = abuf->addr;
10513   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10514
10515 {
10516   HI tmp_tmpd;
10517   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10518   HI tmp_tmp_mem;
10519   BI tmp_postinc;
10520   tmp_postinc = FLD (f_memmode);
10521 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10522 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
10523 ; if (NEBI (tmp_postinc, 0)) {
10524 {
10525 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10526   tmp_addr = ADDSI (tmp_addr, 2);
10527 }
10528   {
10529     SI opval = tmp_addr;
10530     SET_H_GR (FLD (f_operand1), opval);
10531     written |= (1 << 11);
10532     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10533   }
10534 }
10535 }
10536 ; tmp_tmp_mem; }));
10537 {
10538   SI tmp_oldregval;
10539   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10540   {
10541     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10542     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10543     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10544   }
10545 }
10546 {
10547   {
10548     BI opval = LTHI (tmp_tmpd, 0);
10549     CPU (h_nbit) = opval;
10550     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10551   }
10552   {
10553     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10554     CPU (h_zbit) = opval;
10555     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10556   }
10557 SET_H_CBIT_MOVE (0);
10558 SET_H_VBIT_MOVE (0);
10559 {
10560   {
10561     BI opval = 0;
10562     CPU (h_xbit) = opval;
10563     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10564   }
10565   {
10566     BI opval = 0;
10567     SET_H_INSN_PREFIXED_P (opval);
10568     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10569   }
10570 }
10571 }
10572 }
10573
10574   abuf->written = written;
10575 #undef FLD
10576 }
10577   NEXT (vpc);
10578
10579   CASE (sem, INSN_AND_M_D_M) : /* and-m.d [${Rs}${inc}],${Rd} */
10580 {
10581   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10582   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10583 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10584   int UNUSED written = 0;
10585   IADDR UNUSED pc = abuf->addr;
10586   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10587
10588 {
10589   SI tmp_tmpd;
10590   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10591   SI tmp_tmp_mem;
10592   BI tmp_postinc;
10593   tmp_postinc = FLD (f_memmode);
10594 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10595 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
10596 ; if (NEBI (tmp_postinc, 0)) {
10597 {
10598 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10599   tmp_addr = ADDSI (tmp_addr, 4);
10600 }
10601   {
10602     SI opval = tmp_addr;
10603     SET_H_GR (FLD (f_operand1), opval);
10604     written |= (1 << 10);
10605     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10606   }
10607 }
10608 }
10609 ; tmp_tmp_mem; }));
10610   {
10611     SI opval = tmp_tmpd;
10612     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10613     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10614   }
10615 {
10616   {
10617     BI opval = LTSI (tmp_tmpd, 0);
10618     CPU (h_nbit) = opval;
10619     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10620   }
10621   {
10622     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10623     CPU (h_zbit) = opval;
10624     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10625   }
10626 SET_H_CBIT_MOVE (0);
10627 SET_H_VBIT_MOVE (0);
10628 {
10629   {
10630     BI opval = 0;
10631     CPU (h_xbit) = opval;
10632     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10633   }
10634   {
10635     BI opval = 0;
10636     SET_H_INSN_PREFIXED_P (opval);
10637     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10638   }
10639 }
10640 }
10641 }
10642
10643   abuf->written = written;
10644 #undef FLD
10645 }
10646   NEXT (vpc);
10647
10648   CASE (sem, INSN_ANDCBR) : /* and.b ${sconst8}],${Rd} */
10649 {
10650   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10651   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10652 #define FLD(f) abuf->fields.sfmt_addcbr.f
10653   int UNUSED written = 0;
10654   IADDR UNUSED pc = abuf->addr;
10655   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10656
10657 {
10658   QI tmp_tmpd;
10659   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
10660 {
10661   SI tmp_oldregval;
10662   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10663   {
10664     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10665     SET_H_GR (FLD (f_operand2), opval);
10666     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10667   }
10668 }
10669 {
10670   {
10671     BI opval = LTQI (tmp_tmpd, 0);
10672     CPU (h_nbit) = opval;
10673     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10674   }
10675   {
10676     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10677     CPU (h_zbit) = opval;
10678     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10679   }
10680 SET_H_CBIT_MOVE (0);
10681 SET_H_VBIT_MOVE (0);
10682 {
10683   {
10684     BI opval = 0;
10685     CPU (h_xbit) = opval;
10686     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10687   }
10688   {
10689     BI opval = 0;
10690     SET_H_INSN_PREFIXED_P (opval);
10691     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10692   }
10693 }
10694 }
10695 }
10696
10697 #undef FLD
10698 }
10699   NEXT (vpc);
10700
10701   CASE (sem, INSN_ANDCWR) : /* and.w ${sconst16}],${Rd} */
10702 {
10703   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10704   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10705 #define FLD(f) abuf->fields.sfmt_addcwr.f
10706   int UNUSED written = 0;
10707   IADDR UNUSED pc = abuf->addr;
10708   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10709
10710 {
10711   HI tmp_tmpd;
10712   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
10713 {
10714   SI tmp_oldregval;
10715   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10716   {
10717     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10718     SET_H_GR (FLD (f_operand2), opval);
10719     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10720   }
10721 }
10722 {
10723   {
10724     BI opval = LTHI (tmp_tmpd, 0);
10725     CPU (h_nbit) = opval;
10726     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10727   }
10728   {
10729     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10730     CPU (h_zbit) = opval;
10731     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10732   }
10733 SET_H_CBIT_MOVE (0);
10734 SET_H_VBIT_MOVE (0);
10735 {
10736   {
10737     BI opval = 0;
10738     CPU (h_xbit) = opval;
10739     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10740   }
10741   {
10742     BI opval = 0;
10743     SET_H_INSN_PREFIXED_P (opval);
10744     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10745   }
10746 }
10747 }
10748 }
10749
10750 #undef FLD
10751 }
10752   NEXT (vpc);
10753
10754   CASE (sem, INSN_ANDCDR) : /* and.d ${const32}],${Rd} */
10755 {
10756   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10757   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10758 #define FLD(f) abuf->fields.sfmt_addcdr.f
10759   int UNUSED written = 0;
10760   IADDR UNUSED pc = abuf->addr;
10761   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
10762
10763 {
10764   SI tmp_tmpd;
10765   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
10766   {
10767     SI opval = tmp_tmpd;
10768     SET_H_GR (FLD (f_operand2), opval);
10769     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10770   }
10771 {
10772   {
10773     BI opval = LTSI (tmp_tmpd, 0);
10774     CPU (h_nbit) = opval;
10775     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10776   }
10777   {
10778     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10779     CPU (h_zbit) = opval;
10780     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10781   }
10782 SET_H_CBIT_MOVE (0);
10783 SET_H_VBIT_MOVE (0);
10784 {
10785   {
10786     BI opval = 0;
10787     CPU (h_xbit) = opval;
10788     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10789   }
10790   {
10791     BI opval = 0;
10792     SET_H_INSN_PREFIXED_P (opval);
10793     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10794   }
10795 }
10796 }
10797 }
10798
10799 #undef FLD
10800 }
10801   NEXT (vpc);
10802
10803   CASE (sem, INSN_ANDQ) : /* andq $i,$Rd */
10804 {
10805   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10806   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10807 #define FLD(f) abuf->fields.sfmt_andq.f
10808   int UNUSED written = 0;
10809   IADDR UNUSED pc = abuf->addr;
10810   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10811
10812 {
10813   SI tmp_tmpd;
10814   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
10815   {
10816     SI opval = tmp_tmpd;
10817     SET_H_GR (FLD (f_operand2), opval);
10818     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10819   }
10820 {
10821   {
10822     BI opval = LTSI (tmp_tmpd, 0);
10823     CPU (h_nbit) = opval;
10824     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10825   }
10826   {
10827     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10828     CPU (h_zbit) = opval;
10829     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10830   }
10831 SET_H_CBIT_MOVE (0);
10832 SET_H_VBIT_MOVE (0);
10833 {
10834   {
10835     BI opval = 0;
10836     CPU (h_xbit) = opval;
10837     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10838   }
10839   {
10840     BI opval = 0;
10841     SET_H_INSN_PREFIXED_P (opval);
10842     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10843   }
10844 }
10845 }
10846 }
10847
10848 #undef FLD
10849 }
10850   NEXT (vpc);
10851
10852   CASE (sem, INSN_ORR_B_R) : /* orr.b $Rs,$Rd */
10853 {
10854   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10855   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10856 #define FLD(f) abuf->fields.sfmt_addc_m.f
10857   int UNUSED written = 0;
10858   IADDR UNUSED pc = abuf->addr;
10859   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10860
10861 {
10862   QI tmp_tmpd;
10863   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10864 {
10865   SI tmp_oldregval;
10866   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10867   {
10868     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10869     SET_H_GR (FLD (f_operand2), opval);
10870     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10871   }
10872 }
10873 {
10874   {
10875     BI opval = LTQI (tmp_tmpd, 0);
10876     CPU (h_nbit) = opval;
10877     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10878   }
10879   {
10880     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10881     CPU (h_zbit) = opval;
10882     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10883   }
10884 SET_H_CBIT_MOVE (0);
10885 SET_H_VBIT_MOVE (0);
10886 {
10887   {
10888     BI opval = 0;
10889     CPU (h_xbit) = opval;
10890     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10891   }
10892   {
10893     BI opval = 0;
10894     SET_H_INSN_PREFIXED_P (opval);
10895     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10896   }
10897 }
10898 }
10899 }
10900
10901 #undef FLD
10902 }
10903   NEXT (vpc);
10904
10905   CASE (sem, INSN_ORR_W_R) : /* orr.w $Rs,$Rd */
10906 {
10907   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10908   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10909 #define FLD(f) abuf->fields.sfmt_addc_m.f
10910   int UNUSED written = 0;
10911   IADDR UNUSED pc = abuf->addr;
10912   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10913
10914 {
10915   HI tmp_tmpd;
10916   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10917 {
10918   SI tmp_oldregval;
10919   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10920   {
10921     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10922     SET_H_GR (FLD (f_operand2), opval);
10923     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10924   }
10925 }
10926 {
10927   {
10928     BI opval = LTHI (tmp_tmpd, 0);
10929     CPU (h_nbit) = opval;
10930     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10931   }
10932   {
10933     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10934     CPU (h_zbit) = opval;
10935     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10936   }
10937 SET_H_CBIT_MOVE (0);
10938 SET_H_VBIT_MOVE (0);
10939 {
10940   {
10941     BI opval = 0;
10942     CPU (h_xbit) = opval;
10943     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10944   }
10945   {
10946     BI opval = 0;
10947     SET_H_INSN_PREFIXED_P (opval);
10948     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10949   }
10950 }
10951 }
10952 }
10953
10954 #undef FLD
10955 }
10956   NEXT (vpc);
10957
10958   CASE (sem, INSN_ORR_D_R) : /* orr.d $Rs,$Rd */
10959 {
10960   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10961   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10962 #define FLD(f) abuf->fields.sfmt_addc_m.f
10963   int UNUSED written = 0;
10964   IADDR UNUSED pc = abuf->addr;
10965   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10966
10967 {
10968   SI tmp_tmpd;
10969   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10970   {
10971     SI opval = tmp_tmpd;
10972     SET_H_GR (FLD (f_operand2), opval);
10973     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10974   }
10975 {
10976   {
10977     BI opval = LTSI (tmp_tmpd, 0);
10978     CPU (h_nbit) = opval;
10979     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10980   }
10981   {
10982     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10983     CPU (h_zbit) = opval;
10984     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10985   }
10986 SET_H_CBIT_MOVE (0);
10987 SET_H_VBIT_MOVE (0);
10988 {
10989   {
10990     BI opval = 0;
10991     CPU (h_xbit) = opval;
10992     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10993   }
10994   {
10995     BI opval = 0;
10996     SET_H_INSN_PREFIXED_P (opval);
10997     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10998   }
10999 }
11000 }
11001 }
11002
11003 #undef FLD
11004 }
11005   NEXT (vpc);
11006
11007   CASE (sem, INSN_OR_M_B_M) : /* or-m.b [${Rs}${inc}],${Rd} */
11008 {
11009   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11010   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11011 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
11012   int UNUSED written = 0;
11013   IADDR UNUSED pc = abuf->addr;
11014   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11015
11016 {
11017   QI tmp_tmpd;
11018   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
11019   QI tmp_tmp_mem;
11020   BI tmp_postinc;
11021   tmp_postinc = FLD (f_memmode);
11022 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
11023 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
11024 ; if (NEBI (tmp_postinc, 0)) {
11025 {
11026 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
11027   tmp_addr = ADDSI (tmp_addr, 1);
11028 }
11029   {
11030     SI opval = tmp_addr;
11031     SET_H_GR (FLD (f_operand1), opval);
11032     written |= (1 << 11);
11033     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11034   }
11035 }
11036 }
11037 ; tmp_tmp_mem; }));
11038 {
11039   SI tmp_oldregval;
11040   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
11041   {
11042     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11043     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
11044     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11045   }
11046 }
11047 {
11048   {
11049     BI opval = LTQI (tmp_tmpd, 0);
11050     CPU (h_nbit) = opval;
11051     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11052   }
11053   {
11054     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11055     CPU (h_zbit) = opval;
11056     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11057   }
11058 SET_H_CBIT_MOVE (0);
11059 SET_H_VBIT_MOVE (0);
11060 {
11061   {
11062     BI opval = 0;
11063     CPU (h_xbit) = opval;
11064     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11065   }
11066   {
11067     BI opval = 0;
11068     SET_H_INSN_PREFIXED_P (opval);
11069     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11070   }
11071 }
11072 }
11073 }
11074
11075   abuf->written = written;
11076 #undef FLD
11077 }
11078   NEXT (vpc);
11079
11080   CASE (sem, INSN_OR_M_W_M) : /* or-m.w [${Rs}${inc}],${Rd} */
11081 {
11082   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11083   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11084 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
11085   int UNUSED written = 0;
11086   IADDR UNUSED pc = abuf->addr;
11087   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11088
11089 {
11090   HI tmp_tmpd;
11091   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
11092   HI tmp_tmp_mem;
11093   BI tmp_postinc;
11094   tmp_postinc = FLD (f_memmode);
11095 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
11096 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
11097 ; if (NEBI (tmp_postinc, 0)) {
11098 {
11099 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
11100   tmp_addr = ADDSI (tmp_addr, 2);
11101 }
11102   {
11103     SI opval = tmp_addr;
11104     SET_H_GR (FLD (f_operand1), opval);
11105     written |= (1 << 11);
11106     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11107   }
11108 }
11109 }
11110 ; tmp_tmp_mem; }));
11111 {
11112   SI tmp_oldregval;
11113   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
11114   {
11115     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11116     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
11117     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11118   }
11119 }
11120 {
11121   {
11122     BI opval = LTHI (tmp_tmpd, 0);
11123     CPU (h_nbit) = opval;
11124     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11125   }
11126   {
11127     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11128     CPU (h_zbit) = opval;
11129     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11130   }
11131 SET_H_CBIT_MOVE (0);
11132 SET_H_VBIT_MOVE (0);
11133 {
11134   {
11135     BI opval = 0;
11136     CPU (h_xbit) = opval;
11137     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11138   }
11139   {
11140     BI opval = 0;
11141     SET_H_INSN_PREFIXED_P (opval);
11142     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11143   }
11144 }
11145 }
11146 }
11147
11148   abuf->written = written;
11149 #undef FLD
11150 }
11151   NEXT (vpc);
11152
11153   CASE (sem, INSN_OR_M_D_M) : /* or-m.d [${Rs}${inc}],${Rd} */
11154 {
11155   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11156   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11157 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
11158   int UNUSED written = 0;
11159   IADDR UNUSED pc = abuf->addr;
11160   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11161
11162 {
11163   SI tmp_tmpd;
11164   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
11165   SI tmp_tmp_mem;
11166   BI tmp_postinc;
11167   tmp_postinc = FLD (f_memmode);
11168 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
11169 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
11170 ; if (NEBI (tmp_postinc, 0)) {
11171 {
11172 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
11173   tmp_addr = ADDSI (tmp_addr, 4);
11174 }
11175   {
11176     SI opval = tmp_addr;
11177     SET_H_GR (FLD (f_operand1), opval);
11178     written |= (1 << 10);
11179     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11180   }
11181 }
11182 }
11183 ; tmp_tmp_mem; }));
11184   {
11185     SI opval = tmp_tmpd;
11186     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
11187     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11188   }
11189 {
11190   {
11191     BI opval = LTSI (tmp_tmpd, 0);
11192     CPU (h_nbit) = opval;
11193     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11194   }
11195   {
11196     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11197     CPU (h_zbit) = opval;
11198     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11199   }
11200 SET_H_CBIT_MOVE (0);
11201 SET_H_VBIT_MOVE (0);
11202 {
11203   {
11204     BI opval = 0;
11205     CPU (h_xbit) = opval;
11206     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11207   }
11208   {
11209     BI opval = 0;
11210     SET_H_INSN_PREFIXED_P (opval);
11211     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11212   }
11213 }
11214 }
11215 }
11216
11217   abuf->written = written;
11218 #undef FLD
11219 }
11220   NEXT (vpc);
11221
11222   CASE (sem, INSN_ORCBR) : /* or.b ${sconst8}],${Rd} */
11223 {
11224   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11225   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11226 #define FLD(f) abuf->fields.sfmt_addcbr.f
11227   int UNUSED written = 0;
11228   IADDR UNUSED pc = abuf->addr;
11229   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
11230
11231 {
11232   QI tmp_tmpd;
11233   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
11234 {
11235   SI tmp_oldregval;
11236   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11237   {
11238     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11239     SET_H_GR (FLD (f_operand2), opval);
11240     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11241   }
11242 }
11243 {
11244   {
11245     BI opval = LTQI (tmp_tmpd, 0);
11246     CPU (h_nbit) = opval;
11247     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11248   }
11249   {
11250     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11251     CPU (h_zbit) = opval;
11252     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11253   }
11254 SET_H_CBIT_MOVE (0);
11255 SET_H_VBIT_MOVE (0);
11256 {
11257   {
11258     BI opval = 0;
11259     CPU (h_xbit) = opval;
11260     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11261   }
11262   {
11263     BI opval = 0;
11264     SET_H_INSN_PREFIXED_P (opval);
11265     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11266   }
11267 }
11268 }
11269 }
11270
11271 #undef FLD
11272 }
11273   NEXT (vpc);
11274
11275   CASE (sem, INSN_ORCWR) : /* or.w ${sconst16}],${Rd} */
11276 {
11277   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11278   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11279 #define FLD(f) abuf->fields.sfmt_addcwr.f
11280   int UNUSED written = 0;
11281   IADDR UNUSED pc = abuf->addr;
11282   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
11283
11284 {
11285   HI tmp_tmpd;
11286   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
11287 {
11288   SI tmp_oldregval;
11289   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11290   {
11291     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11292     SET_H_GR (FLD (f_operand2), opval);
11293     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11294   }
11295 }
11296 {
11297   {
11298     BI opval = LTHI (tmp_tmpd, 0);
11299     CPU (h_nbit) = opval;
11300     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11301   }
11302   {
11303     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11304     CPU (h_zbit) = opval;
11305     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11306   }
11307 SET_H_CBIT_MOVE (0);
11308 SET_H_VBIT_MOVE (0);
11309 {
11310   {
11311     BI opval = 0;
11312     CPU (h_xbit) = opval;
11313     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11314   }
11315   {
11316     BI opval = 0;
11317     SET_H_INSN_PREFIXED_P (opval);
11318     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11319   }
11320 }
11321 }
11322 }
11323
11324 #undef FLD
11325 }
11326   NEXT (vpc);
11327
11328   CASE (sem, INSN_ORCDR) : /* or.d ${const32}],${Rd} */
11329 {
11330   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11331   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11332 #define FLD(f) abuf->fields.sfmt_addcdr.f
11333   int UNUSED written = 0;
11334   IADDR UNUSED pc = abuf->addr;
11335   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
11336
11337 {
11338   SI tmp_tmpd;
11339   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
11340   {
11341     SI opval = tmp_tmpd;
11342     SET_H_GR (FLD (f_operand2), opval);
11343     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11344   }
11345 {
11346   {
11347     BI opval = LTSI (tmp_tmpd, 0);
11348     CPU (h_nbit) = opval;
11349     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11350   }
11351   {
11352     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11353     CPU (h_zbit) = opval;
11354     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11355   }
11356 SET_H_CBIT_MOVE (0);
11357 SET_H_VBIT_MOVE (0);
11358 {
11359   {
11360     BI opval = 0;
11361     CPU (h_xbit) = opval;
11362     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11363   }
11364   {
11365     BI opval = 0;
11366     SET_H_INSN_PREFIXED_P (opval);
11367     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11368   }
11369 }
11370 }
11371 }
11372
11373 #undef FLD
11374 }
11375   NEXT (vpc);
11376
11377   CASE (sem, INSN_ORQ) : /* orq $i,$Rd */
11378 {
11379   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11380   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11381 #define FLD(f) abuf->fields.sfmt_andq.f
11382   int UNUSED written = 0;
11383   IADDR UNUSED pc = abuf->addr;
11384   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11385
11386 {
11387   SI tmp_tmpd;
11388   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
11389   {
11390     SI opval = tmp_tmpd;
11391     SET_H_GR (FLD (f_operand2), opval);
11392     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11393   }
11394 {
11395   {
11396     BI opval = LTSI (tmp_tmpd, 0);
11397     CPU (h_nbit) = opval;
11398     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11399   }
11400   {
11401     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11402     CPU (h_zbit) = opval;
11403     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11404   }
11405 SET_H_CBIT_MOVE (0);
11406 SET_H_VBIT_MOVE (0);
11407 {
11408   {
11409     BI opval = 0;
11410     CPU (h_xbit) = opval;
11411     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11412   }
11413   {
11414     BI opval = 0;
11415     SET_H_INSN_PREFIXED_P (opval);
11416     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11417   }
11418 }
11419 }
11420 }
11421
11422 #undef FLD
11423 }
11424   NEXT (vpc);
11425
11426   CASE (sem, INSN_XOR) : /* xor $Rs,$Rd */
11427 {
11428   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11429   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11430 #define FLD(f) abuf->fields.sfmt_muls_b.f
11431   int UNUSED written = 0;
11432   IADDR UNUSED pc = abuf->addr;
11433   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11434
11435 {
11436   SI tmp_tmpd;
11437   tmp_tmpd = XORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
11438   {
11439     SI opval = tmp_tmpd;
11440     SET_H_GR (FLD (f_operand2), opval);
11441     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11442   }
11443 {
11444   {
11445     BI opval = LTSI (tmp_tmpd, 0);
11446     CPU (h_nbit) = opval;
11447     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11448   }
11449   {
11450     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11451     CPU (h_zbit) = opval;
11452     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11453   }
11454 SET_H_CBIT_MOVE (0);
11455 SET_H_VBIT_MOVE (0);
11456 {
11457   {
11458     BI opval = 0;
11459     CPU (h_xbit) = opval;
11460     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11461   }
11462   {
11463     BI opval = 0;
11464     SET_H_INSN_PREFIXED_P (opval);
11465     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11466   }
11467 }
11468 }
11469 }
11470
11471 #undef FLD
11472 }
11473   NEXT (vpc);
11474
11475   CASE (sem, INSN_SWAP) : /* swap${swapoption} ${Rs} */
11476 {
11477   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11478   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11479 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
11480   int UNUSED written = 0;
11481   IADDR UNUSED pc = abuf->addr;
11482   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11483
11484 {
11485   SI tmp_tmps;
11486   SI tmp_tmpd;
11487   tmp_tmps = GET_H_GR (FLD (f_operand1));
11488   tmp_tmpd = ({   SI tmp_tmpcode;
11489   SI tmp_tmpval;
11490   SI tmp_tmpres;
11491   tmp_tmpcode = FLD (f_operand2);
11492 ;   tmp_tmpval = tmp_tmps;
11493 ; if (EQSI (tmp_tmpcode, 0)) {
11494   tmp_tmpres = (cgen_rtx_error (current_cpu, "SWAP without swap modifier isn't implemented"), 0);
11495 }
11496  else if (EQSI (tmp_tmpcode, 1)) {
11497   tmp_tmpres = ({   SI tmp_tmpr;
11498   tmp_tmpr = tmp_tmpval;
11499 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11500 }
11501  else if (EQSI (tmp_tmpcode, 2)) {
11502   tmp_tmpres = ({   SI tmp_tmpb;
11503   tmp_tmpb = tmp_tmpval;
11504 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11505 }
11506  else if (EQSI (tmp_tmpcode, 3)) {
11507   tmp_tmpres = ({   SI tmp_tmpr;
11508   tmp_tmpr = ({   SI tmp_tmpb;
11509   tmp_tmpb = tmp_tmpval;
11510 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11511 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11512 }
11513  else if (EQSI (tmp_tmpcode, 4)) {
11514   tmp_tmpres = ({   SI tmp_tmpb;
11515   tmp_tmpb = tmp_tmpval;
11516 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11517 }
11518  else if (EQSI (tmp_tmpcode, 5)) {
11519   tmp_tmpres = ({   SI tmp_tmpr;
11520   tmp_tmpr = ({   SI tmp_tmpb;
11521   tmp_tmpb = tmp_tmpval;
11522 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11523 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11524 }
11525  else if (EQSI (tmp_tmpcode, 6)) {
11526   tmp_tmpres = ({   SI tmp_tmpb;
11527   tmp_tmpb = ({   SI tmp_tmpb;
11528   tmp_tmpb = tmp_tmpval;
11529 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11530 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11531 }
11532  else if (EQSI (tmp_tmpcode, 7)) {
11533   tmp_tmpres = ({   SI tmp_tmpr;
11534   tmp_tmpr = ({   SI tmp_tmpb;
11535   tmp_tmpb = ({   SI tmp_tmpb;
11536   tmp_tmpb = tmp_tmpval;
11537 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11538 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11539 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11540 }
11541  else if (EQSI (tmp_tmpcode, 8)) {
11542   tmp_tmpres = INVSI (tmp_tmpval);
11543 }
11544  else if (EQSI (tmp_tmpcode, 9)) {
11545   tmp_tmpres = ({   SI tmp_tmpr;
11546   tmp_tmpr = INVSI (tmp_tmpval);
11547 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11548 }
11549  else if (EQSI (tmp_tmpcode, 10)) {
11550   tmp_tmpres = ({   SI tmp_tmpb;
11551   tmp_tmpb = INVSI (tmp_tmpval);
11552 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11553 }
11554  else if (EQSI (tmp_tmpcode, 11)) {
11555   tmp_tmpres = ({   SI tmp_tmpr;
11556   tmp_tmpr = ({   SI tmp_tmpb;
11557   tmp_tmpb = INVSI (tmp_tmpval);
11558 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11559 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11560 }
11561  else if (EQSI (tmp_tmpcode, 12)) {
11562   tmp_tmpres = ({   SI tmp_tmpb;
11563   tmp_tmpb = INVSI (tmp_tmpval);
11564 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11565 }
11566  else if (EQSI (tmp_tmpcode, 13)) {
11567   tmp_tmpres = ({   SI tmp_tmpr;
11568   tmp_tmpr = ({   SI tmp_tmpb;
11569   tmp_tmpb = INVSI (tmp_tmpval);
11570 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11571 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11572 }
11573  else if (EQSI (tmp_tmpcode, 14)) {
11574   tmp_tmpres = ({   SI tmp_tmpb;
11575   tmp_tmpb = ({   SI tmp_tmpb;
11576   tmp_tmpb = INVSI (tmp_tmpval);
11577 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11578 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11579 }
11580  else if (EQSI (tmp_tmpcode, 15)) {
11581   tmp_tmpres = ({   SI tmp_tmpr;
11582   tmp_tmpr = ({   SI tmp_tmpb;
11583   tmp_tmpb = ({   SI tmp_tmpb;
11584   tmp_tmpb = INVSI (tmp_tmpval);
11585 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11586 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11587 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11588 }
11589 ; tmp_tmpres; });
11590   {
11591     SI opval = tmp_tmpd;
11592     SET_H_GR (FLD (f_operand1), opval);
11593     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11594   }
11595 {
11596   {
11597     BI opval = LTSI (tmp_tmpd, 0);
11598     CPU (h_nbit) = opval;
11599     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11600   }
11601   {
11602     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11603     CPU (h_zbit) = opval;
11604     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11605   }
11606 SET_H_CBIT_MOVE (0);
11607 SET_H_VBIT_MOVE (0);
11608 {
11609   {
11610     BI opval = 0;
11611     CPU (h_xbit) = opval;
11612     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11613   }
11614   {
11615     BI opval = 0;
11616     SET_H_INSN_PREFIXED_P (opval);
11617     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11618   }
11619 }
11620 }
11621 }
11622
11623 #undef FLD
11624 }
11625   NEXT (vpc);
11626
11627   CASE (sem, INSN_ASRR_B_R) : /* asrr.b $Rs,$Rd */
11628 {
11629   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11630   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11631 #define FLD(f) abuf->fields.sfmt_addc_m.f
11632   int UNUSED written = 0;
11633   IADDR UNUSED pc = abuf->addr;
11634   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11635
11636 {
11637   QI tmp_tmpd;
11638   SI tmp_cnt1;
11639   SI tmp_cnt2;
11640   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11641   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11642   tmp_tmpd = SRASI (EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11643 {
11644   SI tmp_oldregval;
11645   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11646   {
11647     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11648     SET_H_GR (FLD (f_operand2), opval);
11649     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11650   }
11651 }
11652 {
11653   {
11654     BI opval = LTQI (tmp_tmpd, 0);
11655     CPU (h_nbit) = opval;
11656     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11657   }
11658   {
11659     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11660     CPU (h_zbit) = opval;
11661     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11662   }
11663 SET_H_CBIT_MOVE (0);
11664 SET_H_VBIT_MOVE (0);
11665 {
11666   {
11667     BI opval = 0;
11668     CPU (h_xbit) = opval;
11669     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11670   }
11671   {
11672     BI opval = 0;
11673     SET_H_INSN_PREFIXED_P (opval);
11674     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11675   }
11676 }
11677 }
11678 }
11679
11680 #undef FLD
11681 }
11682   NEXT (vpc);
11683
11684   CASE (sem, INSN_ASRR_W_R) : /* asrr.w $Rs,$Rd */
11685 {
11686   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11687   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11688 #define FLD(f) abuf->fields.sfmt_addc_m.f
11689   int UNUSED written = 0;
11690   IADDR UNUSED pc = abuf->addr;
11691   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11692
11693 {
11694   HI tmp_tmpd;
11695   SI tmp_cnt1;
11696   SI tmp_cnt2;
11697   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11698   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11699   tmp_tmpd = SRASI (EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11700 {
11701   SI tmp_oldregval;
11702   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11703   {
11704     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11705     SET_H_GR (FLD (f_operand2), opval);
11706     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11707   }
11708 }
11709 {
11710   {
11711     BI opval = LTHI (tmp_tmpd, 0);
11712     CPU (h_nbit) = opval;
11713     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11714   }
11715   {
11716     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11717     CPU (h_zbit) = opval;
11718     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11719   }
11720 SET_H_CBIT_MOVE (0);
11721 SET_H_VBIT_MOVE (0);
11722 {
11723   {
11724     BI opval = 0;
11725     CPU (h_xbit) = opval;
11726     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11727   }
11728   {
11729     BI opval = 0;
11730     SET_H_INSN_PREFIXED_P (opval);
11731     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11732   }
11733 }
11734 }
11735 }
11736
11737 #undef FLD
11738 }
11739   NEXT (vpc);
11740
11741   CASE (sem, INSN_ASRR_D_R) : /* asrr.d $Rs,$Rd */
11742 {
11743   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11744   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11745 #define FLD(f) abuf->fields.sfmt_addc_m.f
11746   int UNUSED written = 0;
11747   IADDR UNUSED pc = abuf->addr;
11748   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11749
11750 {
11751   SI tmp_tmpd;
11752   SI tmp_cnt1;
11753   SI tmp_cnt2;
11754   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11755   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11756   tmp_tmpd = SRASI (EXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11757   {
11758     SI opval = tmp_tmpd;
11759     SET_H_GR (FLD (f_operand2), opval);
11760     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11761   }
11762 {
11763   {
11764     BI opval = LTSI (tmp_tmpd, 0);
11765     CPU (h_nbit) = opval;
11766     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11767   }
11768   {
11769     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11770     CPU (h_zbit) = opval;
11771     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11772   }
11773 SET_H_CBIT_MOVE (0);
11774 SET_H_VBIT_MOVE (0);
11775 {
11776   {
11777     BI opval = 0;
11778     CPU (h_xbit) = opval;
11779     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11780   }
11781   {
11782     BI opval = 0;
11783     SET_H_INSN_PREFIXED_P (opval);
11784     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11785   }
11786 }
11787 }
11788 }
11789
11790 #undef FLD
11791 }
11792   NEXT (vpc);
11793
11794   CASE (sem, INSN_ASRQ) : /* asrq $c,${Rd} */
11795 {
11796   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11797   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11798 #define FLD(f) abuf->fields.sfmt_asrq.f
11799   int UNUSED written = 0;
11800   IADDR UNUSED pc = abuf->addr;
11801   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11802
11803 {
11804   SI tmp_tmpd;
11805   tmp_tmpd = SRASI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11806   {
11807     SI opval = tmp_tmpd;
11808     SET_H_GR (FLD (f_operand2), opval);
11809     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11810   }
11811 {
11812   {
11813     BI opval = LTSI (tmp_tmpd, 0);
11814     CPU (h_nbit) = opval;
11815     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11816   }
11817   {
11818     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11819     CPU (h_zbit) = opval;
11820     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11821   }
11822 SET_H_CBIT_MOVE (0);
11823 SET_H_VBIT_MOVE (0);
11824 {
11825   {
11826     BI opval = 0;
11827     CPU (h_xbit) = opval;
11828     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11829   }
11830   {
11831     BI opval = 0;
11832     SET_H_INSN_PREFIXED_P (opval);
11833     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11834   }
11835 }
11836 }
11837 }
11838
11839 #undef FLD
11840 }
11841   NEXT (vpc);
11842
11843   CASE (sem, INSN_LSRR_B_R) : /* lsrr.b $Rs,$Rd */
11844 {
11845   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11846   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11847 #define FLD(f) abuf->fields.sfmt_addc_m.f
11848   int UNUSED written = 0;
11849   IADDR UNUSED pc = abuf->addr;
11850   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11851
11852 {
11853   SI tmp_tmpd;
11854   SI tmp_cnt;
11855   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11856   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11857 {
11858   SI tmp_oldregval;
11859   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11860   {
11861     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11862     SET_H_GR (FLD (f_operand2), opval);
11863     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11864   }
11865 }
11866 {
11867   {
11868     BI opval = LTQI (tmp_tmpd, 0);
11869     CPU (h_nbit) = opval;
11870     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11871   }
11872   {
11873     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11874     CPU (h_zbit) = opval;
11875     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11876   }
11877 SET_H_CBIT_MOVE (0);
11878 SET_H_VBIT_MOVE (0);
11879 {
11880   {
11881     BI opval = 0;
11882     CPU (h_xbit) = opval;
11883     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11884   }
11885   {
11886     BI opval = 0;
11887     SET_H_INSN_PREFIXED_P (opval);
11888     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11889   }
11890 }
11891 }
11892 }
11893
11894 #undef FLD
11895 }
11896   NEXT (vpc);
11897
11898   CASE (sem, INSN_LSRR_W_R) : /* lsrr.w $Rs,$Rd */
11899 {
11900   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11901   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11902 #define FLD(f) abuf->fields.sfmt_addc_m.f
11903   int UNUSED written = 0;
11904   IADDR UNUSED pc = abuf->addr;
11905   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11906
11907 {
11908   SI tmp_tmpd;
11909   SI tmp_cnt;
11910   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11911   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11912 {
11913   SI tmp_oldregval;
11914   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11915   {
11916     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11917     SET_H_GR (FLD (f_operand2), opval);
11918     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11919   }
11920 }
11921 {
11922   {
11923     BI opval = LTHI (tmp_tmpd, 0);
11924     CPU (h_nbit) = opval;
11925     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11926   }
11927   {
11928     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11929     CPU (h_zbit) = opval;
11930     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11931   }
11932 SET_H_CBIT_MOVE (0);
11933 SET_H_VBIT_MOVE (0);
11934 {
11935   {
11936     BI opval = 0;
11937     CPU (h_xbit) = opval;
11938     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11939   }
11940   {
11941     BI opval = 0;
11942     SET_H_INSN_PREFIXED_P (opval);
11943     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11944   }
11945 }
11946 }
11947 }
11948
11949 #undef FLD
11950 }
11951   NEXT (vpc);
11952
11953   CASE (sem, INSN_LSRR_D_R) : /* lsrr.d $Rs,$Rd */
11954 {
11955   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11956   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11957 #define FLD(f) abuf->fields.sfmt_addc_m.f
11958   int UNUSED written = 0;
11959   IADDR UNUSED pc = abuf->addr;
11960   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11961
11962 {
11963   SI tmp_tmpd;
11964   SI tmp_cnt;
11965   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11966   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11967   {
11968     SI opval = tmp_tmpd;
11969     SET_H_GR (FLD (f_operand2), opval);
11970     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11971   }
11972 {
11973   {
11974     BI opval = LTSI (tmp_tmpd, 0);
11975     CPU (h_nbit) = opval;
11976     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11977   }
11978   {
11979     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11980     CPU (h_zbit) = opval;
11981     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11982   }
11983 SET_H_CBIT_MOVE (0);
11984 SET_H_VBIT_MOVE (0);
11985 {
11986   {
11987     BI opval = 0;
11988     CPU (h_xbit) = opval;
11989     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11990   }
11991   {
11992     BI opval = 0;
11993     SET_H_INSN_PREFIXED_P (opval);
11994     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11995   }
11996 }
11997 }
11998 }
11999
12000 #undef FLD
12001 }
12002   NEXT (vpc);
12003
12004   CASE (sem, INSN_LSRQ) : /* lsrq $c,${Rd} */
12005 {
12006   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12007   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12008 #define FLD(f) abuf->fields.sfmt_asrq.f
12009   int UNUSED written = 0;
12010   IADDR UNUSED pc = abuf->addr;
12011   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12012
12013 {
12014   SI tmp_tmpd;
12015   tmp_tmpd = SRLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
12016   {
12017     SI opval = tmp_tmpd;
12018     SET_H_GR (FLD (f_operand2), opval);
12019     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12020   }
12021 {
12022   {
12023     BI opval = LTSI (tmp_tmpd, 0);
12024     CPU (h_nbit) = opval;
12025     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12026   }
12027   {
12028     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12029     CPU (h_zbit) = opval;
12030     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12031   }
12032 SET_H_CBIT_MOVE (0);
12033 SET_H_VBIT_MOVE (0);
12034 {
12035   {
12036     BI opval = 0;
12037     CPU (h_xbit) = opval;
12038     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12039   }
12040   {
12041     BI opval = 0;
12042     SET_H_INSN_PREFIXED_P (opval);
12043     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12044   }
12045 }
12046 }
12047 }
12048
12049 #undef FLD
12050 }
12051   NEXT (vpc);
12052
12053   CASE (sem, INSN_LSLR_B_R) : /* lslr.b $Rs,$Rd */
12054 {
12055   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12056   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12057 #define FLD(f) abuf->fields.sfmt_addc_m.f
12058   int UNUSED written = 0;
12059   IADDR UNUSED pc = abuf->addr;
12060   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12061
12062 {
12063   SI tmp_tmpd;
12064   SI tmp_cnt;
12065   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
12066   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
12067 {
12068   SI tmp_oldregval;
12069   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
12070   {
12071     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
12072     SET_H_GR (FLD (f_operand2), opval);
12073     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12074   }
12075 }
12076 {
12077   {
12078     BI opval = LTQI (tmp_tmpd, 0);
12079     CPU (h_nbit) = opval;
12080     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12081   }
12082   {
12083     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12084     CPU (h_zbit) = opval;
12085     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12086   }
12087 SET_H_CBIT_MOVE (0);
12088 SET_H_VBIT_MOVE (0);
12089 {
12090   {
12091     BI opval = 0;
12092     CPU (h_xbit) = opval;
12093     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12094   }
12095   {
12096     BI opval = 0;
12097     SET_H_INSN_PREFIXED_P (opval);
12098     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12099   }
12100 }
12101 }
12102 }
12103
12104 #undef FLD
12105 }
12106   NEXT (vpc);
12107
12108   CASE (sem, INSN_LSLR_W_R) : /* lslr.w $Rs,$Rd */
12109 {
12110   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12111   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12112 #define FLD(f) abuf->fields.sfmt_addc_m.f
12113   int UNUSED written = 0;
12114   IADDR UNUSED pc = abuf->addr;
12115   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12116
12117 {
12118   SI tmp_tmpd;
12119   SI tmp_cnt;
12120   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
12121   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
12122 {
12123   SI tmp_oldregval;
12124   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
12125   {
12126     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
12127     SET_H_GR (FLD (f_operand2), opval);
12128     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12129   }
12130 }
12131 {
12132   {
12133     BI opval = LTHI (tmp_tmpd, 0);
12134     CPU (h_nbit) = opval;
12135     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12136   }
12137   {
12138     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12139     CPU (h_zbit) = opval;
12140     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12141   }
12142 SET_H_CBIT_MOVE (0);
12143 SET_H_VBIT_MOVE (0);
12144 {
12145   {
12146     BI opval = 0;
12147     CPU (h_xbit) = opval;
12148     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12149   }
12150   {
12151     BI opval = 0;
12152     SET_H_INSN_PREFIXED_P (opval);
12153     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12154   }
12155 }
12156 }
12157 }
12158
12159 #undef FLD
12160 }
12161   NEXT (vpc);
12162
12163   CASE (sem, INSN_LSLR_D_R) : /* lslr.d $Rs,$Rd */
12164 {
12165   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12166   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12167 #define FLD(f) abuf->fields.sfmt_addc_m.f
12168   int UNUSED written = 0;
12169   IADDR UNUSED pc = abuf->addr;
12170   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12171
12172 {
12173   SI tmp_tmpd;
12174   SI tmp_cnt;
12175   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
12176   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
12177   {
12178     SI opval = tmp_tmpd;
12179     SET_H_GR (FLD (f_operand2), opval);
12180     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12181   }
12182 {
12183   {
12184     BI opval = LTSI (tmp_tmpd, 0);
12185     CPU (h_nbit) = opval;
12186     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12187   }
12188   {
12189     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12190     CPU (h_zbit) = opval;
12191     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12192   }
12193 SET_H_CBIT_MOVE (0);
12194 SET_H_VBIT_MOVE (0);
12195 {
12196   {
12197     BI opval = 0;
12198     CPU (h_xbit) = opval;
12199     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12200   }
12201   {
12202     BI opval = 0;
12203     SET_H_INSN_PREFIXED_P (opval);
12204     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12205   }
12206 }
12207 }
12208 }
12209
12210 #undef FLD
12211 }
12212   NEXT (vpc);
12213
12214   CASE (sem, INSN_LSLQ) : /* lslq $c,${Rd} */
12215 {
12216   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12217   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12218 #define FLD(f) abuf->fields.sfmt_asrq.f
12219   int UNUSED written = 0;
12220   IADDR UNUSED pc = abuf->addr;
12221   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12222
12223 {
12224   SI tmp_tmpd;
12225   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
12226   {
12227     SI opval = tmp_tmpd;
12228     SET_H_GR (FLD (f_operand2), opval);
12229     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12230   }
12231 {
12232   {
12233     BI opval = LTSI (tmp_tmpd, 0);
12234     CPU (h_nbit) = opval;
12235     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12236   }
12237   {
12238     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12239     CPU (h_zbit) = opval;
12240     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12241   }
12242 SET_H_CBIT_MOVE (0);
12243 SET_H_VBIT_MOVE (0);
12244 {
12245   {
12246     BI opval = 0;
12247     CPU (h_xbit) = opval;
12248     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12249   }
12250   {
12251     BI opval = 0;
12252     SET_H_INSN_PREFIXED_P (opval);
12253     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12254   }
12255 }
12256 }
12257 }
12258
12259 #undef FLD
12260 }
12261   NEXT (vpc);
12262
12263   CASE (sem, INSN_BTST) : /* $Rs,$Rd */
12264 {
12265   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12266   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12267 #define FLD(f) abuf->fields.sfmt_muls_b.f
12268   int UNUSED written = 0;
12269   IADDR UNUSED pc = abuf->addr;
12270   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12271
12272 {
12273   SI tmp_tmpd;
12274   SI tmp_cnt;
12275   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, ANDSI (GET_H_GR (FLD (f_operand1)), 31)));
12276 {
12277   {
12278     BI opval = LTSI (tmp_tmpd, 0);
12279     CPU (h_nbit) = opval;
12280     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12281   }
12282   {
12283     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12284     CPU (h_zbit) = opval;
12285     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12286   }
12287 SET_H_CBIT_MOVE (0);
12288 SET_H_VBIT_MOVE (0);
12289 {
12290   {
12291     BI opval = 0;
12292     CPU (h_xbit) = opval;
12293     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12294   }
12295   {
12296     BI opval = 0;
12297     SET_H_INSN_PREFIXED_P (opval);
12298     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12299   }
12300 }
12301 }
12302 }
12303
12304 #undef FLD
12305 }
12306   NEXT (vpc);
12307
12308   CASE (sem, INSN_BTSTQ) : /* btstq $c,${Rd} */
12309 {
12310   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12311   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12312 #define FLD(f) abuf->fields.sfmt_asrq.f
12313   int UNUSED written = 0;
12314   IADDR UNUSED pc = abuf->addr;
12315   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12316
12317 {
12318   SI tmp_tmpd;
12319   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, FLD (f_u5)));
12320 {
12321   {
12322     BI opval = LTSI (tmp_tmpd, 0);
12323     CPU (h_nbit) = opval;
12324     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12325   }
12326   {
12327     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12328     CPU (h_zbit) = opval;
12329     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12330   }
12331 SET_H_CBIT_MOVE (0);
12332 SET_H_VBIT_MOVE (0);
12333 {
12334   {
12335     BI opval = 0;
12336     CPU (h_xbit) = opval;
12337     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12338   }
12339   {
12340     BI opval = 0;
12341     SET_H_INSN_PREFIXED_P (opval);
12342     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12343   }
12344 }
12345 }
12346 }
12347
12348 #undef FLD
12349 }
12350   NEXT (vpc);
12351
12352   CASE (sem, INSN_SETF) : /* setf ${list-of-flags} */
12353 {
12354   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12355   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12356 #define FLD(f) abuf->fields.sfmt_setf.f
12357   int UNUSED written = 0;
12358   IADDR UNUSED pc = abuf->addr;
12359   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12360
12361 {
12362   SI tmp_tmp;
12363   tmp_tmp = FLD (f_dstsrc);
12364 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
12365   {
12366     BI opval = 1;
12367     CPU (h_cbit) = opval;
12368     written |= (1 << 1);
12369     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
12370   }
12371 }
12372 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
12373   {
12374     BI opval = 1;
12375     CPU (h_vbit) = opval;
12376     written |= (1 << 7);
12377     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
12378   }
12379 }
12380 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
12381   {
12382     BI opval = 1;
12383     CPU (h_zbit) = opval;
12384     written |= (1 << 9);
12385     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12386   }
12387 }
12388 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
12389   {
12390     BI opval = 1;
12391     CPU (h_nbit) = opval;
12392     written |= (1 << 3);
12393     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12394   }
12395 }
12396 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
12397   {
12398     BI opval = 1;
12399     CPU (h_xbit) = opval;
12400     written |= (1 << 8);
12401     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12402   }
12403 }
12404 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
12405   {
12406     BI opval = 1;
12407     SET_H_IBIT (opval);
12408     written |= (1 << 2);
12409     TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
12410   }
12411 }
12412 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
12413   {
12414     BI opval = 1;
12415     SET_H_UBIT (opval);
12416     written |= (1 << 6);
12417     TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
12418   }
12419 }
12420 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
12421   {
12422     BI opval = 1;
12423     CPU (h_pbit) = opval;
12424     written |= (1 << 4);
12425     TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
12426   }
12427 }
12428   {
12429     BI opval = 0;
12430     SET_H_INSN_PREFIXED_P (opval);
12431     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12432   }
12433 if (EQSI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
12434   {
12435     BI opval = 0;
12436     CPU (h_xbit) = opval;
12437     written |= (1 << 8);
12438     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12439   }
12440 }
12441 }
12442
12443   abuf->written = written;
12444 #undef FLD
12445 }
12446   NEXT (vpc);
12447
12448   CASE (sem, INSN_CLEARF) : /* clearf ${list-of-flags} */
12449 {
12450   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12451   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12452 #define FLD(f) abuf->fields.sfmt_setf.f
12453   int UNUSED written = 0;
12454   IADDR UNUSED pc = abuf->addr;
12455   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12456
12457 {
12458   SI tmp_tmp;
12459   tmp_tmp = FLD (f_dstsrc);
12460 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
12461   {
12462     BI opval = 0;
12463     CPU (h_cbit) = opval;
12464     written |= (1 << 1);
12465     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
12466   }
12467 }
12468 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
12469   {
12470     BI opval = 0;
12471     CPU (h_vbit) = opval;
12472     written |= (1 << 7);
12473     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
12474   }
12475 }
12476 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
12477   {
12478     BI opval = 0;
12479     CPU (h_zbit) = opval;
12480     written |= (1 << 9);
12481     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12482   }
12483 }
12484 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
12485   {
12486     BI opval = 0;
12487     CPU (h_nbit) = opval;
12488     written |= (1 << 3);
12489     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12490   }
12491 }
12492 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
12493   {
12494     BI opval = 0;
12495     CPU (h_xbit) = opval;
12496     written |= (1 << 8);
12497     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12498   }
12499 }
12500 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
12501   {
12502     BI opval = 0;
12503     SET_H_IBIT (opval);
12504     written |= (1 << 2);
12505     TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
12506   }
12507 }
12508 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
12509   {
12510     BI opval = 0;
12511     SET_H_UBIT (opval);
12512     written |= (1 << 6);
12513     TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
12514   }
12515 }
12516 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
12517   {
12518     BI opval = 0;
12519     CPU (h_pbit) = opval;
12520     written |= (1 << 4);
12521     TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
12522   }
12523 }
12524 {
12525   {
12526     BI opval = 0;
12527     CPU (h_xbit) = opval;
12528     written |= (1 << 8);
12529     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12530   }
12531   {
12532     BI opval = 0;
12533     SET_H_INSN_PREFIXED_P (opval);
12534     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12535   }
12536 }
12537 }
12538
12539   abuf->written = written;
12540 #undef FLD
12541 }
12542   NEXT (vpc);
12543
12544   CASE (sem, INSN_RFE) : /* rfe */
12545 {
12546   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12547   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12548 #define FLD(f) abuf->fields.sfmt_rfe.f
12549   int UNUSED written = 0;
12550   IADDR UNUSED pc = abuf->addr;
12551   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12552
12553 {
12554   USI tmp_oldccs;
12555   USI tmp_samebits;
12556   USI tmp_shiftbits;
12557   USI tmp_keepmask;
12558   BI tmp_p1;
12559   tmp_oldccs = GET_H_SR (((UINT) 13));
12560   tmp_keepmask = 0xc0000000;
12561   tmp_samebits = ANDSI (tmp_oldccs, tmp_keepmask);
12562   tmp_shiftbits = ANDSI (SRLSI (ANDSI (tmp_oldccs, 1073609728), 10), INVSI (tmp_keepmask));
12563   tmp_p1 = NESI (0, ANDSI (tmp_oldccs, 131072));
12564   {
12565     SI opval = ORSI (ORSI (tmp_samebits, tmp_shiftbits), ((ANDBI (CPU (h_rbit), NOTBI (tmp_p1))) ? (0) : (128)));
12566     SET_H_SR (((UINT) 13), opval);
12567     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12568   }
12569 }
12570
12571 #undef FLD
12572 }
12573   NEXT (vpc);
12574
12575   CASE (sem, INSN_SFE) : /* sfe */
12576 {
12577   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12578   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12579 #define FLD(f) abuf->fields.sfmt_rfe.f
12580   int UNUSED written = 0;
12581   IADDR UNUSED pc = abuf->addr;
12582   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12583
12584 {
12585   SI tmp_oldccs;
12586   SI tmp_savemask;
12587   tmp_savemask = 0xc0000000;
12588   tmp_oldccs = GET_H_SR (((UINT) 13));
12589   {
12590     SI opval = ORSI (ANDSI (tmp_savemask, tmp_oldccs), ANDSI (INVSI (tmp_savemask), SLLSI (tmp_oldccs, 10)));
12591     SET_H_SR (((UINT) 13), opval);
12592     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12593   }
12594 }
12595
12596 #undef FLD
12597 }
12598   NEXT (vpc);
12599
12600   CASE (sem, INSN_RFG) : /* rfg */
12601 {
12602   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12603   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12604 #define FLD(f) abuf->fields.fmt_empty.f
12605   int UNUSED written = 0;
12606   IADDR UNUSED pc = abuf->addr;
12607   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12608
12609 crisv32f_rfg_handler (current_cpu, pc);
12610
12611 #undef FLD
12612 }
12613   NEXT (vpc);
12614
12615   CASE (sem, INSN_RFN) : /* rfn */
12616 {
12617   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12618   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12619 #define FLD(f) abuf->fields.sfmt_rfe.f
12620   int UNUSED written = 0;
12621   IADDR UNUSED pc = abuf->addr;
12622   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12623
12624 {
12625 {
12626   USI tmp_oldccs;
12627   USI tmp_samebits;
12628   USI tmp_shiftbits;
12629   USI tmp_keepmask;
12630   BI tmp_p1;
12631   tmp_oldccs = GET_H_SR (((UINT) 13));
12632   tmp_keepmask = 0xc0000000;
12633   tmp_samebits = ANDSI (tmp_oldccs, tmp_keepmask);
12634   tmp_shiftbits = ANDSI (SRLSI (ANDSI (tmp_oldccs, 1073609728), 10), INVSI (tmp_keepmask));
12635   tmp_p1 = NESI (0, ANDSI (tmp_oldccs, 131072));
12636   {
12637     SI opval = ORSI (ORSI (tmp_samebits, tmp_shiftbits), ((ANDBI (CPU (h_rbit), NOTBI (tmp_p1))) ? (0) : (128)));
12638     SET_H_SR (((UINT) 13), opval);
12639     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12640   }
12641 }
12642   {
12643     BI opval = 1;
12644     SET_H_MBIT (opval);
12645     TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval);
12646   }
12647 }
12648
12649 #undef FLD
12650 }
12651   NEXT (vpc);
12652
12653   CASE (sem, INSN_HALT) : /* halt */
12654 {
12655   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12656   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12657 #define FLD(f) abuf->fields.fmt_empty.f
12658   int UNUSED written = 0;
12659   IADDR UNUSED pc = abuf->addr;
12660   SEM_BRANCH_INIT
12661   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12662
12663   {
12664     USI opval = crisv32f_halt_handler (current_cpu, pc);
12665     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12666     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12667   }
12668
12669   SEM_BRANCH_FINI (vpc);
12670 #undef FLD
12671 }
12672   NEXT (vpc);
12673
12674   CASE (sem, INSN_BCC_B) : /* b${cc} ${o-pcrel} */
12675 {
12676   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12677   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12678 #define FLD(f) abuf->fields.sfmt_bcc_b.f
12679   int UNUSED written = 0;
12680   IADDR UNUSED pc = abuf->addr;
12681   SEM_BRANCH_INIT
12682   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12683
12684 {
12685   BI tmp_truthval;
12686   tmp_truthval = ({   SI tmp_tmpcond;
12687   BI tmp_condres;
12688   tmp_tmpcond = FLD (f_operand2);
12689 ; if (EQSI (tmp_tmpcond, 0)) {
12690   tmp_condres = NOTBI (CPU (h_cbit));
12691 }
12692  else if (EQSI (tmp_tmpcond, 1)) {
12693   tmp_condres = CPU (h_cbit);
12694 }
12695  else if (EQSI (tmp_tmpcond, 2)) {
12696   tmp_condres = NOTBI (CPU (h_zbit));
12697 }
12698  else if (EQSI (tmp_tmpcond, 3)) {
12699   tmp_condres = CPU (h_zbit);
12700 }
12701  else if (EQSI (tmp_tmpcond, 4)) {
12702   tmp_condres = NOTBI (CPU (h_vbit));
12703 }
12704  else if (EQSI (tmp_tmpcond, 5)) {
12705   tmp_condres = CPU (h_vbit);
12706 }
12707  else if (EQSI (tmp_tmpcond, 6)) {
12708   tmp_condres = NOTBI (CPU (h_nbit));
12709 }
12710  else if (EQSI (tmp_tmpcond, 7)) {
12711   tmp_condres = CPU (h_nbit);
12712 }
12713  else if (EQSI (tmp_tmpcond, 8)) {
12714   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
12715 }
12716  else if (EQSI (tmp_tmpcond, 9)) {
12717   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
12718 }
12719  else if (EQSI (tmp_tmpcond, 10)) {
12720   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
12721 }
12722  else if (EQSI (tmp_tmpcond, 11)) {
12723   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
12724 }
12725  else if (EQSI (tmp_tmpcond, 12)) {
12726   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
12727 }
12728  else if (EQSI (tmp_tmpcond, 13)) {
12729   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
12730 }
12731  else if (EQSI (tmp_tmpcond, 14)) {
12732   tmp_condres = 1;
12733 }
12734  else if (EQSI (tmp_tmpcond, 15)) {
12735   tmp_condres = CPU (h_pbit);
12736 }
12737 ; tmp_condres; });
12738 crisv32f_branch_taken (current_cpu, pc, FLD (i_o_pcrel), tmp_truthval);
12739 {
12740   {
12741     BI opval = 0;
12742     CPU (h_xbit) = opval;
12743     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12744   }
12745   {
12746     BI opval = 0;
12747     SET_H_INSN_PREFIXED_P (opval);
12748     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12749   }
12750 }
12751 if (tmp_truthval) {
12752 {
12753   {
12754     USI opval = FLD (i_o_pcrel);
12755     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12756     written |= (1 << 8);
12757     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12758   }
12759 }
12760 }
12761 }
12762
12763   abuf->written = written;
12764   SEM_BRANCH_FINI (vpc);
12765 #undef FLD
12766 }
12767   NEXT (vpc);
12768
12769   CASE (sem, INSN_BA_B) : /* ba ${o-pcrel} */
12770 {
12771   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12772   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12773 #define FLD(f) abuf->fields.sfmt_bcc_b.f
12774   int UNUSED written = 0;
12775   IADDR UNUSED pc = abuf->addr;
12776   SEM_BRANCH_INIT
12777   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12778
12779 {
12780 {
12781   {
12782     BI opval = 0;
12783     CPU (h_xbit) = opval;
12784     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12785   }
12786   {
12787     BI opval = 0;
12788     SET_H_INSN_PREFIXED_P (opval);
12789     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12790   }
12791 }
12792 {
12793   {
12794     USI opval = FLD (i_o_pcrel);
12795     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12796     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12797   }
12798 }
12799 }
12800
12801   SEM_BRANCH_FINI (vpc);
12802 #undef FLD
12803 }
12804   NEXT (vpc);
12805
12806   CASE (sem, INSN_BCC_W) : /* b${cc} ${o-word-pcrel} */
12807 {
12808   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12809   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12810 #define FLD(f) abuf->fields.sfmt_bcc_w.f
12811   int UNUSED written = 0;
12812   IADDR UNUSED pc = abuf->addr;
12813   SEM_BRANCH_INIT
12814   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12815
12816 {
12817   BI tmp_truthval;
12818   tmp_truthval = ({   SI tmp_tmpcond;
12819   BI tmp_condres;
12820   tmp_tmpcond = FLD (f_operand2);
12821 ; if (EQSI (tmp_tmpcond, 0)) {
12822   tmp_condres = NOTBI (CPU (h_cbit));
12823 }
12824  else if (EQSI (tmp_tmpcond, 1)) {
12825   tmp_condres = CPU (h_cbit);
12826 }
12827  else if (EQSI (tmp_tmpcond, 2)) {
12828   tmp_condres = NOTBI (CPU (h_zbit));
12829 }
12830  else if (EQSI (tmp_tmpcond, 3)) {
12831   tmp_condres = CPU (h_zbit);
12832 }
12833  else if (EQSI (tmp_tmpcond, 4)) {
12834   tmp_condres = NOTBI (CPU (h_vbit));
12835 }
12836  else if (EQSI (tmp_tmpcond, 5)) {
12837   tmp_condres = CPU (h_vbit);
12838 }
12839  else if (EQSI (tmp_tmpcond, 6)) {
12840   tmp_condres = NOTBI (CPU (h_nbit));
12841 }
12842  else if (EQSI (tmp_tmpcond, 7)) {
12843   tmp_condres = CPU (h_nbit);
12844 }
12845  else if (EQSI (tmp_tmpcond, 8)) {
12846   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
12847 }
12848  else if (EQSI (tmp_tmpcond, 9)) {
12849   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
12850 }
12851  else if (EQSI (tmp_tmpcond, 10)) {
12852   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
12853 }
12854  else if (EQSI (tmp_tmpcond, 11)) {
12855   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
12856 }
12857  else if (EQSI (tmp_tmpcond, 12)) {
12858   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
12859 }
12860  else if (EQSI (tmp_tmpcond, 13)) {
12861   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
12862 }
12863  else if (EQSI (tmp_tmpcond, 14)) {
12864   tmp_condres = 1;
12865 }
12866  else if (EQSI (tmp_tmpcond, 15)) {
12867   tmp_condres = CPU (h_pbit);
12868 }
12869 ; tmp_condres; });
12870 crisv32f_branch_taken (current_cpu, pc, FLD (i_o_word_pcrel), tmp_truthval);
12871 {
12872   {
12873     BI opval = 0;
12874     CPU (h_xbit) = opval;
12875     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12876   }
12877   {
12878     BI opval = 0;
12879     SET_H_INSN_PREFIXED_P (opval);
12880     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12881   }
12882 }
12883 if (tmp_truthval) {
12884 {
12885   {
12886     USI opval = FLD (i_o_word_pcrel);
12887     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12888     written |= (1 << 8);
12889     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12890   }
12891 }
12892 }
12893 }
12894
12895   abuf->written = written;
12896   SEM_BRANCH_FINI (vpc);
12897 #undef FLD
12898 }
12899   NEXT (vpc);
12900
12901   CASE (sem, INSN_BA_W) : /* ba ${o-word-pcrel} */
12902 {
12903   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12904   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12905 #define FLD(f) abuf->fields.sfmt_bcc_w.f
12906   int UNUSED written = 0;
12907   IADDR UNUSED pc = abuf->addr;
12908   SEM_BRANCH_INIT
12909   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12910
12911 {
12912 {
12913   {
12914     BI opval = 0;
12915     CPU (h_xbit) = opval;
12916     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12917   }
12918   {
12919     BI opval = 0;
12920     SET_H_INSN_PREFIXED_P (opval);
12921     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12922   }
12923 }
12924 {
12925   {
12926     USI opval = FLD (i_o_word_pcrel);
12927     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12928     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12929   }
12930 }
12931 }
12932
12933   SEM_BRANCH_FINI (vpc);
12934 #undef FLD
12935 }
12936   NEXT (vpc);
12937
12938   CASE (sem, INSN_JAS_R) : /* jas ${Rs},${Pd} */
12939 {
12940   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12941   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12942 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
12943   int UNUSED written = 0;
12944   IADDR UNUSED pc = abuf->addr;
12945   SEM_BRANCH_INIT
12946   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12947
12948 {
12949 {
12950   {
12951     BI opval = 0;
12952     CPU (h_xbit) = opval;
12953     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12954   }
12955   {
12956     BI opval = 0;
12957     SET_H_INSN_PREFIXED_P (opval);
12958     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12959   }
12960 }
12961 if (ANDIF (EQSI (FLD (f_operand1), 1), EQSI (FLD (f_operand2), 11))) {
12962 cris_flush_simulator_decode_cache (current_cpu, pc);
12963 }
12964 {
12965 {
12966   {
12967     SI opval = ADDSI (pc, 4);
12968     SET_H_SR (FLD (f_operand2), opval);
12969     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12970   }
12971   {
12972     USI opval = GET_H_GR (FLD (f_operand1));
12973     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12974     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12975   }
12976 }
12977 }
12978 }
12979
12980   SEM_BRANCH_FINI (vpc);
12981 #undef FLD
12982 }
12983   NEXT (vpc);
12984
12985   CASE (sem, INSN_JAS_C) : /* jas ${const32},${Pd} */
12986 {
12987   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12988   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12989 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
12990   int UNUSED written = 0;
12991   IADDR UNUSED pc = abuf->addr;
12992   SEM_BRANCH_INIT
12993   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
12994
12995 {
12996 {
12997   {
12998     BI opval = 0;
12999     CPU (h_xbit) = opval;
13000     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13001   }
13002   {
13003     BI opval = 0;
13004     SET_H_INSN_PREFIXED_P (opval);
13005     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13006   }
13007 }
13008 {
13009 {
13010   {
13011     SI opval = ADDSI (pc, 8);
13012     SET_H_SR (FLD (f_operand2), opval);
13013     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
13014   }
13015   {
13016     USI opval = FLD (f_indir_pc__dword);
13017     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
13018     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
13019   }
13020 }
13021 }
13022 }
13023
13024   SEM_BRANCH_FINI (vpc);
13025 #undef FLD
13026 }
13027   NEXT (vpc);
13028
13029   CASE (sem, INSN_JUMP_P) : /* jump ${Ps} */
13030 {
13031   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13032   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13033 #define FLD(f) abuf->fields.sfmt_mcp.f
13034   int UNUSED written = 0;
13035   IADDR UNUSED pc = abuf->addr;
13036   SEM_BRANCH_INIT
13037   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13038
13039 {
13040 {
13041   {
13042     BI opval = 0;
13043     CPU (h_xbit) = opval;
13044     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13045   }
13046   {
13047     BI opval = 0;
13048     SET_H_INSN_PREFIXED_P (opval);
13049     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13050   }
13051 }
13052 {
13053   {
13054     USI opval = GET_H_SR (FLD (f_operand2));
13055     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
13056     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
13057   }
13058 }
13059 }
13060
13061   SEM_BRANCH_FINI (vpc);
13062 #undef FLD
13063 }
13064   NEXT (vpc);
13065
13066   CASE (sem, INSN_BAS_C) : /* bas ${const32},${Pd} */
13067 {
13068   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13069   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13070 #define FLD(f) abuf->fields.sfmt_bas_c.f
13071   int UNUSED written = 0;
13072   IADDR UNUSED pc = abuf->addr;
13073   SEM_BRANCH_INIT
13074   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13075
13076 {
13077 {
13078   {
13079     BI opval = 0;
13080     CPU (h_xbit) = opval;
13081     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13082   }
13083   {
13084     BI opval = 0;
13085     SET_H_INSN_PREFIXED_P (opval);
13086     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13087   }
13088 }
13089 {
13090 {
13091   {
13092     SI opval = ADDSI (pc, 8);
13093     SET_H_SR (FLD (f_operand2), opval);
13094     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
13095   }
13096   {
13097     USI opval = FLD (i_const32_pcrel);
13098     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
13099     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
13100   }
13101 }
13102 }
13103 }
13104
13105   SEM_BRANCH_FINI (vpc);
13106 #undef FLD
13107 }
13108   NEXT (vpc);
13109
13110   CASE (sem, INSN_JASC_R) : /* jasc ${Rs},${Pd} */
13111 {
13112   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13113   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13114 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
13115   int UNUSED written = 0;
13116   IADDR UNUSED pc = abuf->addr;
13117   SEM_BRANCH_INIT
13118   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13119
13120 {
13121 {
13122   {
13123     BI opval = 0;
13124     CPU (h_xbit) = opval;
13125     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13126   }
13127   {
13128     BI opval = 0;
13129     SET_H_INSN_PREFIXED_P (opval);
13130     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13131   }
13132 }
13133 {
13134 {
13135   {
13136     SI opval = ADDSI (pc, 8);
13137     SET_H_SR (FLD (f_operand2), opval);
13138     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
13139   }
13140   {
13141     USI opval = GET_H_GR (FLD (f_operand1));
13142     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
13143     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
13144   }
13145 }
13146 }
13147 }
13148
13149   SEM_BRANCH_FINI (vpc);
13150 #undef FLD
13151 }
13152   NEXT (vpc);
13153
13154   CASE (sem, INSN_JASC_C) : /* jasc ${const32},${Pd} */
13155 {
13156   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13157   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13158 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
13159   int UNUSED written = 0;
13160   IADDR UNUSED pc = abuf->addr;
13161   SEM_BRANCH_INIT
13162   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13163
13164 {
13165 {
13166   {
13167     BI opval = 0;
13168     CPU (h_xbit) = opval;
13169     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13170   }
13171   {
13172     BI opval = 0;
13173     SET_H_INSN_PREFIXED_P (opval);
13174     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13175   }
13176 }
13177 {
13178 {
13179   {
13180     SI opval = ADDSI (pc, 12);
13181     SET_H_SR (FLD (f_operand2), opval);
13182     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
13183   }
13184   {
13185     USI opval = FLD (f_indir_pc__dword);
13186     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
13187     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
13188   }
13189 }
13190 }
13191 }
13192
13193   SEM_BRANCH_FINI (vpc);
13194 #undef FLD
13195 }
13196   NEXT (vpc);
13197
13198   CASE (sem, INSN_BASC_C) : /* basc ${const32},${Pd} */
13199 {
13200   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13201   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13202 #define FLD(f) abuf->fields.sfmt_bas_c.f
13203   int UNUSED written = 0;
13204   IADDR UNUSED pc = abuf->addr;
13205   SEM_BRANCH_INIT
13206   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13207
13208 {
13209 {
13210   {
13211     BI opval = 0;
13212     CPU (h_xbit) = opval;
13213     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13214   }
13215   {
13216     BI opval = 0;
13217     SET_H_INSN_PREFIXED_P (opval);
13218     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13219   }
13220 }
13221 {
13222 {
13223   {
13224     SI opval = ADDSI (pc, 12);
13225     SET_H_SR (FLD (f_operand2), opval);
13226     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
13227   }
13228   {
13229     USI opval = FLD (i_const32_pcrel);
13230     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
13231     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
13232   }
13233 }
13234 }
13235 }
13236
13237   SEM_BRANCH_FINI (vpc);
13238 #undef FLD
13239 }
13240   NEXT (vpc);
13241
13242   CASE (sem, INSN_BREAK) : /* break $n */
13243 {
13244   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13245   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13246 #define FLD(f) abuf->fields.sfmt_break.f
13247   int UNUSED written = 0;
13248   IADDR UNUSED pc = abuf->addr;
13249   SEM_BRANCH_INIT
13250   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13251
13252 {
13253 {
13254   {
13255     BI opval = 0;
13256     CPU (h_xbit) = opval;
13257     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13258   }
13259   {
13260     BI opval = 0;
13261     SET_H_INSN_PREFIXED_P (opval);
13262     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13263   }
13264 }
13265   {
13266     USI opval = crisv32f_break_handler (current_cpu, FLD (f_u4), pc);
13267     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
13268     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
13269   }
13270 }
13271
13272   SEM_BRANCH_FINI (vpc);
13273 #undef FLD
13274 }
13275   NEXT (vpc);
13276
13277   CASE (sem, INSN_BOUND_R_B_R) : /* bound-r.b ${Rs},${Rd} */
13278 {
13279   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13280   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13281 #define FLD(f) abuf->fields.sfmt_muls_b.f
13282   int UNUSED written = 0;
13283   IADDR UNUSED pc = abuf->addr;
13284   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13285
13286 {
13287   SI tmp_tmpopd;
13288   SI tmp_tmpops;
13289   SI tmp_newval;
13290   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
13291   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13292   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13293   {
13294     SI opval = tmp_newval;
13295     SET_H_GR (FLD (f_operand2), opval);
13296     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13297   }
13298 {
13299   {
13300     BI opval = LTSI (tmp_newval, 0);
13301     CPU (h_nbit) = opval;
13302     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13303   }
13304   {
13305     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13306     CPU (h_zbit) = opval;
13307     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13308   }
13309 SET_H_CBIT_MOVE (0);
13310 SET_H_VBIT_MOVE (0);
13311 {
13312   {
13313     BI opval = 0;
13314     CPU (h_xbit) = opval;
13315     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13316   }
13317   {
13318     BI opval = 0;
13319     SET_H_INSN_PREFIXED_P (opval);
13320     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13321   }
13322 }
13323 }
13324 }
13325
13326 #undef FLD
13327 }
13328   NEXT (vpc);
13329
13330   CASE (sem, INSN_BOUND_R_W_R) : /* bound-r.w ${Rs},${Rd} */
13331 {
13332   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13333   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13334 #define FLD(f) abuf->fields.sfmt_muls_b.f
13335   int UNUSED written = 0;
13336   IADDR UNUSED pc = abuf->addr;
13337   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13338
13339 {
13340   SI tmp_tmpopd;
13341   SI tmp_tmpops;
13342   SI tmp_newval;
13343   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
13344   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13345   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13346   {
13347     SI opval = tmp_newval;
13348     SET_H_GR (FLD (f_operand2), opval);
13349     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13350   }
13351 {
13352   {
13353     BI opval = LTSI (tmp_newval, 0);
13354     CPU (h_nbit) = opval;
13355     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13356   }
13357   {
13358     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13359     CPU (h_zbit) = opval;
13360     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13361   }
13362 SET_H_CBIT_MOVE (0);
13363 SET_H_VBIT_MOVE (0);
13364 {
13365   {
13366     BI opval = 0;
13367     CPU (h_xbit) = opval;
13368     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13369   }
13370   {
13371     BI opval = 0;
13372     SET_H_INSN_PREFIXED_P (opval);
13373     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13374   }
13375 }
13376 }
13377 }
13378
13379 #undef FLD
13380 }
13381   NEXT (vpc);
13382
13383   CASE (sem, INSN_BOUND_R_D_R) : /* bound-r.d ${Rs},${Rd} */
13384 {
13385   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13386   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13387 #define FLD(f) abuf->fields.sfmt_muls_b.f
13388   int UNUSED written = 0;
13389   IADDR UNUSED pc = abuf->addr;
13390   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13391
13392 {
13393   SI tmp_tmpopd;
13394   SI tmp_tmpops;
13395   SI tmp_newval;
13396   tmp_tmpops = TRUNCSISI (GET_H_GR (FLD (f_operand1)));
13397   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13398   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13399   {
13400     SI opval = tmp_newval;
13401     SET_H_GR (FLD (f_operand2), opval);
13402     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13403   }
13404 {
13405   {
13406     BI opval = LTSI (tmp_newval, 0);
13407     CPU (h_nbit) = opval;
13408     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13409   }
13410   {
13411     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13412     CPU (h_zbit) = opval;
13413     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13414   }
13415 SET_H_CBIT_MOVE (0);
13416 SET_H_VBIT_MOVE (0);
13417 {
13418   {
13419     BI opval = 0;
13420     CPU (h_xbit) = opval;
13421     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13422   }
13423   {
13424     BI opval = 0;
13425     SET_H_INSN_PREFIXED_P (opval);
13426     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13427   }
13428 }
13429 }
13430 }
13431
13432 #undef FLD
13433 }
13434   NEXT (vpc);
13435
13436   CASE (sem, INSN_BOUND_CB) : /* bound.b [PC+],${Rd} */
13437 {
13438   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13439   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13440 #define FLD(f) abuf->fields.sfmt_bound_cb.f
13441   int UNUSED written = 0;
13442   IADDR UNUSED pc = abuf->addr;
13443   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13444
13445 {
13446   SI tmp_tmpopd;
13447   SI tmp_tmpops;
13448   SI tmp_newval;
13449   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
13450   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13451   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13452   {
13453     SI opval = tmp_newval;
13454     SET_H_GR (FLD (f_operand2), opval);
13455     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13456   }
13457 {
13458   {
13459     BI opval = LTSI (tmp_newval, 0);
13460     CPU (h_nbit) = opval;
13461     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13462   }
13463   {
13464     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13465     CPU (h_zbit) = opval;
13466     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13467   }
13468 SET_H_CBIT_MOVE (0);
13469 SET_H_VBIT_MOVE (0);
13470 {
13471   {
13472     BI opval = 0;
13473     CPU (h_xbit) = opval;
13474     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13475   }
13476   {
13477     BI opval = 0;
13478     SET_H_INSN_PREFIXED_P (opval);
13479     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13480   }
13481 }
13482 }
13483 }
13484
13485 #undef FLD
13486 }
13487   NEXT (vpc);
13488
13489   CASE (sem, INSN_BOUND_CW) : /* bound.w [PC+],${Rd} */
13490 {
13491   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13492   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13493 #define FLD(f) abuf->fields.sfmt_bound_cw.f
13494   int UNUSED written = 0;
13495   IADDR UNUSED pc = abuf->addr;
13496   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13497
13498 {
13499   SI tmp_tmpopd;
13500   SI tmp_tmpops;
13501   SI tmp_newval;
13502   tmp_tmpops = ZEXTSISI (FLD (f_indir_pc__word));
13503   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13504   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13505   {
13506     SI opval = tmp_newval;
13507     SET_H_GR (FLD (f_operand2), opval);
13508     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13509   }
13510 {
13511   {
13512     BI opval = LTSI (tmp_newval, 0);
13513     CPU (h_nbit) = opval;
13514     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13515   }
13516   {
13517     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13518     CPU (h_zbit) = opval;
13519     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13520   }
13521 SET_H_CBIT_MOVE (0);
13522 SET_H_VBIT_MOVE (0);
13523 {
13524   {
13525     BI opval = 0;
13526     CPU (h_xbit) = opval;
13527     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13528   }
13529   {
13530     BI opval = 0;
13531     SET_H_INSN_PREFIXED_P (opval);
13532     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13533   }
13534 }
13535 }
13536 }
13537
13538 #undef FLD
13539 }
13540   NEXT (vpc);
13541
13542   CASE (sem, INSN_BOUND_CD) : /* bound.d [PC+],${Rd} */
13543 {
13544   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13545   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13546 #define FLD(f) abuf->fields.sfmt_bound_cd.f
13547   int UNUSED written = 0;
13548   IADDR UNUSED pc = abuf->addr;
13549   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13550
13551 {
13552   SI tmp_tmpopd;
13553   SI tmp_tmpops;
13554   SI tmp_newval;
13555   tmp_tmpops = FLD (f_indir_pc__dword);
13556   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13557   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13558   {
13559     SI opval = tmp_newval;
13560     SET_H_GR (FLD (f_operand2), opval);
13561     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13562   }
13563 {
13564   {
13565     BI opval = LTSI (tmp_newval, 0);
13566     CPU (h_nbit) = opval;
13567     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13568   }
13569   {
13570     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13571     CPU (h_zbit) = opval;
13572     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13573   }
13574 SET_H_CBIT_MOVE (0);
13575 SET_H_VBIT_MOVE (0);
13576 {
13577   {
13578     BI opval = 0;
13579     CPU (h_xbit) = opval;
13580     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13581   }
13582   {
13583     BI opval = 0;
13584     SET_H_INSN_PREFIXED_P (opval);
13585     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13586   }
13587 }
13588 }
13589 }
13590
13591 #undef FLD
13592 }
13593   NEXT (vpc);
13594
13595   CASE (sem, INSN_SCC) : /* s${cc} ${Rd-sfield} */
13596 {
13597   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13598   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13599 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
13600   int UNUSED written = 0;
13601   IADDR UNUSED pc = abuf->addr;
13602   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13603
13604 {
13605   BI tmp_truthval;
13606   tmp_truthval = ({   SI tmp_tmpcond;
13607   BI tmp_condres;
13608   tmp_tmpcond = FLD (f_operand2);
13609 ; if (EQSI (tmp_tmpcond, 0)) {
13610   tmp_condres = NOTBI (CPU (h_cbit));
13611 }
13612  else if (EQSI (tmp_tmpcond, 1)) {
13613   tmp_condres = CPU (h_cbit);
13614 }
13615  else if (EQSI (tmp_tmpcond, 2)) {
13616   tmp_condres = NOTBI (CPU (h_zbit));
13617 }
13618  else if (EQSI (tmp_tmpcond, 3)) {
13619   tmp_condres = CPU (h_zbit);
13620 }
13621  else if (EQSI (tmp_tmpcond, 4)) {
13622   tmp_condres = NOTBI (CPU (h_vbit));
13623 }
13624  else if (EQSI (tmp_tmpcond, 5)) {
13625   tmp_condres = CPU (h_vbit);
13626 }
13627  else if (EQSI (tmp_tmpcond, 6)) {
13628   tmp_condres = NOTBI (CPU (h_nbit));
13629 }
13630  else if (EQSI (tmp_tmpcond, 7)) {
13631   tmp_condres = CPU (h_nbit);
13632 }
13633  else if (EQSI (tmp_tmpcond, 8)) {
13634   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
13635 }
13636  else if (EQSI (tmp_tmpcond, 9)) {
13637   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
13638 }
13639  else if (EQSI (tmp_tmpcond, 10)) {
13640   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
13641 }
13642  else if (EQSI (tmp_tmpcond, 11)) {
13643   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
13644 }
13645  else if (EQSI (tmp_tmpcond, 12)) {
13646   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
13647 }
13648  else if (EQSI (tmp_tmpcond, 13)) {
13649   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
13650 }
13651  else if (EQSI (tmp_tmpcond, 14)) {
13652   tmp_condres = 1;
13653 }
13654  else if (EQSI (tmp_tmpcond, 15)) {
13655   tmp_condres = CPU (h_pbit);
13656 }
13657 ; tmp_condres; });
13658   {
13659     SI opval = ZEXTBISI (tmp_truthval);
13660     SET_H_GR (FLD (f_operand1), opval);
13661     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13662   }
13663 {
13664   {
13665     BI opval = 0;
13666     CPU (h_xbit) = opval;
13667     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13668   }
13669   {
13670     BI opval = 0;
13671     SET_H_INSN_PREFIXED_P (opval);
13672     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13673   }
13674 }
13675 }
13676
13677 #undef FLD
13678 }
13679   NEXT (vpc);
13680
13681   CASE (sem, INSN_LZ) : /* lz ${Rs},${Rd} */
13682 {
13683   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13684   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13685 #define FLD(f) abuf->fields.sfmt_muls_b.f
13686   int UNUSED written = 0;
13687   IADDR UNUSED pc = abuf->addr;
13688   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13689
13690 {
13691   SI tmp_tmpd;
13692   SI tmp_tmp;
13693   tmp_tmp = GET_H_GR (FLD (f_operand1));
13694   tmp_tmpd = 0;
13695 {
13696 if (GESI (tmp_tmp, 0)) {
13697 {
13698   tmp_tmp = SLLSI (tmp_tmp, 1);
13699   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13700 }
13701 }
13702 if (GESI (tmp_tmp, 0)) {
13703 {
13704   tmp_tmp = SLLSI (tmp_tmp, 1);
13705   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13706 }
13707 }
13708 if (GESI (tmp_tmp, 0)) {
13709 {
13710   tmp_tmp = SLLSI (tmp_tmp, 1);
13711   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13712 }
13713 }
13714 if (GESI (tmp_tmp, 0)) {
13715 {
13716   tmp_tmp = SLLSI (tmp_tmp, 1);
13717   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13718 }
13719 }
13720 if (GESI (tmp_tmp, 0)) {
13721 {
13722   tmp_tmp = SLLSI (tmp_tmp, 1);
13723   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13724 }
13725 }
13726 if (GESI (tmp_tmp, 0)) {
13727 {
13728   tmp_tmp = SLLSI (tmp_tmp, 1);
13729   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13730 }
13731 }
13732 if (GESI (tmp_tmp, 0)) {
13733 {
13734   tmp_tmp = SLLSI (tmp_tmp, 1);
13735   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13736 }
13737 }
13738 if (GESI (tmp_tmp, 0)) {
13739 {
13740   tmp_tmp = SLLSI (tmp_tmp, 1);
13741   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13742 }
13743 }
13744 if (GESI (tmp_tmp, 0)) {
13745 {
13746   tmp_tmp = SLLSI (tmp_tmp, 1);
13747   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13748 }
13749 }
13750 if (GESI (tmp_tmp, 0)) {
13751 {
13752   tmp_tmp = SLLSI (tmp_tmp, 1);
13753   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13754 }
13755 }
13756 if (GESI (tmp_tmp, 0)) {
13757 {
13758   tmp_tmp = SLLSI (tmp_tmp, 1);
13759   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13760 }
13761 }
13762 if (GESI (tmp_tmp, 0)) {
13763 {
13764   tmp_tmp = SLLSI (tmp_tmp, 1);
13765   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13766 }
13767 }
13768 if (GESI (tmp_tmp, 0)) {
13769 {
13770   tmp_tmp = SLLSI (tmp_tmp, 1);
13771   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13772 }
13773 }
13774 if (GESI (tmp_tmp, 0)) {
13775 {
13776   tmp_tmp = SLLSI (tmp_tmp, 1);
13777   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13778 }
13779 }
13780 if (GESI (tmp_tmp, 0)) {
13781 {
13782   tmp_tmp = SLLSI (tmp_tmp, 1);
13783   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13784 }
13785 }
13786 if (GESI (tmp_tmp, 0)) {
13787 {
13788   tmp_tmp = SLLSI (tmp_tmp, 1);
13789   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13790 }
13791 }
13792 if (GESI (tmp_tmp, 0)) {
13793 {
13794   tmp_tmp = SLLSI (tmp_tmp, 1);
13795   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13796 }
13797 }
13798 if (GESI (tmp_tmp, 0)) {
13799 {
13800   tmp_tmp = SLLSI (tmp_tmp, 1);
13801   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13802 }
13803 }
13804 if (GESI (tmp_tmp, 0)) {
13805 {
13806   tmp_tmp = SLLSI (tmp_tmp, 1);
13807   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13808 }
13809 }
13810 if (GESI (tmp_tmp, 0)) {
13811 {
13812   tmp_tmp = SLLSI (tmp_tmp, 1);
13813   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13814 }
13815 }
13816 if (GESI (tmp_tmp, 0)) {
13817 {
13818   tmp_tmp = SLLSI (tmp_tmp, 1);
13819   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13820 }
13821 }
13822 if (GESI (tmp_tmp, 0)) {
13823 {
13824   tmp_tmp = SLLSI (tmp_tmp, 1);
13825   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13826 }
13827 }
13828 if (GESI (tmp_tmp, 0)) {
13829 {
13830   tmp_tmp = SLLSI (tmp_tmp, 1);
13831   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13832 }
13833 }
13834 if (GESI (tmp_tmp, 0)) {
13835 {
13836   tmp_tmp = SLLSI (tmp_tmp, 1);
13837   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13838 }
13839 }
13840 if (GESI (tmp_tmp, 0)) {
13841 {
13842   tmp_tmp = SLLSI (tmp_tmp, 1);
13843   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13844 }
13845 }
13846 if (GESI (tmp_tmp, 0)) {
13847 {
13848   tmp_tmp = SLLSI (tmp_tmp, 1);
13849   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13850 }
13851 }
13852 if (GESI (tmp_tmp, 0)) {
13853 {
13854   tmp_tmp = SLLSI (tmp_tmp, 1);
13855   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13856 }
13857 }
13858 if (GESI (tmp_tmp, 0)) {
13859 {
13860   tmp_tmp = SLLSI (tmp_tmp, 1);
13861   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13862 }
13863 }
13864 if (GESI (tmp_tmp, 0)) {
13865 {
13866   tmp_tmp = SLLSI (tmp_tmp, 1);
13867   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13868 }
13869 }
13870 if (GESI (tmp_tmp, 0)) {
13871 {
13872   tmp_tmp = SLLSI (tmp_tmp, 1);
13873   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13874 }
13875 }
13876 if (GESI (tmp_tmp, 0)) {
13877 {
13878   tmp_tmp = SLLSI (tmp_tmp, 1);
13879   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13880 }
13881 }
13882 if (GESI (tmp_tmp, 0)) {
13883 {
13884   tmp_tmp = SLLSI (tmp_tmp, 1);
13885   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13886 }
13887 }
13888 }
13889   {
13890     SI opval = tmp_tmpd;
13891     SET_H_GR (FLD (f_operand2), opval);
13892     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13893   }
13894 {
13895   {
13896     BI opval = LTSI (tmp_tmpd, 0);
13897     CPU (h_nbit) = opval;
13898     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13899   }
13900   {
13901     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13902     CPU (h_zbit) = opval;
13903     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13904   }
13905 SET_H_CBIT_MOVE (0);
13906 SET_H_VBIT_MOVE (0);
13907 {
13908   {
13909     BI opval = 0;
13910     CPU (h_xbit) = opval;
13911     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13912   }
13913   {
13914     BI opval = 0;
13915     SET_H_INSN_PREFIXED_P (opval);
13916     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13917   }
13918 }
13919 }
13920 }
13921
13922 #undef FLD
13923 }
13924   NEXT (vpc);
13925
13926   CASE (sem, INSN_ADDOQ) : /* addoq $o,$Rs,ACR */
13927 {
13928   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13929   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13930 #define FLD(f) abuf->fields.sfmt_addoq.f
13931   int UNUSED written = 0;
13932   IADDR UNUSED pc = abuf->addr;
13933   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13934
13935 {
13936   {
13937     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s8));
13938     SET_H_PREFIXREG_V32 (opval);
13939     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13940   }
13941   {
13942     BI opval = 1;
13943     SET_H_INSN_PREFIXED_P (opval);
13944     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13945   }
13946 }
13947
13948 #undef FLD
13949 }
13950   NEXT (vpc);
13951
13952   CASE (sem, INSN_ADDO_M_B_M) : /* addo-m.b [${Rs}${inc}],$Rd,ACR */
13953 {
13954   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13955   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13956 #define FLD(f) abuf->fields.sfmt_addc_m.f
13957   int UNUSED written = 0;
13958   IADDR UNUSED pc = abuf->addr;
13959   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13960
13961 {
13962   QI tmp_tmps;
13963   tmp_tmps = ({   SI tmp_addr;
13964   QI tmp_tmp_mem;
13965   BI tmp_postinc;
13966   tmp_postinc = FLD (f_memmode);
13967 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
13968 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
13969 ; if (NEBI (tmp_postinc, 0)) {
13970 {
13971 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13972   tmp_addr = ADDSI (tmp_addr, 1);
13973 }
13974   {
13975     SI opval = tmp_addr;
13976     SET_H_GR (FLD (f_operand1), opval);
13977     written |= (1 << 6);
13978     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13979   }
13980 }
13981 }
13982 ; tmp_tmp_mem; });
13983   {
13984     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (tmp_tmps));
13985     SET_H_PREFIXREG_V32 (opval);
13986     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13987   }
13988   {
13989     BI opval = 1;
13990     SET_H_INSN_PREFIXED_P (opval);
13991     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13992   }
13993 }
13994
13995   abuf->written = written;
13996 #undef FLD
13997 }
13998   NEXT (vpc);
13999
14000   CASE (sem, INSN_ADDO_M_W_M) : /* addo-m.w [${Rs}${inc}],$Rd,ACR */
14001 {
14002   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14003   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14004 #define FLD(f) abuf->fields.sfmt_addc_m.f
14005   int UNUSED written = 0;
14006   IADDR UNUSED pc = abuf->addr;
14007   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14008
14009 {
14010   HI tmp_tmps;
14011   tmp_tmps = ({   SI tmp_addr;
14012   HI tmp_tmp_mem;
14013   BI tmp_postinc;
14014   tmp_postinc = FLD (f_memmode);
14015 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
14016 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
14017 ; if (NEBI (tmp_postinc, 0)) {
14018 {
14019 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
14020   tmp_addr = ADDSI (tmp_addr, 2);
14021 }
14022   {
14023     SI opval = tmp_addr;
14024     SET_H_GR (FLD (f_operand1), opval);
14025     written |= (1 << 6);
14026     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
14027   }
14028 }
14029 }
14030 ; tmp_tmp_mem; });
14031   {
14032     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (tmp_tmps));
14033     SET_H_PREFIXREG_V32 (opval);
14034     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14035   }
14036   {
14037     BI opval = 1;
14038     SET_H_INSN_PREFIXED_P (opval);
14039     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14040   }
14041 }
14042
14043   abuf->written = written;
14044 #undef FLD
14045 }
14046   NEXT (vpc);
14047
14048   CASE (sem, INSN_ADDO_M_D_M) : /* addo-m.d [${Rs}${inc}],$Rd,ACR */
14049 {
14050   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14051   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14052 #define FLD(f) abuf->fields.sfmt_addc_m.f
14053   int UNUSED written = 0;
14054   IADDR UNUSED pc = abuf->addr;
14055   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14056
14057 {
14058   SI tmp_tmps;
14059   tmp_tmps = ({   SI tmp_addr;
14060   SI tmp_tmp_mem;
14061   BI tmp_postinc;
14062   tmp_postinc = FLD (f_memmode);
14063 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
14064 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
14065 ; if (NEBI (tmp_postinc, 0)) {
14066 {
14067 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
14068   tmp_addr = ADDSI (tmp_addr, 4);
14069 }
14070   {
14071     SI opval = tmp_addr;
14072     SET_H_GR (FLD (f_operand1), opval);
14073     written |= (1 << 6);
14074     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
14075   }
14076 }
14077 }
14078 ; tmp_tmp_mem; });
14079   {
14080     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), tmp_tmps);
14081     SET_H_PREFIXREG_V32 (opval);
14082     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14083   }
14084   {
14085     BI opval = 1;
14086     SET_H_INSN_PREFIXED_P (opval);
14087     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14088   }
14089 }
14090
14091   abuf->written = written;
14092 #undef FLD
14093 }
14094   NEXT (vpc);
14095
14096   CASE (sem, INSN_ADDO_CB) : /* addo.b [PC+],$Rd,ACR */
14097 {
14098   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14099   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14100 #define FLD(f) abuf->fields.sfmt_bound_cb.f
14101   int UNUSED written = 0;
14102   IADDR UNUSED pc = abuf->addr;
14103   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
14104
14105 {
14106   {
14107     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))));
14108     SET_H_PREFIXREG_V32 (opval);
14109     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14110   }
14111   {
14112     BI opval = 1;
14113     SET_H_INSN_PREFIXED_P (opval);
14114     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14115   }
14116 }
14117
14118 #undef FLD
14119 }
14120   NEXT (vpc);
14121
14122   CASE (sem, INSN_ADDO_CW) : /* addo.w [PC+],$Rd,ACR */
14123 {
14124   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14125   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14126 #define FLD(f) abuf->fields.sfmt_bound_cw.f
14127   int UNUSED written = 0;
14128   IADDR UNUSED pc = abuf->addr;
14129   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
14130
14131 {
14132   {
14133     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))));
14134     SET_H_PREFIXREG_V32 (opval);
14135     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14136   }
14137   {
14138     BI opval = 1;
14139     SET_H_INSN_PREFIXED_P (opval);
14140     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14141   }
14142 }
14143
14144 #undef FLD
14145 }
14146   NEXT (vpc);
14147
14148   CASE (sem, INSN_ADDO_CD) : /* addo.d [PC+],$Rd,ACR */
14149 {
14150   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14151   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14152 #define FLD(f) abuf->fields.sfmt_bound_cd.f
14153   int UNUSED written = 0;
14154   IADDR UNUSED pc = abuf->addr;
14155   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
14156
14157 {
14158   {
14159     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
14160     SET_H_PREFIXREG_V32 (opval);
14161     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14162   }
14163   {
14164     BI opval = 1;
14165     SET_H_INSN_PREFIXED_P (opval);
14166     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14167   }
14168 }
14169
14170 #undef FLD
14171 }
14172   NEXT (vpc);
14173
14174   CASE (sem, INSN_ADDI_ACR_B_R) : /* addi-acr.b ${Rs-dfield}.m,${Rd-sfield},ACR */
14175 {
14176   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14177   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14178 #define FLD(f) abuf->fields.sfmt_muls_b.f
14179   int UNUSED written = 0;
14180   IADDR UNUSED pc = abuf->addr;
14181   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14182
14183 {
14184   {
14185     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
14186     SET_H_PREFIXREG_V32 (opval);
14187     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14188   }
14189   {
14190     BI opval = 1;
14191     SET_H_INSN_PREFIXED_P (opval);
14192     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14193   }
14194 }
14195
14196 #undef FLD
14197 }
14198   NEXT (vpc);
14199
14200   CASE (sem, INSN_ADDI_ACR_W_R) : /* addi-acr.w ${Rs-dfield}.m,${Rd-sfield},ACR */
14201 {
14202   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14203   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14204 #define FLD(f) abuf->fields.sfmt_muls_b.f
14205   int UNUSED written = 0;
14206   IADDR UNUSED pc = abuf->addr;
14207   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14208
14209 {
14210   {
14211     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
14212     SET_H_PREFIXREG_V32 (opval);
14213     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14214   }
14215   {
14216     BI opval = 1;
14217     SET_H_INSN_PREFIXED_P (opval);
14218     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14219   }
14220 }
14221
14222 #undef FLD
14223 }
14224   NEXT (vpc);
14225
14226   CASE (sem, INSN_ADDI_ACR_D_R) : /* addi-acr.d ${Rs-dfield}.m,${Rd-sfield},ACR */
14227 {
14228   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14229   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14230 #define FLD(f) abuf->fields.sfmt_muls_b.f
14231   int UNUSED written = 0;
14232   IADDR UNUSED pc = abuf->addr;
14233   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14234
14235 {
14236   {
14237     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
14238     SET_H_PREFIXREG_V32 (opval);
14239     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14240   }
14241   {
14242     BI opval = 1;
14243     SET_H_INSN_PREFIXED_P (opval);
14244     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14245   }
14246 }
14247
14248 #undef FLD
14249 }
14250   NEXT (vpc);
14251
14252   CASE (sem, INSN_FIDXI) : /* fidxi [$Rs] */
14253 {
14254   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14255   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14256 #define FLD(f) abuf->fields.sfmt_mcp.f
14257   int UNUSED written = 0;
14258   IADDR UNUSED pc = abuf->addr;
14259   SEM_BRANCH_INIT
14260   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14261
14262   {
14263     USI opval = crisv32f_fidxi_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
14264     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
14265     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
14266   }
14267
14268   SEM_BRANCH_FINI (vpc);
14269 #undef FLD
14270 }
14271   NEXT (vpc);
14272
14273   CASE (sem, INSN_FTAGI) : /* fidxi [$Rs] */
14274 {
14275   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14276   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14277 #define FLD(f) abuf->fields.sfmt_mcp.f
14278   int UNUSED written = 0;
14279   IADDR UNUSED pc = abuf->addr;
14280   SEM_BRANCH_INIT
14281   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14282
14283   {
14284     USI opval = crisv32f_ftagi_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
14285     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
14286     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
14287   }
14288
14289   SEM_BRANCH_FINI (vpc);
14290 #undef FLD
14291 }
14292   NEXT (vpc);
14293
14294   CASE (sem, INSN_FIDXD) : /* fidxd [$Rs] */
14295 {
14296   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14297   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14298 #define FLD(f) abuf->fields.sfmt_mcp.f
14299   int UNUSED written = 0;
14300   IADDR UNUSED pc = abuf->addr;
14301   SEM_BRANCH_INIT
14302   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14303
14304   {
14305     USI opval = crisv32f_fidxd_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
14306     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
14307     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
14308   }
14309
14310   SEM_BRANCH_FINI (vpc);
14311 #undef FLD
14312 }
14313   NEXT (vpc);
14314
14315   CASE (sem, INSN_FTAGD) : /* ftagd [$Rs] */
14316 {
14317   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14318   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14319 #define FLD(f) abuf->fields.sfmt_mcp.f
14320   int UNUSED written = 0;
14321   IADDR UNUSED pc = abuf->addr;
14322   SEM_BRANCH_INIT
14323   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14324
14325   {
14326     USI opval = crisv32f_ftagd_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
14327     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
14328     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
14329   }
14330
14331   SEM_BRANCH_FINI (vpc);
14332 #undef FLD
14333 }
14334   NEXT (vpc);
14335
14336
14337     }
14338   ENDSWITCH (sem) /* End of semantic switch.  */
14339
14340   /* At this point `vpc' contains the next insn to execute.  */
14341 }
14342
14343 #undef DEFINE_SWITCH
14344 #endif /* DEFINE_SWITCH */