sim/d10v/d10v_sim.h

   1 #include <stdio.h>
   2 #include <ctype.h>
   3 #include <limits.h>
   4 #include "ansidecl.h"
   5 #include "sim/callback.h"
   6 #include "opcode/d10v.h"
   7 #include "bfd.h"
   8
   9 #define DEBUG_TRACE             0x00000001
  10 #define DEBUG_VALUES            0x00000002
  11 #define DEBUG_LINE_NUMBER       0x00000004
  12 #define DEBUG_MEMSIZE           0x00000008
  13 #define DEBUG_INSTRUCTION       0x00000010
  14 #define DEBUG_TRAP              0x00000020
  15 #define DEBUG_MEMORY            0x00000040
  16
  17 #ifndef DEBUG
  18 #define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
  19 #endif
  20
  21 extern int d10v_debug;
  22
  23 #include "sim/sim.h"
  24 #include "sim-config.h"
  25 #include "sim-types.h"
  26
  27 typedef unsigned8 uint8;
  28 typedef unsigned16 uint16;
  29 typedef signed16 int16;
  30 typedef unsigned32 uint32;
  31 typedef signed32 int32;
  32 typedef unsigned64 uint64;
  33 typedef signed64 int64;
  34
  35 /* FIXME: D10V defines */
  36 typedef uint16 reg_t;
  37
  38 struct simops
  39 {
  40   long opcode;
  41   int  is_long;
  42   long mask;
  43   int format;
  44   int cycles;
  45   int unit;
  46   int exec_type;
  47   void (*func)(SIM_DESC, SIM_CPU *);
  48   int numops;
  49   int operands[9];
  50 };
  51
  52 enum _ins_type
  53 {
  54   INS_UNKNOWN,                  /* unknown instruction */
  55   INS_COND_TRUE,                /* # times EXExxx executed other instruction */
  56   INS_COND_FALSE,               /* # times EXExxx did not execute other instruction */
  57   INS_COND_JUMP,                /* # times JUMP skipped other instruction */
  58   INS_CYCLES,                   /* # cycles */
  59   INS_LONG,                     /* long instruction (both containers, ie FM == 11) */
  60   INS_LEFTRIGHT,                /* # times instruction encoded as L -> R (ie, FM == 01) */
  61   INS_RIGHTLEFT,                /* # times instruction encoded as L <- R (ie, FM == 10) */
  62   INS_PARALLEL,                 /* # times instruction encoded as L || R (ie, RM == 00) */
  63
  64   INS_LEFT,                     /* normal left instructions */
  65   INS_LEFT_PARALLEL,            /* left side of || */
  66   INS_LEFT_COND_TEST,           /* EXExx test on left side */
  67   INS_LEFT_COND_EXE,            /* execution after EXExxx test on right side succeeded */
  68   INS_LEFT_NOPS,                /* NOP on left side */
  69
  70   INS_RIGHT,                    /* normal right instructions */
  71   INS_RIGHT_PARALLEL,           /* right side of || */
  72   INS_RIGHT_COND_TEST,          /* EXExx test on right side */
  73   INS_RIGHT_COND_EXE,           /* execution after EXExxx test on left side succeeded */
  74   INS_RIGHT_NOPS,               /* NOP on right side */
  75
  76   INS_MAX
  77 };
  78
  79 extern unsigned long ins_type_counters[ (int)INS_MAX ];
  80
  81 enum {
  82   SP_IDX = 15,
  83 };
  84
  85 /* Write-back slots */
  86 union slot_data {
  87   unsigned_1 _1;
  88   unsigned_2 _2;
  89   unsigned_4 _4;
  90   unsigned_8 _8;
  91 };
  92 struct slot {
  93   void *dest;
  94   int size;
  95   union slot_data data;
  96   union slot_data mask;
  97 };
  98 enum {
  99  NR_SLOTS = 16,
 100 };
 101 #define SLOT (State.slot)
 102 #define SLOT_NR (State.slot_nr)
 103 #define SLOT_PEND_MASK(DEST, MSK, VAL) \
 104   do \
 105     { \
 106       SLOT[SLOT_NR].dest = &(DEST); \
 107       SLOT[SLOT_NR].size = sizeof (DEST); \
 108       switch (sizeof (DEST)) \
 109         { \
 110         case 1: \
 111           SLOT[SLOT_NR].data._1 = (unsigned_1) (VAL); \
 112           SLOT[SLOT_NR].mask._1 = (unsigned_1) (MSK); \
 113           break; \
 114         case 2: \
 115           SLOT[SLOT_NR].data._2 = (unsigned_2) (VAL); \
 116           SLOT[SLOT_NR].mask._2 = (unsigned_2) (MSK); \
 117           break; \
 118         case 4: \
 119           SLOT[SLOT_NR].data._4 = (unsigned_4) (VAL); \
 120           SLOT[SLOT_NR].mask._4 = (unsigned_4) (MSK); \
 121           break; \
 122         case 8: \
 123           SLOT[SLOT_NR].data._8 = (unsigned_8) (VAL); \
 124           SLOT[SLOT_NR].mask._8 = (unsigned_8) (MSK); \
 125           break; \
 126         } \
 127       SLOT_NR = (SLOT_NR + 1); \
 128     } \
 129   while (0)
 130 #define SLOT_PEND(DEST, VAL) SLOT_PEND_MASK(DEST, 0, VAL)
 131 #define SLOT_DISCARD() (SLOT_NR = 0)
 132 #define SLOT_FLUSH() \
 133   do \
 134     { \
 135       int i; \
 136       for (i = 0; i < SLOT_NR; i++) \
 137         { \
 138           switch (SLOT[i].size) \
 139             { \
 140             case 1: \
 141               *(unsigned_1*) SLOT[i].dest &= SLOT[i].mask._1; \
 142               *(unsigned_1*) SLOT[i].dest |= SLOT[i].data._1; \
 143               break; \
 144             case 2: \
 145               *(unsigned_2*) SLOT[i].dest &= SLOT[i].mask._2; \
 146               *(unsigned_2*) SLOT[i].dest |= SLOT[i].data._2; \
 147               break; \
 148             case 4: \
 149               *(unsigned_4*) SLOT[i].dest &= SLOT[i].mask._4; \
 150               *(unsigned_4*) SLOT[i].dest |= SLOT[i].data._4; \
 151               break; \
 152             case 8: \
 153               *(unsigned_8*) SLOT[i].dest &= SLOT[i].mask._8; \
 154               *(unsigned_8*) SLOT[i].dest |= SLOT[i].data._8; \
 155               break; \
 156             } \
 157         } \
 158       SLOT_NR = 0; \
 159     } \
 160   while (0)
 161 #define SLOT_DUMP() \
 162   do \
 163     { \
 164       int i; \
 165       for (i = 0; i < SLOT_NR; i++) \
 166         { \
 167           switch (SLOT[i].size) \
 168             { \
 169             case 1: \
 170               printf ("SLOT %d *0x%08lx & 0x%02x | 0x%02x\n", i, \
 171                       (long) SLOT[i].dest, \
 172                       (unsigned) SLOT[i].mask._1, \
 173                       (unsigned) SLOT[i].data._1); \
 174               break; \
 175             case 2: \
 176               printf ("SLOT %d *0x%08lx & 0x%04x | 0x%04x\n", i, \
 177                       (long) SLOT[i].dest, \
 178                       (unsigned) SLOT[i].mask._2, \
 179                       (unsigned) SLOT[i].data._2); \
 180               break; \
 181             case 4: \
 182               printf ("SLOT %d *0x%08lx & 0x%08x | 0x%08x\n", i, \
 183                       (long) SLOT[i].dest, \
 184                       (unsigned) SLOT[i].mask._4, \
 185                       (unsigned) SLOT[i].data._4); \
 186               break; \
 187             case 8: \
 188               printf ("SLOT %d *0x%08lx & 0x%08x%08x | 0x%08x%08x\n", i, \
 189                       (long) SLOT[i].dest, \
 190                       (unsigned) (SLOT[i].mask._8 >> 32),  \
 191                       (unsigned) SLOT[i].mask._8, \
 192                       (unsigned) (SLOT[i].data._8 >> 32),  \
 193                       (unsigned) SLOT[i].data._8); \
 194               break; \
 195             } \
 196         } \
 197     } \
 198   while (0)
 199
 200 /* d10v memory: There are three separate d10v memory regions IMEM,
 201    UMEM and DMEM.  The IMEM and DMEM are further broken down into
 202    blocks (very like VM pages). */
 203
 204 enum
 205 {
 206   IMAP_BLOCK_SIZE = 0x20000,
 207   DMAP_BLOCK_SIZE = 0x4000,
 208 };
 209
 210 /* Implement the three memory regions using sparse arrays.  Allocate
 211    memory using ``segments''.  A segment must be at least as large as
 212    a BLOCK - ensures that an access that doesn't cross a block
 213    boundary can't cross a segment boundary */
 214
 215 enum
 216 {
 217   SEGMENT_SIZE = 0x20000, /* 128KB - MAX(IMAP_BLOCK_SIZE,DMAP_BLOCK_SIZE) */
 218   IMEM_SEGMENTS = 8, /* 1MB */
 219   DMEM_SEGMENTS = 8, /* 1MB */
 220   UMEM_SEGMENTS = 128 /* 16MB */
 221 };
 222
 223 struct d10v_memory
 224 {
 225   uint8 *insn[IMEM_SEGMENTS];
 226   uint8 *data[DMEM_SEGMENTS];
 227   uint8 *unif[UMEM_SEGMENTS];
 228 };
 229
 230 struct _state
 231 {
 232   reg_t regs[16];               /* general-purpose registers */
 233 #define GPR(N) (State.regs[(N)] + 0)
 234 #define SET_GPR(N,VAL) SLOT_PEND (State.regs[(N)], (VAL))
 235
 236 #define GPR32(N) ((((uint32) State.regs[(N) + 0]) << 16) \
 237                   | (uint16) State.regs[(N) + 1])
 238 #define SET_GPR32(N,VAL) do { SET_GPR (OP[0] + 0, (VAL) >> 16); SET_GPR (OP[0] + 1, (VAL)); } while (0)
 239
 240   reg_t cregs[16];              /* control registers */
 241 #define CREG(N) (State.cregs[(N)] + 0)
 242 #define SET_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 0)
 243 #define SET_HW_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 1)
 244
 245   reg_t sp[2];                  /* holding area for SPI(0)/SPU(1) */
 246 #define HELD_SP(N) (State.sp[(N)] + 0)
 247 #define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL))
 248
 249   int64 a[2];                   /* accumulators */
 250 #define ACC(N) (State.a[(N)] + 0)
 251 #define SET_ACC(N,VAL) SLOT_PEND (State.a[(N)], (VAL) & MASK40)
 252
 253   /* writeback info */
 254   struct slot slot[NR_SLOTS];
 255   int slot_nr;
 256
 257   /* trace data */
 258   struct {
 259     uint16 psw;
 260   } trace;
 261
 262   uint8 exe;
 263   int   pc_changed;
 264
 265   /* NOTE: everything below this line is not reset by
 266      sim_create_inferior() */
 267
 268   struct d10v_memory mem;
 269
 270   enum _ins_type ins_type;
 271
 272 };
 273
 274 extern struct _state State;
 275
 276
 277 extern uint16 OP[4];
 278 extern struct simops Simops[];
 279
 280 enum
 281 {
 282   PSW_CR = 0,
 283   BPSW_CR = 1,
 284   PC_CR = 2,
 285   BPC_CR = 3,
 286   DPSW_CR = 4,
 287   DPC_CR = 5,
 288   RPT_C_CR = 7,
 289   RPT_S_CR = 8,
 290   RPT_E_CR = 9,
 291   MOD_S_CR = 10,
 292   MOD_E_CR = 11,
 293   IBA_CR = 14,
 294 };
 295
 296 enum
 297 {
 298   PSW_SM_BIT = 0x8000,
 299   PSW_EA_BIT = 0x2000,
 300   PSW_DB_BIT = 0x1000,
 301   PSW_DM_BIT = 0x0800,
 302   PSW_IE_BIT = 0x0400,
 303   PSW_RP_BIT = 0x0200,
 304   PSW_MD_BIT = 0x0100,
 305   PSW_FX_BIT = 0x0080,
 306   PSW_ST_BIT = 0x0040,
 307   PSW_F0_BIT = 0x0008,
 308   PSW_F1_BIT = 0x0004,
 309   PSW_C_BIT =  0x0001,
 310 };
 311
 312 #define PSW CREG (PSW_CR)
 313 #define SET_PSW(VAL) SET_CREG (PSW_CR, (VAL))
 314 #define SET_HW_PSW(VAL) SET_HW_CREG (PSW_CR, (VAL))
 315 #define SET_PSW_BIT(MASK,VAL) move_to_cr (sd, cpu, PSW_CR, ~((reg_t) MASK), (VAL) ? (MASK) : 0, 1)
 316
 317 #define PSW_SM ((PSW & PSW_SM_BIT) != 0)
 318 #define SET_PSW_SM(VAL) SET_PSW_BIT (PSW_SM_BIT, (VAL))
 319
 320 #define PSW_EA ((PSW & PSW_EA_BIT) != 0)
 321 #define SET_PSW_EA(VAL) SET_PSW_BIT (PSW_EA_BIT, (VAL))
 322
 323 #define PSW_DB ((PSW & PSW_DB_BIT) != 0)
 324 #define SET_PSW_DB(VAL) SET_PSW_BIT (PSW_DB_BIT, (VAL))
 325
 326 #define PSW_DM ((PSW & PSW_DM_BIT) != 0)
 327 #define SET_PSW_DM(VAL) SET_PSW_BIT (PSW_DM_BIT, (VAL))
 328
 329 #define PSW_IE ((PSW & PSW_IE_BIT) != 0)
 330 #define SET_PSW_IE(VAL) SET_PSW_BIT (PSW_IE_BIT, (VAL))
 331
 332 #define PSW_RP ((PSW & PSW_RP_BIT) != 0)
 333 #define SET_PSW_RP(VAL) SET_PSW_BIT (PSW_RP_BIT, (VAL))
 334
 335 #define PSW_MD ((PSW & PSW_MD_BIT) != 0)
 336 #define SET_PSW_MD(VAL) SET_PSW_BIT (PSW_MD_BIT, (VAL))
 337
 338 #define PSW_FX ((PSW & PSW_FX_BIT) != 0)
 339 #define SET_PSW_FX(VAL) SET_PSW_BIT (PSW_FX_BIT, (VAL))
 340
 341 #define PSW_ST ((PSW & PSW_ST_BIT) != 0)
 342 #define SET_PSW_ST(VAL) SET_PSW_BIT (PSW_ST_BIT, (VAL))
 343
 344 #define PSW_F0 ((PSW & PSW_F0_BIT) != 0)
 345 #define SET_PSW_F0(VAL) SET_PSW_BIT (PSW_F0_BIT, (VAL))
 346
 347 #define PSW_F1 ((PSW & PSW_F1_BIT) != 0)
 348 #define SET_PSW_F1(VAL) SET_PSW_BIT (PSW_F1_BIT, (VAL))
 349
 350 #define PSW_C ((PSW & PSW_C_BIT) != 0)
 351 #define SET_PSW_C(VAL) SET_PSW_BIT (PSW_C_BIT, (VAL))
 352
 353 /* See simopsc.:move_to_cr() for registers that can not be read-from
 354    or assigned-to directly */
 355
 356 #define PC      CREG (PC_CR)
 357 #define SET_PC(VAL) SET_CREG (PC_CR, (VAL))
 358
 359 #define BPSW    CREG (BPSW_CR)
 360 #define SET_BPSW(VAL) SET_CREG (BPSW_CR, (VAL))
 361
 362 #define BPC     CREG (BPC_CR)
 363 #define SET_BPC(VAL) SET_CREG (BPC_CR, (VAL))
 364
 365 #define DPSW    CREG (DPSW_CR)
 366 #define SET_DPSW(VAL) SET_CREG (DPSW_CR, (VAL))
 367
 368 #define DPC     CREG (DPC_CR)
 369 #define SET_DPC(VAL) SET_CREG (DPC_CR, (VAL))
 370
 371 #define RPT_C   CREG (RPT_C_CR)
 372 #define SET_RPT_C(VAL) SET_CREG (RPT_C_CR, (VAL))
 373
 374 #define RPT_S   CREG (RPT_S_CR)
 375 #define SET_RPT_S(VAL) SET_CREG (RPT_S_CR, (VAL))
 376
 377 #define RPT_E   CREG (RPT_E_CR)
 378 #define SET_RPT_E(VAL) SET_CREG (RPT_E_CR, (VAL))
 379
 380 #define MOD_S   CREG (MOD_S_CR)
 381 #define SET_MOD_S(VAL) SET_CREG (MOD_S_CR, (VAL))
 382
 383 #define MOD_E   CREG (MOD_E_CR)
 384 #define SET_MOD_E(VAL) SET_CREG (MOD_E_CR, (VAL))
 385
 386 #define IBA     CREG (IBA_CR)
 387 #define SET_IBA(VAL) SET_CREG (IBA_CR, (VAL))
 388
 389
 390 #define SIG_D10V_STOP   -1
 391 #define SIG_D10V_EXIT   -2
 392 #define SIG_D10V_BUS    -3
 393
 394 /* TODO: Resolve conflicts with common headers.  */
 395 #undef SEXT8
 396 #undef SEXT16
 397 #undef SEXT32
 398 #undef MASK32
 399
 400 #define SEXT3(x)        ((((x)&0x7)^(~3))+4)
 401
 402 /* sign-extend a 4-bit number */
 403 #define SEXT4(x)        ((((x)&0xf)^(~7))+8)
 404
 405 /* sign-extend an 8-bit number */
 406 #define SEXT8(x)        ((((x)&0xff)^(~0x7f))+0x80)
 407
 408 /* sign-extend a 16-bit number */
 409 #define SEXT16(x)       ((((x)&0xffff)^(~0x7fff))+0x8000)
 410
 411 /* sign-extend a 32-bit number */
 412 #define SEXT32(x)       ((((x)&SIGNED64(0xffffffff))^(~SIGNED64(0x7fffffff)))+SIGNED64(0x80000000))
 413
 414 /* sign extend a 40 bit number */
 415 #define SEXT40(x)       ((((x)&SIGNED64(0xffffffffff))^(~SIGNED64(0x7fffffffff)))+SIGNED64(0x8000000000))
 416
 417 /* sign extend a 44 bit number */
 418 #define SEXT44(x)       ((((x)&SIGNED64(0xfffffffffff))^(~SIGNED64(0x7ffffffffff)))+SIGNED64(0x80000000000))
 419
 420 /* sign extend a 56 bit number */
 421 #define SEXT56(x)       ((((x)&SIGNED64(0xffffffffffffff))^(~SIGNED64(0x7fffffffffffff)))+SIGNED64(0x80000000000000))
 422
 423 /* sign extend a 60 bit number */
 424 #define SEXT60(x)       ((((x)&SIGNED64(0xfffffffffffffff))^(~SIGNED64(0x7ffffffffffffff)))+SIGNED64(0x800000000000000))
 425
 426 #define MAX32   SIGNED64(0x7fffffff)
 427 #define MIN32   SIGNED64(0xff80000000)
 428 #define MASK32  SIGNED64(0xffffffff)
 429 #define MASK40  SIGNED64(0xffffffffff)
 430
 431 /* The alignment of MOD_E in the following macro depends upon "i"
 432    always being a power of 2. */
 433 #define INC_ADDR(x,i) \
 434 do \
 435   { \
 436     int test_i = i < 0 ? i : ~((i) - 1); \
 437     if (PSW_MD && GPR (x) == (MOD_E & test_i)) \
 438       SET_GPR (x, MOD_S & test_i); \
 439     else \
 440       SET_GPR (x, GPR (x) + (i)); \
 441   } \
 442 while (0)
 443
 444 extern uint8 *dmem_addr (SIM_DESC, SIM_CPU *, uint16 offset);
 445 extern uint8 *imem_addr (SIM_DESC, SIM_CPU *, uint32);
 446
 447 #define RB(x)   (*(dmem_addr (sd, cpu, x)))
 448 #define SB(addr,data)   ( RB(addr) = (data & 0xff))
 449
 450 #if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE)
 451 #define ENDIAN_INLINE static __inline__
 452 #include "endian.c"
 453 #undef ENDIAN_INLINE
 454
 455 #else
 456 extern uint32 get_longword (uint8 *);
 457 extern uint16 get_word (uint8 *);
 458 extern int64 get_longlong (uint8 *);
 459 extern void write_word (uint8 *addr, uint16 data);
 460 extern void write_longword (uint8 *addr, uint32 data);
 461 extern void write_longlong (uint8 *addr, int64 data);
 462 #endif
 463
 464 #define SW(addr,data)           write_word (dmem_addr (sd, cpu, addr), data)
 465 #define RW(x)                   get_word (dmem_addr (sd, cpu, x))
 466 #define SLW(addr,data)          write_longword (dmem_addr (sd, cpu, addr), data)
 467 #define RLW(x)                  get_longword (dmem_addr (sd, cpu, x))
 468 #define READ_16(x)              get_word(x)
 469 #define WRITE_16(addr,data)     write_word(addr,data)
 470 #define READ_64(x)              get_longlong(x)
 471 #define WRITE_64(addr,data)     write_longlong(addr,data)
 472
 473 #define JMP(x)                  do { SET_PC (x); State.pc_changed = 1; } while (0)
 474
 475 #define RIE_VECTOR_START 0xffc2
 476 #define AE_VECTOR_START 0xffc3
 477 #define TRAP_VECTOR_START 0xffc4        /* vector for trap 0 */
 478 #define DBT_VECTOR_START 0xffd4
 479 #define SDBT_VECTOR_START 0xffd5
 480
 481 /* Scedule a store of VAL into cr[CR].  MASK indicates the bits in
 482    cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) |
 483    (VAL & ~MASK)).  In addition, unless PSW_HW_P, a VAL intended for
 484    PSW is masked for zero bits. */
 485
 486 extern reg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, reg_t mask, reg_t val, int psw_hw_p);