]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/d10v/interp.c
5 #include "gdb/callback.h"
6 #include "gdb/remote-sim.h"
9 #include "sim-options.h"
11 #include "gdb/sim-d10v.h"
12 #include "gdb/signals.h"
17 enum _leftright
{ LEFT_FIRST
, RIGHT_FIRST
};
23 /* Set this to true to get the previous segment layout. */
25 int old_segment_mapping
;
27 unsigned long ins_type_counters
[ (int)INS_MAX
];
31 static long hash (long insn
, int format
);
32 static struct hash_entry
*lookup_hash (SIM_DESC
, SIM_CPU
*, uint32 ins
, int size
);
33 static void get_operands (struct simops
*s
, uint32 ins
);
34 static void do_long (SIM_DESC
, SIM_CPU
*, uint32 ins
);
35 static void do_2_short (SIM_DESC
, SIM_CPU
*, uint16 ins1
, uint16 ins2
, enum _leftright leftright
);
36 static void do_parallel (SIM_DESC
, SIM_CPU
*, uint16 ins1
, uint16 ins2
);
37 static char *add_commas (char *buf
, int sizeof_buf
, unsigned long value
);
38 static INLINE uint8
*map_memory (SIM_DESC
, SIM_CPU
*, unsigned phys_addr
);
43 struct hash_entry
*next
;
50 struct hash_entry hash_table
[MAX_HASH
+1];
53 hash (long insn
, int format
)
55 if (format
& LONG_OPCODE
)
56 return ((insn
& 0x3F000000) >> 24);
58 return((insn
& 0x7E00) >> 9);
61 INLINE
static struct hash_entry
*
62 lookup_hash (SIM_DESC sd
, SIM_CPU
*cpu
, uint32 ins
, int size
)
67 h
= &hash_table
[(ins
& 0x3F000000) >> 24];
69 h
= &hash_table
[(ins
& 0x7E00) >> 9];
71 while ((ins
& h
->mask
) != h
->opcode
|| h
->size
!= size
)
74 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGILL
);
81 get_operands (struct simops
*s
, uint32 ins
)
83 int i
, shift
, bits
, flags
;
85 for (i
=0; i
< s
->numops
; i
++)
87 shift
= s
->operands
[3*i
];
88 bits
= s
->operands
[3*i
+1];
89 flags
= s
->operands
[3*i
+2];
90 mask
= 0x7FFFFFFF >> (31 - bits
);
91 OP
[i
] = (ins
>> shift
) & mask
;
93 /* FIXME: for tracing, update values that need to be updated each
94 instruction decode cycle */
95 State
.trace
.psw
= PSW
;
99 do_long (SIM_DESC sd
, SIM_CPU
*cpu
, uint32 ins
)
101 struct hash_entry
*h
;
103 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
104 sim_io_printf (sd
, "do_long 0x%x\n", ins
);
106 h
= lookup_hash (sd
, cpu
, ins
, 1);
109 get_operands (h
->ops
, ins
);
110 State
.ins_type
= INS_LONG
;
111 ins_type_counters
[ (int)State
.ins_type
]++;
112 (h
->ops
->func
) (sd
, cpu
);
116 do_2_short (SIM_DESC sd
, SIM_CPU
*cpu
, uint16 ins1
, uint16 ins2
, enum _leftright leftright
)
118 struct hash_entry
*h
;
119 enum _ins_type first
, second
;
122 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
123 sim_io_printf (sd
, "do_2_short 0x%x (%s) -> 0x%x\n", ins1
,
124 leftright
? "left" : "right", ins2
);
127 if (leftright
== LEFT_FIRST
)
131 ins_type_counters
[ (int)INS_LEFTRIGHT
]++;
137 ins_type_counters
[ (int)INS_RIGHTLEFT
]++;
140 /* Issue the first instruction */
141 h
= lookup_hash (sd
, cpu
, ins1
, 0);
144 get_operands (h
->ops
, ins1
);
145 State
.ins_type
= first
;
146 ins_type_counters
[ (int)State
.ins_type
]++;
147 (h
->ops
->func
) (sd
, cpu
);
149 /* Issue the second instruction (if the PC hasn't changed) */
150 if (!State
.pc_changed
)
152 /* finish any existing instructions */
154 h
= lookup_hash (sd
, cpu
, ins2
, 0);
157 get_operands (h
->ops
, ins2
);
158 State
.ins_type
= second
;
159 ins_type_counters
[ (int)State
.ins_type
]++;
160 ins_type_counters
[ (int)INS_CYCLES
]++;
161 (h
->ops
->func
) (sd
, cpu
);
164 ins_type_counters
[ (int)INS_COND_JUMP
]++;
168 do_parallel (SIM_DESC sd
, SIM_CPU
*cpu
, uint16 ins1
, uint16 ins2
)
170 struct hash_entry
*h1
, *h2
;
172 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
173 sim_io_printf (sd
, "do_parallel 0x%x || 0x%x\n", ins1
, ins2
);
175 ins_type_counters
[ (int)INS_PARALLEL
]++;
176 h1
= lookup_hash (sd
, cpu
, ins1
, 0);
179 h2
= lookup_hash (sd
, cpu
, ins2
, 0);
183 if (h1
->ops
->exec_type
== PARONLY
)
185 get_operands (h1
->ops
, ins1
);
186 State
.ins_type
= INS_LEFT_COND_TEST
;
187 ins_type_counters
[ (int)State
.ins_type
]++;
188 (h1
->ops
->func
) (sd
, cpu
);
191 ins_type_counters
[ (int)INS_COND_TRUE
]++;
192 get_operands (h2
->ops
, ins2
);
193 State
.ins_type
= INS_RIGHT_COND_EXE
;
194 ins_type_counters
[ (int)State
.ins_type
]++;
195 (h2
->ops
->func
) (sd
, cpu
);
198 ins_type_counters
[ (int)INS_COND_FALSE
]++;
200 else if (h2
->ops
->exec_type
== PARONLY
)
202 get_operands (h2
->ops
, ins2
);
203 State
.ins_type
= INS_RIGHT_COND_TEST
;
204 ins_type_counters
[ (int)State
.ins_type
]++;
205 (h2
->ops
->func
) (sd
, cpu
);
208 ins_type_counters
[ (int)INS_COND_TRUE
]++;
209 get_operands (h1
->ops
, ins1
);
210 State
.ins_type
= INS_LEFT_COND_EXE
;
211 ins_type_counters
[ (int)State
.ins_type
]++;
212 (h1
->ops
->func
) (sd
, cpu
);
215 ins_type_counters
[ (int)INS_COND_FALSE
]++;
219 get_operands (h1
->ops
, ins1
);
220 State
.ins_type
= INS_LEFT_PARALLEL
;
221 ins_type_counters
[ (int)State
.ins_type
]++;
222 (h1
->ops
->func
) (sd
, cpu
);
223 get_operands (h2
->ops
, ins2
);
224 State
.ins_type
= INS_RIGHT_PARALLEL
;
225 ins_type_counters
[ (int)State
.ins_type
]++;
226 (h2
->ops
->func
) (sd
, cpu
);
231 add_commas (char *buf
, int sizeof_buf
, unsigned long value
)
234 char *endbuf
= buf
+ sizeof_buf
- 1;
244 *--endbuf
= (value
% 10) + '0';
245 } while ((value
/= 10) != 0);
254 for (i
= 0; i
< IMEM_SEGMENTS
; i
++)
256 if (State
.mem
.insn
[i
])
257 free (State
.mem
.insn
[i
]);
259 for (i
= 0; i
< DMEM_SEGMENTS
; i
++)
261 if (State
.mem
.data
[i
])
262 free (State
.mem
.data
[i
]);
264 for (i
= 0; i
< UMEM_SEGMENTS
; i
++)
266 if (State
.mem
.unif
[i
])
267 free (State
.mem
.unif
[i
]);
269 /* Always allocate dmem segment 0. This contains the IMAP and DMAP
271 State
.mem
.data
[0] = calloc (1, SEGMENT_SIZE
);
274 /* For tracing - leave info on last access around. */
275 static char *last_segname
= "invalid";
276 static char *last_from
= "invalid";
277 static char *last_to
= "invalid";
281 IMAP0_OFFSET
= 0xff00,
282 DMAP0_OFFSET
= 0xff08,
283 DMAP2_SHADDOW
= 0xff04,
284 DMAP2_OFFSET
= 0xff0c
288 set_dmap_register (SIM_DESC sd
, int reg_nr
, unsigned long value
)
290 uint8
*raw
= map_memory (sd
, NULL
, SIM_D10V_MEMORY_DATA
291 + DMAP0_OFFSET
+ 2 * reg_nr
);
292 WRITE_16 (raw
, value
);
294 if ((d10v_debug
& DEBUG_MEMORY
))
296 sim_io_printf (sd
, "mem: dmap%d=0x%04lx\n", reg_nr
, value
);
302 dmap_register (SIM_DESC sd
, SIM_CPU
*cpu
, void *regcache
, int reg_nr
)
304 uint8
*raw
= map_memory (sd
, cpu
, SIM_D10V_MEMORY_DATA
305 + DMAP0_OFFSET
+ 2 * reg_nr
);
306 return READ_16 (raw
);
310 set_imap_register (SIM_DESC sd
, int reg_nr
, unsigned long value
)
312 uint8
*raw
= map_memory (sd
, NULL
, SIM_D10V_MEMORY_DATA
313 + IMAP0_OFFSET
+ 2 * reg_nr
);
314 WRITE_16 (raw
, value
);
316 if ((d10v_debug
& DEBUG_MEMORY
))
318 sim_io_printf (sd
, "mem: imap%d=0x%04lx\n", reg_nr
, value
);
324 imap_register (SIM_DESC sd
, SIM_CPU
*cpu
, void *regcache
, int reg_nr
)
326 uint8
*raw
= map_memory (sd
, cpu
, SIM_D10V_MEMORY_DATA
327 + IMAP0_OFFSET
+ 2 * reg_nr
);
328 return READ_16 (raw
);
343 return HELD_SP (HELD_SPU_IDX
);
352 return HELD_SP (HELD_SPI_IDX
);
356 set_spi_register (unsigned long value
)
359 SET_GPR (SP_IDX
, value
);
360 SET_HELD_SP (HELD_SPI_IDX
, value
);
364 set_spu_register (unsigned long value
)
367 SET_GPR (SP_IDX
, value
);
368 SET_HELD_SP (HELD_SPU_IDX
, value
);
371 /* Given a virtual address in the DMAP address space, translate it
372 into a physical address. */
375 sim_d10v_translate_dmap_addr (SIM_DESC sd
,
377 unsigned long offset
,
381 unsigned long (*dmap_register
) (SIM_DESC
,
388 last_from
= "logical-data";
389 if (offset
>= DMAP_BLOCK_SIZE
* SIM_D10V_NR_DMAP_REGS
)
391 /* Logical address out side of data segments, not supported */
394 regno
= (offset
/ DMAP_BLOCK_SIZE
);
395 offset
= (offset
% DMAP_BLOCK_SIZE
);
396 if ((offset
% DMAP_BLOCK_SIZE
) + nr_bytes
> DMAP_BLOCK_SIZE
)
398 /* Don't cross a BLOCK boundary */
399 nr_bytes
= DMAP_BLOCK_SIZE
- (offset
% DMAP_BLOCK_SIZE
);
401 map
= dmap_register (sd
, cpu
, regcache
, regno
);
404 /* Always maps to data memory */
405 int iospi
= (offset
/ 0x1000) % 4;
406 int iosp
= (map
>> (4 * (3 - iospi
))) % 0x10;
407 last_to
= "io-space";
408 *phys
= (SIM_D10V_MEMORY_DATA
+ (iosp
* 0x10000) + 0xc000 + offset
);
412 int sp
= ((map
& 0x3000) >> 12);
413 int segno
= (map
& 0x3ff);
416 case 0: /* 00: Unified memory */
417 *phys
= SIM_D10V_MEMORY_UNIFIED
+ (segno
* DMAP_BLOCK_SIZE
) + offset
;
420 case 1: /* 01: Instruction Memory */
421 *phys
= SIM_D10V_MEMORY_INSN
+ (segno
* DMAP_BLOCK_SIZE
) + offset
;
422 last_to
= "chip-insn";
424 case 2: /* 10: Internal data memory */
425 *phys
= SIM_D10V_MEMORY_DATA
+ (segno
<< 16) + (regno
* DMAP_BLOCK_SIZE
) + offset
;
426 last_to
= "chip-data";
428 case 3: /* 11: Reserved */
435 /* Given a virtual address in the IMAP address space, translate it
436 into a physical address. */
439 sim_d10v_translate_imap_addr (SIM_DESC sd
,
441 unsigned long offset
,
445 unsigned long (*imap_register
) (SIM_DESC
,
454 last_from
= "logical-insn";
455 if (offset
>= (IMAP_BLOCK_SIZE
* SIM_D10V_NR_IMAP_REGS
))
457 /* Logical address outside of IMAP segments, not supported */
460 regno
= (offset
/ IMAP_BLOCK_SIZE
);
461 offset
= (offset
% IMAP_BLOCK_SIZE
);
462 if (offset
+ nr_bytes
> IMAP_BLOCK_SIZE
)
464 /* Don't cross a BLOCK boundary */
465 nr_bytes
= IMAP_BLOCK_SIZE
- offset
;
467 map
= imap_register (sd
, cpu
, regcache
, regno
);
468 sp
= (map
& 0x3000) >> 12;
469 segno
= (map
& 0x007f);
472 case 0: /* 00: unified memory */
473 *phys
= SIM_D10V_MEMORY_UNIFIED
+ (segno
<< 17) + offset
;
476 case 1: /* 01: instruction memory */
477 *phys
= SIM_D10V_MEMORY_INSN
+ (IMAP_BLOCK_SIZE
* regno
) + offset
;
478 last_to
= "chip-insn";
483 case 3: /* 11: for testing - instruction memory */
484 offset
= (offset
% 0x800);
485 *phys
= SIM_D10V_MEMORY_INSN
+ offset
;
486 if (offset
+ nr_bytes
> 0x800)
487 /* don't cross VM boundary */
488 nr_bytes
= 0x800 - offset
;
489 last_to
= "test-insn";
496 sim_d10v_translate_addr (SIM_DESC sd
,
498 unsigned long memaddr
,
500 unsigned long *targ_addr
,
502 unsigned long (*dmap_register
) (SIM_DESC
,
506 unsigned long (*imap_register
) (SIM_DESC
,
515 last_from
= "unknown";
518 seg
= (memaddr
>> 24);
519 off
= (memaddr
& 0xffffffL
);
521 /* However, if we've asked to use the previous generation of segment
522 mapping, rearrange the segments as follows. */
524 if (old_segment_mapping
)
528 case 0x00: /* DMAP translated memory */
531 case 0x01: /* IMAP translated memory */
534 case 0x10: /* On-chip data memory */
537 case 0x11: /* On-chip insn memory */
540 case 0x12: /* Unified memory */
548 case 0x00: /* Physical unified memory */
549 last_from
= "phys-unified";
551 phys
= SIM_D10V_MEMORY_UNIFIED
+ off
;
552 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
553 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
556 case 0x01: /* Physical instruction memory */
557 last_from
= "phys-insn";
558 last_to
= "chip-insn";
559 phys
= SIM_D10V_MEMORY_INSN
+ off
;
560 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
561 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
564 case 0x02: /* Physical data memory segment */
565 last_from
= "phys-data";
566 last_to
= "chip-data";
567 phys
= SIM_D10V_MEMORY_DATA
+ off
;
568 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
569 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
572 case 0x10: /* in logical data address segment */
573 nr_bytes
= sim_d10v_translate_dmap_addr (sd
, cpu
, off
, nr_bytes
, &phys
,
574 regcache
, dmap_register
);
577 case 0x11: /* in logical instruction address segment */
578 nr_bytes
= sim_d10v_translate_imap_addr (sd
, cpu
, off
, nr_bytes
, &phys
,
579 regcache
, imap_register
);
590 /* Return a pointer into the raw buffer designated by phys_addr. It
591 is assumed that the client has already ensured that the access
592 isn't going to cross a segment boundary. */
595 map_memory (SIM_DESC sd
, SIM_CPU
*cpu
, unsigned phys_addr
)
600 int segment
= ((phys_addr
>> 24) & 0xff);
605 case 0x00: /* Unified memory */
607 memory
= &State
.mem
.unif
[(phys_addr
/ SEGMENT_SIZE
) % UMEM_SEGMENTS
];
608 last_segname
= "umem";
612 case 0x01: /* On-chip insn memory */
614 memory
= &State
.mem
.insn
[(phys_addr
/ SEGMENT_SIZE
) % IMEM_SEGMENTS
];
615 last_segname
= "imem";
619 case 0x02: /* On-chip data memory */
621 if ((phys_addr
& 0xff00) == 0xff00)
623 phys_addr
= (phys_addr
& 0xffff);
624 if (phys_addr
== DMAP2_SHADDOW
)
626 phys_addr
= DMAP2_OFFSET
;
627 last_segname
= "dmap";
630 last_segname
= "reg";
633 last_segname
= "dmem";
634 memory
= &State
.mem
.data
[(phys_addr
/ SEGMENT_SIZE
) % DMEM_SEGMENTS
];
640 last_segname
= "scrap";
641 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGBUS
);
645 *memory
= xcalloc (1, SEGMENT_SIZE
);
647 offset
= (phys_addr
% SEGMENT_SIZE
);
648 raw
= *memory
+ offset
;
652 /* Transfer data to/from simulated memory. Since a bug in either the
653 simulated program or in gdb or the simulator itself may cause a
654 bogus address to be passed in, we need to do some sanity checking
655 on addresses to make sure they are within bounds. When an address
656 fails the bounds check, treat it as a zero length read/write rather
657 than aborting the entire run. */
660 xfer_mem (SIM_DESC sd
,
662 unsigned char *buffer
,
669 phys_size
= sim_d10v_translate_addr (sd
, NULL
, virt
, size
, &phys
, NULL
,
670 dmap_register
, imap_register
);
674 memory
= map_memory (sd
, NULL
, phys
);
677 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
681 "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n",
682 write_p
? "write" : "read",
683 phys_size
, virt
, last_from
,
685 (long) memory
, last_segname
);
691 memcpy (memory
, buffer
, phys_size
);
695 memcpy (buffer
, memory
, phys_size
);
703 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
705 /* FIXME: this should be performing a virtual transfer */
706 return xfer_mem (sd
, addr
, buffer
, size
, 1);
710 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
712 /* FIXME: this should be performing a virtual transfer */
713 return xfer_mem (sd
, addr
, buffer
, size
, 0);
717 d10v_pc_get (sim_cpu
*cpu
)
723 d10v_pc_set (sim_cpu
*cpu
, sim_cia pc
)
725 SIM_DESC sd
= CPU_STATE (cpu
);
730 free_state (SIM_DESC sd
)
732 if (STATE_MODULES (sd
) != NULL
)
733 sim_module_uninstall (sd
);
734 sim_cpu_free_all (sd
);
738 static int d10v_reg_fetch (SIM_CPU
*, int, unsigned char *, int);
739 static int d10v_reg_store (SIM_CPU
*, int, unsigned char *, int);
742 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
,
743 struct bfd
*abfd
, char * const *argv
)
746 struct hash_entry
*h
;
747 static int init_p
= 0;
750 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
751 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
753 /* The cpu data is kept in a separately allocated chunk of memory. */
754 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
760 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
766 /* The parser will print an error message for us, so we silently return. */
767 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
773 /* Check for/establish the a reference program image. */
774 if (sim_analyze_program (sd
,
775 (STATE_PROG_ARGV (sd
) != NULL
776 ? *STATE_PROG_ARGV (sd
)
777 : NULL
), abfd
) != SIM_RC_OK
)
783 /* Configure/verify the target byte order and other runtime
784 configuration options. */
785 if (sim_config (sd
) != SIM_RC_OK
)
787 sim_module_uninstall (sd
);
791 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
793 /* Uninstall the modules to avoid memory leaks,
794 file descriptor leaks, etc. */
795 sim_module_uninstall (sd
);
799 /* CPU specific initialization. */
800 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
802 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
804 CPU_REG_FETCH (cpu
) = d10v_reg_fetch
;
805 CPU_REG_STORE (cpu
) = d10v_reg_store
;
806 CPU_PC_FETCH (cpu
) = d10v_pc_get
;
807 CPU_PC_STORE (cpu
) = d10v_pc_set
;
810 old_segment_mapping
= 0;
812 /* NOTE: This argument parsing is only effective when this function
813 is called by GDB. Standalone argument parsing is handled by
815 for (p
= argv
+ 1; *p
; ++p
)
817 if (strcmp (*p
, "-oldseg") == 0)
818 old_segment_mapping
= 1;
820 else if (strcmp (*p
, "-t") == 0)
822 else if (strncmp (*p
, "-t", 2) == 0)
823 d10v_debug
= atoi (*p
+ 2);
827 /* put all the opcodes in the hash table */
830 for (s
= Simops
; s
->func
; s
++)
832 h
= &hash_table
[hash(s
->opcode
,s
->format
)];
834 /* go to the last entry in the chain */
840 h
->next
= (struct hash_entry
*) calloc(1,sizeof(struct hash_entry
));
842 perror ("malloc failure");
848 h
->opcode
= s
->opcode
;
849 h
->size
= s
->is_long
;
853 /* reset the processor state */
854 if (!State
.mem
.data
[0])
861 dmem_addr (SIM_DESC sd
, SIM_CPU
*cpu
, uint16 offset
)
867 /* Note: DMEM address range is 0..0x10000. Calling code can compute
868 things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
869 is uint16 this is modulo'ed onto 0x0e5d. */
871 phys_size
= sim_d10v_translate_dmap_addr (sd
, cpu
, offset
, 1, &phys
, NULL
,
874 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGBUS
);
875 mem
= map_memory (sd
, cpu
, phys
);
877 if ((d10v_debug
& DEBUG_MEMORY
))
881 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
883 phys
, phys_size
, last_to
,
884 (long) mem
, last_segname
);
891 imem_addr (SIM_DESC sd
, SIM_CPU
*cpu
, uint32 offset
)
895 int phys_size
= sim_d10v_translate_imap_addr (sd
, cpu
, offset
, 1, &phys
, NULL
,
898 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGBUS
);
899 mem
= map_memory (sd
, cpu
, phys
);
901 if ((d10v_debug
& DEBUG_MEMORY
))
905 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
907 phys
, phys_size
, last_to
,
908 (long) mem
, last_segname
);
915 step_once (SIM_DESC sd
, SIM_CPU
*cpu
)
920 /* TODO: Unindent this block. */
922 iaddr
= imem_addr (sd
, cpu
, (uint32
)PC
<< 2);
924 inst
= get_longword( iaddr
);
926 State
.pc_changed
= 0;
927 ins_type_counters
[ (int)INS_CYCLES
]++;
929 switch (inst
& 0xC0000000)
932 /* long instruction */
933 do_long (sd
, cpu
, inst
& 0x3FFFFFFF);
937 do_2_short (sd
, cpu
, inst
& 0x7FFF, (inst
& 0x3FFF8000) >> 15, RIGHT_FIRST
);
941 do_2_short (sd
, cpu
, (inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF, LEFT_FIRST
);
944 do_parallel (sd
, cpu
, (inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF);
948 /* If the PC of the current instruction matches RPT_E then
949 schedule a branch to the loop start. If one of those
950 instructions happens to be a branch, than that instruction
952 if (!State
.pc_changed
)
954 if (PSW_RP
&& PC
== RPT_E
)
956 /* Note: The behavour of a branch instruction at RPT_E
957 is implementation dependant, this simulator takes the
958 branch. Branching to RPT_E is valid, the instruction
959 must be executed before the loop is taken. */
968 SET_RPT_C (RPT_C
- 1);
976 /* Check for a breakpoint trap on this instruction. This
977 overrides any pending branches or loops */
978 if (PSW_DB
&& PC
== IBA
)
982 SET_PSW (PSW
& PSW_SM_BIT
);
983 SET_PC (SDBT_VECTOR_START
);
986 /* Writeback all the DATA / PC changes */
992 sim_engine_run (SIM_DESC sd
,
993 int next_cpu_nr
, /* ignore */
994 int nr_cpus
, /* ignore */
999 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
1001 cpu
= STATE_CPU (sd
, 0);
1007 case GDB_SIGNAL_BUS
:
1010 SET_HW_PSW ((PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
1011 JMP (AE_VECTOR_START
);
1014 case GDB_SIGNAL_ILL
:
1017 SET_HW_PSW ((PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
1018 JMP (RIE_VECTOR_START
);
1022 /* just ignore it */
1028 step_once (sd
, cpu
);
1029 if (sim_events_tick (sd
))
1030 sim_events_process (sd
);
1035 sim_info (SIM_DESC sd
, int verbose
)
1042 unsigned long left
= ins_type_counters
[ (int)INS_LEFT
] + ins_type_counters
[ (int)INS_LEFT_COND_EXE
];
1043 unsigned long left_nops
= ins_type_counters
[ (int)INS_LEFT_NOPS
];
1044 unsigned long left_parallel
= ins_type_counters
[ (int)INS_LEFT_PARALLEL
];
1045 unsigned long left_cond
= ins_type_counters
[ (int)INS_LEFT_COND_TEST
];
1046 unsigned long left_total
= left
+ left_parallel
+ left_cond
+ left_nops
;
1048 unsigned long right
= ins_type_counters
[ (int)INS_RIGHT
] + ins_type_counters
[ (int)INS_RIGHT_COND_EXE
];
1049 unsigned long right_nops
= ins_type_counters
[ (int)INS_RIGHT_NOPS
];
1050 unsigned long right_parallel
= ins_type_counters
[ (int)INS_RIGHT_PARALLEL
];
1051 unsigned long right_cond
= ins_type_counters
[ (int)INS_RIGHT_COND_TEST
];
1052 unsigned long right_total
= right
+ right_parallel
+ right_cond
+ right_nops
;
1054 unsigned long unknown
= ins_type_counters
[ (int)INS_UNKNOWN
];
1055 unsigned long ins_long
= ins_type_counters
[ (int)INS_LONG
];
1056 unsigned long parallel
= ins_type_counters
[ (int)INS_PARALLEL
];
1057 unsigned long leftright
= ins_type_counters
[ (int)INS_LEFTRIGHT
];
1058 unsigned long rightleft
= ins_type_counters
[ (int)INS_RIGHTLEFT
];
1059 unsigned long cond_true
= ins_type_counters
[ (int)INS_COND_TRUE
];
1060 unsigned long cond_false
= ins_type_counters
[ (int)INS_COND_FALSE
];
1061 unsigned long cond_jump
= ins_type_counters
[ (int)INS_COND_JUMP
];
1062 unsigned long cycles
= ins_type_counters
[ (int)INS_CYCLES
];
1063 unsigned long total
= (unknown
+ left_total
+ right_total
+ ins_long
);
1065 int size
= strlen (add_commas (buf1
, sizeof (buf1
), total
));
1066 int parallel_size
= strlen (add_commas (buf1
, sizeof (buf1
),
1067 (left_parallel
> right_parallel
) ? left_parallel
: right_parallel
));
1068 int cond_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_cond
> right_cond
) ? left_cond
: right_cond
));
1069 int nop_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_nops
> right_nops
) ? left_nops
: right_nops
));
1070 int normal_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left
> right
) ? left
: right
));
1073 "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1074 size
, add_commas (buf1
, sizeof (buf1
), left_total
),
1075 normal_size
, add_commas (buf2
, sizeof (buf2
), left
),
1076 parallel_size
, add_commas (buf3
, sizeof (buf3
), left_parallel
),
1077 cond_size
, add_commas (buf4
, sizeof (buf4
), left_cond
),
1078 nop_size
, add_commas (buf5
, sizeof (buf5
), left_nops
));
1081 "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1082 size
, add_commas (buf1
, sizeof (buf1
), right_total
),
1083 normal_size
, add_commas (buf2
, sizeof (buf2
), right
),
1084 parallel_size
, add_commas (buf3
, sizeof (buf3
), right_parallel
),
1085 cond_size
, add_commas (buf4
, sizeof (buf4
), right_cond
),
1086 nop_size
, add_commas (buf5
, sizeof (buf5
), right_nops
));
1090 "executed %*s long instruction(s)\n",
1091 size
, add_commas (buf1
, sizeof (buf1
), ins_long
));
1095 "executed %*s parallel instruction(s)\n",
1096 size
, add_commas (buf1
, sizeof (buf1
), parallel
));
1100 "executed %*s instruction(s) encoded L->R\n",
1101 size
, add_commas (buf1
, sizeof (buf1
), leftright
));
1105 "executed %*s instruction(s) encoded R->L\n",
1106 size
, add_commas (buf1
, sizeof (buf1
), rightleft
));
1110 "executed %*s unknown instruction(s)\n",
1111 size
, add_commas (buf1
, sizeof (buf1
), unknown
));
1115 "executed %*s instruction(s) due to EXExxx condition being true\n",
1116 size
, add_commas (buf1
, sizeof (buf1
), cond_true
));
1120 "skipped %*s instruction(s) due to EXExxx condition being false\n",
1121 size
, add_commas (buf1
, sizeof (buf1
), cond_false
));
1125 "skipped %*s instruction(s) due to conditional branch succeeding\n",
1126 size
, add_commas (buf1
, sizeof (buf1
), cond_jump
));
1129 "executed %*s cycle(s)\n",
1130 size
, add_commas (buf1
, sizeof (buf1
), cycles
));
1133 "executed %*s total instructions\n",
1134 size
, add_commas (buf1
, sizeof (buf1
), total
));
1138 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
1139 char * const *argv
, char * const *env
)
1141 bfd_vma start_address
;
1143 /* reset all state information */
1144 memset (&State
.regs
, 0, (uintptr_t)&State
.mem
- (uintptr_t)&State
.regs
);
1146 /* There was a hack here to copy the values of argc and argv into r0
1147 and r1. The values were also saved into some high memory that
1148 won't be overwritten by the stack (0x7C00). The reason for doing
1149 this was to allow the 'run' program to accept arguments. Without
1150 the hack, this is not possible anymore. If the simulator is run
1151 from the debugger, arguments cannot be passed in, so this makes
1156 start_address
= bfd_get_start_address (abfd
);
1158 start_address
= 0xffc0 << 2;
1161 sim_io_printf (sd
, "sim_create_inferior: PC=0x%lx\n", (long) start_address
);
1164 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1165 SET_CREG (PC_CR
, start_address
>> 2);
1168 /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board
1169 initializes imap0 and imap1 to 0x1000 as part of its ROM
1171 if (old_segment_mapping
)
1173 /* External memory startup. This is the HARD reset state. */
1174 set_imap_register (sd
, 0, 0x0000);
1175 set_imap_register (sd
, 1, 0x007f);
1176 set_dmap_register (sd
, 0, 0x2000);
1177 set_dmap_register (sd
, 1, 0x2000);
1178 set_dmap_register (sd
, 2, 0x0000); /* Old DMAP */
1179 set_dmap_register (sd
, 3, 0x0000);
1183 /* Internal memory startup. This is the ROM intialized state. */
1184 set_imap_register (sd
, 0, 0x1000);
1185 set_imap_register (sd
, 1, 0x1000);
1186 set_dmap_register (sd
, 0, 0x2000);
1187 set_dmap_register (sd
, 1, 0x2000);
1188 set_dmap_register (sd
, 2, 0x2000); /* DMAP2 initial internal value is
1189 0x2000 on the new board. */
1190 set_dmap_register (sd
, 3, 0x0000);
1198 d10v_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1200 SIM_DESC sd
= CPU_STATE (cpu
);
1202 switch ((enum sim_d10v_regs
) rn
)
1204 case SIM_D10V_R0_REGNUM
:
1205 case SIM_D10V_R1_REGNUM
:
1206 case SIM_D10V_R2_REGNUM
:
1207 case SIM_D10V_R3_REGNUM
:
1208 case SIM_D10V_R4_REGNUM
:
1209 case SIM_D10V_R5_REGNUM
:
1210 case SIM_D10V_R6_REGNUM
:
1211 case SIM_D10V_R7_REGNUM
:
1212 case SIM_D10V_R8_REGNUM
:
1213 case SIM_D10V_R9_REGNUM
:
1214 case SIM_D10V_R10_REGNUM
:
1215 case SIM_D10V_R11_REGNUM
:
1216 case SIM_D10V_R12_REGNUM
:
1217 case SIM_D10V_R13_REGNUM
:
1218 case SIM_D10V_R14_REGNUM
:
1219 case SIM_D10V_R15_REGNUM
:
1220 WRITE_16 (memory
, GPR (rn
- SIM_D10V_R0_REGNUM
));
1223 case SIM_D10V_CR0_REGNUM
:
1224 case SIM_D10V_CR1_REGNUM
:
1225 case SIM_D10V_CR2_REGNUM
:
1226 case SIM_D10V_CR3_REGNUM
:
1227 case SIM_D10V_CR4_REGNUM
:
1228 case SIM_D10V_CR5_REGNUM
:
1229 case SIM_D10V_CR6_REGNUM
:
1230 case SIM_D10V_CR7_REGNUM
:
1231 case SIM_D10V_CR8_REGNUM
:
1232 case SIM_D10V_CR9_REGNUM
:
1233 case SIM_D10V_CR10_REGNUM
:
1234 case SIM_D10V_CR11_REGNUM
:
1235 case SIM_D10V_CR12_REGNUM
:
1236 case SIM_D10V_CR13_REGNUM
:
1237 case SIM_D10V_CR14_REGNUM
:
1238 case SIM_D10V_CR15_REGNUM
:
1239 WRITE_16 (memory
, CREG (rn
- SIM_D10V_CR0_REGNUM
));
1242 case SIM_D10V_A0_REGNUM
:
1243 case SIM_D10V_A1_REGNUM
:
1244 WRITE_64 (memory
, ACC (rn
- SIM_D10V_A0_REGNUM
));
1247 case SIM_D10V_SPI_REGNUM
:
1248 /* PSW_SM indicates that the current SP is the USER
1250 WRITE_16 (memory
, spi_register ());
1253 case SIM_D10V_SPU_REGNUM
:
1254 /* PSW_SM indicates that the current SP is the USER
1256 WRITE_16 (memory
, spu_register ());
1259 case SIM_D10V_IMAP0_REGNUM
:
1260 case SIM_D10V_IMAP1_REGNUM
:
1261 WRITE_16 (memory
, imap_register (sd
, cpu
, NULL
, rn
- SIM_D10V_IMAP0_REGNUM
));
1264 case SIM_D10V_DMAP0_REGNUM
:
1265 case SIM_D10V_DMAP1_REGNUM
:
1266 case SIM_D10V_DMAP2_REGNUM
:
1267 case SIM_D10V_DMAP3_REGNUM
:
1268 WRITE_16 (memory
, dmap_register (sd
, cpu
, NULL
, rn
- SIM_D10V_DMAP0_REGNUM
));
1271 case SIM_D10V_TS2_DMAP_REGNUM
:
1282 d10v_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1284 SIM_DESC sd
= CPU_STATE (cpu
);
1286 switch ((enum sim_d10v_regs
) rn
)
1288 case SIM_D10V_R0_REGNUM
:
1289 case SIM_D10V_R1_REGNUM
:
1290 case SIM_D10V_R2_REGNUM
:
1291 case SIM_D10V_R3_REGNUM
:
1292 case SIM_D10V_R4_REGNUM
:
1293 case SIM_D10V_R5_REGNUM
:
1294 case SIM_D10V_R6_REGNUM
:
1295 case SIM_D10V_R7_REGNUM
:
1296 case SIM_D10V_R8_REGNUM
:
1297 case SIM_D10V_R9_REGNUM
:
1298 case SIM_D10V_R10_REGNUM
:
1299 case SIM_D10V_R11_REGNUM
:
1300 case SIM_D10V_R12_REGNUM
:
1301 case SIM_D10V_R13_REGNUM
:
1302 case SIM_D10V_R14_REGNUM
:
1303 case SIM_D10V_R15_REGNUM
:
1304 SET_GPR (rn
- SIM_D10V_R0_REGNUM
, READ_16 (memory
));
1307 case SIM_D10V_CR0_REGNUM
:
1308 case SIM_D10V_CR1_REGNUM
:
1309 case SIM_D10V_CR2_REGNUM
:
1310 case SIM_D10V_CR3_REGNUM
:
1311 case SIM_D10V_CR4_REGNUM
:
1312 case SIM_D10V_CR5_REGNUM
:
1313 case SIM_D10V_CR6_REGNUM
:
1314 case SIM_D10V_CR7_REGNUM
:
1315 case SIM_D10V_CR8_REGNUM
:
1316 case SIM_D10V_CR9_REGNUM
:
1317 case SIM_D10V_CR10_REGNUM
:
1318 case SIM_D10V_CR11_REGNUM
:
1319 case SIM_D10V_CR12_REGNUM
:
1320 case SIM_D10V_CR13_REGNUM
:
1321 case SIM_D10V_CR14_REGNUM
:
1322 case SIM_D10V_CR15_REGNUM
:
1323 SET_CREG (rn
- SIM_D10V_CR0_REGNUM
, READ_16 (memory
));
1326 case SIM_D10V_A0_REGNUM
:
1327 case SIM_D10V_A1_REGNUM
:
1328 SET_ACC (rn
- SIM_D10V_A0_REGNUM
, READ_64 (memory
) & MASK40
);
1331 case SIM_D10V_SPI_REGNUM
:
1332 /* PSW_SM indicates that the current SP is the USER
1334 set_spi_register (READ_16 (memory
));
1337 case SIM_D10V_SPU_REGNUM
:
1338 set_spu_register (READ_16 (memory
));
1341 case SIM_D10V_IMAP0_REGNUM
:
1342 case SIM_D10V_IMAP1_REGNUM
:
1343 set_imap_register (sd
, rn
- SIM_D10V_IMAP0_REGNUM
, READ_16(memory
));
1346 case SIM_D10V_DMAP0_REGNUM
:
1347 case SIM_D10V_DMAP1_REGNUM
:
1348 case SIM_D10V_DMAP2_REGNUM
:
1349 case SIM_D10V_DMAP3_REGNUM
:
1350 set_dmap_register (sd
, rn
- SIM_D10V_DMAP0_REGNUM
, READ_16(memory
));
1353 case SIM_D10V_TS2_DMAP_REGNUM
: