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[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
1 #include <signal.h>
2 #include <errno.h>
3 #include <sys/types.h>
4 #include <sys/stat.h>
5 #include <unistd.h>
6
7 #include "d10v_sim.h"
8 #include "simops.h"
9 #include "sys/syscall.h"
10
11 enum op_types {
12 OP_VOID,
13 OP_REG,
14 OP_REG_OUTPUT,
15 OP_DREG,
16 OP_DREG_OUTPUT,
17 OP_ACCUM,
18 OP_ACCUM_OUTPUT,
19 OP_ACCUM_REVERSE,
20 OP_CR,
21 OP_CR_OUTPUT,
22 OP_CR_REVERSE,
23 OP_FLAG,
24 OP_FLAG_OUTPUT,
25 OP_CONSTANT16,
26 OP_CONSTANT3,
27 OP_CONSTANT4,
28 OP_MEMREF,
29 OP_MEMREF2,
30 OP_POSTDEC,
31 OP_POSTINC,
32 OP_PREDEC
33 };
34
35 #ifdef DEBUG
36 static void trace_input PARAMS ((char *name,
37 enum op_types in1,
38 enum op_types in2,
39 enum op_types in3));
40
41 static void trace_output PARAMS ((enum op_types result));
42
43 #ifndef SIZE_INSTRUCTION
44 #define SIZE_INSTRUCTION 10
45 #endif
46
47 #ifndef SIZE_OPERANDS
48 #define SIZE_OPERANDS 24
49 #endif
50
51 #ifndef SIZE_VALUES
52 #define SIZE_VALUES 13
53 #endif
54
55 static void
56 trace_input (name, in1, in2, in3)
57 char *name;
58 enum op_types in1;
59 enum op_types in2;
60 enum op_types in3;
61 {
62 char *comma;
63 enum op_types in[3];
64 int i;
65 char buf[80];
66 char *p;
67 long tmp;
68 char *type;
69
70 if ((d10v_debug & DEBUG_TRACE) == 0)
71 return;
72
73 switch (State.ins_type)
74 {
75 default:
76 case INS_UNKNOWN: type = " ?"; break;
77 case INS_LEFT: type = " L"; break;
78 case INS_RIGHT: type = " R"; break;
79 case INS_LEFT_PARALLEL: type = "*L"; break;
80 case INS_RIGHT_PARALLEL: type = "*R"; break;
81 case INS_LONG: type = " B"; break;
82 }
83
84 (*d10v_callback->printf_filtered) (d10v_callback,
85 "0x%.6x %s: %-*s",
86 (unsigned)PC, type,
87 SIZE_INSTRUCTION, name);
88
89 in[0] = in1;
90 in[1] = in2;
91 in[2] = in3;
92 comma = "";
93 p = buf;
94 for (i = 0; i < 3; i++)
95 {
96 switch (in[i])
97 {
98 case OP_VOID:
99 break;
100
101 case OP_REG:
102 case OP_REG_OUTPUT:
103 case OP_DREG:
104 case OP_DREG_OUTPUT:
105 sprintf (p, "%sr%d", comma, OP[i]);
106 p += strlen (p);
107 comma = ",";
108 break;
109
110 case OP_CR:
111 case OP_CR_OUTPUT:
112 case OP_CR_REVERSE:
113 sprintf (p, "%scr%d", comma, OP[i]);
114 p += strlen (p);
115 comma = ",";
116 break;
117
118 case OP_ACCUM:
119 case OP_ACCUM_OUTPUT:
120 case OP_ACCUM_REVERSE:
121 sprintf (p, "%sa%d", comma, OP[i]);
122 p += strlen (p);
123 comma = ",";
124 break;
125
126 case OP_CONSTANT16:
127 sprintf (p, "%s%d", comma, OP[i]);
128 p += strlen (p);
129 comma = ",";
130 break;
131
132 case OP_CONSTANT4:
133 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
134 p += strlen (p);
135 comma = ",";
136 break;
137
138 case OP_CONSTANT3:
139 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
140 p += strlen (p);
141 comma = ",";
142 break;
143
144 case OP_MEMREF:
145 sprintf (p, "%s@r%d", comma, OP[i]);
146 p += strlen (p);
147 comma = ",";
148 break;
149
150 case OP_MEMREF2:
151 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
152 p += strlen (p);
153 comma = ",";
154 break;
155
156 case OP_POSTINC:
157 sprintf (p, "%s@r%d+", comma, OP[i]);
158 p += strlen (p);
159 comma = ",";
160 break;
161
162 case OP_POSTDEC:
163 sprintf (p, "%s@r%d-", comma, OP[i]);
164 p += strlen (p);
165 comma = ",";
166 break;
167
168 case OP_PREDEC:
169 sprintf (p, "%s@-r%d", comma, OP[i]);
170 p += strlen (p);
171 comma = ",";
172 break;
173
174 case OP_FLAG:
175 case OP_FLAG_OUTPUT:
176 if (OP[i] == 0)
177 sprintf (p, "%sf0", comma);
178
179 else if (OP[i] == 1)
180 sprintf (p, "%sf1", comma);
181
182 else
183 sprintf (p, "%sc", comma);
184
185 p += strlen (p);
186 comma = ",";
187 break;
188 }
189 }
190
191 if ((d10v_debug & DEBUG_VALUES) == 0)
192 {
193 *p++ = '\n';
194 *p = '\0';
195 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
196 }
197 else
198 {
199 *p = '\0';
200 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
201
202 p = buf;
203 for (i = 0; i < 3; i++)
204 {
205 buf[0] = '\0';
206 switch (in[i])
207 {
208 case OP_VOID:
209 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
210 break;
211
212 case OP_REG_OUTPUT:
213 case OP_DREG_OUTPUT:
214 case OP_CR_OUTPUT:
215 case OP_ACCUM_OUTPUT:
216 case OP_FLAG_OUTPUT:
217 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
218 break;
219
220 case OP_REG:
221 case OP_MEMREF:
222 case OP_POSTDEC:
223 case OP_POSTINC:
224 case OP_PREDEC:
225 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
226 (uint16)State.regs[OP[i]]);
227 break;
228
229 case OP_DREG:
230 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
231 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
232 break;
233
234 case OP_CR:
235 case OP_CR_REVERSE:
236 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
237 (uint16)State.cregs[OP[i]]);
238 break;
239
240 case OP_ACCUM:
241 case OP_ACCUM_REVERSE:
242 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
243 ((int)(State.a[OP[i]] >> 32) & 0xff),
244 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
245 break;
246
247 case OP_CONSTANT16:
248 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
249 (uint16)OP[i]);
250 break;
251
252 case OP_CONSTANT4:
253 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
254 (uint16)SEXT4(OP[i]));
255 break;
256
257 case OP_CONSTANT3:
258 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
259 (uint16)SEXT3(OP[i]));
260 break;
261
262 case OP_FLAG:
263 if (OP[i] == 0)
264 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
265 State.F0 != 0);
266
267 else if (OP[i] == 1)
268 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
269 State.F1 != 0);
270
271 else
272 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
273 State.C != 0);
274
275 break;
276
277 case OP_MEMREF2:
278 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
279 (uint16)OP[i]);
280 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
281 (uint16)State.regs[OP[++i]]);
282 break;
283 }
284 }
285 }
286 }
287
288 static void
289 trace_output (result)
290 enum op_types result;
291 {
292 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
293 {
294 long tmp;
295
296 switch (result)
297 {
298 default:
299 putchar ('\n');
300 break;
301
302 case OP_REG:
303 case OP_REG_OUTPUT:
304 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
305 (uint16)State.regs[OP[0]],
306 State.F0 != 0, State.F1 != 0, State.C != 0);
307 break;
308
309 case OP_DREG:
310 case OP_DREG_OUTPUT:
311 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
312 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
313 State.F0 != 0, State.F1 != 0, State.C != 0);
314 break;
315
316 case OP_CR:
317 case OP_CR_OUTPUT:
318 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
319 (uint16)State.cregs[OP[0]],
320 State.F0 != 0, State.F1 != 0, State.C != 0);
321 break;
322
323 case OP_CR_REVERSE:
324 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
325 (uint16)State.cregs[OP[1]],
326 State.F0 != 0, State.F1 != 0, State.C != 0);
327 break;
328
329 case OP_ACCUM:
330 case OP_ACCUM_OUTPUT:
331 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
332 ((int)(State.a[OP[0]] >> 32) & 0xff),
333 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
334 State.F0 != 0, State.F1 != 0, State.C != 0);
335 break;
336
337 case OP_ACCUM_REVERSE:
338 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
339 ((int)(State.a[OP[1]] >> 32) & 0xff),
340 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
341 State.F0 != 0, State.F1 != 0, State.C != 0);
342 break;
343
344 case OP_FLAG:
345 case OP_FLAG_OUTPUT:
346 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
347 State.F0 != 0, State.F1 != 0, State.C != 0);
348 break;
349 }
350 }
351 }
352
353 #else
354 #define trace_input(NAME, IN1, IN2, IN3)
355 #define trace_output(RESULT)
356 #endif
357
358 /* abs */
359 void
360 OP_4607 ()
361 {
362 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
363 State.F1 = State.F0;
364 if ((int16)(State.regs[OP[0]]) < 0)
365 {
366 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
367 State.F0 = 1;
368 }
369 else
370 State.F0 = 0;
371 trace_output (OP_REG);
372 }
373
374 /* abs */
375 void
376 OP_5607 ()
377 {
378 int64 tmp;
379
380 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
381 State.F1 = State.F0;
382 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
383
384 if (State.a[OP[0]] < 0 )
385 {
386 tmp = -State.a[OP[0]];
387 if (State.ST)
388 {
389 if (tmp > MAX32)
390 State.a[OP[0]] = MAX32;
391 else if (tmp < MIN32)
392 State.a[OP[0]] = MIN32;
393 else
394 State.a[OP[0]] = tmp & MASK40;
395 }
396 else
397 State.a[OP[0]] = tmp & MASK40;
398 State.F0 = 1;
399 }
400 else
401 State.F0 = 0;
402 trace_output (OP_ACCUM);
403 }
404
405 /* add */
406 void
407 OP_200 ()
408 {
409 uint16 tmp = State.regs[OP[0]];
410 trace_input ("add", OP_REG, OP_REG, OP_VOID);
411 State.regs[OP[0]] += State.regs[OP[1]];
412 if ( tmp > State.regs[OP[0]])
413 State.C = 1;
414 else
415 State.C = 0;
416 trace_output (OP_REG);
417 }
418
419 /* add */
420 void
421 OP_1201 ()
422 {
423 int64 tmp;
424 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
425
426 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
427 if (State.ST)
428 {
429 if ( tmp > MAX32)
430 State.a[OP[0]] = MAX32;
431 else if ( tmp < MIN32)
432 State.a[OP[0]] = MIN32;
433 else
434 State.a[OP[0]] = tmp & MASK40;
435 }
436 else
437 State.a[OP[0]] = tmp & MASK40;
438 trace_output (OP_ACCUM);
439 }
440
441 /* add */
442 void
443 OP_1203 ()
444 {
445 int64 tmp;
446 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
447
448 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
449 if (State.ST)
450 {
451 if (tmp > MAX32)
452 State.a[OP[0]] = MAX32;
453 else if ( tmp < MIN32)
454 State.a[OP[0]] = MIN32;
455 else
456 State.a[OP[0]] = tmp & MASK40;
457 }
458 else
459 State.a[OP[0]] = tmp & MASK40;
460 trace_output (OP_ACCUM);
461 }
462
463 /* add2w */
464 void
465 OP_1200 ()
466 {
467 uint32 tmp;
468 uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
469 uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
470
471 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
472 tmp = tmp1 + tmp2;
473 if ( (tmp < tmp1) || (tmp < tmp2) )
474 State.C = 1;
475 else
476 State.C = 0;
477 State.regs[OP[0]] = tmp >> 16;
478 State.regs[OP[0]+1] = tmp & 0xFFFF;
479 trace_output (OP_DREG);
480 }
481
482 /* add3 */
483 void
484 OP_1000000 ()
485 {
486 uint16 tmp = State.regs[OP[0]];
487 State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
488
489 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
490 if ( tmp > State.regs[OP[0]])
491 State.C = 1;
492 else
493 State.C = 0;
494 trace_output (OP_REG);
495 }
496
497 /* addac3 */
498 void
499 OP_17000200 ()
500 {
501 int64 tmp;
502 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
503
504 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
505 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
506 State.regs[OP[0]+1] = tmp & 0xffff;
507 trace_output (OP_DREG);
508 }
509
510 /* addac3 */
511 void
512 OP_17000202 ()
513 {
514 int64 tmp;
515 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
516
517 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
518 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
519 State.regs[OP[0]+1] = tmp & 0xffff;
520 trace_output (OP_DREG);
521 }
522
523 /* addac3s */
524 void
525 OP_17001200 ()
526 {
527 int64 tmp;
528 State.F1 = State.F0;
529
530 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
531 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
532 if ( tmp > MAX32)
533 {
534 State.regs[OP[0]] = 0x7fff;
535 State.regs[OP[0]+1] = 0xffff;
536 State.F0 = 1;
537 }
538 else if (tmp < MIN32)
539 {
540 State.regs[OP[0]] = 0x8000;
541 State.regs[OP[0]+1] = 0;
542 State.F0 = 1;
543 }
544 else
545 {
546 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
547 State.regs[OP[0]+1] = tmp & 0xffff;
548 State.F0 = 0;
549 }
550 trace_output (OP_DREG);
551 }
552
553 /* addac3s */
554 void
555 OP_17001202 ()
556 {
557 int64 tmp;
558 State.F1 = State.F0;
559
560 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
561 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
562 if ( tmp > MAX32)
563 {
564 State.regs[OP[0]] = 0x7fff;
565 State.regs[OP[0]+1] = 0xffff;
566 State.F0 = 1;
567 }
568 else if (tmp < MIN32)
569 {
570 State.regs[OP[0]] = 0x8000;
571 State.regs[OP[0]+1] = 0;
572 State.F0 = 1;
573 }
574 else
575 {
576 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
577 State.regs[OP[0]+1] = tmp & 0xffff;
578 State.F0 = 0;
579 }
580 trace_output (OP_DREG);
581 }
582
583 /* addi */
584 void
585 OP_201 ()
586 {
587 if (OP[1] == 0)
588 OP[1] = 16;
589 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
590 State.regs[OP[0]] += OP[1];
591 trace_output (OP_REG);
592 }
593
594 /* and */
595 void
596 OP_C00 ()
597 {
598 trace_input ("and", OP_REG, OP_REG, OP_VOID);
599 State.regs[OP[0]] &= State.regs[OP[1]];
600 trace_output (OP_REG);
601 }
602
603 /* and3 */
604 void
605 OP_6000000 ()
606 {
607 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
608 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
609 trace_output (OP_REG);
610 }
611
612 /* bclri */
613 void
614 OP_C01 ()
615 {
616 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
617 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
618 trace_output (OP_REG);
619 }
620
621 /* bl.s */
622 void
623 OP_4900 ()
624 {
625 trace_input ("bl.s", OP_CONSTANT16, OP_VOID, OP_VOID);
626 State.regs[13] = PC+1;
627 PC += SEXT8 (OP[0]);
628 trace_output (OP_VOID);
629 }
630
631 /* bl.l */
632 void
633 OP_24800000 ()
634 {
635 trace_input ("bl.l", OP_CONSTANT16, OP_VOID, OP_VOID);
636 State.regs[13] = PC+1;
637 PC += OP[0];
638 trace_output (OP_VOID);
639 }
640
641 /* bnoti */
642 void
643 OP_A01 ()
644 {
645 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
646 State.regs[OP[0]] ^= 0x8000 >> OP[1];
647 trace_output (OP_REG);
648 }
649
650 /* bra.s */
651 void
652 OP_4800 ()
653 {
654 trace_input ("bra.s", OP_CONSTANT16, OP_VOID, OP_VOID);
655 PC += SEXT8 (OP[0]);
656 trace_output (OP_VOID);
657 }
658
659 /* bra.l */
660 void
661 OP_24000000 ()
662 {
663 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
664 PC += OP[0];
665 trace_output (OP_VOID);
666 }
667
668 /* brf0f.s */
669 void
670 OP_4A00 ()
671 {
672 trace_input ("brf0f.s", OP_CONSTANT16, OP_VOID, OP_VOID);
673 if (State.F0 == 0)
674 PC += SEXT8 (OP[0]);
675 trace_output (OP_FLAG);
676 }
677
678 /* brf0f.l */
679 void
680 OP_25000000 ()
681 {
682 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
683 if (State.F0 == 0)
684 PC += OP[0];
685 trace_output (OP_FLAG);
686 }
687
688 /* brf0t.s */
689 void
690 OP_4B00 ()
691 {
692 trace_input ("brf0t.s", OP_CONSTANT16, OP_VOID, OP_VOID);
693 if (State.F0)
694 PC += SEXT8 (OP[0]);
695 trace_output (OP_FLAG);
696 }
697
698 /* brf0t.l */
699 void
700 OP_25800000 ()
701 {
702 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
703 if (State.F0)
704 PC += OP[0];
705 trace_output (OP_FLAG);
706 }
707
708 /* bseti */
709 void
710 OP_801 ()
711 {
712 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
713 State.regs[OP[0]] |= 0x8000 >> OP[1];
714 trace_output (OP_REG);
715 }
716
717 /* btsti */
718 void
719 OP_E01 ()
720 {
721 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
722 State.F1 = State.F0;
723 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
724 trace_output (OP_FLAG);
725 }
726
727 /* clrac */
728 void
729 OP_5601 ()
730 {
731 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
732 State.a[OP[0]] = 0;
733 trace_output (OP_ACCUM);
734 }
735
736 /* cmp */
737 void
738 OP_600 ()
739 {
740 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
741 State.F1 = State.F0;
742 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
743 trace_output (OP_FLAG);
744 }
745
746 /* cmp */
747 void
748 OP_1603 ()
749 {
750 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
751 State.F1 = State.F0;
752 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
753 trace_output (OP_FLAG);
754 }
755
756 /* cmpeq */
757 void
758 OP_400 ()
759 {
760 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
761 State.F1 = State.F0;
762 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
763 trace_output (OP_FLAG);
764 }
765
766 /* cmpeq */
767 void
768 OP_1403 ()
769 {
770 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
771 State.F1 = State.F0;
772 State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
773 trace_output (OP_FLAG);
774 }
775
776 /* cmpeqi.s */
777 void
778 OP_401 ()
779 {
780 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT16, OP_VOID);
781 State.F1 = State.F0;
782 State.F0 = (State.regs[OP[0]] == SEXT4(OP[1])) ? 1 : 0;
783 trace_output (OP_FLAG);
784 }
785
786 /* cmpeqi.l */
787 void
788 OP_2000000 ()
789 {
790 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
791 State.F1 = State.F0;
792 State.F0 = (State.regs[OP[0]] == OP[1]) ? 1 : 0;
793 trace_output (OP_FLAG);
794 }
795
796 /* cmpi.s */
797 void
798 OP_601 ()
799 {
800 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
801 State.F1 = State.F0;
802 State.F0 = ((int16)(State.regs[OP[0]]) < SEXT4(OP[1])) ? 1 : 0;
803 trace_output (OP_FLAG);
804 }
805
806 /* cmpi.l */
807 void
808 OP_3000000 ()
809 {
810 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
811 State.F1 = State.F0;
812 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
813 trace_output (OP_FLAG);
814 }
815
816 /* cmpu */
817 void
818 OP_4600 ()
819 {
820 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
821 State.F1 = State.F0;
822 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
823 trace_output (OP_FLAG);
824 }
825
826 /* cmpui */
827 void
828 OP_23000000 ()
829 {
830 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
831 State.F1 = State.F0;
832 State.F0 = (State.regs[OP[0]] < OP[1]) ? 1 : 0;
833 trace_output (OP_FLAG);
834 }
835
836 /* cpfg */
837 void
838 OP_4E09 ()
839 {
840 uint8 *src, *dst;
841
842 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
843 if (OP[0] == 0)
844 dst = &State.F0;
845 else
846 dst = &State.F1;
847
848 if (OP[1] == 0)
849 src = &State.F0;
850 else if (OP[1] == 1)
851 src = &State.F1;
852 else
853 src = &State.C;
854
855 *dst = *src;
856 trace_output (OP_FLAG);
857 }
858
859 /* dbt */
860 void
861 OP_5F20 ()
862 {
863 d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC);
864 State.exception = SIGTRAP;
865 }
866
867 /* divs */
868 void
869 OP_14002800 ()
870 {
871 uint16 foo, tmp, tmpf;
872
873 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
874 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
875 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
876 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
877 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
878 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
879 trace_output (OP_DREG);
880 }
881
882 /* exef0f */
883 void
884 OP_4E04 ()
885 {
886 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
887 State.exe = (State.F0 == 0);
888 trace_output (OP_FLAG);
889 }
890
891 /* exef0t */
892 void
893 OP_4E24 ()
894 {
895 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
896 State.exe = (State.F0 != 0);
897 trace_output (OP_FLAG);
898 }
899
900 /* exef1f */
901 void
902 OP_4E40 ()
903 {
904 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
905 State.exe = (State.F1 == 0);
906 trace_output (OP_FLAG);
907 }
908
909 /* exef1t */
910 void
911 OP_4E42 ()
912 {
913 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
914 State.exe = (State.F1 != 0);
915 trace_output (OP_FLAG);
916 }
917
918 /* exefaf */
919 void
920 OP_4E00 ()
921 {
922 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
923 State.exe = (State.F0 == 0) & (State.F1 == 0);
924 trace_output (OP_FLAG);
925 }
926
927 /* exefat */
928 void
929 OP_4E02 ()
930 {
931 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
932 State.exe = (State.F0 == 0) & (State.F1 != 0);
933 trace_output (OP_FLAG);
934 }
935
936 /* exetaf */
937 void
938 OP_4E20 ()
939 {
940 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
941 State.exe = (State.F0 != 0) & (State.F1 == 0);
942 trace_output (OP_FLAG);
943 }
944
945 /* exetat */
946 void
947 OP_4E22 ()
948 {
949 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
950 State.exe = (State.F0 != 0) & (State.F1 != 0);
951 trace_output (OP_FLAG);
952 }
953
954 /* exp */
955 void
956 OP_15002A00 ()
957 {
958 uint32 tmp, foo;
959 int i;
960
961 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
962 if (((int16)State.regs[OP[1]]) >= 0)
963 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
964 else
965 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
966
967 foo = 0x40000000;
968 for (i=1;i<17;i++)
969 {
970 if (tmp & foo)
971 {
972 State.regs[OP[0]] = i-1;
973 trace_output (OP_REG);
974 return;
975 }
976 foo >>= 1;
977 }
978 State.regs[OP[0]] = 16;
979 trace_output (OP_REG);
980 }
981
982 /* exp */
983 void
984 OP_15002A02 ()
985 {
986 int64 tmp, foo;
987 int i;
988
989 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
990 if (SEXT40(State.a[OP[1]]) >= 0)
991 tmp = State.a[OP[1]];
992 else
993 tmp = ~(State.a[OP[1]]);
994
995 foo = 0x4000000000LL;
996 for (i=1;i<25;i++)
997 {
998 if (tmp & foo)
999 {
1000 State.regs[OP[0]] = i-9;
1001 trace_output (OP_REG);
1002 return;
1003 }
1004 foo >>= 1;
1005 }
1006 State.regs[OP[0]] = 16;
1007 trace_output (OP_REG);
1008 }
1009
1010 /* jl */
1011 void
1012 OP_4D00 ()
1013 {
1014 trace_input ("jl", OP_REG, OP_VOID, OP_VOID);
1015 State.regs[13] = PC+1;
1016 PC = State.regs[OP[0]];
1017 trace_output (OP_VOID);
1018 }
1019
1020 /* jmp */
1021 void
1022 OP_4C00 ()
1023 {
1024 trace_input ("jmp", OP_REG, OP_VOID, OP_VOID);
1025 PC = State.regs[OP[0]];
1026 trace_output (OP_VOID);
1027 }
1028
1029 /* ld */
1030 void
1031 OP_30000000 ()
1032 {
1033 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1034 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1035 trace_output (OP_REG);
1036 }
1037
1038 /* ld */
1039 void
1040 OP_6401 ()
1041 {
1042 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1043 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1044 INC_ADDR(State.regs[OP[1]],-2);
1045 trace_output (OP_REG);
1046 }
1047
1048 /* ld */
1049 void
1050 OP_6001 ()
1051 {
1052 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1053 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1054 INC_ADDR(State.regs[OP[1]],2);
1055 trace_output (OP_REG);
1056 }
1057
1058 /* ld */
1059 void
1060 OP_6000 ()
1061 {
1062 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1063 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1064 trace_output (OP_REG);
1065 }
1066
1067 /* ld2w */
1068 void
1069 OP_31000000 ()
1070 {
1071 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1072 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1073 State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2);
1074 trace_output (OP_DREG);
1075 }
1076
1077 /* ld2w */
1078 void
1079 OP_6601 ()
1080 {
1081 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1082 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1083 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1084 INC_ADDR(State.regs[OP[1]],-4);
1085 trace_output (OP_DREG);
1086 }
1087
1088 /* ld2w */
1089 void
1090 OP_6201 ()
1091 {
1092 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1093 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1094 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1095 INC_ADDR(State.regs[OP[1]],4);
1096 trace_output (OP_REG);
1097 }
1098
1099 /* ld2w */
1100 void
1101 OP_6200 ()
1102 {
1103 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1104 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1105 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1106 trace_output (OP_REG);
1107 }
1108
1109 /* ldb */
1110 void
1111 OP_38000000 ()
1112 {
1113 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1114 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1115 SEXT8 (State.regs[OP[0]]);
1116 trace_output (OP_REG);
1117 }
1118
1119 /* ldb */
1120 void
1121 OP_7000 ()
1122 {
1123 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1124 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1125 SEXT8 (State.regs[OP[0]]);
1126 trace_output (OP_REG);
1127 }
1128
1129 /* ldi.s */
1130 void
1131 OP_4001 ()
1132 {
1133 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1134 State.regs[OP[0]] = SEXT4(OP[1]);
1135 trace_output (OP_REG);
1136 }
1137
1138 /* ldi.l */
1139 void
1140 OP_20000000 ()
1141 {
1142 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1143 State.regs[OP[0]] = OP[1];
1144 trace_output (OP_REG);
1145 }
1146
1147 /* ldub */
1148 void
1149 OP_39000000 ()
1150 {
1151 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1152 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1153 trace_output (OP_REG);
1154 }
1155
1156 /* ldub */
1157 void
1158 OP_7200 ()
1159 {
1160 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1161 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1162 trace_output (OP_REG);
1163 }
1164
1165 /* mac */
1166 void
1167 OP_2A00 ()
1168 {
1169 int64 tmp;
1170
1171 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1172 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1173
1174 if (State.FX)
1175 tmp = SEXT40( (tmp << 1) & MASK40);
1176
1177 if (State.ST && tmp > MAX32)
1178 tmp = MAX32;
1179
1180 tmp += SEXT40(State.a[OP[0]]);
1181 if (State.ST)
1182 {
1183 if (tmp > MAX32)
1184 State.a[OP[0]] = MAX32;
1185 else if (tmp < MIN32)
1186 State.a[OP[0]] = MIN32;
1187 else
1188 State.a[OP[0]] = tmp & MASK40;
1189 }
1190 else
1191 State.a[OP[0]] = tmp & MASK40;
1192 trace_output (OP_ACCUM);
1193 }
1194
1195 /* macsu */
1196 void
1197 OP_1A00 ()
1198 {
1199 int64 tmp;
1200
1201 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1202 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1203 if (State.FX)
1204 tmp = SEXT40( (tmp << 1) & MASK40);
1205
1206 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1207 trace_output (OP_ACCUM);
1208 }
1209
1210 /* macu */
1211 void
1212 OP_3A00 ()
1213 {
1214 int64 tmp;
1215
1216 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1217 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1218 if (State.FX)
1219 tmp = SEXT40( (tmp << 1) & MASK40);
1220 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1221 trace_output (OP_ACCUM);
1222 }
1223
1224 /* max */
1225 void
1226 OP_2600 ()
1227 {
1228 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1229 State.F1 = State.F0;
1230 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
1231 {
1232 State.regs[OP[0]] = State.regs[OP[1]];
1233 State.F0 = 1;
1234 }
1235 else
1236 State.F0 = 0;
1237 trace_output (OP_REG);
1238 }
1239
1240 /* max */
1241 void
1242 OP_3600 ()
1243 {
1244 int64 tmp;
1245
1246 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1247 State.F1 = State.F0;
1248 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1249 if (tmp > SEXT40(State.a[OP[0]]))
1250 {
1251 State.a[OP[0]] = tmp & MASK40;
1252 State.F0 = 1;
1253 }
1254 else
1255 State.F0 = 0;
1256 trace_output (OP_ACCUM);
1257 }
1258
1259 /* max */
1260 void
1261 OP_3602 ()
1262 {
1263 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1264 State.F1 = State.F0;
1265 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1266 {
1267 State.a[OP[0]] = State.a[OP[1]];
1268 State.F0 = 1;
1269 }
1270 else
1271 State.F0 = 0;
1272 trace_output (OP_ACCUM);
1273 }
1274
1275
1276 /* min */
1277 void
1278 OP_2601 ()
1279 {
1280 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1281 State.F1 = State.F0;
1282 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
1283 {
1284 State.regs[OP[0]] = State.regs[OP[1]];
1285 State.F0 = 1;
1286 }
1287 else
1288 State.F0 = 0;
1289 trace_output (OP_REG);
1290 }
1291
1292 /* min */
1293 void
1294 OP_3601 ()
1295 {
1296 int64 tmp;
1297
1298 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1299 State.F1 = State.F0;
1300 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1301 if (tmp < SEXT40(State.a[OP[0]]))
1302 {
1303 State.a[OP[0]] = tmp & MASK40;
1304 State.F0 = 1;
1305 }
1306 else
1307 State.F0 = 0;
1308 trace_output (OP_ACCUM);
1309 }
1310
1311 /* min */
1312 void
1313 OP_3603 ()
1314 {
1315 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1316 State.F1 = State.F0;
1317 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1318 {
1319 State.a[OP[0]] = State.a[OP[1]];
1320 State.F0 = 1;
1321 }
1322 else
1323 State.F0 = 0;
1324 trace_output (OP_ACCUM);
1325 }
1326
1327 /* msb */
1328 void
1329 OP_2800 ()
1330 {
1331 int64 tmp;
1332
1333 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1334 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1335
1336 if (State.FX)
1337 tmp = SEXT40 ((tmp << 1) & MASK40);
1338
1339 if (State.ST && tmp > MAX32)
1340 tmp = MAX32;
1341
1342 tmp = SEXT40(State.a[OP[0]]) - tmp;
1343 if (State.ST)
1344 {
1345 if (tmp > MAX32)
1346 State.a[OP[0]] = MAX32;
1347 else if (tmp < MIN32)
1348 State.a[OP[0]] = MIN32;
1349 else
1350 State.a[OP[0]] = tmp & MASK40;
1351 }
1352 else
1353 State.a[OP[0]] = tmp & MASK40;
1354 trace_output (OP_ACCUM);
1355 }
1356
1357 /* msbsu */
1358 void
1359 OP_1800 ()
1360 {
1361 int64 tmp;
1362
1363 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1364 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1365 if (State.FX)
1366 tmp = SEXT40( (tmp << 1) & MASK40);
1367
1368 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1369 trace_output (OP_ACCUM);
1370 }
1371
1372 /* msbu */
1373 void
1374 OP_3800 ()
1375 {
1376 int64 tmp;
1377
1378 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1379 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1380 if (State.FX)
1381 tmp = SEXT40( (tmp << 1) & MASK40);
1382
1383 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1384 trace_output (OP_ACCUM);
1385 }
1386
1387 /* mul */
1388 void
1389 OP_2E00 ()
1390 {
1391 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1392 State.regs[OP[0]] *= State.regs[OP[1]];
1393 trace_output (OP_REG);
1394 }
1395
1396 /* mulx */
1397 void
1398 OP_2C00 ()
1399 {
1400 int64 tmp;
1401
1402 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1403 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1404
1405 if (State.FX)
1406 tmp = SEXT40 ((tmp << 1) & MASK40);
1407
1408 if (State.ST && tmp > MAX32)
1409 State.a[OP[0]] = MAX32;
1410 else
1411 State.a[OP[0]] = tmp & MASK40;
1412 trace_output (OP_ACCUM);
1413 }
1414
1415 /* mulxsu */
1416 void
1417 OP_1C00 ()
1418 {
1419 int64 tmp;
1420
1421 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1422 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1423
1424 if (State.FX)
1425 tmp <<= 1;
1426
1427 State.a[OP[0]] = tmp & MASK40;
1428 trace_output (OP_ACCUM);
1429 }
1430
1431 /* mulxu */
1432 void
1433 OP_3C00 ()
1434 {
1435 int64 tmp;
1436
1437 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1438 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1439
1440 if (State.FX)
1441 tmp <<= 1;
1442
1443 State.a[OP[0]] = tmp & MASK40;
1444 trace_output (OP_ACCUM);
1445 }
1446
1447 /* mv */
1448 void
1449 OP_4000 ()
1450 {
1451 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1452 State.regs[OP[0]] = State.regs[OP[1]];
1453 trace_output (OP_REG);
1454 }
1455
1456 /* mv2w */
1457 void
1458 OP_5000 ()
1459 {
1460 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1461 State.regs[OP[0]] = State.regs[OP[1]];
1462 State.regs[OP[0]+1] = State.regs[OP[1]+1];
1463 trace_output (OP_DREG);
1464 }
1465
1466 /* mv2wfac */
1467 void
1468 OP_3E00 ()
1469 {
1470 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1471 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1472 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
1473 trace_output (OP_DREG);
1474 }
1475
1476 /* mv2wtac */
1477 void
1478 OP_3E01 ()
1479 {
1480 trace_input ("mv2wtac", OP_ACCUM_OUTPUT, OP_DREG, OP_VOID);
1481 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
1482 trace_output (OP_ACCUM);
1483 }
1484
1485 /* mvac */
1486 void
1487 OP_3E03 ()
1488 {
1489 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1490 State.a[OP[0]] = State.a[OP[1]];
1491 trace_output (OP_ACCUM);
1492 }
1493
1494 /* mvb */
1495 void
1496 OP_5400 ()
1497 {
1498 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1499 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
1500 trace_output (OP_REG);
1501 }
1502
1503 /* mvf0f */
1504 void
1505 OP_4400 ()
1506 {
1507 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1508 if (State.F0 == 0)
1509 State.regs[OP[0]] = State.regs[OP[1]];
1510 trace_output (OP_REG);
1511 }
1512
1513 /* mvf0t */
1514 void
1515 OP_4401 ()
1516 {
1517 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1518 if (State.F0)
1519 State.regs[OP[0]] = State.regs[OP[1]];
1520 trace_output (OP_REG);
1521 }
1522
1523 /* mvfacg */
1524 void
1525 OP_1E04 ()
1526 {
1527 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1528 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
1529 trace_output (OP_ACCUM);
1530 }
1531
1532 /* mvfachi */
1533 void
1534 OP_1E00 ()
1535 {
1536 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1537 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1538 trace_output (OP_REG);
1539 }
1540
1541 /* mvfaclo */
1542 void
1543 OP_1E02 ()
1544 {
1545 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1546 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
1547 trace_output (OP_REG);
1548 }
1549
1550 /* mvfc */
1551 void
1552 OP_5200 ()
1553 {
1554 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1555 if (OP[1] == 0)
1556 {
1557 /* PSW is treated specially */
1558 PSW = 0;
1559 if (State.SM) PSW |= 0x8000;
1560 if (State.EA) PSW |= 0x2000;
1561 if (State.DB) PSW |= 0x1000;
1562 if (State.IE) PSW |= 0x400;
1563 if (State.RP) PSW |= 0x200;
1564 if (State.MD) PSW |= 0x100;
1565 if (State.FX) PSW |= 0x80;
1566 if (State.ST) PSW |= 0x40;
1567 if (State.F0) PSW |= 8;
1568 if (State.F1) PSW |= 4;
1569 if (State.C) PSW |= 1;
1570 }
1571 State.regs[OP[0]] = State.cregs[OP[1]];
1572 trace_output (OP_REG);
1573 }
1574
1575 /* mvtacg */
1576 void
1577 OP_1E41 ()
1578 {
1579 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1580 State.a[OP[1]] &= MASK32;
1581 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
1582 trace_output (OP_ACCUM_REVERSE);
1583 }
1584
1585 /* mvtachi */
1586 void
1587 OP_1E01 ()
1588 {
1589 uint16 tmp;
1590
1591 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1592 tmp = State.a[OP[1]] & 0xffff;
1593 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
1594 trace_output (OP_ACCUM_REVERSE);
1595 }
1596
1597 /* mvtaclo */
1598 void
1599 OP_1E21 ()
1600 {
1601 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1602 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
1603 trace_output (OP_ACCUM_REVERSE);
1604 }
1605
1606 /* mvtc */
1607 void
1608 OP_5600 ()
1609 {
1610 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1611 State.cregs[OP[1]] = State.regs[OP[0]];
1612 if (OP[1] == 0)
1613 {
1614 /* PSW is treated specially */
1615 State.SM = (PSW & 0x8000) ? 1 : 0;
1616 State.EA = (PSW & 0x2000) ? 1 : 0;
1617 State.DB = (PSW & 0x1000) ? 1 : 0;
1618 State.IE = (PSW & 0x400) ? 1 : 0;
1619 State.RP = (PSW & 0x200) ? 1 : 0;
1620 State.MD = (PSW & 0x100) ? 1 : 0;
1621 State.FX = (PSW & 0x80) ? 1 : 0;
1622 State.ST = (PSW & 0x40) ? 1 : 0;
1623 State.F0 = (PSW & 8) ? 1 : 0;
1624 State.F1 = (PSW & 4) ? 1 : 0;
1625 State.C = PSW & 1;
1626 if (State.ST && !State.FX)
1627 {
1628 (*d10v_callback->printf_filtered) (d10v_callback,
1629 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1630 PC<<2);
1631 State.exception = SIGILL;
1632 }
1633 }
1634 trace_output (OP_CR_REVERSE);
1635 }
1636
1637 /* mvub */
1638 void
1639 OP_5401 ()
1640 {
1641 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1642 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
1643 trace_output (OP_REG);
1644 }
1645
1646 /* neg */
1647 void
1648 OP_4605 ()
1649 {
1650 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
1651 State.regs[OP[0]] = 0 - State.regs[OP[0]];
1652 trace_output (OP_REG);
1653 }
1654
1655 /* neg */
1656 void
1657 OP_5605 ()
1658 {
1659 int64 tmp;
1660
1661 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
1662 tmp = -SEXT40(State.a[OP[0]]);
1663 if (State.ST)
1664 {
1665 if ( tmp > MAX32)
1666 State.a[OP[0]] = MAX32;
1667 else if (tmp < MIN32)
1668 State.a[OP[0]] = MIN32;
1669 else
1670 State.a[OP[0]] = tmp & MASK40;
1671 }
1672 else
1673 State.a[OP[0]] = tmp & MASK40;
1674 trace_output (OP_ACCUM);
1675 }
1676
1677
1678 /* nop */
1679 void
1680 OP_5E00 ()
1681 {
1682 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1683 trace_output (OP_VOID);
1684
1685 if (State.ins_type == INS_LEFT || State.ins_type == INS_LEFT_PARALLEL)
1686 left_nops++;
1687 else
1688 right_nops++;
1689 }
1690
1691 /* not */
1692 void
1693 OP_4603 ()
1694 {
1695 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
1696 State.regs[OP[0]] = ~(State.regs[OP[0]]);
1697 trace_output (OP_REG);
1698 }
1699
1700 /* or */
1701 void
1702 OP_800 ()
1703 {
1704 trace_input ("or", OP_REG, OP_REG, OP_VOID);
1705 State.regs[OP[0]] |= State.regs[OP[1]];
1706 trace_output (OP_REG);
1707 }
1708
1709 /* or3 */
1710 void
1711 OP_4000000 ()
1712 {
1713 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
1714 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
1715 trace_output (OP_REG);
1716 }
1717
1718 /* rac */
1719 void
1720 OP_5201 ()
1721 {
1722 int64 tmp;
1723 int shift = SEXT3 (OP[2]);
1724
1725 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1726 if (OP[1] != 0)
1727 {
1728 (*d10v_callback->printf_filtered) (d10v_callback,
1729 "ERROR at PC 0x%x: instruction only valid for A0\n",
1730 PC<<2);
1731 State.exception = SIGILL;
1732 }
1733
1734 State.F1 = State.F0;
1735 if (shift >=0)
1736 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1737 else
1738 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
1739 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
1740 if (tmp > MAX32)
1741 {
1742 State.regs[OP[0]] = 0x7fff;
1743 State.regs[OP[0]+1] = 0xffff;
1744 State.F0 = 1;
1745 }
1746 else if (tmp < MIN32)
1747 {
1748 State.regs[OP[0]] = 0x8000;
1749 State.regs[OP[0]+1] = 0;
1750 State.F0 = 1;
1751 }
1752 else
1753 {
1754 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1755 State.regs[OP[0]+1] = tmp & 0xffff;
1756 State.F0 = 0;
1757 }
1758 trace_output (OP_DREG);
1759 }
1760
1761 /* rachi */
1762 void
1763 OP_4201 ()
1764 {
1765 int64 tmp;
1766 int shift = SEXT3 (OP[2]);
1767
1768 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1769 State.F1 = State.F0;
1770 if (shift >=0)
1771 tmp = SEXT44 (State.a[1]) << shift;
1772 else
1773 tmp = SEXT44 (State.a[1]) >> -shift;
1774 tmp += 0x8000;
1775
1776 if (tmp > MAX32)
1777 {
1778 State.regs[OP[0]] = 0x7fff;
1779 State.F0 = 1;
1780 }
1781 else if (tmp < 0xfff80000000LL)
1782 {
1783 State.regs[OP[0]] = 0x8000;
1784 State.F0 = 1;
1785 }
1786 else
1787 {
1788 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1789 State.F0 = 0;
1790 }
1791 trace_output (OP_REG);
1792 }
1793
1794 /* rep */
1795 void
1796 OP_27000000 ()
1797 {
1798 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
1799 RPT_S = PC + 1;
1800 RPT_E = PC + OP[1];
1801 RPT_C = State.regs[OP[0]];
1802 State.RP = 1;
1803 if (RPT_C == 0)
1804 {
1805 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
1806 State.exception = SIGILL;
1807 }
1808 if (OP[1] < 4)
1809 {
1810 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
1811 State.exception = SIGILL;
1812 }
1813 trace_output (OP_VOID);
1814 }
1815
1816 /* repi */
1817 void
1818 OP_2F000000 ()
1819 {
1820 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
1821 RPT_S = PC + 1;
1822 RPT_E = PC + OP[1];
1823 RPT_C = OP[0];
1824 State.RP = 1;
1825 if (RPT_C == 0)
1826 {
1827 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
1828 State.exception = SIGILL;
1829 }
1830 if (OP[1] < 4)
1831 {
1832 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
1833 State.exception = SIGILL;
1834 }
1835 trace_output (OP_VOID);
1836 }
1837
1838 /* rtd */
1839 void
1840 OP_5F60 ()
1841 {
1842 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
1843 State.exception = SIGILL;
1844 }
1845
1846 /* rte */
1847 void
1848 OP_5F40 ()
1849 {
1850 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
1851 PC = BPC;
1852 PSW = BPSW;
1853 trace_output (OP_VOID);
1854 }
1855
1856 /* sadd */
1857 void
1858 OP_1223 ()
1859 {
1860 int64 tmp;
1861
1862 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
1863 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
1864 if (State.ST)
1865 {
1866 if (tmp > MAX32)
1867 State.a[OP[0]] = MAX32;
1868 else if (tmp < MIN32)
1869 State.a[OP[0]] = MIN32;
1870 else
1871 State.a[OP[0]] = tmp & MASK40;
1872 }
1873 else
1874 State.a[OP[0]] = tmp & MASK40;
1875 trace_output (OP_ACCUM);
1876 }
1877
1878 /* setf0f */
1879 void
1880 OP_4611 ()
1881 {
1882 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
1883 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
1884 trace_output (OP_REG);
1885 }
1886
1887 /* setf0t */
1888 void
1889 OP_4613 ()
1890 {
1891 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
1892 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
1893 trace_output (OP_REG);
1894 }
1895
1896 /* sleep */
1897 void
1898 OP_5FC0 ()
1899 {
1900 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
1901 State.IE = 1;
1902 trace_output (OP_VOID);
1903 }
1904
1905 /* sll */
1906 void
1907 OP_2200 ()
1908 {
1909 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
1910 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
1911 trace_output (OP_REG);
1912 }
1913
1914 /* sll */
1915 void
1916 OP_3200 ()
1917 {
1918 int64 tmp;
1919 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
1920 if ((State.regs[OP[1]] & 31) <= 16)
1921 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
1922 else
1923 {
1924 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
1925 State.exception = SIGILL;
1926 return;
1927 }
1928
1929 if (State.ST)
1930 {
1931 if (tmp > MAX32)
1932 State.a[OP[0]] = MAX32;
1933 else if (tmp < 0xffffff80000000LL)
1934 State.a[OP[0]] = MIN32;
1935 else
1936 State.a[OP[0]] = tmp & MASK40;
1937 }
1938 else
1939 State.a[OP[0]] = tmp & MASK40;
1940 trace_output (OP_ACCUM);
1941 }
1942
1943 /* slli */
1944 void
1945 OP_2201 ()
1946 {
1947 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
1948 State.regs[OP[0]] <<= OP[1];
1949 trace_output (OP_REG);
1950 }
1951
1952 /* slli */
1953 void
1954 OP_3201 ()
1955 {
1956 int64 tmp;
1957
1958 if (OP[1] == 0)
1959 OP[1] = 16;
1960
1961 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
1962 tmp = SEXT40(State.a[OP[0]]) << OP[1];
1963
1964 if (State.ST)
1965 {
1966 if (tmp > MAX32)
1967 State.a[OP[0]] = MAX32;
1968 else if (tmp < 0xffffff80000000LL)
1969 State.a[OP[0]] = MIN32;
1970 else
1971 State.a[OP[0]] = tmp & MASK40;
1972 }
1973 else
1974 State.a[OP[0]] = tmp & MASK40;
1975 trace_output (OP_ACCUM);
1976 }
1977
1978 /* slx */
1979 void
1980 OP_460B ()
1981 {
1982 uint16 tmp;
1983
1984 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
1985 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
1986 trace_output (OP_REG);
1987 }
1988
1989 /* sra */
1990 void
1991 OP_2400 ()
1992 {
1993 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
1994 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
1995 trace_output (OP_REG);
1996 }
1997
1998 /* sra */
1999 void
2000 OP_3400 ()
2001 {
2002 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2003 if ((State.regs[OP[1]] & 31) <= 16)
2004 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
2005 else
2006 {
2007 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2008 State.exception = SIGILL;
2009 return;
2010 }
2011
2012 trace_output (OP_ACCUM);
2013 }
2014
2015 /* srai */
2016 void
2017 OP_2401 ()
2018 {
2019 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2020 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
2021 trace_output (OP_REG);
2022 }
2023
2024 /* srai */
2025 void
2026 OP_3401 ()
2027 {
2028 if (OP[1] == 0)
2029 OP[1] = 16;
2030
2031 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2032 State.a[OP[0]] >>= OP[1];
2033 trace_output (OP_ACCUM);
2034 }
2035
2036 /* srl */
2037 void
2038 OP_2000 ()
2039 {
2040 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2041 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
2042 trace_output (OP_REG);
2043 }
2044
2045 /* srl */
2046 void
2047 OP_3000 ()
2048 {
2049 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2050 if ((State.regs[OP[1]] & 31) <= 16)
2051 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
2052 else
2053 {
2054 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2055 State.exception = SIGILL;
2056 return;
2057 }
2058
2059 trace_output (OP_ACCUM);
2060 }
2061
2062 /* srli */
2063 void
2064 OP_2001 ()
2065 {
2066 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2067 State.regs[OP[0]] >>= OP[1];
2068 trace_output (OP_REG);
2069 }
2070
2071 /* srli */
2072 void
2073 OP_3001 ()
2074 {
2075 if (OP[1] == 0)
2076 OP[1] = 16;
2077
2078 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2079 State.a[OP[0]] >>= OP[1];
2080 trace_output (OP_ACCUM);
2081 }
2082
2083 /* srx */
2084 void
2085 OP_4609 ()
2086 {
2087 uint16 tmp;
2088
2089 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2090 tmp = State.F0 << 15;
2091 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
2092 trace_output (OP_REG);
2093 }
2094
2095 /* st */
2096 void
2097 OP_34000000 ()
2098 {
2099 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2100 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
2101 trace_output (OP_VOID);
2102 }
2103
2104 /* st */
2105 void
2106 OP_6800 ()
2107 {
2108 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2109 SW (State.regs[OP[1]], State.regs[OP[0]]);
2110 trace_output (OP_VOID);
2111 }
2112
2113 /* st */
2114 void
2115 OP_6C1F ()
2116 {
2117 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2118 if ( OP[1] != 15 )
2119 {
2120 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2121 State.exception = SIGILL;
2122 return;
2123 }
2124 State.regs[OP[1]] -= 2;
2125 SW (State.regs[OP[1]], State.regs[OP[0]]);
2126 trace_output (OP_VOID);
2127 }
2128
2129 /* st */
2130 void
2131 OP_6801 ()
2132 {
2133 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2134 SW (State.regs[OP[1]], State.regs[OP[0]]);
2135 INC_ADDR (State.regs[OP[1]],2);
2136 trace_output (OP_VOID);
2137 }
2138
2139 /* st */
2140 void
2141 OP_6C01 ()
2142 {
2143 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2144 SW (State.regs[OP[1]], State.regs[OP[0]]);
2145 INC_ADDR (State.regs[OP[1]],-2);
2146 trace_output (OP_VOID);
2147 }
2148
2149 /* st2w */
2150 void
2151 OP_35000000 ()
2152 {
2153 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2154 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2155 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
2156 trace_output (OP_VOID);
2157 }
2158
2159 /* st2w */
2160 void
2161 OP_6A00 ()
2162 {
2163 trace_input ("st2w", OP_REG, OP_MEMREF, OP_VOID);
2164 SW (State.regs[OP[1]], State.regs[OP[0]]);
2165 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2166 trace_output (OP_VOID);
2167 }
2168
2169 /* st2w */
2170 void
2171 OP_6E1F ()
2172 {
2173 trace_input ("st2w", OP_REG, OP_PREDEC, OP_VOID);
2174 if ( OP[1] != 15 )
2175 {
2176 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2177 State.exception = SIGILL;
2178 return;
2179 }
2180 State.regs[OP[1]] -= 4;
2181 SW (State.regs[OP[1]], State.regs[OP[0]]);
2182 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2183 trace_output (OP_VOID);
2184 }
2185
2186 /* st2w */
2187 void
2188 OP_6A01 ()
2189 {
2190 trace_input ("st2w", OP_REG, OP_POSTDEC, OP_VOID);
2191 SW (State.regs[OP[1]], State.regs[OP[0]]);
2192 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2193 INC_ADDR (State.regs[OP[1]],4);
2194 trace_output (OP_VOID);
2195 }
2196
2197 /* st2w */
2198 void
2199 OP_6E01 ()
2200 {
2201 trace_input ("st2w", OP_REG, OP_POSTINC, OP_VOID);
2202 SW (State.regs[OP[1]], State.regs[OP[0]]);
2203 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2204 INC_ADDR (State.regs[OP[1]],-4);
2205 trace_output (OP_VOID);
2206 }
2207
2208 /* stb */
2209 void
2210 OP_3C000000 ()
2211 {
2212 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2213 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2214 trace_output (OP_VOID);
2215 }
2216
2217 /* stb */
2218 void
2219 OP_7800 ()
2220 {
2221 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2222 SB (State.regs[OP[1]], State.regs[OP[0]]);
2223 trace_output (OP_VOID);
2224 }
2225
2226 /* stop */
2227 void
2228 OP_5FE0 ()
2229 {
2230 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2231 State.exception = SIGQUIT;
2232 trace_output (OP_VOID);
2233 }
2234
2235 /* sub */
2236 void
2237 OP_0 ()
2238 {
2239 int32 tmp;
2240
2241 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2242 tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
2243 State.C = (tmp & 0xffff0000) ? 1 : 0;
2244 State.regs[OP[0]] = tmp & 0xffff;
2245 trace_output (OP_REG);
2246 }
2247
2248 /* sub */
2249 void
2250 OP_1001 ()
2251 {
2252 int64 tmp;
2253
2254 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2255 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2256 if (State.ST)
2257 {
2258 if ( tmp > MAX32)
2259 State.a[OP[0]] = MAX32;
2260 else if ( tmp < MIN32)
2261 State.a[OP[0]] = MIN32;
2262 else
2263 State.a[OP[0]] = tmp & MASK40;
2264 }
2265 else
2266 State.a[OP[0]] = tmp & MASK40;
2267
2268 trace_output (OP_ACCUM);
2269 }
2270
2271 /* sub */
2272
2273 void
2274 OP_1003 ()
2275 {
2276 int64 tmp;
2277
2278 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2279 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2280 if (State.ST)
2281 {
2282 if (tmp > MAX32)
2283 State.a[OP[0]] = MAX32;
2284 else if ( tmp < MIN32)
2285 State.a[OP[0]] = MIN32;
2286 else
2287 State.a[OP[0]] = tmp & MASK40;
2288 }
2289 else
2290 State.a[OP[0]] = tmp & MASK40;
2291
2292 trace_output (OP_ACCUM);
2293 }
2294
2295 /* sub2w */
2296 void
2297 OP_1000 ()
2298 {
2299 int64 tmp;
2300 int32 a,b;
2301
2302 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2303 a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2304 b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2305 tmp = a-b;
2306 State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;
2307 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2308 State.regs[OP[0]+1] = tmp & 0xffff;
2309 trace_output (OP_DREG);
2310 }
2311
2312 /* subac3 */
2313 void
2314 OP_17000000 ()
2315 {
2316 int64 tmp;
2317
2318 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2319 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2320 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2321 State.regs[OP[0]+1] = tmp & 0xffff;
2322 trace_output (OP_DREG);
2323 }
2324
2325 /* subac3 */
2326 void
2327 OP_17000002 ()
2328 {
2329 int64 tmp;
2330
2331 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2332 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2333 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2334 State.regs[OP[0]+1] = tmp & 0xffff;
2335 trace_output (OP_DREG);
2336 }
2337
2338 /* subac3s */
2339 void
2340 OP_17001000 ()
2341 {
2342 int64 tmp;
2343
2344 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2345 State.F1 = State.F0;
2346 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2347 if ( tmp > MAX32)
2348 {
2349 State.regs[OP[0]] = 0x7fff;
2350 State.regs[OP[0]+1] = 0xffff;
2351 State.F0 = 1;
2352 }
2353 else if (tmp < MIN32)
2354 {
2355 State.regs[OP[0]] = 0x8000;
2356 State.regs[OP[0]+1] = 0;
2357 State.F0 = 1;
2358 }
2359 else
2360 {
2361 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2362 State.regs[OP[0]+1] = tmp & 0xffff;
2363 State.F0 = 0;
2364 }
2365 trace_output (OP_DREG);
2366 }
2367
2368 /* subac3s */
2369 void
2370 OP_17001002 ()
2371 {
2372 int64 tmp;
2373
2374 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2375 State.F1 = State.F0;
2376 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2377 if ( tmp > MAX32)
2378 {
2379 State.regs[OP[0]] = 0x7fff;
2380 State.regs[OP[0]+1] = 0xffff;
2381 State.F0 = 1;
2382 }
2383 else if (tmp < MIN32)
2384 {
2385 State.regs[OP[0]] = 0x8000;
2386 State.regs[OP[0]+1] = 0;
2387 State.F0 = 1;
2388 }
2389 else
2390 {
2391 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2392 State.regs[OP[0]+1] = tmp & 0xffff;
2393 State.F0 = 0;
2394 }
2395 trace_output (OP_DREG);
2396 }
2397
2398 /* subi */
2399 void
2400 OP_1 ()
2401 {
2402 int32 tmp;
2403 if (OP[1] == 0)
2404 OP[1] = 16;
2405
2406 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2407 tmp = (int16)State.regs[OP[0]] - OP[1];
2408 State.C = (tmp & 0xffff0000) ? 1 : 0;
2409 State.regs[OP[0]] = tmp & 0xffff;
2410 trace_output (OP_REG);
2411 }
2412
2413 /* trap */
2414 void
2415 OP_5F00 ()
2416 {
2417 trace_input ("trap", OP_CONSTANT16, OP_REG, OP_VOID);
2418 trace_output (OP_VOID);
2419
2420 switch (OP[0])
2421 {
2422 default:
2423 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
2424 State.exception = SIGILL;
2425
2426 case 0:
2427 /* Trap 0 is used for simulating low-level I/O */
2428 {
2429 int save_errno = errno;
2430 errno = 0;
2431
2432 /* Registers passed to trap 0 */
2433
2434 #define FUNC State.regs[2] /* function number, return value */
2435 #define PARM1 State.regs[3] /* optional parm 1 */
2436 #define PARM2 State.regs[4] /* optional parm 2 */
2437 #define PARM3 State.regs[5] /* optional parm 3 */
2438
2439 /* Registers set by trap 0 */
2440
2441 #define RETVAL State.regs[2] /* return value */
2442 #define RETERR State.regs[3] /* return error code */
2443
2444 /* Turn a pointer in a register into a pointer into real memory. */
2445
2446 #define MEMPTR(x) ((char *)((x) + State.imem))
2447
2448 switch (FUNC)
2449 {
2450 #if !defined(__GO32__) && !defined(_WIN32)
2451 #ifdef SYS_fork
2452 case SYS_fork:
2453 RETVAL = fork ();
2454 break;
2455 #endif
2456 #ifdef SYS_execve
2457 case SYS_execve:
2458 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2459 (char **)MEMPTR (PARM3));
2460 break;
2461 #endif
2462 #ifdef SYS_execv
2463 case SYS_execv:
2464 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2465 break;
2466 #endif
2467 #ifdef SYS_pipe
2468 case SYS_pipe:
2469 {
2470 reg_t buf;
2471 int host_fd[2];
2472
2473 buf = PARM1;
2474 RETVAL = pipe (host_fd);
2475 SW (buf, host_fd[0]);
2476 buf += sizeof(uint16);
2477 SW (buf, host_fd[1]);
2478 }
2479 break;
2480 #endif
2481 #ifdef SYS_wait
2482 case SYS_wait:
2483 {
2484 int status;
2485
2486 RETVAL = wait (&status);
2487 SW (PARM1, status);
2488 }
2489 break;
2490 #endif
2491 #endif
2492
2493 #ifdef SYS_read
2494 case SYS_read:
2495 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2496 PARM3);
2497 break;
2498 #endif
2499 #ifdef SYS_write
2500 case SYS_write:
2501 if (PARM1 == 1)
2502 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2503 MEMPTR (PARM2), PARM3);
2504 else
2505 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2506 MEMPTR (PARM2), PARM3);
2507 break;
2508 #endif
2509 #ifdef SYS_lseek
2510 case SYS_lseek:
2511 RETVAL = d10v_callback->lseek (d10v_callback, PARM1, PARM2, PARM3);
2512 break;
2513 #endif
2514 #ifdef SYS_close
2515 case SYS_close:
2516 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2517 break;
2518 #endif
2519 #ifdef SYS_open
2520 case SYS_open:
2521 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2522 break;
2523 #endif
2524 #ifdef SYS_exit
2525 case SYS_exit:
2526 /* EXIT - caller can look in PARM1 to work out the
2527 reason */
2528 State.exception = SIGQUIT;
2529 break;
2530 #endif
2531
2532 #ifdef SYS_stat
2533 case SYS_stat:
2534 /* stat system call */
2535 {
2536 struct stat host_stat;
2537 reg_t buf;
2538
2539 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2540
2541 buf = PARM2;
2542
2543 /* The hard-coded offsets and sizes were determined by using
2544 * the D10V compiler on a test program that used struct stat.
2545 */
2546 SW (buf, host_stat.st_dev);
2547 SW (buf+2, host_stat.st_ino);
2548 SW (buf+4, host_stat.st_mode);
2549 SW (buf+6, host_stat.st_nlink);
2550 SW (buf+8, host_stat.st_uid);
2551 SW (buf+10, host_stat.st_gid);
2552 SW (buf+12, host_stat.st_rdev);
2553 SLW (buf+16, host_stat.st_size);
2554 SLW (buf+20, host_stat.st_atime);
2555 SLW (buf+28, host_stat.st_mtime);
2556 SLW (buf+36, host_stat.st_ctime);
2557 }
2558 break;
2559 #endif
2560
2561 #ifdef SYS_chown
2562 case SYS_chown:
2563 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2564 break;
2565 #endif
2566 #ifdef SYS_chmod
2567 case SYS_chmod:
2568 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2569 break;
2570 #endif
2571 #ifdef SYS_utime
2572 case SYS_utime:
2573 /* Cast the second argument to void *, to avoid type mismatch
2574 if a prototype is present. */
2575 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2576 break;
2577 #endif
2578 default:
2579 abort ();
2580 }
2581 RETERR = errno;
2582 errno = save_errno;
2583 break;
2584 }
2585
2586 case 1:
2587 /* Trap 1 prints a string */
2588 {
2589 char *fstr = State.regs[2] + State.imem;
2590 fputs (fstr, stdout);
2591 break;
2592 }
2593
2594 case 2:
2595 /* Trap 2 calls printf */
2596 {
2597 char *fstr = State.regs[2] + State.imem;
2598 (*d10v_callback->printf_filtered) (d10v_callback, fstr,
2599 (int16)State.regs[3],
2600 (int16)State.regs[4],
2601 (int16)State.regs[5]);
2602 break;
2603 }
2604
2605 case 3:
2606 /* Trap 3 writes a character */
2607 putchar (State.regs[2]);
2608 break;
2609 }
2610 }
2611
2612 /* tst0i */
2613 void
2614 OP_7000000 ()
2615 {
2616 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
2617 State.F1 = State.F0;
2618 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
2619 trace_output (OP_FLAG);
2620 }
2621
2622 /* tst1i */
2623 void
2624 OP_F000000 ()
2625 {
2626 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
2627 State.F1 = State.F0;
2628 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
2629 trace_output (OP_FLAG);
2630 }
2631
2632 /* wait */
2633 void
2634 OP_5F80 ()
2635 {
2636 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
2637 State.IE = 1;
2638 trace_output (OP_VOID);
2639 }
2640
2641 /* xor */
2642 void
2643 OP_A00 ()
2644 {
2645 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
2646 State.regs[OP[0]] ^= State.regs[OP[1]];
2647 trace_output (OP_REG);
2648 }
2649
2650 /* xor3 */
2651 void
2652 OP_5000000 ()
2653 {
2654 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2655 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
2656 trace_output (OP_REG);
2657 }
2658
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