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[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
1 /* This must come before any other includes. */
2 #include "defs.h"
3
4 #include <signal.h>
5 #include <errno.h>
6 #include <sys/types.h>
7 #include <sys/stat.h>
8 #ifdef HAVE_UNISTD_H
9 #include <unistd.h>
10 #endif
11 #include <string.h>
12
13 #include "bfd.h"
14
15 #include "sim-main.h"
16 #include "sim-signal.h"
17 #include "simops.h"
18 #include "target-newlib-syscall.h"
19
20 #include "d10v-sim.h"
21
22 #define EXCEPTION(sig) sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, sig)
23
24 enum op_types {
25 OP_VOID,
26 OP_REG,
27 OP_REG_OUTPUT,
28 OP_DREG,
29 OP_DREG_OUTPUT,
30 OP_ACCUM,
31 OP_ACCUM_OUTPUT,
32 OP_ACCUM_REVERSE,
33 OP_CR,
34 OP_CR_OUTPUT,
35 OP_CR_REVERSE,
36 OP_FLAG,
37 OP_FLAG_OUTPUT,
38 OP_CONSTANT16,
39 OP_CONSTANT8,
40 OP_CONSTANT3,
41 OP_CONSTANT4,
42 OP_MEMREF,
43 OP_MEMREF2,
44 OP_MEMREF3,
45 OP_POSTDEC,
46 OP_POSTINC,
47 OP_PREDEC,
48 OP_R0,
49 OP_R1,
50 OP_R2,
51 };
52
53
54 enum {
55 PSW_MASK = (PSW_SM_BIT
56 | PSW_EA_BIT
57 | PSW_DB_BIT
58 | PSW_IE_BIT
59 | PSW_RP_BIT
60 | PSW_MD_BIT
61 | PSW_FX_BIT
62 | PSW_ST_BIT
63 | PSW_F0_BIT
64 | PSW_F1_BIT
65 | PSW_C_BIT),
66 /* The following bits in the PSW _can't_ be set by instructions such
67 as mvtc. */
68 PSW_HW_MASK = (PSW_MASK | PSW_DM_BIT)
69 };
70
71 reg_t
72 move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, reg_t mask, reg_t val, int psw_hw_p)
73 {
74 /* A MASK bit is set when the corresponding bit in the CR should
75 be left alone */
76 /* This assumes that (VAL & MASK) == 0 */
77 switch (cr)
78 {
79 case PSW_CR:
80 if (psw_hw_p)
81 val &= PSW_HW_MASK;
82 else
83 val &= PSW_MASK;
84 if ((mask & PSW_SM_BIT) == 0)
85 {
86 int new_psw_sm = (val & PSW_SM_BIT) != 0;
87 /* save old SP */
88 SET_HELD_SP (PSW_SM, GPR (SP_IDX));
89 if (PSW_SM != new_psw_sm)
90 /* restore new SP */
91 SET_GPR (SP_IDX, HELD_SP (new_psw_sm));
92 }
93 if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
94 {
95 if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
96 {
97 sim_io_printf
98 (sd,
99 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
100 PC<<2);
101 EXCEPTION (SIM_SIGILL);
102 }
103 }
104 /* keep an up-to-date psw around for tracing */
105 State.trace.psw = (State.trace.psw & mask) | val;
106 break;
107 case BPSW_CR:
108 case DPSW_CR:
109 /* Just like PSW, mask things like DM out. */
110 if (psw_hw_p)
111 val &= PSW_HW_MASK;
112 else
113 val &= PSW_MASK;
114 break;
115 case MOD_S_CR:
116 case MOD_E_CR:
117 val &= ~1;
118 break;
119 default:
120 break;
121 }
122 /* only issue an update if the register is being changed */
123 if ((State.cregs[cr] & ~mask) != val)
124 SLOT_PEND_MASK (State.cregs[cr], mask, val);
125 return val;
126 }
127
128 #ifdef DEBUG
129 static void trace_input_func (SIM_DESC sd,
130 const char *name,
131 enum op_types in1,
132 enum op_types in2,
133 enum op_types in3);
134
135 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (sd, name, in1, in2, in3); } while (0)
136
137 #ifndef SIZE_INSTRUCTION
138 #define SIZE_INSTRUCTION 8
139 #endif
140
141 #ifndef SIZE_OPERANDS
142 #define SIZE_OPERANDS 18
143 #endif
144
145 #ifndef SIZE_VALUES
146 #define SIZE_VALUES 13
147 #endif
148
149 #ifndef SIZE_LOCATION
150 #define SIZE_LOCATION 20
151 #endif
152
153 #ifndef SIZE_PC
154 #define SIZE_PC 6
155 #endif
156
157 #ifndef SIZE_LINE_NUMBER
158 #define SIZE_LINE_NUMBER 4
159 #endif
160
161 static void
162 trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
163 {
164 char *comma;
165 enum op_types in[3];
166 int i;
167 char buf[1024];
168 char *p;
169 long tmp;
170 char *type;
171 const char *filename;
172 const char *functionname;
173 unsigned int linenumber;
174 bfd_vma byte_pc;
175
176 if ((d10v_debug & DEBUG_TRACE) == 0)
177 return;
178
179 switch (State.ins_type)
180 {
181 default:
182 case INS_UNKNOWN: type = " ?"; break;
183 case INS_LEFT: type = " L"; break;
184 case INS_RIGHT: type = " R"; break;
185 case INS_LEFT_PARALLEL: type = "*L"; break;
186 case INS_RIGHT_PARALLEL: type = "*R"; break;
187 case INS_LEFT_COND_TEST: type = "?L"; break;
188 case INS_RIGHT_COND_TEST: type = "?R"; break;
189 case INS_LEFT_COND_EXE: type = "&L"; break;
190 case INS_RIGHT_COND_EXE: type = "&R"; break;
191 case INS_LONG: type = " B"; break;
192 }
193
194 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
195 sim_io_printf (sd,
196 "0x%.*x %s: %-*s ",
197 SIZE_PC, (unsigned)PC,
198 type,
199 SIZE_INSTRUCTION, name);
200
201 else
202 {
203 buf[0] = '\0';
204 byte_pc = PC;
205 if (STATE_TEXT_SECTION (sd)
206 && byte_pc >= STATE_TEXT_START (sd)
207 && byte_pc < STATE_TEXT_END (sd))
208 {
209 filename = (const char *)0;
210 functionname = (const char *)0;
211 linenumber = 0;
212 if (bfd_find_nearest_line (STATE_PROG_BFD (sd),
213 STATE_TEXT_SECTION (sd),
214 (struct bfd_symbol **)0,
215 byte_pc - STATE_TEXT_START (sd),
216 &filename, &functionname, &linenumber))
217 {
218 p = buf;
219 if (linenumber)
220 {
221 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
222 p += strlen (p);
223 }
224 else
225 {
226 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
227 p += SIZE_LINE_NUMBER+2;
228 }
229
230 if (functionname)
231 {
232 sprintf (p, "%s ", functionname);
233 p += strlen (p);
234 }
235 else if (filename)
236 {
237 char *q = strrchr (filename, '/');
238 sprintf (p, "%s ", (q) ? q+1 : filename);
239 p += strlen (p);
240 }
241
242 if (*p == ' ')
243 *p = '\0';
244 }
245 }
246
247 sim_io_printf (sd,
248 "0x%.*x %s: %-*.*s %-*s ",
249 SIZE_PC, (unsigned)PC,
250 type,
251 SIZE_LOCATION, SIZE_LOCATION, buf,
252 SIZE_INSTRUCTION, name);
253 }
254
255 in[0] = in1;
256 in[1] = in2;
257 in[2] = in3;
258 comma = "";
259 p = buf;
260 for (i = 0; i < 3; i++)
261 {
262 switch (in[i])
263 {
264 case OP_VOID:
265 case OP_R0:
266 case OP_R1:
267 case OP_R2:
268 break;
269
270 case OP_REG:
271 case OP_REG_OUTPUT:
272 case OP_DREG:
273 case OP_DREG_OUTPUT:
274 sprintf (p, "%sr%d", comma, OP[i]);
275 p += strlen (p);
276 comma = ",";
277 break;
278
279 case OP_CR:
280 case OP_CR_OUTPUT:
281 case OP_CR_REVERSE:
282 sprintf (p, "%scr%d", comma, OP[i]);
283 p += strlen (p);
284 comma = ",";
285 break;
286
287 case OP_ACCUM:
288 case OP_ACCUM_OUTPUT:
289 case OP_ACCUM_REVERSE:
290 sprintf (p, "%sa%d", comma, OP[i]);
291 p += strlen (p);
292 comma = ",";
293 break;
294
295 case OP_CONSTANT16:
296 sprintf (p, "%s%d", comma, OP[i]);
297 p += strlen (p);
298 comma = ",";
299 break;
300
301 case OP_CONSTANT8:
302 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
303 p += strlen (p);
304 comma = ",";
305 break;
306
307 case OP_CONSTANT4:
308 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
309 p += strlen (p);
310 comma = ",";
311 break;
312
313 case OP_CONSTANT3:
314 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
315 p += strlen (p);
316 comma = ",";
317 break;
318
319 case OP_MEMREF:
320 sprintf (p, "%s@r%d", comma, OP[i]);
321 p += strlen (p);
322 comma = ",";
323 break;
324
325 case OP_MEMREF2:
326 sprintf (p, "%s@(%d,r%d)", comma, (int16_t)OP[i], OP[i+1]);
327 p += strlen (p);
328 comma = ",";
329 break;
330
331 case OP_MEMREF3:
332 sprintf (p, "%s@%d", comma, OP[i]);
333 p += strlen (p);
334 comma = ",";
335 break;
336
337 case OP_POSTINC:
338 sprintf (p, "%s@r%d+", comma, OP[i]);
339 p += strlen (p);
340 comma = ",";
341 break;
342
343 case OP_POSTDEC:
344 sprintf (p, "%s@r%d-", comma, OP[i]);
345 p += strlen (p);
346 comma = ",";
347 break;
348
349 case OP_PREDEC:
350 sprintf (p, "%s@-r%d", comma, OP[i]);
351 p += strlen (p);
352 comma = ",";
353 break;
354
355 case OP_FLAG:
356 case OP_FLAG_OUTPUT:
357 if (OP[i] == 0)
358 sprintf (p, "%sf0", comma);
359
360 else if (OP[i] == 1)
361 sprintf (p, "%sf1", comma);
362
363 else
364 sprintf (p, "%sc", comma);
365
366 p += strlen (p);
367 comma = ",";
368 break;
369 }
370 }
371
372 if ((d10v_debug & DEBUG_VALUES) == 0)
373 {
374 *p++ = '\n';
375 *p = '\0';
376 sim_io_printf (sd, "%s", buf);
377 }
378 else
379 {
380 *p = '\0';
381 sim_io_printf (sd, "%-*s", SIZE_OPERANDS, buf);
382
383 p = buf;
384 for (i = 0; i < 3; i++)
385 {
386 buf[0] = '\0';
387 switch (in[i])
388 {
389 case OP_VOID:
390 sim_io_printf (sd, "%*s", SIZE_VALUES, "");
391 break;
392
393 case OP_REG_OUTPUT:
394 case OP_DREG_OUTPUT:
395 case OP_CR_OUTPUT:
396 case OP_ACCUM_OUTPUT:
397 case OP_FLAG_OUTPUT:
398 sim_io_printf (sd, "%*s", SIZE_VALUES, "---");
399 break;
400
401 case OP_REG:
402 case OP_MEMREF:
403 case OP_POSTDEC:
404 case OP_POSTINC:
405 case OP_PREDEC:
406 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
407 (uint16_t) GPR (OP[i]));
408 break;
409
410 case OP_MEMREF3:
411 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16_t) OP[i]);
412 break;
413
414 case OP_DREG:
415 tmp = (long)((((uint32_t) GPR (OP[i])) << 16) | ((uint32_t) GPR (OP[i] + 1)));
416 sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
417 break;
418
419 case OP_CR:
420 case OP_CR_REVERSE:
421 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
422 (uint16_t) CREG (OP[i]));
423 break;
424
425 case OP_ACCUM:
426 case OP_ACCUM_REVERSE:
427 sim_io_printf (sd, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
428 ((int)(ACC (OP[i]) >> 32) & 0xff),
429 ((unsigned long) ACC (OP[i])) & 0xffffffff);
430 break;
431
432 case OP_CONSTANT16:
433 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
434 (uint16_t)OP[i]);
435 break;
436
437 case OP_CONSTANT4:
438 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
439 (uint16_t)SEXT4(OP[i]));
440 break;
441
442 case OP_CONSTANT8:
443 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
444 (uint16_t)SEXT8(OP[i]));
445 break;
446
447 case OP_CONSTANT3:
448 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
449 (uint16_t)SEXT3(OP[i]));
450 break;
451
452 case OP_FLAG:
453 if (OP[i] == 0)
454 sim_io_printf (sd, "%*sF0 = %d", SIZE_VALUES-6, "",
455 PSW_F0 != 0);
456
457 else if (OP[i] == 1)
458 sim_io_printf (sd, "%*sF1 = %d", SIZE_VALUES-6, "",
459 PSW_F1 != 0);
460
461 else
462 sim_io_printf (sd, "%*sC = %d", SIZE_VALUES-5, "",
463 PSW_C != 0);
464
465 break;
466
467 case OP_MEMREF2:
468 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
469 (uint16_t)OP[i]);
470 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
471 (uint16_t)GPR (OP[i + 1]));
472 i++;
473 break;
474
475 case OP_R0:
476 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
477 (uint16_t) GPR (0));
478 break;
479
480 case OP_R1:
481 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
482 (uint16_t) GPR (1));
483 break;
484
485 case OP_R2:
486 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
487 (uint16_t) GPR (2));
488 break;
489
490 }
491 }
492 }
493
494 sim_io_flush_stdout (sd);
495 }
496
497 static void
498 do_trace_output_flush (SIM_DESC sd)
499 {
500 sim_io_flush_stdout (sd);
501 }
502
503 static void
504 do_trace_output_finish (SIM_DESC sd)
505 {
506 sim_io_printf (sd,
507 " F0=%d F1=%d C=%d\n",
508 (State.trace.psw & PSW_F0_BIT) != 0,
509 (State.trace.psw & PSW_F1_BIT) != 0,
510 (State.trace.psw & PSW_C_BIT) != 0);
511 sim_io_flush_stdout (sd);
512 }
513
514 static void
515 trace_output_40 (SIM_DESC sd, uint64_t val)
516 {
517 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
518 {
519 sim_io_printf (sd,
520 " :: %*s0x%.2x%.8lx",
521 SIZE_VALUES - 12,
522 "",
523 ((int)(val >> 32) & 0xff),
524 ((unsigned long) val) & 0xffffffff);
525 do_trace_output_finish (sd);
526 }
527 }
528
529 static void
530 trace_output_32 (SIM_DESC sd, uint32_t val)
531 {
532 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
533 {
534 sim_io_printf (sd,
535 " :: %*s0x%.8x",
536 SIZE_VALUES - 10,
537 "",
538 (int) val);
539 do_trace_output_finish (sd);
540 }
541 }
542
543 static void
544 trace_output_16 (SIM_DESC sd, uint16_t val)
545 {
546 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
547 {
548 sim_io_printf (sd,
549 " :: %*s0x%.4x",
550 SIZE_VALUES - 6,
551 "",
552 (int) val);
553 do_trace_output_finish (sd);
554 }
555 }
556
557 static void
558 trace_output_void (SIM_DESC sd)
559 {
560 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
561 {
562 sim_io_printf (sd, "\n");
563 do_trace_output_flush (sd);
564 }
565 }
566
567 static void
568 trace_output_flag (SIM_DESC sd)
569 {
570 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
571 {
572 sim_io_printf (sd,
573 " :: %*s",
574 SIZE_VALUES,
575 "");
576 do_trace_output_finish (sd);
577 }
578 }
579
580
581
582
583 #else
584 #define trace_input(NAME, IN1, IN2, IN3)
585 #define trace_output(RESULT)
586 #endif
587
588 /* abs */
589 void
590 OP_4607 (SIM_DESC sd, SIM_CPU *cpu)
591 {
592 int16_t tmp;
593 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
594 SET_PSW_F1 (PSW_F0);
595 tmp = GPR(OP[0]);
596 if (tmp < 0)
597 {
598 tmp = - tmp;
599 SET_PSW_F0 (1);
600 }
601 else
602 SET_PSW_F0 (0);
603 SET_GPR (OP[0], tmp);
604 trace_output_16 (sd, tmp);
605 }
606
607 /* abs */
608 void
609 OP_5607 (SIM_DESC sd, SIM_CPU *cpu)
610 {
611 int64_t tmp;
612 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
613 SET_PSW_F1 (PSW_F0);
614
615 tmp = SEXT40 (ACC (OP[0]));
616 if (tmp < 0 )
617 {
618 tmp = - tmp;
619 if (PSW_ST)
620 {
621 if (tmp > SEXT40(MAX32))
622 tmp = (MAX32);
623 else if (tmp < SEXT40(MIN32))
624 tmp = (MIN32);
625 else
626 tmp = (tmp & MASK40);
627 }
628 else
629 tmp = (tmp & MASK40);
630 SET_PSW_F0 (1);
631 }
632 else
633 {
634 tmp = (tmp & MASK40);
635 SET_PSW_F0 (0);
636 }
637 SET_ACC (OP[0], tmp);
638 trace_output_40 (sd, tmp);
639 }
640
641 /* add */
642 void
643 OP_200 (SIM_DESC sd, SIM_CPU *cpu)
644 {
645 uint16_t a = GPR (OP[0]);
646 uint16_t b = GPR (OP[1]);
647 uint16_t tmp = (a + b);
648 trace_input ("add", OP_REG, OP_REG, OP_VOID);
649 SET_PSW_C (a > tmp);
650 SET_GPR (OP[0], tmp);
651 trace_output_16 (sd, tmp);
652 }
653
654 /* add */
655 void
656 OP_1201 (SIM_DESC sd, SIM_CPU *cpu)
657 {
658 int64_t tmp;
659 tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
660
661 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
662 if (PSW_ST)
663 {
664 if (tmp > SEXT40(MAX32))
665 tmp = (MAX32);
666 else if (tmp < SEXT40(MIN32))
667 tmp = (MIN32);
668 else
669 tmp = (tmp & MASK40);
670 }
671 else
672 tmp = (tmp & MASK40);
673 SET_ACC (OP[0], tmp);
674 trace_output_40 (sd, tmp);
675 }
676
677 /* add */
678 void
679 OP_1203 (SIM_DESC sd, SIM_CPU *cpu)
680 {
681 int64_t tmp;
682 tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
683
684 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
685 if (PSW_ST)
686 {
687 if (tmp > SEXT40(MAX32))
688 tmp = (MAX32);
689 else if (tmp < SEXT40(MIN32))
690 tmp = (MIN32);
691 else
692 tmp = (tmp & MASK40);
693 }
694 else
695 tmp = (tmp & MASK40);
696 SET_ACC (OP[0], tmp);
697 trace_output_40 (sd, tmp);
698 }
699
700 /* add2w */
701 void
702 OP_1200 (SIM_DESC sd, SIM_CPU *cpu)
703 {
704 uint32_t tmp;
705 uint32_t a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
706 uint32_t b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
707 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
708 tmp = a + b;
709 SET_PSW_C (tmp < a);
710 SET_GPR (OP[0] + 0, (tmp >> 16));
711 SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
712 trace_output_32 (sd, tmp);
713 }
714
715 /* add3 */
716 void
717 OP_1000000 (SIM_DESC sd, SIM_CPU *cpu)
718 {
719 uint16_t a = GPR (OP[1]);
720 uint16_t b = OP[2];
721 uint16_t tmp = (a + b);
722 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
723 SET_PSW_C (tmp < a);
724 SET_GPR (OP[0], tmp);
725 trace_output_16 (sd, tmp);
726 }
727
728 /* addac3 */
729 void
730 OP_17000200 (SIM_DESC sd, SIM_CPU *cpu)
731 {
732 int64_t tmp;
733 tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
734
735 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
736 SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
737 SET_GPR (OP[0] + 1, (tmp & 0xffff));
738 trace_output_32 (sd, tmp);
739 }
740
741 /* addac3 */
742 void
743 OP_17000202 (SIM_DESC sd, SIM_CPU *cpu)
744 {
745 int64_t tmp;
746 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
747
748 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
749 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
750 SET_GPR (OP[0] + 1, tmp & 0xffff);
751 trace_output_32 (sd, tmp);
752 }
753
754 /* addac3s */
755 void
756 OP_17001200 (SIM_DESC sd, SIM_CPU *cpu)
757 {
758 int64_t tmp;
759 SET_PSW_F1 (PSW_F0);
760
761 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
762 tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
763 if (tmp > SEXT40(MAX32))
764 {
765 tmp = (MAX32);
766 SET_PSW_F0 (1);
767 }
768 else if (tmp < SEXT40(MIN32))
769 {
770 tmp = (MIN32);
771 SET_PSW_F0 (1);
772 }
773 else
774 {
775 SET_PSW_F0 (0);
776 }
777 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
778 SET_GPR (OP[0] + 1, (tmp & 0xffff));
779 trace_output_32 (sd, tmp);
780 }
781
782 /* addac3s */
783 void
784 OP_17001202 (SIM_DESC sd, SIM_CPU *cpu)
785 {
786 int64_t tmp;
787 SET_PSW_F1 (PSW_F0);
788
789 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
790 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
791 if (tmp > SEXT40(MAX32))
792 {
793 tmp = (MAX32);
794 SET_PSW_F0 (1);
795 }
796 else if (tmp < SEXT40(MIN32))
797 {
798 tmp = (MIN32);
799 SET_PSW_F0 (1);
800 }
801 else
802 {
803 SET_PSW_F0 (0);
804 }
805 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
806 SET_GPR (OP[0] + 1, (tmp & 0xffff));
807 trace_output_32 (sd, tmp);
808 }
809
810 /* addi */
811 void
812 OP_201 (SIM_DESC sd, SIM_CPU *cpu)
813 {
814 uint16_t a = GPR (OP[0]);
815 uint16_t b;
816 uint16_t tmp;
817 if (OP[1] == 0)
818 OP[1] = 16;
819 b = OP[1];
820 tmp = (a + b);
821 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
822 SET_PSW_C (tmp < a);
823 SET_GPR (OP[0], tmp);
824 trace_output_16 (sd, tmp);
825 }
826
827 /* and */
828 void
829 OP_C00 (SIM_DESC sd, SIM_CPU *cpu)
830 {
831 uint16_t tmp = GPR (OP[0]) & GPR (OP[1]);
832 trace_input ("and", OP_REG, OP_REG, OP_VOID);
833 SET_GPR (OP[0], tmp);
834 trace_output_16 (sd, tmp);
835 }
836
837 /* and3 */
838 void
839 OP_6000000 (SIM_DESC sd, SIM_CPU *cpu)
840 {
841 uint16_t tmp = GPR (OP[1]) & OP[2];
842 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
843 SET_GPR (OP[0], tmp);
844 trace_output_16 (sd, tmp);
845 }
846
847 /* bclri */
848 void
849 OP_C01 (SIM_DESC sd, SIM_CPU *cpu)
850 {
851 int16_t tmp;
852 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
853 tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
854 SET_GPR (OP[0], tmp);
855 trace_output_16 (sd, tmp);
856 }
857
858 /* bl.s */
859 void
860 OP_4900 (SIM_DESC sd, SIM_CPU *cpu)
861 {
862 trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
863 SET_GPR (13, PC + 1);
864 JMP( PC + SEXT8 (OP[0]));
865 trace_output_void (sd);
866 }
867
868 /* bl.l */
869 void
870 OP_24800000 (SIM_DESC sd, SIM_CPU *cpu)
871 {
872 trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
873 SET_GPR (13, (PC + 1));
874 JMP (PC + OP[0]);
875 trace_output_void (sd);
876 }
877
878 /* bnoti */
879 void
880 OP_A01 (SIM_DESC sd, SIM_CPU *cpu)
881 {
882 int16_t tmp;
883 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
884 tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
885 SET_GPR (OP[0], tmp);
886 trace_output_16 (sd, tmp);
887 }
888
889 /* bra.s */
890 void
891 OP_4800 (SIM_DESC sd, SIM_CPU *cpu)
892 {
893 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
894 JMP (PC + SEXT8 (OP[0]));
895 trace_output_void (sd);
896 }
897
898 /* bra.l */
899 void
900 OP_24000000 (SIM_DESC sd, SIM_CPU *cpu)
901 {
902 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
903 JMP (PC + OP[0]);
904 trace_output_void (sd);
905 }
906
907 /* brf0f.s */
908 void
909 OP_4A00 (SIM_DESC sd, SIM_CPU *cpu)
910 {
911 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
912 if (!PSW_F0)
913 JMP (PC + SEXT8 (OP[0]));
914 trace_output_flag (sd);
915 }
916
917 /* brf0f.l */
918 void
919 OP_25000000 (SIM_DESC sd, SIM_CPU *cpu)
920 {
921 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
922 if (!PSW_F0)
923 JMP (PC + OP[0]);
924 trace_output_flag (sd);
925 }
926
927 /* brf0t.s */
928 void
929 OP_4B00 (SIM_DESC sd, SIM_CPU *cpu)
930 {
931 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
932 if (PSW_F0)
933 JMP (PC + SEXT8 (OP[0]));
934 trace_output_flag (sd);
935 }
936
937 /* brf0t.l */
938 void
939 OP_25800000 (SIM_DESC sd, SIM_CPU *cpu)
940 {
941 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
942 if (PSW_F0)
943 JMP (PC + OP[0]);
944 trace_output_flag (sd);
945 }
946
947 /* bseti */
948 void
949 OP_801 (SIM_DESC sd, SIM_CPU *cpu)
950 {
951 int16_t tmp;
952 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
953 tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
954 SET_GPR (OP[0], tmp);
955 trace_output_16 (sd, tmp);
956 }
957
958 /* btsti */
959 void
960 OP_E01 (SIM_DESC sd, SIM_CPU *cpu)
961 {
962 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
963 SET_PSW_F1 (PSW_F0);
964 SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
965 trace_output_flag (sd);
966 }
967
968 /* clrac */
969 void
970 OP_5601 (SIM_DESC sd, SIM_CPU *cpu)
971 {
972 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
973 SET_ACC (OP[0], 0);
974 trace_output_40 (sd, 0);
975 }
976
977 /* cmp */
978 void
979 OP_600 (SIM_DESC sd, SIM_CPU *cpu)
980 {
981 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
982 SET_PSW_F1 (PSW_F0);
983 SET_PSW_F0 (((int16_t)(GPR (OP[0])) < (int16_t)(GPR (OP[1]))) ? 1 : 0);
984 trace_output_flag (sd);
985 }
986
987 /* cmp */
988 void
989 OP_1603 (SIM_DESC sd, SIM_CPU *cpu)
990 {
991 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
992 SET_PSW_F1 (PSW_F0);
993 SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
994 trace_output_flag (sd);
995 }
996
997 /* cmpeq */
998 void
999 OP_400 (SIM_DESC sd, SIM_CPU *cpu)
1000 {
1001 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
1002 SET_PSW_F1 (PSW_F0);
1003 SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
1004 trace_output_flag (sd);
1005 }
1006
1007 /* cmpeq */
1008 void
1009 OP_1403 (SIM_DESC sd, SIM_CPU *cpu)
1010 {
1011 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
1012 SET_PSW_F1 (PSW_F0);
1013 SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
1014 trace_output_flag (sd);
1015 }
1016
1017 /* cmpeqi.s */
1018 void
1019 OP_401 (SIM_DESC sd, SIM_CPU *cpu)
1020 {
1021 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1022 SET_PSW_F1 (PSW_F0);
1023 SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
1024 trace_output_flag (sd);
1025 }
1026
1027 /* cmpeqi.l */
1028 void
1029 OP_2000000 (SIM_DESC sd, SIM_CPU *cpu)
1030 {
1031 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1032 SET_PSW_F1 (PSW_F0);
1033 SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1034 trace_output_flag (sd);
1035 }
1036
1037 /* cmpi.s */
1038 void
1039 OP_601 (SIM_DESC sd, SIM_CPU *cpu)
1040 {
1041 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1042 SET_PSW_F1 (PSW_F0);
1043 SET_PSW_F0 (((int16_t)(GPR (OP[0])) < (int16_t)SEXT4(OP[1])) ? 1 : 0);
1044 trace_output_flag (sd);
1045 }
1046
1047 /* cmpi.l */
1048 void
1049 OP_3000000 (SIM_DESC sd, SIM_CPU *cpu)
1050 {
1051 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1052 SET_PSW_F1 (PSW_F0);
1053 SET_PSW_F0 (((int16_t)(GPR (OP[0])) < (int16_t)(OP[1])) ? 1 : 0);
1054 trace_output_flag (sd);
1055 }
1056
1057 /* cmpu */
1058 void
1059 OP_4600 (SIM_DESC sd, SIM_CPU *cpu)
1060 {
1061 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
1062 SET_PSW_F1 (PSW_F0);
1063 SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
1064 trace_output_flag (sd);
1065 }
1066
1067 /* cmpui */
1068 void
1069 OP_23000000 (SIM_DESC sd, SIM_CPU *cpu)
1070 {
1071 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
1072 SET_PSW_F1 (PSW_F0);
1073 SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
1074 trace_output_flag (sd);
1075 }
1076
1077 /* cpfg */
1078 void
1079 OP_4E09 (SIM_DESC sd, SIM_CPU *cpu)
1080 {
1081 uint8_t val;
1082
1083 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1084
1085 if (OP[1] == 0)
1086 val = PSW_F0;
1087 else if (OP[1] == 1)
1088 val = PSW_F1;
1089 else
1090 val = PSW_C;
1091 if (OP[0] == 0)
1092 SET_PSW_F0 (val);
1093 else
1094 SET_PSW_F1 (val);
1095
1096 trace_output_flag (sd);
1097 }
1098
1099 /* cpfg */
1100 void
1101 OP_4E0F (SIM_DESC sd, SIM_CPU *cpu)
1102 {
1103 uint8_t val;
1104
1105 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1106
1107 if (OP[1] == 0)
1108 val = PSW_F0;
1109 else if (OP[1] == 1)
1110 val = PSW_F1;
1111 else
1112 val = PSW_C;
1113 if (OP[0] == 0)
1114 SET_PSW_F0 (val);
1115 else
1116 SET_PSW_F1 (val);
1117
1118 trace_output_flag (sd);
1119 }
1120
1121 /* dbt */
1122 void
1123 OP_5F20 (SIM_DESC sd, SIM_CPU *cpu)
1124 {
1125 /* sim_io_printf (sd, "***** DBT ***** PC=%x\n",PC); */
1126
1127 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1128 The conditional below is for either of the instruction pairs
1129 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1130 where the dbt instruction should be interpreted.
1131
1132 The module `sim-break' provides a more effective mechanism for
1133 detecting GDB planted breakpoints. The code below may,
1134 eventually, be changed to use that mechanism. */
1135
1136 if (State.ins_type == INS_LEFT
1137 || State.ins_type == INS_RIGHT)
1138 {
1139 trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
1140 SET_DPC (PC + 1);
1141 SET_DPSW (PSW);
1142 SET_HW_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
1143 JMP (DBT_VECTOR_START);
1144 trace_output_void (sd);
1145 }
1146 else
1147 sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGTRAP);
1148 }
1149
1150 /* divs */
1151 void
1152 OP_14002800 (SIM_DESC sd, SIM_CPU *cpu)
1153 {
1154 uint16_t foo, tmp, tmpf;
1155 uint16_t hi;
1156 uint16_t lo;
1157
1158 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1159 foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
1160 tmp = (int16_t)foo - (int16_t)(GPR (OP[1]));
1161 tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
1162 hi = ((tmpf == 1) ? tmp : foo);
1163 lo = ((GPR (OP[0] + 1) << 1) | tmpf);
1164 SET_GPR (OP[0] + 0, hi);
1165 SET_GPR (OP[0] + 1, lo);
1166 trace_output_32 (sd, ((uint32_t) hi << 16) | lo);
1167 }
1168
1169 /* exef0f */
1170 void
1171 OP_4E04 (SIM_DESC sd, SIM_CPU *cpu)
1172 {
1173 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1174 State.exe = (PSW_F0 == 0);
1175 trace_output_flag (sd);
1176 }
1177
1178 /* exef0t */
1179 void
1180 OP_4E24 (SIM_DESC sd, SIM_CPU *cpu)
1181 {
1182 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1183 State.exe = (PSW_F0 != 0);
1184 trace_output_flag (sd);
1185 }
1186
1187 /* exef1f */
1188 void
1189 OP_4E40 (SIM_DESC sd, SIM_CPU *cpu)
1190 {
1191 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1192 State.exe = (PSW_F1 == 0);
1193 trace_output_flag (sd);
1194 }
1195
1196 /* exef1t */
1197 void
1198 OP_4E42 (SIM_DESC sd, SIM_CPU *cpu)
1199 {
1200 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1201 State.exe = (PSW_F1 != 0);
1202 trace_output_flag (sd);
1203 }
1204
1205 /* exefaf */
1206 void
1207 OP_4E00 (SIM_DESC sd, SIM_CPU *cpu)
1208 {
1209 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1210 State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
1211 trace_output_flag (sd);
1212 }
1213
1214 /* exefat */
1215 void
1216 OP_4E02 (SIM_DESC sd, SIM_CPU *cpu)
1217 {
1218 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1219 State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
1220 trace_output_flag (sd);
1221 }
1222
1223 /* exetaf */
1224 void
1225 OP_4E20 (SIM_DESC sd, SIM_CPU *cpu)
1226 {
1227 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1228 State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
1229 trace_output_flag (sd);
1230 }
1231
1232 /* exetat */
1233 void
1234 OP_4E22 (SIM_DESC sd, SIM_CPU *cpu)
1235 {
1236 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1237 State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
1238 trace_output_flag (sd);
1239 }
1240
1241 /* exp */
1242 void
1243 OP_15002A00 (SIM_DESC sd, SIM_CPU *cpu)
1244 {
1245 uint32_t tmp, foo;
1246 int i;
1247
1248 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1249 if (((int16_t)GPR (OP[1])) >= 0)
1250 tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
1251 else
1252 tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
1253
1254 foo = 0x40000000;
1255 for (i=1;i<17;i++)
1256 {
1257 if (tmp & foo)
1258 {
1259 SET_GPR (OP[0], (i - 1));
1260 trace_output_16 (sd, i - 1);
1261 return;
1262 }
1263 foo >>= 1;
1264 }
1265 SET_GPR (OP[0], 16);
1266 trace_output_16 (sd, 16);
1267 }
1268
1269 /* exp */
1270 void
1271 OP_15002A02 (SIM_DESC sd, SIM_CPU *cpu)
1272 {
1273 int64_t tmp, foo;
1274 int i;
1275
1276 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1277 tmp = SEXT40(ACC (OP[1]));
1278 if (tmp < 0)
1279 tmp = ~tmp & MASK40;
1280
1281 foo = 0x4000000000LL;
1282 for (i=1;i<25;i++)
1283 {
1284 if (tmp & foo)
1285 {
1286 SET_GPR (OP[0], i - 9);
1287 trace_output_16 (sd, i - 9);
1288 return;
1289 }
1290 foo >>= 1;
1291 }
1292 SET_GPR (OP[0], 16);
1293 trace_output_16 (sd, 16);
1294 }
1295
1296 /* jl */
1297 void
1298 OP_4D00 (SIM_DESC sd, SIM_CPU *cpu)
1299 {
1300 trace_input ("jl", OP_REG, OP_R0, OP_R1);
1301 SET_GPR (13, PC + 1);
1302 JMP (GPR (OP[0]));
1303 trace_output_void (sd);
1304 }
1305
1306 /* jmp */
1307 void
1308 OP_4C00 (SIM_DESC sd, SIM_CPU *cpu)
1309 {
1310 trace_input ("jmp", OP_REG,
1311 (OP[0] == 13) ? OP_R0 : OP_VOID,
1312 (OP[0] == 13) ? OP_R1 : OP_VOID);
1313
1314 JMP (GPR (OP[0]));
1315 trace_output_void (sd);
1316 }
1317
1318 /* ld */
1319 void
1320 OP_30000000 (SIM_DESC sd, SIM_CPU *cpu)
1321 {
1322 uint16_t tmp;
1323 uint16_t addr = OP[1] + GPR (OP[2]);
1324 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1325 if ((addr & 1))
1326 {
1327 trace_output_void (sd);
1328 EXCEPTION (SIM_SIGBUS);
1329 }
1330 tmp = RW (addr);
1331 SET_GPR (OP[0], tmp);
1332 trace_output_16 (sd, tmp);
1333 }
1334
1335 /* ld */
1336 void
1337 OP_6401 (SIM_DESC sd, SIM_CPU *cpu)
1338 {
1339 uint16_t tmp;
1340 uint16_t addr = GPR (OP[1]);
1341 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1342 if ((addr & 1))
1343 {
1344 trace_output_void (sd);
1345 EXCEPTION (SIM_SIGBUS);
1346 }
1347 tmp = RW (addr);
1348 SET_GPR (OP[0], tmp);
1349 if (OP[0] != OP[1])
1350 INC_ADDR (OP[1], -2);
1351 trace_output_16 (sd, tmp);
1352 }
1353
1354 /* ld */
1355 void
1356 OP_6001 (SIM_DESC sd, SIM_CPU *cpu)
1357 {
1358 uint16_t tmp;
1359 uint16_t addr = GPR (OP[1]);
1360 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1361 if ((addr & 1))
1362 {
1363 trace_output_void (sd);
1364 EXCEPTION (SIM_SIGBUS);
1365 }
1366 tmp = RW (addr);
1367 SET_GPR (OP[0], tmp);
1368 if (OP[0] != OP[1])
1369 INC_ADDR (OP[1], 2);
1370 trace_output_16 (sd, tmp);
1371 }
1372
1373 /* ld */
1374 void
1375 OP_6000 (SIM_DESC sd, SIM_CPU *cpu)
1376 {
1377 uint16_t tmp;
1378 uint16_t addr = GPR (OP[1]);
1379 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1380 if ((addr & 1))
1381 {
1382 trace_output_void (sd);
1383 EXCEPTION (SIM_SIGBUS);
1384 }
1385 tmp = RW (addr);
1386 SET_GPR (OP[0], tmp);
1387 trace_output_16 (sd, tmp);
1388 }
1389
1390 /* ld */
1391 void
1392 OP_32010000 (SIM_DESC sd, SIM_CPU *cpu)
1393 {
1394 uint16_t tmp;
1395 uint16_t addr = OP[1];
1396 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1397 if ((addr & 1))
1398 {
1399 trace_output_void (sd);
1400 EXCEPTION (SIM_SIGBUS);
1401 }
1402 tmp = RW (addr);
1403 SET_GPR (OP[0], tmp);
1404 trace_output_16 (sd, tmp);
1405 }
1406
1407 /* ld2w */
1408 void
1409 OP_31000000 (SIM_DESC sd, SIM_CPU *cpu)
1410 {
1411 int32_t tmp;
1412 uint16_t addr = OP[1] + GPR (OP[2]);
1413 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1414 if ((addr & 1))
1415 {
1416 trace_output_void (sd);
1417 EXCEPTION (SIM_SIGBUS);
1418 }
1419 tmp = RLW (addr);
1420 SET_GPR32 (OP[0], tmp);
1421 trace_output_32 (sd, tmp);
1422 }
1423
1424 /* ld2w */
1425 void
1426 OP_6601 (SIM_DESC sd, SIM_CPU *cpu)
1427 {
1428 uint16_t addr = GPR (OP[1]);
1429 int32_t tmp;
1430 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1431 if ((addr & 1))
1432 {
1433 trace_output_void (sd);
1434 EXCEPTION (SIM_SIGBUS);
1435 }
1436 tmp = RLW (addr);
1437 SET_GPR32 (OP[0], tmp);
1438 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1439 INC_ADDR (OP[1], -4);
1440 trace_output_32 (sd, tmp);
1441 }
1442
1443 /* ld2w */
1444 void
1445 OP_6201 (SIM_DESC sd, SIM_CPU *cpu)
1446 {
1447 int32_t tmp;
1448 uint16_t addr = GPR (OP[1]);
1449 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1450 if ((addr & 1))
1451 {
1452 trace_output_void (sd);
1453 EXCEPTION (SIM_SIGBUS);
1454 }
1455 tmp = RLW (addr);
1456 SET_GPR32 (OP[0], tmp);
1457 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1458 INC_ADDR (OP[1], 4);
1459 trace_output_32 (sd, tmp);
1460 }
1461
1462 /* ld2w */
1463 void
1464 OP_6200 (SIM_DESC sd, SIM_CPU *cpu)
1465 {
1466 uint16_t addr = GPR (OP[1]);
1467 int32_t tmp;
1468 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1469 if ((addr & 1))
1470 {
1471 trace_output_void (sd);
1472 EXCEPTION (SIM_SIGBUS);
1473 }
1474 tmp = RLW (addr);
1475 SET_GPR32 (OP[0], tmp);
1476 trace_output_32 (sd, tmp);
1477 }
1478
1479 /* ld2w */
1480 void
1481 OP_33010000 (SIM_DESC sd, SIM_CPU *cpu)
1482 {
1483 int32_t tmp;
1484 uint16_t addr = OP[1];
1485 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1486 if ((addr & 1))
1487 {
1488 trace_output_void (sd);
1489 EXCEPTION (SIM_SIGBUS);
1490 }
1491 tmp = RLW (addr);
1492 SET_GPR32 (OP[0], tmp);
1493 trace_output_32 (sd, tmp);
1494 }
1495
1496 /* ldb */
1497 void
1498 OP_38000000 (SIM_DESC sd, SIM_CPU *cpu)
1499 {
1500 int16_t tmp;
1501 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1502 tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
1503 SET_GPR (OP[0], tmp);
1504 trace_output_16 (sd, tmp);
1505 }
1506
1507 /* ldb */
1508 void
1509 OP_7000 (SIM_DESC sd, SIM_CPU *cpu)
1510 {
1511 int16_t tmp;
1512 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1513 tmp = SEXT8 (RB (GPR (OP[1])));
1514 SET_GPR (OP[0], tmp);
1515 trace_output_16 (sd, tmp);
1516 }
1517
1518 /* ldi.s */
1519 void
1520 OP_4001 (SIM_DESC sd, SIM_CPU *cpu)
1521 {
1522 int16_t tmp;
1523 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1524 tmp = SEXT4 (OP[1]);
1525 SET_GPR (OP[0], tmp);
1526 trace_output_16 (sd, tmp);
1527 }
1528
1529 /* ldi.l */
1530 void
1531 OP_20000000 (SIM_DESC sd, SIM_CPU *cpu)
1532 {
1533 int16_t tmp;
1534 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1535 tmp = OP[1];
1536 SET_GPR (OP[0], tmp);
1537 trace_output_16 (sd, tmp);
1538 }
1539
1540 /* ldub */
1541 void
1542 OP_39000000 (SIM_DESC sd, SIM_CPU *cpu)
1543 {
1544 int16_t tmp;
1545 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1546 tmp = RB (OP[1] + GPR (OP[2]));
1547 SET_GPR (OP[0], tmp);
1548 trace_output_16 (sd, tmp);
1549 }
1550
1551 /* ldub */
1552 void
1553 OP_7200 (SIM_DESC sd, SIM_CPU *cpu)
1554 {
1555 int16_t tmp;
1556 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1557 tmp = RB (GPR (OP[1]));
1558 SET_GPR (OP[0], tmp);
1559 trace_output_16 (sd, tmp);
1560 }
1561
1562 /* mac */
1563 void
1564 OP_2A00 (SIM_DESC sd, SIM_CPU *cpu)
1565 {
1566 int64_t tmp;
1567
1568 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1569 tmp = SEXT40 ((int16_t)(GPR (OP[1])) * (int16_t)(GPR (OP[2])));
1570
1571 if (PSW_FX)
1572 tmp = SEXT40( (tmp << 1) & MASK40);
1573
1574 if (PSW_ST && tmp > SEXT40(MAX32))
1575 tmp = (MAX32);
1576
1577 tmp += SEXT40 (ACC (OP[0]));
1578 if (PSW_ST)
1579 {
1580 if (tmp > SEXT40(MAX32))
1581 tmp = (MAX32);
1582 else if (tmp < SEXT40(MIN32))
1583 tmp = (MIN32);
1584 else
1585 tmp = (tmp & MASK40);
1586 }
1587 else
1588 tmp = (tmp & MASK40);
1589 SET_ACC (OP[0], tmp);
1590 trace_output_40 (sd, tmp);
1591 }
1592
1593 /* macsu */
1594 void
1595 OP_1A00 (SIM_DESC sd, SIM_CPU *cpu)
1596 {
1597 int64_t tmp;
1598
1599 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1600 tmp = SEXT40 ((int16_t) GPR (OP[1]) * GPR (OP[2]));
1601 if (PSW_FX)
1602 tmp = SEXT40 ((tmp << 1) & MASK40);
1603 tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
1604 SET_ACC (OP[0], tmp);
1605 trace_output_40 (sd, tmp);
1606 }
1607
1608 /* macu */
1609 void
1610 OP_3A00 (SIM_DESC sd, SIM_CPU *cpu)
1611 {
1612 uint64_t tmp;
1613 uint32_t src1;
1614 uint32_t src2;
1615
1616 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1617 src1 = (uint16_t) GPR (OP[1]);
1618 src2 = (uint16_t) GPR (OP[2]);
1619 tmp = src1 * src2;
1620 if (PSW_FX)
1621 tmp = (tmp << 1);
1622 tmp = ((ACC (OP[0]) + tmp) & MASK40);
1623 SET_ACC (OP[0], tmp);
1624 trace_output_40 (sd, tmp);
1625 }
1626
1627 /* max */
1628 void
1629 OP_2600 (SIM_DESC sd, SIM_CPU *cpu)
1630 {
1631 int16_t tmp;
1632 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1633 SET_PSW_F1 (PSW_F0);
1634 if ((int16_t) GPR (OP[1]) > (int16_t)GPR (OP[0]))
1635 {
1636 tmp = GPR (OP[1]);
1637 SET_PSW_F0 (1);
1638 }
1639 else
1640 {
1641 tmp = GPR (OP[0]);
1642 SET_PSW_F0 (0);
1643 }
1644 SET_GPR (OP[0], tmp);
1645 trace_output_16 (sd, tmp);
1646 }
1647
1648 /* max */
1649 void
1650 OP_3600 (SIM_DESC sd, SIM_CPU *cpu)
1651 {
1652 int64_t tmp;
1653
1654 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1655 SET_PSW_F1 (PSW_F0);
1656 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1657 if (tmp > SEXT40 (ACC (OP[0])))
1658 {
1659 tmp = (tmp & MASK40);
1660 SET_PSW_F0 (1);
1661 }
1662 else
1663 {
1664 tmp = ACC (OP[0]);
1665 SET_PSW_F0 (0);
1666 }
1667 SET_ACC (OP[0], tmp);
1668 trace_output_40 (sd, tmp);
1669 }
1670
1671 /* max */
1672 void
1673 OP_3602 (SIM_DESC sd, SIM_CPU *cpu)
1674 {
1675 int64_t tmp;
1676 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1677 SET_PSW_F1 (PSW_F0);
1678 if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
1679 {
1680 tmp = ACC (OP[1]);
1681 SET_PSW_F0 (1);
1682 }
1683 else
1684 {
1685 tmp = ACC (OP[0]);
1686 SET_PSW_F0 (0);
1687 }
1688 SET_ACC (OP[0], tmp);
1689 trace_output_40 (sd, tmp);
1690 }
1691
1692
1693 /* min */
1694 void
1695 OP_2601 (SIM_DESC sd, SIM_CPU *cpu)
1696 {
1697 int16_t tmp;
1698 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1699 SET_PSW_F1 (PSW_F0);
1700 if ((int16_t)GPR (OP[1]) < (int16_t)GPR (OP[0]))
1701 {
1702 tmp = GPR (OP[1]);
1703 SET_PSW_F0 (1);
1704 }
1705 else
1706 {
1707 tmp = GPR (OP[0]);
1708 SET_PSW_F0 (0);
1709 }
1710 SET_GPR (OP[0], tmp);
1711 trace_output_16 (sd, tmp);
1712 }
1713
1714 /* min */
1715 void
1716 OP_3601 (SIM_DESC sd, SIM_CPU *cpu)
1717 {
1718 int64_t tmp;
1719
1720 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1721 SET_PSW_F1 (PSW_F0);
1722 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1723 if (tmp < SEXT40(ACC (OP[0])))
1724 {
1725 tmp = (tmp & MASK40);
1726 SET_PSW_F0 (1);
1727 }
1728 else
1729 {
1730 tmp = ACC (OP[0]);
1731 SET_PSW_F0 (0);
1732 }
1733 SET_ACC (OP[0], tmp);
1734 trace_output_40 (sd, tmp);
1735 }
1736
1737 /* min */
1738 void
1739 OP_3603 (SIM_DESC sd, SIM_CPU *cpu)
1740 {
1741 int64_t tmp;
1742 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1743 SET_PSW_F1 (PSW_F0);
1744 if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
1745 {
1746 tmp = ACC (OP[1]);
1747 SET_PSW_F0 (1);
1748 }
1749 else
1750 {
1751 tmp = ACC (OP[0]);
1752 SET_PSW_F0 (0);
1753 }
1754 SET_ACC (OP[0], tmp);
1755 trace_output_40 (sd, tmp);
1756 }
1757
1758 /* msb */
1759 void
1760 OP_2800 (SIM_DESC sd, SIM_CPU *cpu)
1761 {
1762 int64_t tmp;
1763
1764 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1765 tmp = SEXT40 ((int16_t)(GPR (OP[1])) * (int16_t)(GPR (OP[2])));
1766
1767 if (PSW_FX)
1768 tmp = SEXT40 ((tmp << 1) & MASK40);
1769
1770 if (PSW_ST && tmp > SEXT40(MAX32))
1771 tmp = (MAX32);
1772
1773 tmp = SEXT40(ACC (OP[0])) - tmp;
1774 if (PSW_ST)
1775 {
1776 if (tmp > SEXT40(MAX32))
1777 tmp = (MAX32);
1778 else if (tmp < SEXT40(MIN32))
1779 tmp = (MIN32);
1780 else
1781 tmp = (tmp & MASK40);
1782 }
1783 else
1784 {
1785 tmp = (tmp & MASK40);
1786 }
1787 SET_ACC (OP[0], tmp);
1788 trace_output_40 (sd, tmp);
1789 }
1790
1791 /* msbsu */
1792 void
1793 OP_1800 (SIM_DESC sd, SIM_CPU *cpu)
1794 {
1795 int64_t tmp;
1796
1797 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1798 tmp = SEXT40 ((int16_t)GPR (OP[1]) * GPR (OP[2]));
1799 if (PSW_FX)
1800 tmp = SEXT40( (tmp << 1) & MASK40);
1801 tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
1802 SET_ACC (OP[0], tmp);
1803 trace_output_40 (sd, tmp);
1804 }
1805
1806 /* msbu */
1807 void
1808 OP_3800 (SIM_DESC sd, SIM_CPU *cpu)
1809 {
1810 uint64_t tmp;
1811 uint32_t src1;
1812 uint32_t src2;
1813
1814 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1815 src1 = (uint16_t) GPR (OP[1]);
1816 src2 = (uint16_t) GPR (OP[2]);
1817 tmp = src1 * src2;
1818 if (PSW_FX)
1819 tmp = (tmp << 1);
1820 tmp = ((ACC (OP[0]) - tmp) & MASK40);
1821 SET_ACC (OP[0], tmp);
1822 trace_output_40 (sd, tmp);
1823 }
1824
1825 /* mul */
1826 void
1827 OP_2E00 (SIM_DESC sd, SIM_CPU *cpu)
1828 {
1829 int16_t tmp;
1830 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1831 tmp = GPR (OP[0]) * GPR (OP[1]);
1832 SET_GPR (OP[0], tmp);
1833 trace_output_16 (sd, tmp);
1834 }
1835
1836 /* mulx */
1837 void
1838 OP_2C00 (SIM_DESC sd, SIM_CPU *cpu)
1839 {
1840 int64_t tmp;
1841
1842 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1843 tmp = SEXT40 ((int16_t)(GPR (OP[1])) * (int16_t)(GPR (OP[2])));
1844
1845 if (PSW_FX)
1846 tmp = SEXT40 ((tmp << 1) & MASK40);
1847
1848 if (PSW_ST && tmp > SEXT40(MAX32))
1849 tmp = (MAX32);
1850 else
1851 tmp = (tmp & MASK40);
1852 SET_ACC (OP[0], tmp);
1853 trace_output_40 (sd, tmp);
1854 }
1855
1856 /* mulxsu */
1857 void
1858 OP_1C00 (SIM_DESC sd, SIM_CPU *cpu)
1859 {
1860 int64_t tmp;
1861
1862 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1863 tmp = SEXT40 ((int16_t)(GPR (OP[1])) * GPR (OP[2]));
1864
1865 if (PSW_FX)
1866 tmp <<= 1;
1867 tmp = (tmp & MASK40);
1868 SET_ACC (OP[0], tmp);
1869 trace_output_40 (sd, tmp);
1870 }
1871
1872 /* mulxu */
1873 void
1874 OP_3C00 (SIM_DESC sd, SIM_CPU *cpu)
1875 {
1876 uint64_t tmp;
1877 uint32_t src1;
1878 uint32_t src2;
1879
1880 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1881 src1 = (uint16_t) GPR (OP[1]);
1882 src2 = (uint16_t) GPR (OP[2]);
1883 tmp = src1 * src2;
1884 if (PSW_FX)
1885 tmp <<= 1;
1886 tmp = (tmp & MASK40);
1887 SET_ACC (OP[0], tmp);
1888 trace_output_40 (sd, tmp);
1889 }
1890
1891 /* mv */
1892 void
1893 OP_4000 (SIM_DESC sd, SIM_CPU *cpu)
1894 {
1895 int16_t tmp;
1896 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1897 tmp = GPR (OP[1]);
1898 SET_GPR (OP[0], tmp);
1899 trace_output_16 (sd, tmp);
1900 }
1901
1902 /* mv2w */
1903 void
1904 OP_5000 (SIM_DESC sd, SIM_CPU *cpu)
1905 {
1906 int32_t tmp;
1907 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1908 tmp = GPR32 (OP[1]);
1909 SET_GPR32 (OP[0], tmp);
1910 trace_output_32 (sd, tmp);
1911 }
1912
1913 /* mv2wfac */
1914 void
1915 OP_3E00 (SIM_DESC sd, SIM_CPU *cpu)
1916 {
1917 int32_t tmp;
1918 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1919 tmp = ACC (OP[1]);
1920 SET_GPR32 (OP[0], tmp);
1921 trace_output_32 (sd, tmp);
1922 }
1923
1924 /* mv2wtac */
1925 void
1926 OP_3E01 (SIM_DESC sd, SIM_CPU *cpu)
1927 {
1928 int64_t tmp;
1929 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1930 tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
1931 SET_ACC (OP[1], tmp);
1932 trace_output_40 (sd, tmp);
1933 }
1934
1935 /* mvac */
1936 void
1937 OP_3E03 (SIM_DESC sd, SIM_CPU *cpu)
1938 {
1939 int64_t tmp;
1940 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1941 tmp = ACC (OP[1]);
1942 SET_ACC (OP[0], tmp);
1943 trace_output_40 (sd, tmp);
1944 }
1945
1946 /* mvb */
1947 void
1948 OP_5400 (SIM_DESC sd, SIM_CPU *cpu)
1949 {
1950 int16_t tmp;
1951 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1952 tmp = SEXT8 (GPR (OP[1]) & 0xff);
1953 SET_GPR (OP[0], tmp);
1954 trace_output_16 (sd, tmp);
1955 }
1956
1957 /* mvf0f */
1958 void
1959 OP_4400 (SIM_DESC sd, SIM_CPU *cpu)
1960 {
1961 int16_t tmp;
1962 trace_input ("mvf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1963 if (PSW_F0 == 0)
1964 {
1965 tmp = GPR (OP[1]);
1966 SET_GPR (OP[0], tmp);
1967 }
1968 else
1969 tmp = GPR (OP[0]);
1970 trace_output_16 (sd, tmp);
1971 }
1972
1973 /* mvf0t */
1974 void
1975 OP_4401 (SIM_DESC sd, SIM_CPU *cpu)
1976 {
1977 int16_t tmp;
1978 trace_input ("mvf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1979 if (PSW_F0)
1980 {
1981 tmp = GPR (OP[1]);
1982 SET_GPR (OP[0], tmp);
1983 }
1984 else
1985 tmp = GPR (OP[0]);
1986 trace_output_16 (sd, tmp);
1987 }
1988
1989 /* mvfacg */
1990 void
1991 OP_1E04 (SIM_DESC sd, SIM_CPU *cpu)
1992 {
1993 int16_t tmp;
1994 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1995 tmp = ((ACC (OP[1]) >> 32) & 0xff);
1996 SET_GPR (OP[0], tmp);
1997 trace_output_16 (sd, tmp);
1998 }
1999
2000 /* mvfachi */
2001 void
2002 OP_1E00 (SIM_DESC sd, SIM_CPU *cpu)
2003 {
2004 int16_t tmp;
2005 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2006 tmp = (ACC (OP[1]) >> 16);
2007 SET_GPR (OP[0], tmp);
2008 trace_output_16 (sd, tmp);
2009 }
2010
2011 /* mvfaclo */
2012 void
2013 OP_1E02 (SIM_DESC sd, SIM_CPU *cpu)
2014 {
2015 int16_t tmp;
2016 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2017 tmp = ACC (OP[1]);
2018 SET_GPR (OP[0], tmp);
2019 trace_output_16 (sd, tmp);
2020 }
2021
2022 /* mvfc */
2023 void
2024 OP_5200 (SIM_DESC sd, SIM_CPU *cpu)
2025 {
2026 int16_t tmp;
2027 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
2028 tmp = CREG (OP[1]);
2029 SET_GPR (OP[0], tmp);
2030 trace_output_16 (sd, tmp);
2031 }
2032
2033 /* mvtacg */
2034 void
2035 OP_1E41 (SIM_DESC sd, SIM_CPU *cpu)
2036 {
2037 int64_t tmp;
2038 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2039 tmp = ((ACC (OP[1]) & MASK32)
2040 | ((int64_t)(GPR (OP[0]) & 0xff) << 32));
2041 SET_ACC (OP[1], tmp);
2042 trace_output_40 (sd, tmp);
2043 }
2044
2045 /* mvtachi */
2046 void
2047 OP_1E01 (SIM_DESC sd, SIM_CPU *cpu)
2048 {
2049 uint64_t tmp;
2050 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2051 tmp = ACC (OP[1]) & 0xffff;
2052 tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
2053 SET_ACC (OP[1], tmp);
2054 trace_output_40 (sd, tmp);
2055 }
2056
2057 /* mvtaclo */
2058 void
2059 OP_1E21 (SIM_DESC sd, SIM_CPU *cpu)
2060 {
2061 int64_t tmp;
2062 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
2063 tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
2064 SET_ACC (OP[1], tmp);
2065 trace_output_40 (sd, tmp);
2066 }
2067
2068 /* mvtc */
2069 void
2070 OP_5600 (SIM_DESC sd, SIM_CPU *cpu)
2071 {
2072 int16_t tmp;
2073 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2074 tmp = GPR (OP[0]);
2075 tmp = SET_CREG (OP[1], tmp);
2076 trace_output_16 (sd, tmp);
2077 }
2078
2079 /* mvub */
2080 void
2081 OP_5401 (SIM_DESC sd, SIM_CPU *cpu)
2082 {
2083 int16_t tmp;
2084 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2085 tmp = (GPR (OP[1]) & 0xff);
2086 SET_GPR (OP[0], tmp);
2087 trace_output_16 (sd, tmp);
2088 }
2089
2090 /* neg */
2091 void
2092 OP_4605 (SIM_DESC sd, SIM_CPU *cpu)
2093 {
2094 int16_t tmp;
2095 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2096 tmp = - GPR (OP[0]);
2097 SET_GPR (OP[0], tmp);
2098 trace_output_16 (sd, tmp);
2099 }
2100
2101 /* neg */
2102 void
2103 OP_5605 (SIM_DESC sd, SIM_CPU *cpu)
2104 {
2105 int64_t tmp;
2106
2107 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
2108 tmp = -SEXT40(ACC (OP[0]));
2109 if (PSW_ST)
2110 {
2111 if (tmp > SEXT40(MAX32))
2112 tmp = (MAX32);
2113 else if (tmp < SEXT40(MIN32))
2114 tmp = (MIN32);
2115 else
2116 tmp = (tmp & MASK40);
2117 }
2118 else
2119 tmp = (tmp & MASK40);
2120 SET_ACC (OP[0], tmp);
2121 trace_output_40 (sd, tmp);
2122 }
2123
2124
2125 /* nop */
2126 void
2127 OP_5E00 (SIM_DESC sd, SIM_CPU *cpu)
2128 {
2129 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
2130
2131 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
2132 switch (State.ins_type)
2133 {
2134 default:
2135 ins_type_counters[ (int)INS_UNKNOWN ]++;
2136 break;
2137
2138 case INS_LEFT_PARALLEL:
2139 /* Don't count a parallel op that includes a NOP as a true parallel op */
2140 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
2141 ins_type_counters[ (int)INS_RIGHT ]++;
2142 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2143 break;
2144
2145 case INS_LEFT:
2146 case INS_LEFT_COND_EXE:
2147 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2148 break;
2149
2150 case INS_RIGHT_PARALLEL:
2151 /* Don't count a parallel op that includes a NOP as a true parallel op */
2152 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
2153 ins_type_counters[ (int)INS_LEFT ]++;
2154 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2155 break;
2156
2157 case INS_RIGHT:
2158 case INS_RIGHT_COND_EXE:
2159 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2160 break;
2161 }
2162
2163 trace_output_void (sd);
2164 }
2165
2166 /* not */
2167 void
2168 OP_4603 (SIM_DESC sd, SIM_CPU *cpu)
2169 {
2170 int16_t tmp;
2171 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2172 tmp = ~GPR (OP[0]);
2173 SET_GPR (OP[0], tmp);
2174 trace_output_16 (sd, tmp);
2175 }
2176
2177 /* or */
2178 void
2179 OP_800 (SIM_DESC sd, SIM_CPU *cpu)
2180 {
2181 int16_t tmp;
2182 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2183 tmp = (GPR (OP[0]) | GPR (OP[1]));
2184 SET_GPR (OP[0], tmp);
2185 trace_output_16 (sd, tmp);
2186 }
2187
2188 /* or3 */
2189 void
2190 OP_4000000 (SIM_DESC sd, SIM_CPU *cpu)
2191 {
2192 int16_t tmp;
2193 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2194 tmp = (GPR (OP[1]) | OP[2]);
2195 SET_GPR (OP[0], tmp);
2196 trace_output_16 (sd, tmp);
2197 }
2198
2199 /* rac */
2200 void
2201 OP_5201 (SIM_DESC sd, SIM_CPU *cpu)
2202 {
2203 int64_t tmp;
2204 int shift = SEXT3 (OP[2]);
2205
2206 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2207 if (OP[1] != 0)
2208 {
2209 sim_io_printf (sd,
2210 "ERROR at PC 0x%x: instruction only valid for A0\n",
2211 PC<<2);
2212 EXCEPTION (SIM_SIGILL);
2213 }
2214
2215 SET_PSW_F1 (PSW_F0);
2216 tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2217 if (shift >=0)
2218 tmp <<= shift;
2219 else
2220 tmp >>= -shift;
2221 tmp += 0x8000;
2222 tmp >>= 16; /* look at bits 0:43 */
2223 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2224 {
2225 tmp = 0x7fffffff;
2226 SET_PSW_F0 (1);
2227 }
2228 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2229 {
2230 tmp = 0x80000000;
2231 SET_PSW_F0 (1);
2232 }
2233 else
2234 {
2235 SET_PSW_F0 (0);
2236 }
2237 SET_GPR32 (OP[0], tmp);
2238 trace_output_32 (sd, tmp);
2239 }
2240
2241 /* rachi */
2242 void
2243 OP_4201 (SIM_DESC sd, SIM_CPU *cpu)
2244 {
2245 int64_t tmp;
2246 int shift = SEXT3 (OP[2]);
2247
2248 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2249 SET_PSW_F1 (PSW_F0);
2250 if (shift >=0)
2251 tmp = SEXT40 (ACC (OP[1])) << shift;
2252 else
2253 tmp = SEXT40 (ACC (OP[1])) >> -shift;
2254 tmp += 0x8000;
2255
2256 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2257 {
2258 tmp = 0x7fff;
2259 SET_PSW_F0 (1);
2260 }
2261 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2262 {
2263 tmp = 0x8000;
2264 SET_PSW_F0 (1);
2265 }
2266 else
2267 {
2268 tmp = (tmp >> 16);
2269 SET_PSW_F0 (0);
2270 }
2271 SET_GPR (OP[0], tmp);
2272 trace_output_16 (sd, tmp);
2273 }
2274
2275 /* rep */
2276 void
2277 OP_27000000 (SIM_DESC sd, SIM_CPU *cpu)
2278 {
2279 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2280 SET_RPT_S (PC + 1);
2281 SET_RPT_E (PC + OP[1]);
2282 SET_RPT_C (GPR (OP[0]));
2283 SET_PSW_RP (1);
2284 if (GPR (OP[0]) == 0)
2285 {
2286 sim_io_printf (sd, "ERROR: rep with count=0 is illegal.\n");
2287 EXCEPTION (SIM_SIGILL);
2288 }
2289 if (OP[1] < 4)
2290 {
2291 sim_io_printf (sd, "ERROR: rep must include at least 4 instructions.\n");
2292 EXCEPTION (SIM_SIGILL);
2293 }
2294 trace_output_void (sd);
2295 }
2296
2297 /* repi */
2298 void
2299 OP_2F000000 (SIM_DESC sd, SIM_CPU *cpu)
2300 {
2301 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2302 SET_RPT_S (PC + 1);
2303 SET_RPT_E (PC + OP[1]);
2304 SET_RPT_C (OP[0]);
2305 SET_PSW_RP (1);
2306 if (OP[0] == 0)
2307 {
2308 sim_io_printf (sd, "ERROR: repi with count=0 is illegal.\n");
2309 EXCEPTION (SIM_SIGILL);
2310 }
2311 if (OP[1] < 4)
2312 {
2313 sim_io_printf (sd, "ERROR: repi must include at least 4 instructions.\n");
2314 EXCEPTION (SIM_SIGILL);
2315 }
2316 trace_output_void (sd);
2317 }
2318
2319 /* rtd */
2320 void
2321 OP_5F60 (SIM_DESC sd, SIM_CPU *cpu)
2322 {
2323 trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
2324 SET_CREG (PSW_CR, DPSW);
2325 JMP(DPC);
2326 trace_output_void (sd);
2327 }
2328
2329 /* rte */
2330 void
2331 OP_5F40 (SIM_DESC sd, SIM_CPU *cpu)
2332 {
2333 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2334 SET_CREG (PSW_CR, BPSW);
2335 JMP(BPC);
2336 trace_output_void (sd);
2337 }
2338
2339 /* sac */
2340 void OP_5209 (SIM_DESC sd, SIM_CPU *cpu)
2341 {
2342 int64_t tmp;
2343
2344 trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2345
2346 tmp = SEXT40(ACC (OP[1]));
2347
2348 SET_PSW_F1 (PSW_F0);
2349
2350 if (tmp > SEXT40(MAX32))
2351 {
2352 tmp = (MAX32);
2353 SET_PSW_F0 (1);
2354 }
2355 else if (tmp < SEXT40(MIN32))
2356 {
2357 tmp = 0x80000000;
2358 SET_PSW_F0 (1);
2359 }
2360 else
2361 {
2362 tmp = (tmp & MASK32);
2363 SET_PSW_F0 (0);
2364 }
2365
2366 SET_GPR32 (OP[0], tmp);
2367
2368 trace_output_40 (sd, tmp);
2369 }
2370
2371 /* sachi */
2372 void
2373 OP_4209 (SIM_DESC sd, SIM_CPU *cpu)
2374 {
2375 int64_t tmp;
2376
2377 trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2378
2379 tmp = SEXT40(ACC (OP[1]));
2380
2381 SET_PSW_F1 (PSW_F0);
2382
2383 if (tmp > SEXT40(MAX32))
2384 {
2385 tmp = 0x7fff;
2386 SET_PSW_F0 (1);
2387 }
2388 else if (tmp < SEXT40(MIN32))
2389 {
2390 tmp = 0x8000;
2391 SET_PSW_F0 (1);
2392 }
2393 else
2394 {
2395 tmp >>= 16;
2396 SET_PSW_F0 (0);
2397 }
2398
2399 SET_GPR (OP[0], tmp);
2400
2401 trace_output_16 (sd, OP[0]);
2402 }
2403
2404 /* sadd */
2405 void
2406 OP_1223 (SIM_DESC sd, SIM_CPU *cpu)
2407 {
2408 int64_t tmp;
2409
2410 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2411 tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
2412 if (PSW_ST)
2413 {
2414 if (tmp > SEXT40(MAX32))
2415 tmp = (MAX32);
2416 else if (tmp < SEXT40(MIN32))
2417 tmp = (MIN32);
2418 else
2419 tmp = (tmp & MASK40);
2420 }
2421 else
2422 tmp = (tmp & MASK40);
2423 SET_ACC (OP[0], tmp);
2424 trace_output_40 (sd, tmp);
2425 }
2426
2427 /* setf0f */
2428 void
2429 OP_4611 (SIM_DESC sd, SIM_CPU *cpu)
2430 {
2431 int16_t tmp;
2432 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2433 tmp = ((PSW_F0 == 0) ? 1 : 0);
2434 SET_GPR (OP[0], tmp);
2435 trace_output_16 (sd, tmp);
2436 }
2437
2438 /* setf0t */
2439 void
2440 OP_4613 (SIM_DESC sd, SIM_CPU *cpu)
2441 {
2442 int16_t tmp;
2443 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2444 tmp = ((PSW_F0 == 1) ? 1 : 0);
2445 SET_GPR (OP[0], tmp);
2446 trace_output_16 (sd, tmp);
2447 }
2448
2449 /* slae */
2450 void
2451 OP_3220 (SIM_DESC sd, SIM_CPU *cpu)
2452 {
2453 int64_t tmp;
2454 int16_t reg;
2455
2456 trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
2457
2458 reg = SEXT16 (GPR (OP[1]));
2459
2460 if (reg >= 17 || reg <= -17)
2461 {
2462 sim_io_printf (sd, "ERROR: shift value %d too large.\n", reg);
2463 EXCEPTION (SIM_SIGILL);
2464 }
2465
2466 tmp = SEXT40 (ACC (OP[0]));
2467
2468 if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32)))
2469 {
2470 sim_io_printf (sd, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp >> 32) & 0xff), ((unsigned long) tmp) & 0xffffffff);
2471 EXCEPTION (SIM_SIGILL);
2472 }
2473
2474 if (reg >= 0 && reg <= 16)
2475 {
2476 tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1])));
2477 if (PSW_ST)
2478 {
2479 if (tmp > SEXT40(MAX32))
2480 tmp = (MAX32);
2481 else if (tmp < SEXT40(MIN32))
2482 tmp = (MIN32);
2483 else
2484 tmp = (tmp & MASK40);
2485 }
2486 else
2487 tmp = (tmp & MASK40);
2488 }
2489 else
2490 {
2491 tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1]));
2492 }
2493
2494 SET_ACC(OP[0], tmp);
2495
2496 trace_output_40 (sd, tmp);
2497 }
2498
2499 /* sleep */
2500 void
2501 OP_5FC0 (SIM_DESC sd, SIM_CPU *cpu)
2502 {
2503 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2504 SET_PSW_IE (1);
2505 trace_output_void (sd);
2506 }
2507
2508 /* sll */
2509 void
2510 OP_2200 (SIM_DESC sd, SIM_CPU *cpu)
2511 {
2512 int16_t tmp;
2513 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2514 tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
2515 SET_GPR (OP[0], tmp);
2516 trace_output_16 (sd, tmp);
2517 }
2518
2519 /* sll */
2520 void
2521 OP_3200 (SIM_DESC sd, SIM_CPU *cpu)
2522 {
2523 int64_t tmp;
2524 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2525 if ((GPR (OP[1]) & 31) <= 16)
2526 tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
2527 else
2528 {
2529 sim_io_printf (sd, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2530 EXCEPTION (SIM_SIGILL);
2531 }
2532
2533 if (PSW_ST)
2534 {
2535 if (tmp > SEXT40(MAX32))
2536 tmp = (MAX32);
2537 else if (tmp < SEXT40(MIN32))
2538 tmp = (MIN32);
2539 else
2540 tmp = (tmp & MASK40);
2541 }
2542 else
2543 tmp = (tmp & MASK40);
2544 SET_ACC (OP[0], tmp);
2545 trace_output_40 (sd, tmp);
2546 }
2547
2548 /* slli */
2549 void
2550 OP_2201 (SIM_DESC sd, SIM_CPU *cpu)
2551 {
2552 int16_t tmp;
2553 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2554 tmp = (GPR (OP[0]) << OP[1]);
2555 SET_GPR (OP[0], tmp);
2556 trace_output_16 (sd, tmp);
2557 }
2558
2559 /* slli */
2560 void
2561 OP_3201 (SIM_DESC sd, SIM_CPU *cpu)
2562 {
2563 int64_t tmp;
2564
2565 if (OP[1] == 0)
2566 OP[1] = 16;
2567
2568 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2569 tmp = SEXT40(ACC (OP[0])) << OP[1];
2570
2571 if (PSW_ST)
2572 {
2573 if (tmp > SEXT40(MAX32))
2574 tmp = (MAX32);
2575 else if (tmp < SEXT40(MIN32))
2576 tmp = (MIN32);
2577 else
2578 tmp = (tmp & MASK40);
2579 }
2580 else
2581 tmp = (tmp & MASK40);
2582 SET_ACC (OP[0], tmp);
2583 trace_output_40 (sd, tmp);
2584 }
2585
2586 /* slx */
2587 void
2588 OP_460B (SIM_DESC sd, SIM_CPU *cpu)
2589 {
2590 int16_t tmp;
2591 trace_input ("slx", OP_REG, OP_VOID, OP_VOID);
2592 tmp = ((GPR (OP[0]) << 1) | PSW_F0);
2593 SET_GPR (OP[0], tmp);
2594 trace_output_16 (sd, tmp);
2595 }
2596
2597 /* sra */
2598 void
2599 OP_2400 (SIM_DESC sd, SIM_CPU *cpu)
2600 {
2601 int16_t tmp;
2602 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2603 tmp = (((int16_t)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
2604 SET_GPR (OP[0], tmp);
2605 trace_output_16 (sd, tmp);
2606 }
2607
2608 /* sra */
2609 void
2610 OP_3400 (SIM_DESC sd, SIM_CPU *cpu)
2611 {
2612 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2613 if ((GPR (OP[1]) & 31) <= 16)
2614 {
2615 int64_t tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
2616 SET_ACC (OP[0], tmp);
2617 trace_output_40 (sd, tmp);
2618 }
2619 else
2620 {
2621 sim_io_printf (sd, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2622 EXCEPTION (SIM_SIGILL);
2623 }
2624 }
2625
2626 /* srai */
2627 void
2628 OP_2401 (SIM_DESC sd, SIM_CPU *cpu)
2629 {
2630 int16_t tmp;
2631 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2632 tmp = (((int16_t)(GPR (OP[0]))) >> OP[1]);
2633 SET_GPR (OP[0], tmp);
2634 trace_output_16 (sd, tmp);
2635 }
2636
2637 /* srai */
2638 void
2639 OP_3401 (SIM_DESC sd, SIM_CPU *cpu)
2640 {
2641 int64_t tmp;
2642 if (OP[1] == 0)
2643 OP[1] = 16;
2644
2645 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2646 tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
2647 SET_ACC (OP[0], tmp);
2648 trace_output_40 (sd, tmp);
2649 }
2650
2651 /* srl */
2652 void
2653 OP_2000 (SIM_DESC sd, SIM_CPU *cpu)
2654 {
2655 int16_t tmp;
2656 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2657 tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
2658 SET_GPR (OP[0], tmp);
2659 trace_output_16 (sd, tmp);
2660 }
2661
2662 /* srl */
2663 void
2664 OP_3000 (SIM_DESC sd, SIM_CPU *cpu)
2665 {
2666 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2667 if ((GPR (OP[1]) & 31) <= 16)
2668 {
2669 int64_t tmp = ((uint64_t)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
2670 SET_ACC (OP[0], tmp);
2671 trace_output_40 (sd, tmp);
2672 }
2673 else
2674 {
2675 sim_io_printf (sd, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2676 EXCEPTION (SIM_SIGILL);
2677 }
2678
2679 }
2680
2681 /* srli */
2682 void
2683 OP_2001 (SIM_DESC sd, SIM_CPU *cpu)
2684 {
2685 int16_t tmp;
2686 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2687 tmp = (GPR (OP[0]) >> OP[1]);
2688 SET_GPR (OP[0], tmp);
2689 trace_output_16 (sd, tmp);
2690 }
2691
2692 /* srli */
2693 void
2694 OP_3001 (SIM_DESC sd, SIM_CPU *cpu)
2695 {
2696 int64_t tmp;
2697 if (OP[1] == 0)
2698 OP[1] = 16;
2699
2700 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2701 tmp = ((uint64_t)(ACC (OP[0]) & MASK40) >> OP[1]);
2702 SET_ACC (OP[0], tmp);
2703 trace_output_40 (sd, tmp);
2704 }
2705
2706 /* srx */
2707 void
2708 OP_4609 (SIM_DESC sd, SIM_CPU *cpu)
2709 {
2710 uint16_t tmp;
2711 trace_input ("srx", OP_REG, OP_VOID, OP_VOID);
2712 tmp = PSW_F0 << 15;
2713 tmp = ((GPR (OP[0]) >> 1) | tmp);
2714 SET_GPR (OP[0], tmp);
2715 trace_output_16 (sd, tmp);
2716 }
2717
2718 /* st */
2719 void
2720 OP_34000000 (SIM_DESC sd, SIM_CPU *cpu)
2721 {
2722 uint16_t addr = OP[1] + GPR (OP[2]);
2723 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2724 if ((addr & 1))
2725 {
2726 trace_output_void (sd);
2727 EXCEPTION (SIM_SIGBUS);
2728 }
2729 SW (addr, GPR (OP[0]));
2730 trace_output_void (sd);
2731 }
2732
2733 /* st */
2734 void
2735 OP_6800 (SIM_DESC sd, SIM_CPU *cpu)
2736 {
2737 uint16_t addr = GPR (OP[1]);
2738 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2739 if ((addr & 1))
2740 {
2741 trace_output_void (sd);
2742 EXCEPTION (SIM_SIGBUS);
2743 }
2744 SW (addr, GPR (OP[0]));
2745 trace_output_void (sd);
2746 }
2747
2748 /* st */
2749 /* st Rsrc1,@-SP */
2750 void
2751 OP_6C1F (SIM_DESC sd, SIM_CPU *cpu)
2752 {
2753 uint16_t addr = GPR (OP[1]) - 2;
2754 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2755 if (OP[1] != 15)
2756 {
2757 sim_io_printf (sd, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2758 EXCEPTION (SIM_SIGILL);
2759 }
2760 if ((addr & 1))
2761 {
2762 trace_output_void (sd);
2763 EXCEPTION (SIM_SIGBUS);
2764 }
2765 SW (addr, GPR (OP[0]));
2766 SET_GPR (OP[1], addr);
2767 trace_output_void (sd);
2768 }
2769
2770 /* st */
2771 void
2772 OP_6801 (SIM_DESC sd, SIM_CPU *cpu)
2773 {
2774 uint16_t addr = GPR (OP[1]);
2775 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2776 if ((addr & 1))
2777 {
2778 trace_output_void (sd);
2779 EXCEPTION (SIM_SIGBUS);
2780 }
2781 SW (addr, GPR (OP[0]));
2782 INC_ADDR (OP[1], 2);
2783 trace_output_void (sd);
2784 }
2785
2786 /* st */
2787 void
2788 OP_6C01 (SIM_DESC sd, SIM_CPU *cpu)
2789 {
2790 uint16_t addr = GPR (OP[1]);
2791 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2792 if ( OP[1] == 15 )
2793 {
2794 sim_io_printf (sd, "ERROR: cannot post-decrement register r15 (SP).\n");
2795 EXCEPTION (SIM_SIGILL);
2796 }
2797 if ((addr & 1))
2798 {
2799 trace_output_void (sd);
2800 EXCEPTION (SIM_SIGBUS);
2801 }
2802 SW (addr, GPR (OP[0]));
2803 INC_ADDR (OP[1], -2);
2804 trace_output_void (sd);
2805 }
2806
2807 /* st */
2808 void
2809 OP_36010000 (SIM_DESC sd, SIM_CPU *cpu)
2810 {
2811 uint16_t addr = OP[1];
2812 trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
2813 if ((addr & 1))
2814 {
2815 trace_output_void (sd);
2816 EXCEPTION (SIM_SIGBUS);
2817 }
2818 SW (addr, GPR (OP[0]));
2819 trace_output_void (sd);
2820 }
2821
2822 /* st2w */
2823 void
2824 OP_35000000 (SIM_DESC sd, SIM_CPU *cpu)
2825 {
2826 uint16_t addr = GPR (OP[2])+ OP[1];
2827 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2828 if ((addr & 1))
2829 {
2830 trace_output_void (sd);
2831 EXCEPTION (SIM_SIGBUS);
2832 }
2833 SW (addr + 0, GPR (OP[0] + 0));
2834 SW (addr + 2, GPR (OP[0] + 1));
2835 trace_output_void (sd);
2836 }
2837
2838 /* st2w */
2839 void
2840 OP_6A00 (SIM_DESC sd, SIM_CPU *cpu)
2841 {
2842 uint16_t addr = GPR (OP[1]);
2843 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2844 if ((addr & 1))
2845 {
2846 trace_output_void (sd);
2847 EXCEPTION (SIM_SIGBUS);
2848 }
2849 SW (addr + 0, GPR (OP[0] + 0));
2850 SW (addr + 2, GPR (OP[0] + 1));
2851 trace_output_void (sd);
2852 }
2853
2854 /* st2w */
2855 void
2856 OP_6E1F (SIM_DESC sd, SIM_CPU *cpu)
2857 {
2858 uint16_t addr = GPR (OP[1]) - 4;
2859 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2860 if ( OP[1] != 15 )
2861 {
2862 sim_io_printf (sd, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2863 EXCEPTION (SIM_SIGILL);
2864 }
2865 if ((addr & 1))
2866 {
2867 trace_output_void (sd);
2868 EXCEPTION (SIM_SIGBUS);
2869 }
2870 SW (addr + 0, GPR (OP[0] + 0));
2871 SW (addr + 2, GPR (OP[0] + 1));
2872 SET_GPR (OP[1], addr);
2873 trace_output_void (sd);
2874 }
2875
2876 /* st2w */
2877 void
2878 OP_6A01 (SIM_DESC sd, SIM_CPU *cpu)
2879 {
2880 uint16_t addr = GPR (OP[1]);
2881 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2882 if ((addr & 1))
2883 {
2884 trace_output_void (sd);
2885 EXCEPTION (SIM_SIGBUS);
2886 }
2887 SW (addr + 0, GPR (OP[0] + 0));
2888 SW (addr + 2, GPR (OP[0] + 1));
2889 INC_ADDR (OP[1], 4);
2890 trace_output_void (sd);
2891 }
2892
2893 /* st2w */
2894 void
2895 OP_6E01 (SIM_DESC sd, SIM_CPU *cpu)
2896 {
2897 uint16_t addr = GPR (OP[1]);
2898 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2899 if ( OP[1] == 15 )
2900 {
2901 sim_io_printf (sd, "ERROR: cannot post-decrement register r15 (SP).\n");
2902 EXCEPTION (SIM_SIGILL);
2903 }
2904 if ((addr & 1))
2905 {
2906 trace_output_void (sd);
2907 EXCEPTION (SIM_SIGBUS);
2908 }
2909 SW (addr + 0, GPR (OP[0] + 0));
2910 SW (addr + 2, GPR (OP[0] + 1));
2911 INC_ADDR (OP[1], -4);
2912 trace_output_void (sd);
2913 }
2914
2915 /* st2w */
2916 void
2917 OP_37010000 (SIM_DESC sd, SIM_CPU *cpu)
2918 {
2919 uint16_t addr = OP[1];
2920 trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
2921 if ((addr & 1))
2922 {
2923 trace_output_void (sd);
2924 EXCEPTION (SIM_SIGBUS);
2925 }
2926 SW (addr + 0, GPR (OP[0] + 0));
2927 SW (addr + 2, GPR (OP[0] + 1));
2928 trace_output_void (sd);
2929 }
2930
2931 /* stb */
2932 void
2933 OP_3C000000 (SIM_DESC sd, SIM_CPU *cpu)
2934 {
2935 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2936 SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
2937 trace_output_void (sd);
2938 }
2939
2940 /* stb */
2941 void
2942 OP_7800 (SIM_DESC sd, SIM_CPU *cpu)
2943 {
2944 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2945 SB (GPR (OP[1]), GPR (OP[0]));
2946 trace_output_void (sd);
2947 }
2948
2949 /* stop */
2950 void
2951 OP_5FE0 (SIM_DESC sd, SIM_CPU *cpu)
2952 {
2953 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2954 trace_output_void (sd);
2955 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, 0);
2956 }
2957
2958 /* sub */
2959 void
2960 OP_0 (SIM_DESC sd, SIM_CPU *cpu)
2961 {
2962 uint16_t a = GPR (OP[0]);
2963 uint16_t b = GPR (OP[1]);
2964 uint16_t tmp = (a - b);
2965 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2966 /* see ../common/sim-alu.h for a more extensive discussion on how to
2967 compute the carry/overflow bits. */
2968 SET_PSW_C (a >= b);
2969 SET_GPR (OP[0], tmp);
2970 trace_output_16 (sd, tmp);
2971 }
2972
2973 /* sub */
2974 void
2975 OP_1001 (SIM_DESC sd, SIM_CPU *cpu)
2976 {
2977 int64_t tmp;
2978
2979 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2980 tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
2981 if (PSW_ST)
2982 {
2983 if (tmp > SEXT40(MAX32))
2984 tmp = (MAX32);
2985 else if (tmp < SEXT40(MIN32))
2986 tmp = (MIN32);
2987 else
2988 tmp = (tmp & MASK40);
2989 }
2990 else
2991 tmp = (tmp & MASK40);
2992 SET_ACC (OP[0], tmp);
2993
2994 trace_output_40 (sd, tmp);
2995 }
2996
2997 /* sub */
2998
2999 void
3000 OP_1003 (SIM_DESC sd, SIM_CPU *cpu)
3001 {
3002 int64_t tmp;
3003
3004 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
3005 tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
3006 if (PSW_ST)
3007 {
3008 if (tmp > SEXT40(MAX32))
3009 tmp = (MAX32);
3010 else if (tmp < SEXT40(MIN32))
3011 tmp = (MIN32);
3012 else
3013 tmp = (tmp & MASK40);
3014 }
3015 else
3016 tmp = (tmp & MASK40);
3017 SET_ACC (OP[0], tmp);
3018
3019 trace_output_40 (sd, tmp);
3020 }
3021
3022 /* sub2w */
3023 void
3024 OP_1000 (SIM_DESC sd, SIM_CPU *cpu)
3025 {
3026 uint32_t tmp, a, b;
3027
3028 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
3029 a = (uint32_t)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
3030 b = (uint32_t)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
3031 /* see ../common/sim-alu.h for a more extensive discussion on how to
3032 compute the carry/overflow bits */
3033 tmp = a - b;
3034 SET_PSW_C (a >= b);
3035 SET_GPR32 (OP[0], tmp);
3036 trace_output_32 (sd, tmp);
3037 }
3038
3039 /* subac3 */
3040 void
3041 OP_17000000 (SIM_DESC sd, SIM_CPU *cpu)
3042 {
3043 int64_t tmp;
3044
3045 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
3046 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
3047 SET_GPR32 (OP[0], tmp);
3048 trace_output_32 (sd, tmp);
3049 }
3050
3051 /* subac3 */
3052 void
3053 OP_17000002 (SIM_DESC sd, SIM_CPU *cpu)
3054 {
3055 int64_t tmp;
3056
3057 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
3058 tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
3059 SET_GPR32 (OP[0], tmp);
3060 trace_output_32 (sd, tmp);
3061 }
3062
3063 /* subac3s */
3064 void
3065 OP_17001000 (SIM_DESC sd, SIM_CPU *cpu)
3066 {
3067 int64_t tmp;
3068
3069 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
3070 SET_PSW_F1 (PSW_F0);
3071 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
3072 if (tmp > SEXT40(MAX32))
3073 {
3074 tmp = (MAX32);
3075 SET_PSW_F0 (1);
3076 }
3077 else if (tmp < SEXT40(MIN32))
3078 {
3079 tmp = (MIN32);
3080 SET_PSW_F0 (1);
3081 }
3082 else
3083 {
3084 SET_PSW_F0 (0);
3085 }
3086 SET_GPR32 (OP[0], tmp);
3087 trace_output_32 (sd, tmp);
3088 }
3089
3090 /* subac3s */
3091 void
3092 OP_17001002 (SIM_DESC sd, SIM_CPU *cpu)
3093 {
3094 int64_t tmp;
3095
3096 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
3097 SET_PSW_F1 (PSW_F0);
3098 tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
3099 if (tmp > SEXT40(MAX32))
3100 {
3101 tmp = (MAX32);
3102 SET_PSW_F0 (1);
3103 }
3104 else if (tmp < SEXT40(MIN32))
3105 {
3106 tmp = (MIN32);
3107 SET_PSW_F0 (1);
3108 }
3109 else
3110 {
3111 SET_PSW_F0 (0);
3112 }
3113 SET_GPR32 (OP[0], tmp);
3114 trace_output_32 (sd, tmp);
3115 }
3116
3117 /* subi */
3118 void
3119 OP_1 (SIM_DESC sd, SIM_CPU *cpu)
3120 {
3121 unsigned tmp;
3122 if (OP[1] == 0)
3123 OP[1] = 16;
3124
3125 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
3126 /* see ../common/sim-alu.h for a more extensive discussion on how to
3127 compute the carry/overflow bits. */
3128 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
3129 tmp = ((unsigned)(uint16_t) GPR (OP[0])
3130 + (unsigned)(uint16_t) ( - OP[1]));
3131 SET_PSW_C (tmp >= (1 << 16));
3132 SET_GPR (OP[0], tmp);
3133 trace_output_16 (sd, tmp);
3134 }
3135
3136 /* trap */
3137 void
3138 OP_5F00 (SIM_DESC sd, SIM_CPU *cpu)
3139 {
3140 host_callback *cb = STATE_CALLBACK (sd);
3141
3142 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
3143 trace_output_void (sd);
3144
3145 switch (OP[0])
3146 {
3147 default:
3148 #if (DEBUG & DEBUG_TRAP) == 0
3149 {
3150 uint16_t vec = OP[0] + TRAP_VECTOR_START;
3151 SET_BPC (PC + 1);
3152 SET_BPSW (PSW);
3153 SET_PSW (PSW & PSW_SM_BIT);
3154 JMP (vec);
3155 break;
3156 }
3157 #else /* if debugging use trap to print registers */
3158 {
3159 int i;
3160 static int first_time = 1;
3161
3162 if (first_time)
3163 {
3164 first_time = 0;
3165 sim_io_printf (sd, "Trap # PC ");
3166 for (i = 0; i < 16; i++)
3167 sim_io_printf (sd, " %sr%d", (i > 9) ? "" : " ", i);
3168 sim_io_printf (sd, " a0 a1 f0 f1 c\n");
3169 }
3170
3171 sim_io_printf (sd, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
3172
3173 for (i = 0; i < 16; i++)
3174 sim_io_printf (sd, " %.4x", (int) GPR (i));
3175
3176 for (i = 0; i < 2; i++)
3177 sim_io_printf (sd, " %.2x%.8lx",
3178 ((int)(ACC (i) >> 32) & 0xff),
3179 ((unsigned long) ACC (i)) & 0xffffffff);
3180
3181 sim_io_printf (sd, " %d %d %d\n",
3182 PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
3183 sim_io_flush_stdout (sd);
3184 break;
3185 }
3186 #endif
3187 case 15: /* new system call trap */
3188 /* Trap 15 is used for simulating low-level I/O */
3189 {
3190 uint32_t result = 0;
3191 errno = 0;
3192
3193 /* Registers passed to trap 0 */
3194
3195 #define FUNC GPR (4) /* function number */
3196 #define PARM1 GPR (0) /* optional parm 1 */
3197 #define PARM2 GPR (1) /* optional parm 2 */
3198 #define PARM3 GPR (2) /* optional parm 3 */
3199 #define PARM4 GPR (3) /* optional parm 3 */
3200
3201 /* Registers set by trap 0 */
3202
3203 #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
3204 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3205 #define RETERR(X) SET_GPR (4, (X)) /* return error code */
3206
3207 /* Turn a pointer in a register into a pointer into real memory. */
3208
3209 #define MEMPTR(x) ((char *)(dmem_addr (sd, cpu, x)))
3210
3211 switch (FUNC)
3212 {
3213 #if !defined(__GO32__) && !defined(_WIN32)
3214 case TARGET_NEWLIB_D10V_SYS_fork:
3215 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
3216 RETVAL (fork ());
3217 trace_output_16 (sd, result);
3218 break;
3219
3220 #define getpid() 47
3221 case TARGET_NEWLIB_D10V_SYS_getpid:
3222 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3223 RETVAL (getpid ());
3224 trace_output_16 (sd, result);
3225 break;
3226
3227 case TARGET_NEWLIB_D10V_SYS_kill:
3228 trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
3229 if (PARM1 == getpid ())
3230 {
3231 trace_output_void (sd);
3232 sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, PARM2);
3233 }
3234 else
3235 {
3236 int os_sig = -1;
3237 switch (PARM2)
3238 {
3239 #ifdef SIGHUP
3240 case 1: os_sig = SIGHUP; break;
3241 #endif
3242 #ifdef SIGINT
3243 case 2: os_sig = SIGINT; break;
3244 #endif
3245 #ifdef SIGQUIT
3246 case 3: os_sig = SIGQUIT; break;
3247 #endif
3248 #ifdef SIGILL
3249 case 4: os_sig = SIGILL; break;
3250 #endif
3251 #ifdef SIGTRAP
3252 case 5: os_sig = SIGTRAP; break;
3253 #endif
3254 #ifdef SIGABRT
3255 case 6: os_sig = SIGABRT; break;
3256 #elif defined(SIGIOT)
3257 case 6: os_sig = SIGIOT; break;
3258 #endif
3259 #ifdef SIGEMT
3260 case 7: os_sig = SIGEMT; break;
3261 #endif
3262 #ifdef SIGFPE
3263 case 8: os_sig = SIGFPE; break;
3264 #endif
3265 #ifdef SIGKILL
3266 case 9: os_sig = SIGKILL; break;
3267 #endif
3268 #ifdef SIGBUS
3269 case 10: os_sig = SIGBUS; break;
3270 #endif
3271 #ifdef SIGSEGV
3272 case 11: os_sig = SIGSEGV; break;
3273 #endif
3274 #ifdef SIGSYS
3275 case 12: os_sig = SIGSYS; break;
3276 #endif
3277 #ifdef SIGPIPE
3278 case 13: os_sig = SIGPIPE; break;
3279 #endif
3280 #ifdef SIGALRM
3281 case 14: os_sig = SIGALRM; break;
3282 #endif
3283 #ifdef SIGTERM
3284 case 15: os_sig = SIGTERM; break;
3285 #endif
3286 #ifdef SIGURG
3287 case 16: os_sig = SIGURG; break;
3288 #endif
3289 #ifdef SIGSTOP
3290 case 17: os_sig = SIGSTOP; break;
3291 #endif
3292 #ifdef SIGTSTP
3293 case 18: os_sig = SIGTSTP; break;
3294 #endif
3295 #ifdef SIGCONT
3296 case 19: os_sig = SIGCONT; break;
3297 #endif
3298 #ifdef SIGCHLD
3299 case 20: os_sig = SIGCHLD; break;
3300 #elif defined(SIGCLD)
3301 case 20: os_sig = SIGCLD; break;
3302 #endif
3303 #ifdef SIGTTIN
3304 case 21: os_sig = SIGTTIN; break;
3305 #endif
3306 #ifdef SIGTTOU
3307 case 22: os_sig = SIGTTOU; break;
3308 #endif
3309 #ifdef SIGIO
3310 case 23: os_sig = SIGIO; break;
3311 #elif defined (SIGPOLL)
3312 case 23: os_sig = SIGPOLL; break;
3313 #endif
3314 #ifdef SIGXCPU
3315 case 24: os_sig = SIGXCPU; break;
3316 #endif
3317 #ifdef SIGXFSZ
3318 case 25: os_sig = SIGXFSZ; break;
3319 #endif
3320 #ifdef SIGVTALRM
3321 case 26: os_sig = SIGVTALRM; break;
3322 #endif
3323 #ifdef SIGPROF
3324 case 27: os_sig = SIGPROF; break;
3325 #endif
3326 #ifdef SIGWINCH
3327 case 28: os_sig = SIGWINCH; break;
3328 #endif
3329 #ifdef SIGLOST
3330 case 29: os_sig = SIGLOST; break;
3331 #endif
3332 #ifdef SIGUSR1
3333 case 30: os_sig = SIGUSR1; break;
3334 #endif
3335 #ifdef SIGUSR2
3336 case 31: os_sig = SIGUSR2; break;
3337 #endif
3338 }
3339
3340 if (os_sig == -1)
3341 {
3342 trace_output_void (sd);
3343 sim_io_printf (sd, "Unknown signal %d\n", PARM2);
3344 sim_io_flush_stdout (sd);
3345 EXCEPTION (SIM_SIGILL);
3346 }
3347 else
3348 {
3349 RETVAL (kill (PARM1, PARM2));
3350 trace_output_16 (sd, result);
3351 }
3352 }
3353 break;
3354
3355 case TARGET_NEWLIB_D10V_SYS_execve:
3356 trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
3357 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
3358 (char **)MEMPTR (PARM3)));
3359 trace_output_16 (sd, result);
3360 break;
3361
3362 case TARGET_NEWLIB_D10V_SYS_execv:
3363 trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
3364 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
3365 trace_output_16 (sd, result);
3366 break;
3367
3368 case TARGET_NEWLIB_D10V_SYS_pipe:
3369 {
3370 reg_t buf;
3371 int host_fd[2];
3372
3373 trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
3374 buf = PARM1;
3375 RETVAL (pipe (host_fd));
3376 SW (buf, host_fd[0]);
3377 buf += sizeof(uint16_t);
3378 SW (buf, host_fd[1]);
3379 trace_output_16 (sd, result);
3380 }
3381 break;
3382
3383 #if 0
3384 case TARGET_NEWLIB_D10V_SYS_wait:
3385 {
3386 int status;
3387 trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
3388 RETVAL (wait (&status));
3389 if (PARM1)
3390 SW (PARM1, status);
3391 trace_output_16 (sd, result);
3392 }
3393 break;
3394 #endif
3395 #else
3396 case TARGET_NEWLIB_D10V_SYS_getpid:
3397 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3398 RETVAL (1);
3399 trace_output_16 (sd, result);
3400 break;
3401
3402 case TARGET_NEWLIB_D10V_SYS_kill:
3403 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
3404 trace_output_void (sd);
3405 sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, PARM2);
3406 break;
3407 #endif
3408
3409 case TARGET_NEWLIB_D10V_SYS_read:
3410 trace_input ("<read>", OP_R0, OP_R1, OP_R2);
3411 RETVAL (cb->read (cb, PARM1, MEMPTR (PARM2), PARM3));
3412 trace_output_16 (sd, result);
3413 break;
3414
3415 case TARGET_NEWLIB_D10V_SYS_write:
3416 trace_input ("<write>", OP_R0, OP_R1, OP_R2);
3417 if (PARM1 == 1)
3418 RETVAL ((int)cb->write_stdout (cb, MEMPTR (PARM2), PARM3));
3419 else
3420 RETVAL ((int)cb->write (cb, PARM1, MEMPTR (PARM2), PARM3));
3421 trace_output_16 (sd, result);
3422 break;
3423
3424 case TARGET_NEWLIB_D10V_SYS_lseek:
3425 trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
3426 RETVAL32 (cb->lseek (cb, PARM1,
3427 ((((unsigned long) PARM2) << 16)
3428 || (unsigned long) PARM3),
3429 PARM4));
3430 trace_output_32 (sd, result);
3431 break;
3432
3433 case TARGET_NEWLIB_D10V_SYS_close:
3434 trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
3435 RETVAL (cb->close (cb, PARM1));
3436 trace_output_16 (sd, result);
3437 break;
3438
3439 case TARGET_NEWLIB_D10V_SYS_open:
3440 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
3441 RETVAL (cb->open (cb, MEMPTR (PARM1), PARM2));
3442 trace_output_16 (sd, result);
3443 break;
3444
3445 case TARGET_NEWLIB_D10V_SYS_exit:
3446 trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
3447 trace_output_void (sd);
3448 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (0));
3449 break;
3450
3451 case TARGET_NEWLIB_D10V_SYS_stat:
3452 trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
3453 /* stat system call */
3454 {
3455 struct stat host_stat;
3456 reg_t buf;
3457
3458 RETVAL (stat (MEMPTR (PARM1), &host_stat));
3459
3460 buf = PARM2;
3461
3462 /* The hard-coded offsets and sizes were determined by using
3463 * the D10V compiler on a test program that used struct stat.
3464 */
3465 SW (buf, host_stat.st_dev);
3466 SW (buf+2, host_stat.st_ino);
3467 SW (buf+4, host_stat.st_mode);
3468 SW (buf+6, host_stat.st_nlink);
3469 SW (buf+8, host_stat.st_uid);
3470 SW (buf+10, host_stat.st_gid);
3471 SW (buf+12, host_stat.st_rdev);
3472 SLW (buf+16, host_stat.st_size);
3473 SLW (buf+20, host_stat.st_atime);
3474 SLW (buf+28, host_stat.st_mtime);
3475 SLW (buf+36, host_stat.st_ctime);
3476 }
3477 trace_output_16 (sd, result);
3478 break;
3479
3480 case TARGET_NEWLIB_D10V_SYS_chown:
3481 trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3482 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
3483 trace_output_16 (sd, result);
3484 break;
3485
3486 case TARGET_NEWLIB_D10V_SYS_chmod:
3487 trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3488 RETVAL (chmod (MEMPTR (PARM1), PARM2));
3489 trace_output_16 (sd, result);
3490 break;
3491
3492 #if 0
3493 case TARGET_NEWLIB_D10V_SYS_utime:
3494 trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3495 /* Cast the second argument to void *, to avoid type mismatch
3496 if a prototype is present. */
3497 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
3498 trace_output_16 (sd, result);
3499 break;
3500 #endif
3501
3502 #if 0
3503 case TARGET_NEWLIB_D10V_SYS_time:
3504 trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3505 RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
3506 trace_output_32 (sd, result);
3507 break;
3508 #endif
3509
3510 default:
3511 cb->error (cb, "Unknown syscall %d", FUNC);
3512 }
3513 if ((uint16_t) result == (uint16_t) -1)
3514 RETERR (cb->get_errno (cb));
3515 else
3516 RETERR (0);
3517 break;
3518 }
3519 }
3520 }
3521
3522 /* tst0i */
3523 void
3524 OP_7000000 (SIM_DESC sd, SIM_CPU *cpu)
3525 {
3526 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3527 SET_PSW_F1 (PSW_F0);;
3528 SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
3529 trace_output_flag (sd);
3530 }
3531
3532 /* tst1i */
3533 void
3534 OP_F000000 (SIM_DESC sd, SIM_CPU *cpu)
3535 {
3536 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3537 SET_PSW_F1 (PSW_F0);
3538 SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
3539 trace_output_flag (sd);
3540 }
3541
3542 /* wait */
3543 void
3544 OP_5F80 (SIM_DESC sd, SIM_CPU *cpu)
3545 {
3546 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3547 SET_PSW_IE (1);
3548 trace_output_void (sd);
3549 }
3550
3551 /* xor */
3552 void
3553 OP_A00 (SIM_DESC sd, SIM_CPU *cpu)
3554 {
3555 int16_t tmp;
3556 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3557 tmp = (GPR (OP[0]) ^ GPR (OP[1]));
3558 SET_GPR (OP[0], tmp);
3559 trace_output_16 (sd, tmp);
3560 }
3561
3562 /* xor3 */
3563 void
3564 OP_5000000 (SIM_DESC sd, SIM_CPU *cpu)
3565 {
3566 int16_t tmp;
3567 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3568 tmp = (GPR (OP[1]) ^ OP[2]);
3569 SET_GPR (OP[0], tmp);
3570 trace_output_16 (sd, tmp);
3571 }
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