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[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
1 /* This must come before any other includes. */
2 #include "defs.h"
3
4 #include <signal.h>
5 #include <errno.h>
6 #include <sys/types.h>
7 #include <sys/stat.h>
8 #include <unistd.h>
9 #include <string.h>
10
11 #include "bfd.h"
12
13 #include "sim-main.h"
14 #include "sim-signal.h"
15 #include "simops.h"
16 #include "target-newlib-syscall.h"
17
18 #include "d10v-sim.h"
19
20 #define EXCEPTION(sig) sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, sig)
21
22 enum op_types {
23 OP_VOID,
24 OP_REG,
25 OP_REG_OUTPUT,
26 OP_DREG,
27 OP_DREG_OUTPUT,
28 OP_ACCUM,
29 OP_ACCUM_OUTPUT,
30 OP_ACCUM_REVERSE,
31 OP_CR,
32 OP_CR_OUTPUT,
33 OP_CR_REVERSE,
34 OP_FLAG,
35 OP_FLAG_OUTPUT,
36 OP_CONSTANT16,
37 OP_CONSTANT8,
38 OP_CONSTANT3,
39 OP_CONSTANT4,
40 OP_MEMREF,
41 OP_MEMREF2,
42 OP_MEMREF3,
43 OP_POSTDEC,
44 OP_POSTINC,
45 OP_PREDEC,
46 OP_R0,
47 OP_R1,
48 OP_R2,
49 };
50
51
52 enum {
53 PSW_MASK = (PSW_SM_BIT
54 | PSW_EA_BIT
55 | PSW_DB_BIT
56 | PSW_IE_BIT
57 | PSW_RP_BIT
58 | PSW_MD_BIT
59 | PSW_FX_BIT
60 | PSW_ST_BIT
61 | PSW_F0_BIT
62 | PSW_F1_BIT
63 | PSW_C_BIT),
64 /* The following bits in the PSW _can't_ be set by instructions such
65 as mvtc. */
66 PSW_HW_MASK = (PSW_MASK | PSW_DM_BIT)
67 };
68
69 reg_t
70 move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, reg_t mask, reg_t val, int psw_hw_p)
71 {
72 /* A MASK bit is set when the corresponding bit in the CR should
73 be left alone */
74 /* This assumes that (VAL & MASK) == 0 */
75 switch (cr)
76 {
77 case PSW_CR:
78 if (psw_hw_p)
79 val &= PSW_HW_MASK;
80 else
81 val &= PSW_MASK;
82 if ((mask & PSW_SM_BIT) == 0)
83 {
84 int new_psw_sm = (val & PSW_SM_BIT) != 0;
85 /* save old SP */
86 SET_HELD_SP (PSW_SM, GPR (SP_IDX));
87 if (PSW_SM != new_psw_sm)
88 /* restore new SP */
89 SET_GPR (SP_IDX, HELD_SP (new_psw_sm));
90 }
91 if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
92 {
93 if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
94 {
95 sim_io_printf
96 (sd,
97 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
98 PC<<2);
99 EXCEPTION (SIM_SIGILL);
100 }
101 }
102 /* keep an up-to-date psw around for tracing */
103 State.trace.psw = (State.trace.psw & mask) | val;
104 break;
105 case BPSW_CR:
106 case DPSW_CR:
107 /* Just like PSW, mask things like DM out. */
108 if (psw_hw_p)
109 val &= PSW_HW_MASK;
110 else
111 val &= PSW_MASK;
112 break;
113 case MOD_S_CR:
114 case MOD_E_CR:
115 val &= ~1;
116 break;
117 default:
118 break;
119 }
120 /* only issue an update if the register is being changed */
121 if ((State.cregs[cr] & ~mask) != val)
122 SLOT_PEND_MASK (State.cregs[cr], mask, val);
123 return val;
124 }
125
126 #ifdef DEBUG
127 static void trace_input_func (SIM_DESC sd,
128 const char *name,
129 enum op_types in1,
130 enum op_types in2,
131 enum op_types in3);
132
133 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (sd, name, in1, in2, in3); } while (0)
134
135 #ifndef SIZE_INSTRUCTION
136 #define SIZE_INSTRUCTION 8
137 #endif
138
139 #ifndef SIZE_OPERANDS
140 #define SIZE_OPERANDS 18
141 #endif
142
143 #ifndef SIZE_VALUES
144 #define SIZE_VALUES 13
145 #endif
146
147 #ifndef SIZE_LOCATION
148 #define SIZE_LOCATION 20
149 #endif
150
151 #ifndef SIZE_PC
152 #define SIZE_PC 6
153 #endif
154
155 #ifndef SIZE_LINE_NUMBER
156 #define SIZE_LINE_NUMBER 4
157 #endif
158
159 static void
160 trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
161 {
162 char *comma;
163 enum op_types in[3];
164 int i;
165 char buf[1024];
166 char *p;
167 long tmp;
168 char *type;
169 const char *filename;
170 const char *functionname;
171 unsigned int linenumber;
172 bfd_vma byte_pc;
173
174 if ((d10v_debug & DEBUG_TRACE) == 0)
175 return;
176
177 switch (State.ins_type)
178 {
179 default:
180 case INS_UNKNOWN: type = " ?"; break;
181 case INS_LEFT: type = " L"; break;
182 case INS_RIGHT: type = " R"; break;
183 case INS_LEFT_PARALLEL: type = "*L"; break;
184 case INS_RIGHT_PARALLEL: type = "*R"; break;
185 case INS_LEFT_COND_TEST: type = "?L"; break;
186 case INS_RIGHT_COND_TEST: type = "?R"; break;
187 case INS_LEFT_COND_EXE: type = "&L"; break;
188 case INS_RIGHT_COND_EXE: type = "&R"; break;
189 case INS_LONG: type = " B"; break;
190 }
191
192 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
193 sim_io_printf (sd,
194 "0x%.*x %s: %-*s ",
195 SIZE_PC, (unsigned)PC,
196 type,
197 SIZE_INSTRUCTION, name);
198
199 else
200 {
201 buf[0] = '\0';
202 byte_pc = PC;
203 if (STATE_TEXT_SECTION (sd)
204 && byte_pc >= STATE_TEXT_START (sd)
205 && byte_pc < STATE_TEXT_END (sd))
206 {
207 filename = (const char *)0;
208 functionname = (const char *)0;
209 linenumber = 0;
210 if (bfd_find_nearest_line (STATE_PROG_BFD (sd),
211 STATE_TEXT_SECTION (sd),
212 (struct bfd_symbol **)0,
213 byte_pc - STATE_TEXT_START (sd),
214 &filename, &functionname, &linenumber))
215 {
216 p = buf;
217 if (linenumber)
218 {
219 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
220 p += strlen (p);
221 }
222 else
223 {
224 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
225 p += SIZE_LINE_NUMBER+2;
226 }
227
228 if (functionname)
229 {
230 sprintf (p, "%s ", functionname);
231 p += strlen (p);
232 }
233 else if (filename)
234 {
235 char *q = strrchr (filename, '/');
236 sprintf (p, "%s ", (q) ? q+1 : filename);
237 p += strlen (p);
238 }
239
240 if (*p == ' ')
241 *p = '\0';
242 }
243 }
244
245 sim_io_printf (sd,
246 "0x%.*x %s: %-*.*s %-*s ",
247 SIZE_PC, (unsigned)PC,
248 type,
249 SIZE_LOCATION, SIZE_LOCATION, buf,
250 SIZE_INSTRUCTION, name);
251 }
252
253 in[0] = in1;
254 in[1] = in2;
255 in[2] = in3;
256 comma = "";
257 p = buf;
258 for (i = 0; i < 3; i++)
259 {
260 switch (in[i])
261 {
262 case OP_VOID:
263 case OP_R0:
264 case OP_R1:
265 case OP_R2:
266 break;
267
268 case OP_REG:
269 case OP_REG_OUTPUT:
270 case OP_DREG:
271 case OP_DREG_OUTPUT:
272 sprintf (p, "%sr%d", comma, OP[i]);
273 p += strlen (p);
274 comma = ",";
275 break;
276
277 case OP_CR:
278 case OP_CR_OUTPUT:
279 case OP_CR_REVERSE:
280 sprintf (p, "%scr%d", comma, OP[i]);
281 p += strlen (p);
282 comma = ",";
283 break;
284
285 case OP_ACCUM:
286 case OP_ACCUM_OUTPUT:
287 case OP_ACCUM_REVERSE:
288 sprintf (p, "%sa%d", comma, OP[i]);
289 p += strlen (p);
290 comma = ",";
291 break;
292
293 case OP_CONSTANT16:
294 sprintf (p, "%s%d", comma, OP[i]);
295 p += strlen (p);
296 comma = ",";
297 break;
298
299 case OP_CONSTANT8:
300 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
301 p += strlen (p);
302 comma = ",";
303 break;
304
305 case OP_CONSTANT4:
306 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
307 p += strlen (p);
308 comma = ",";
309 break;
310
311 case OP_CONSTANT3:
312 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
313 p += strlen (p);
314 comma = ",";
315 break;
316
317 case OP_MEMREF:
318 sprintf (p, "%s@r%d", comma, OP[i]);
319 p += strlen (p);
320 comma = ",";
321 break;
322
323 case OP_MEMREF2:
324 sprintf (p, "%s@(%d,r%d)", comma, (int16_t)OP[i], OP[i+1]);
325 p += strlen (p);
326 comma = ",";
327 break;
328
329 case OP_MEMREF3:
330 sprintf (p, "%s@%d", comma, OP[i]);
331 p += strlen (p);
332 comma = ",";
333 break;
334
335 case OP_POSTINC:
336 sprintf (p, "%s@r%d+", comma, OP[i]);
337 p += strlen (p);
338 comma = ",";
339 break;
340
341 case OP_POSTDEC:
342 sprintf (p, "%s@r%d-", comma, OP[i]);
343 p += strlen (p);
344 comma = ",";
345 break;
346
347 case OP_PREDEC:
348 sprintf (p, "%s@-r%d", comma, OP[i]);
349 p += strlen (p);
350 comma = ",";
351 break;
352
353 case OP_FLAG:
354 case OP_FLAG_OUTPUT:
355 if (OP[i] == 0)
356 sprintf (p, "%sf0", comma);
357
358 else if (OP[i] == 1)
359 sprintf (p, "%sf1", comma);
360
361 else
362 sprintf (p, "%sc", comma);
363
364 p += strlen (p);
365 comma = ",";
366 break;
367 }
368 }
369
370 if ((d10v_debug & DEBUG_VALUES) == 0)
371 {
372 *p++ = '\n';
373 *p = '\0';
374 sim_io_printf (sd, "%s", buf);
375 }
376 else
377 {
378 *p = '\0';
379 sim_io_printf (sd, "%-*s", SIZE_OPERANDS, buf);
380
381 p = buf;
382 for (i = 0; i < 3; i++)
383 {
384 buf[0] = '\0';
385 switch (in[i])
386 {
387 case OP_VOID:
388 sim_io_printf (sd, "%*s", SIZE_VALUES, "");
389 break;
390
391 case OP_REG_OUTPUT:
392 case OP_DREG_OUTPUT:
393 case OP_CR_OUTPUT:
394 case OP_ACCUM_OUTPUT:
395 case OP_FLAG_OUTPUT:
396 sim_io_printf (sd, "%*s", SIZE_VALUES, "---");
397 break;
398
399 case OP_REG:
400 case OP_MEMREF:
401 case OP_POSTDEC:
402 case OP_POSTINC:
403 case OP_PREDEC:
404 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
405 (uint16_t) GPR (OP[i]));
406 break;
407
408 case OP_MEMREF3:
409 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16_t) OP[i]);
410 break;
411
412 case OP_DREG:
413 tmp = (long)((((uint32_t) GPR (OP[i])) << 16) | ((uint32_t) GPR (OP[i] + 1)));
414 sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
415 break;
416
417 case OP_CR:
418 case OP_CR_REVERSE:
419 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
420 (uint16_t) CREG (OP[i]));
421 break;
422
423 case OP_ACCUM:
424 case OP_ACCUM_REVERSE:
425 sim_io_printf (sd, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
426 ((int)(ACC (OP[i]) >> 32) & 0xff),
427 ((unsigned long) ACC (OP[i])) & 0xffffffff);
428 break;
429
430 case OP_CONSTANT16:
431 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
432 (uint16_t)OP[i]);
433 break;
434
435 case OP_CONSTANT4:
436 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
437 (uint16_t)SEXT4(OP[i]));
438 break;
439
440 case OP_CONSTANT8:
441 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
442 (uint16_t)SEXT8(OP[i]));
443 break;
444
445 case OP_CONSTANT3:
446 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
447 (uint16_t)SEXT3(OP[i]));
448 break;
449
450 case OP_FLAG:
451 if (OP[i] == 0)
452 sim_io_printf (sd, "%*sF0 = %d", SIZE_VALUES-6, "",
453 PSW_F0 != 0);
454
455 else if (OP[i] == 1)
456 sim_io_printf (sd, "%*sF1 = %d", SIZE_VALUES-6, "",
457 PSW_F1 != 0);
458
459 else
460 sim_io_printf (sd, "%*sC = %d", SIZE_VALUES-5, "",
461 PSW_C != 0);
462
463 break;
464
465 case OP_MEMREF2:
466 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
467 (uint16_t)OP[i]);
468 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
469 (uint16_t)GPR (OP[i + 1]));
470 i++;
471 break;
472
473 case OP_R0:
474 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
475 (uint16_t) GPR (0));
476 break;
477
478 case OP_R1:
479 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
480 (uint16_t) GPR (1));
481 break;
482
483 case OP_R2:
484 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
485 (uint16_t) GPR (2));
486 break;
487
488 }
489 }
490 }
491
492 sim_io_flush_stdout (sd);
493 }
494
495 static void
496 do_trace_output_flush (SIM_DESC sd)
497 {
498 sim_io_flush_stdout (sd);
499 }
500
501 static void
502 do_trace_output_finish (SIM_DESC sd)
503 {
504 sim_io_printf (sd,
505 " F0=%d F1=%d C=%d\n",
506 (State.trace.psw & PSW_F0_BIT) != 0,
507 (State.trace.psw & PSW_F1_BIT) != 0,
508 (State.trace.psw & PSW_C_BIT) != 0);
509 sim_io_flush_stdout (sd);
510 }
511
512 static void
513 trace_output_40 (SIM_DESC sd, uint64_t val)
514 {
515 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
516 {
517 sim_io_printf (sd,
518 " :: %*s0x%.2x%.8lx",
519 SIZE_VALUES - 12,
520 "",
521 ((int)(val >> 32) & 0xff),
522 ((unsigned long) val) & 0xffffffff);
523 do_trace_output_finish (sd);
524 }
525 }
526
527 static void
528 trace_output_32 (SIM_DESC sd, uint32_t val)
529 {
530 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
531 {
532 sim_io_printf (sd,
533 " :: %*s0x%.8x",
534 SIZE_VALUES - 10,
535 "",
536 (int) val);
537 do_trace_output_finish (sd);
538 }
539 }
540
541 static void
542 trace_output_16 (SIM_DESC sd, uint16_t val)
543 {
544 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
545 {
546 sim_io_printf (sd,
547 " :: %*s0x%.4x",
548 SIZE_VALUES - 6,
549 "",
550 (int) val);
551 do_trace_output_finish (sd);
552 }
553 }
554
555 static void
556 trace_output_void (SIM_DESC sd)
557 {
558 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
559 {
560 sim_io_printf (sd, "\n");
561 do_trace_output_flush (sd);
562 }
563 }
564
565 static void
566 trace_output_flag (SIM_DESC sd)
567 {
568 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
569 {
570 sim_io_printf (sd,
571 " :: %*s",
572 SIZE_VALUES,
573 "");
574 do_trace_output_finish (sd);
575 }
576 }
577
578
579
580
581 #else
582 #define trace_input(NAME, IN1, IN2, IN3)
583 #define trace_output(RESULT)
584 #endif
585
586 /* abs */
587 void
588 OP_4607 (SIM_DESC sd, SIM_CPU *cpu)
589 {
590 int16_t tmp;
591 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
592 SET_PSW_F1 (PSW_F0);
593 tmp = GPR(OP[0]);
594 if (tmp < 0)
595 {
596 tmp = - tmp;
597 SET_PSW_F0 (1);
598 }
599 else
600 SET_PSW_F0 (0);
601 SET_GPR (OP[0], tmp);
602 trace_output_16 (sd, tmp);
603 }
604
605 /* abs */
606 void
607 OP_5607 (SIM_DESC sd, SIM_CPU *cpu)
608 {
609 int64_t tmp;
610 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
611 SET_PSW_F1 (PSW_F0);
612
613 tmp = SEXT40 (ACC (OP[0]));
614 if (tmp < 0 )
615 {
616 tmp = - tmp;
617 if (PSW_ST)
618 {
619 if (tmp > SEXT40(MAX32))
620 tmp = (MAX32);
621 else if (tmp < SEXT40(MIN32))
622 tmp = (MIN32);
623 else
624 tmp = (tmp & MASK40);
625 }
626 else
627 tmp = (tmp & MASK40);
628 SET_PSW_F0 (1);
629 }
630 else
631 {
632 tmp = (tmp & MASK40);
633 SET_PSW_F0 (0);
634 }
635 SET_ACC (OP[0], tmp);
636 trace_output_40 (sd, tmp);
637 }
638
639 /* add */
640 void
641 OP_200 (SIM_DESC sd, SIM_CPU *cpu)
642 {
643 uint16_t a = GPR (OP[0]);
644 uint16_t b = GPR (OP[1]);
645 uint16_t tmp = (a + b);
646 trace_input ("add", OP_REG, OP_REG, OP_VOID);
647 SET_PSW_C (a > tmp);
648 SET_GPR (OP[0], tmp);
649 trace_output_16 (sd, tmp);
650 }
651
652 /* add */
653 void
654 OP_1201 (SIM_DESC sd, SIM_CPU *cpu)
655 {
656 int64_t tmp;
657 tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
658
659 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
660 if (PSW_ST)
661 {
662 if (tmp > SEXT40(MAX32))
663 tmp = (MAX32);
664 else if (tmp < SEXT40(MIN32))
665 tmp = (MIN32);
666 else
667 tmp = (tmp & MASK40);
668 }
669 else
670 tmp = (tmp & MASK40);
671 SET_ACC (OP[0], tmp);
672 trace_output_40 (sd, tmp);
673 }
674
675 /* add */
676 void
677 OP_1203 (SIM_DESC sd, SIM_CPU *cpu)
678 {
679 int64_t tmp;
680 tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
681
682 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
683 if (PSW_ST)
684 {
685 if (tmp > SEXT40(MAX32))
686 tmp = (MAX32);
687 else if (tmp < SEXT40(MIN32))
688 tmp = (MIN32);
689 else
690 tmp = (tmp & MASK40);
691 }
692 else
693 tmp = (tmp & MASK40);
694 SET_ACC (OP[0], tmp);
695 trace_output_40 (sd, tmp);
696 }
697
698 /* add2w */
699 void
700 OP_1200 (SIM_DESC sd, SIM_CPU *cpu)
701 {
702 uint32_t tmp;
703 uint32_t a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
704 uint32_t b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
705 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
706 tmp = a + b;
707 SET_PSW_C (tmp < a);
708 SET_GPR (OP[0] + 0, (tmp >> 16));
709 SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
710 trace_output_32 (sd, tmp);
711 }
712
713 /* add3 */
714 void
715 OP_1000000 (SIM_DESC sd, SIM_CPU *cpu)
716 {
717 uint16_t a = GPR (OP[1]);
718 uint16_t b = OP[2];
719 uint16_t tmp = (a + b);
720 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
721 SET_PSW_C (tmp < a);
722 SET_GPR (OP[0], tmp);
723 trace_output_16 (sd, tmp);
724 }
725
726 /* addac3 */
727 void
728 OP_17000200 (SIM_DESC sd, SIM_CPU *cpu)
729 {
730 int64_t tmp;
731 tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
732
733 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
734 SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
735 SET_GPR (OP[0] + 1, (tmp & 0xffff));
736 trace_output_32 (sd, tmp);
737 }
738
739 /* addac3 */
740 void
741 OP_17000202 (SIM_DESC sd, SIM_CPU *cpu)
742 {
743 int64_t tmp;
744 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
745
746 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
747 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
748 SET_GPR (OP[0] + 1, tmp & 0xffff);
749 trace_output_32 (sd, tmp);
750 }
751
752 /* addac3s */
753 void
754 OP_17001200 (SIM_DESC sd, SIM_CPU *cpu)
755 {
756 int64_t tmp;
757 SET_PSW_F1 (PSW_F0);
758
759 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
760 tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
761 if (tmp > SEXT40(MAX32))
762 {
763 tmp = (MAX32);
764 SET_PSW_F0 (1);
765 }
766 else if (tmp < SEXT40(MIN32))
767 {
768 tmp = (MIN32);
769 SET_PSW_F0 (1);
770 }
771 else
772 {
773 SET_PSW_F0 (0);
774 }
775 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
776 SET_GPR (OP[0] + 1, (tmp & 0xffff));
777 trace_output_32 (sd, tmp);
778 }
779
780 /* addac3s */
781 void
782 OP_17001202 (SIM_DESC sd, SIM_CPU *cpu)
783 {
784 int64_t tmp;
785 SET_PSW_F1 (PSW_F0);
786
787 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
788 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
789 if (tmp > SEXT40(MAX32))
790 {
791 tmp = (MAX32);
792 SET_PSW_F0 (1);
793 }
794 else if (tmp < SEXT40(MIN32))
795 {
796 tmp = (MIN32);
797 SET_PSW_F0 (1);
798 }
799 else
800 {
801 SET_PSW_F0 (0);
802 }
803 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
804 SET_GPR (OP[0] + 1, (tmp & 0xffff));
805 trace_output_32 (sd, tmp);
806 }
807
808 /* addi */
809 void
810 OP_201 (SIM_DESC sd, SIM_CPU *cpu)
811 {
812 uint16_t a = GPR (OP[0]);
813 uint16_t b;
814 uint16_t tmp;
815 if (OP[1] == 0)
816 OP[1] = 16;
817 b = OP[1];
818 tmp = (a + b);
819 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
820 SET_PSW_C (tmp < a);
821 SET_GPR (OP[0], tmp);
822 trace_output_16 (sd, tmp);
823 }
824
825 /* and */
826 void
827 OP_C00 (SIM_DESC sd, SIM_CPU *cpu)
828 {
829 uint16_t tmp = GPR (OP[0]) & GPR (OP[1]);
830 trace_input ("and", OP_REG, OP_REG, OP_VOID);
831 SET_GPR (OP[0], tmp);
832 trace_output_16 (sd, tmp);
833 }
834
835 /* and3 */
836 void
837 OP_6000000 (SIM_DESC sd, SIM_CPU *cpu)
838 {
839 uint16_t tmp = GPR (OP[1]) & OP[2];
840 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
841 SET_GPR (OP[0], tmp);
842 trace_output_16 (sd, tmp);
843 }
844
845 /* bclri */
846 void
847 OP_C01 (SIM_DESC sd, SIM_CPU *cpu)
848 {
849 int16_t tmp;
850 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
851 tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
852 SET_GPR (OP[0], tmp);
853 trace_output_16 (sd, tmp);
854 }
855
856 /* bl.s */
857 void
858 OP_4900 (SIM_DESC sd, SIM_CPU *cpu)
859 {
860 trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
861 SET_GPR (13, PC + 1);
862 JMP( PC + SEXT8 (OP[0]));
863 trace_output_void (sd);
864 }
865
866 /* bl.l */
867 void
868 OP_24800000 (SIM_DESC sd, SIM_CPU *cpu)
869 {
870 trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
871 SET_GPR (13, (PC + 1));
872 JMP (PC + OP[0]);
873 trace_output_void (sd);
874 }
875
876 /* bnoti */
877 void
878 OP_A01 (SIM_DESC sd, SIM_CPU *cpu)
879 {
880 int16_t tmp;
881 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
882 tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
883 SET_GPR (OP[0], tmp);
884 trace_output_16 (sd, tmp);
885 }
886
887 /* bra.s */
888 void
889 OP_4800 (SIM_DESC sd, SIM_CPU *cpu)
890 {
891 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
892 JMP (PC + SEXT8 (OP[0]));
893 trace_output_void (sd);
894 }
895
896 /* bra.l */
897 void
898 OP_24000000 (SIM_DESC sd, SIM_CPU *cpu)
899 {
900 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
901 JMP (PC + OP[0]);
902 trace_output_void (sd);
903 }
904
905 /* brf0f.s */
906 void
907 OP_4A00 (SIM_DESC sd, SIM_CPU *cpu)
908 {
909 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
910 if (!PSW_F0)
911 JMP (PC + SEXT8 (OP[0]));
912 trace_output_flag (sd);
913 }
914
915 /* brf0f.l */
916 void
917 OP_25000000 (SIM_DESC sd, SIM_CPU *cpu)
918 {
919 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
920 if (!PSW_F0)
921 JMP (PC + OP[0]);
922 trace_output_flag (sd);
923 }
924
925 /* brf0t.s */
926 void
927 OP_4B00 (SIM_DESC sd, SIM_CPU *cpu)
928 {
929 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
930 if (PSW_F0)
931 JMP (PC + SEXT8 (OP[0]));
932 trace_output_flag (sd);
933 }
934
935 /* brf0t.l */
936 void
937 OP_25800000 (SIM_DESC sd, SIM_CPU *cpu)
938 {
939 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
940 if (PSW_F0)
941 JMP (PC + OP[0]);
942 trace_output_flag (sd);
943 }
944
945 /* bseti */
946 void
947 OP_801 (SIM_DESC sd, SIM_CPU *cpu)
948 {
949 int16_t tmp;
950 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
951 tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
952 SET_GPR (OP[0], tmp);
953 trace_output_16 (sd, tmp);
954 }
955
956 /* btsti */
957 void
958 OP_E01 (SIM_DESC sd, SIM_CPU *cpu)
959 {
960 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
961 SET_PSW_F1 (PSW_F0);
962 SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
963 trace_output_flag (sd);
964 }
965
966 /* clrac */
967 void
968 OP_5601 (SIM_DESC sd, SIM_CPU *cpu)
969 {
970 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
971 SET_ACC (OP[0], 0);
972 trace_output_40 (sd, 0);
973 }
974
975 /* cmp */
976 void
977 OP_600 (SIM_DESC sd, SIM_CPU *cpu)
978 {
979 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
980 SET_PSW_F1 (PSW_F0);
981 SET_PSW_F0 (((int16_t)(GPR (OP[0])) < (int16_t)(GPR (OP[1]))) ? 1 : 0);
982 trace_output_flag (sd);
983 }
984
985 /* cmp */
986 void
987 OP_1603 (SIM_DESC sd, SIM_CPU *cpu)
988 {
989 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
990 SET_PSW_F1 (PSW_F0);
991 SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
992 trace_output_flag (sd);
993 }
994
995 /* cmpeq */
996 void
997 OP_400 (SIM_DESC sd, SIM_CPU *cpu)
998 {
999 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
1000 SET_PSW_F1 (PSW_F0);
1001 SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
1002 trace_output_flag (sd);
1003 }
1004
1005 /* cmpeq */
1006 void
1007 OP_1403 (SIM_DESC sd, SIM_CPU *cpu)
1008 {
1009 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
1010 SET_PSW_F1 (PSW_F0);
1011 SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
1012 trace_output_flag (sd);
1013 }
1014
1015 /* cmpeqi.s */
1016 void
1017 OP_401 (SIM_DESC sd, SIM_CPU *cpu)
1018 {
1019 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1020 SET_PSW_F1 (PSW_F0);
1021 SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
1022 trace_output_flag (sd);
1023 }
1024
1025 /* cmpeqi.l */
1026 void
1027 OP_2000000 (SIM_DESC sd, SIM_CPU *cpu)
1028 {
1029 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1030 SET_PSW_F1 (PSW_F0);
1031 SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1032 trace_output_flag (sd);
1033 }
1034
1035 /* cmpi.s */
1036 void
1037 OP_601 (SIM_DESC sd, SIM_CPU *cpu)
1038 {
1039 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1040 SET_PSW_F1 (PSW_F0);
1041 SET_PSW_F0 (((int16_t)(GPR (OP[0])) < (int16_t)SEXT4(OP[1])) ? 1 : 0);
1042 trace_output_flag (sd);
1043 }
1044
1045 /* cmpi.l */
1046 void
1047 OP_3000000 (SIM_DESC sd, SIM_CPU *cpu)
1048 {
1049 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1050 SET_PSW_F1 (PSW_F0);
1051 SET_PSW_F0 (((int16_t)(GPR (OP[0])) < (int16_t)(OP[1])) ? 1 : 0);
1052 trace_output_flag (sd);
1053 }
1054
1055 /* cmpu */
1056 void
1057 OP_4600 (SIM_DESC sd, SIM_CPU *cpu)
1058 {
1059 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
1060 SET_PSW_F1 (PSW_F0);
1061 SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
1062 trace_output_flag (sd);
1063 }
1064
1065 /* cmpui */
1066 void
1067 OP_23000000 (SIM_DESC sd, SIM_CPU *cpu)
1068 {
1069 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
1070 SET_PSW_F1 (PSW_F0);
1071 SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
1072 trace_output_flag (sd);
1073 }
1074
1075 /* cpfg */
1076 void
1077 OP_4E09 (SIM_DESC sd, SIM_CPU *cpu)
1078 {
1079 uint8_t val;
1080
1081 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1082
1083 if (OP[1] == 0)
1084 val = PSW_F0;
1085 else if (OP[1] == 1)
1086 val = PSW_F1;
1087 else
1088 val = PSW_C;
1089 if (OP[0] == 0)
1090 SET_PSW_F0 (val);
1091 else
1092 SET_PSW_F1 (val);
1093
1094 trace_output_flag (sd);
1095 }
1096
1097 /* cpfg */
1098 void
1099 OP_4E0F (SIM_DESC sd, SIM_CPU *cpu)
1100 {
1101 uint8_t val;
1102
1103 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1104
1105 if (OP[1] == 0)
1106 val = PSW_F0;
1107 else if (OP[1] == 1)
1108 val = PSW_F1;
1109 else
1110 val = PSW_C;
1111 if (OP[0] == 0)
1112 SET_PSW_F0 (val);
1113 else
1114 SET_PSW_F1 (val);
1115
1116 trace_output_flag (sd);
1117 }
1118
1119 /* dbt */
1120 void
1121 OP_5F20 (SIM_DESC sd, SIM_CPU *cpu)
1122 {
1123 /* sim_io_printf (sd, "***** DBT ***** PC=%x\n",PC); */
1124
1125 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1126 The conditional below is for either of the instruction pairs
1127 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1128 where the dbt instruction should be interpreted.
1129
1130 The module `sim-break' provides a more effective mechanism for
1131 detecting GDB planted breakpoints. The code below may,
1132 eventually, be changed to use that mechanism. */
1133
1134 if (State.ins_type == INS_LEFT
1135 || State.ins_type == INS_RIGHT)
1136 {
1137 trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
1138 SET_DPC (PC + 1);
1139 SET_DPSW (PSW);
1140 SET_HW_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
1141 JMP (DBT_VECTOR_START);
1142 trace_output_void (sd);
1143 }
1144 else
1145 sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGTRAP);
1146 }
1147
1148 /* divs */
1149 void
1150 OP_14002800 (SIM_DESC sd, SIM_CPU *cpu)
1151 {
1152 uint16_t foo, tmp, tmpf;
1153 uint16_t hi;
1154 uint16_t lo;
1155
1156 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1157 foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
1158 tmp = (int16_t)foo - (int16_t)(GPR (OP[1]));
1159 tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
1160 hi = ((tmpf == 1) ? tmp : foo);
1161 lo = ((GPR (OP[0] + 1) << 1) | tmpf);
1162 SET_GPR (OP[0] + 0, hi);
1163 SET_GPR (OP[0] + 1, lo);
1164 trace_output_32 (sd, ((uint32_t) hi << 16) | lo);
1165 }
1166
1167 /* exef0f */
1168 void
1169 OP_4E04 (SIM_DESC sd, SIM_CPU *cpu)
1170 {
1171 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1172 State.exe = (PSW_F0 == 0);
1173 trace_output_flag (sd);
1174 }
1175
1176 /* exef0t */
1177 void
1178 OP_4E24 (SIM_DESC sd, SIM_CPU *cpu)
1179 {
1180 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1181 State.exe = (PSW_F0 != 0);
1182 trace_output_flag (sd);
1183 }
1184
1185 /* exef1f */
1186 void
1187 OP_4E40 (SIM_DESC sd, SIM_CPU *cpu)
1188 {
1189 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1190 State.exe = (PSW_F1 == 0);
1191 trace_output_flag (sd);
1192 }
1193
1194 /* exef1t */
1195 void
1196 OP_4E42 (SIM_DESC sd, SIM_CPU *cpu)
1197 {
1198 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1199 State.exe = (PSW_F1 != 0);
1200 trace_output_flag (sd);
1201 }
1202
1203 /* exefaf */
1204 void
1205 OP_4E00 (SIM_DESC sd, SIM_CPU *cpu)
1206 {
1207 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1208 State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
1209 trace_output_flag (sd);
1210 }
1211
1212 /* exefat */
1213 void
1214 OP_4E02 (SIM_DESC sd, SIM_CPU *cpu)
1215 {
1216 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1217 State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
1218 trace_output_flag (sd);
1219 }
1220
1221 /* exetaf */
1222 void
1223 OP_4E20 (SIM_DESC sd, SIM_CPU *cpu)
1224 {
1225 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1226 State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
1227 trace_output_flag (sd);
1228 }
1229
1230 /* exetat */
1231 void
1232 OP_4E22 (SIM_DESC sd, SIM_CPU *cpu)
1233 {
1234 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1235 State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
1236 trace_output_flag (sd);
1237 }
1238
1239 /* exp */
1240 void
1241 OP_15002A00 (SIM_DESC sd, SIM_CPU *cpu)
1242 {
1243 uint32_t tmp, foo;
1244 int i;
1245
1246 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1247 if (((int16_t)GPR (OP[1])) >= 0)
1248 tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
1249 else
1250 tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
1251
1252 foo = 0x40000000;
1253 for (i=1;i<17;i++)
1254 {
1255 if (tmp & foo)
1256 {
1257 SET_GPR (OP[0], (i - 1));
1258 trace_output_16 (sd, i - 1);
1259 return;
1260 }
1261 foo >>= 1;
1262 }
1263 SET_GPR (OP[0], 16);
1264 trace_output_16 (sd, 16);
1265 }
1266
1267 /* exp */
1268 void
1269 OP_15002A02 (SIM_DESC sd, SIM_CPU *cpu)
1270 {
1271 int64_t tmp, foo;
1272 int i;
1273
1274 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1275 tmp = SEXT40(ACC (OP[1]));
1276 if (tmp < 0)
1277 tmp = ~tmp & MASK40;
1278
1279 foo = 0x4000000000LL;
1280 for (i=1;i<25;i++)
1281 {
1282 if (tmp & foo)
1283 {
1284 SET_GPR (OP[0], i - 9);
1285 trace_output_16 (sd, i - 9);
1286 return;
1287 }
1288 foo >>= 1;
1289 }
1290 SET_GPR (OP[0], 16);
1291 trace_output_16 (sd, 16);
1292 }
1293
1294 /* jl */
1295 void
1296 OP_4D00 (SIM_DESC sd, SIM_CPU *cpu)
1297 {
1298 trace_input ("jl", OP_REG, OP_R0, OP_R1);
1299 SET_GPR (13, PC + 1);
1300 JMP (GPR (OP[0]));
1301 trace_output_void (sd);
1302 }
1303
1304 /* jmp */
1305 void
1306 OP_4C00 (SIM_DESC sd, SIM_CPU *cpu)
1307 {
1308 trace_input ("jmp", OP_REG,
1309 (OP[0] == 13) ? OP_R0 : OP_VOID,
1310 (OP[0] == 13) ? OP_R1 : OP_VOID);
1311
1312 JMP (GPR (OP[0]));
1313 trace_output_void (sd);
1314 }
1315
1316 /* ld */
1317 void
1318 OP_30000000 (SIM_DESC sd, SIM_CPU *cpu)
1319 {
1320 uint16_t tmp;
1321 uint16_t addr = OP[1] + GPR (OP[2]);
1322 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1323 if ((addr & 1))
1324 {
1325 trace_output_void (sd);
1326 EXCEPTION (SIM_SIGBUS);
1327 }
1328 tmp = RW (addr);
1329 SET_GPR (OP[0], tmp);
1330 trace_output_16 (sd, tmp);
1331 }
1332
1333 /* ld */
1334 void
1335 OP_6401 (SIM_DESC sd, SIM_CPU *cpu)
1336 {
1337 uint16_t tmp;
1338 uint16_t addr = GPR (OP[1]);
1339 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1340 if ((addr & 1))
1341 {
1342 trace_output_void (sd);
1343 EXCEPTION (SIM_SIGBUS);
1344 }
1345 tmp = RW (addr);
1346 SET_GPR (OP[0], tmp);
1347 if (OP[0] != OP[1])
1348 INC_ADDR (OP[1], -2);
1349 trace_output_16 (sd, tmp);
1350 }
1351
1352 /* ld */
1353 void
1354 OP_6001 (SIM_DESC sd, SIM_CPU *cpu)
1355 {
1356 uint16_t tmp;
1357 uint16_t addr = GPR (OP[1]);
1358 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1359 if ((addr & 1))
1360 {
1361 trace_output_void (sd);
1362 EXCEPTION (SIM_SIGBUS);
1363 }
1364 tmp = RW (addr);
1365 SET_GPR (OP[0], tmp);
1366 if (OP[0] != OP[1])
1367 INC_ADDR (OP[1], 2);
1368 trace_output_16 (sd, tmp);
1369 }
1370
1371 /* ld */
1372 void
1373 OP_6000 (SIM_DESC sd, SIM_CPU *cpu)
1374 {
1375 uint16_t tmp;
1376 uint16_t addr = GPR (OP[1]);
1377 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1378 if ((addr & 1))
1379 {
1380 trace_output_void (sd);
1381 EXCEPTION (SIM_SIGBUS);
1382 }
1383 tmp = RW (addr);
1384 SET_GPR (OP[0], tmp);
1385 trace_output_16 (sd, tmp);
1386 }
1387
1388 /* ld */
1389 void
1390 OP_32010000 (SIM_DESC sd, SIM_CPU *cpu)
1391 {
1392 uint16_t tmp;
1393 uint16_t addr = OP[1];
1394 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1395 if ((addr & 1))
1396 {
1397 trace_output_void (sd);
1398 EXCEPTION (SIM_SIGBUS);
1399 }
1400 tmp = RW (addr);
1401 SET_GPR (OP[0], tmp);
1402 trace_output_16 (sd, tmp);
1403 }
1404
1405 /* ld2w */
1406 void
1407 OP_31000000 (SIM_DESC sd, SIM_CPU *cpu)
1408 {
1409 int32_t tmp;
1410 uint16_t addr = OP[1] + GPR (OP[2]);
1411 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1412 if ((addr & 1))
1413 {
1414 trace_output_void (sd);
1415 EXCEPTION (SIM_SIGBUS);
1416 }
1417 tmp = RLW (addr);
1418 SET_GPR32 (OP[0], tmp);
1419 trace_output_32 (sd, tmp);
1420 }
1421
1422 /* ld2w */
1423 void
1424 OP_6601 (SIM_DESC sd, SIM_CPU *cpu)
1425 {
1426 uint16_t addr = GPR (OP[1]);
1427 int32_t tmp;
1428 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1429 if ((addr & 1))
1430 {
1431 trace_output_void (sd);
1432 EXCEPTION (SIM_SIGBUS);
1433 }
1434 tmp = RLW (addr);
1435 SET_GPR32 (OP[0], tmp);
1436 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1437 INC_ADDR (OP[1], -4);
1438 trace_output_32 (sd, tmp);
1439 }
1440
1441 /* ld2w */
1442 void
1443 OP_6201 (SIM_DESC sd, SIM_CPU *cpu)
1444 {
1445 int32_t tmp;
1446 uint16_t addr = GPR (OP[1]);
1447 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1448 if ((addr & 1))
1449 {
1450 trace_output_void (sd);
1451 EXCEPTION (SIM_SIGBUS);
1452 }
1453 tmp = RLW (addr);
1454 SET_GPR32 (OP[0], tmp);
1455 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1456 INC_ADDR (OP[1], 4);
1457 trace_output_32 (sd, tmp);
1458 }
1459
1460 /* ld2w */
1461 void
1462 OP_6200 (SIM_DESC sd, SIM_CPU *cpu)
1463 {
1464 uint16_t addr = GPR (OP[1]);
1465 int32_t tmp;
1466 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1467 if ((addr & 1))
1468 {
1469 trace_output_void (sd);
1470 EXCEPTION (SIM_SIGBUS);
1471 }
1472 tmp = RLW (addr);
1473 SET_GPR32 (OP[0], tmp);
1474 trace_output_32 (sd, tmp);
1475 }
1476
1477 /* ld2w */
1478 void
1479 OP_33010000 (SIM_DESC sd, SIM_CPU *cpu)
1480 {
1481 int32_t tmp;
1482 uint16_t addr = OP[1];
1483 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1484 if ((addr & 1))
1485 {
1486 trace_output_void (sd);
1487 EXCEPTION (SIM_SIGBUS);
1488 }
1489 tmp = RLW (addr);
1490 SET_GPR32 (OP[0], tmp);
1491 trace_output_32 (sd, tmp);
1492 }
1493
1494 /* ldb */
1495 void
1496 OP_38000000 (SIM_DESC sd, SIM_CPU *cpu)
1497 {
1498 int16_t tmp;
1499 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1500 tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
1501 SET_GPR (OP[0], tmp);
1502 trace_output_16 (sd, tmp);
1503 }
1504
1505 /* ldb */
1506 void
1507 OP_7000 (SIM_DESC sd, SIM_CPU *cpu)
1508 {
1509 int16_t tmp;
1510 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1511 tmp = SEXT8 (RB (GPR (OP[1])));
1512 SET_GPR (OP[0], tmp);
1513 trace_output_16 (sd, tmp);
1514 }
1515
1516 /* ldi.s */
1517 void
1518 OP_4001 (SIM_DESC sd, SIM_CPU *cpu)
1519 {
1520 int16_t tmp;
1521 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1522 tmp = SEXT4 (OP[1]);
1523 SET_GPR (OP[0], tmp);
1524 trace_output_16 (sd, tmp);
1525 }
1526
1527 /* ldi.l */
1528 void
1529 OP_20000000 (SIM_DESC sd, SIM_CPU *cpu)
1530 {
1531 int16_t tmp;
1532 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1533 tmp = OP[1];
1534 SET_GPR (OP[0], tmp);
1535 trace_output_16 (sd, tmp);
1536 }
1537
1538 /* ldub */
1539 void
1540 OP_39000000 (SIM_DESC sd, SIM_CPU *cpu)
1541 {
1542 int16_t tmp;
1543 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1544 tmp = RB (OP[1] + GPR (OP[2]));
1545 SET_GPR (OP[0], tmp);
1546 trace_output_16 (sd, tmp);
1547 }
1548
1549 /* ldub */
1550 void
1551 OP_7200 (SIM_DESC sd, SIM_CPU *cpu)
1552 {
1553 int16_t tmp;
1554 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1555 tmp = RB (GPR (OP[1]));
1556 SET_GPR (OP[0], tmp);
1557 trace_output_16 (sd, tmp);
1558 }
1559
1560 /* mac */
1561 void
1562 OP_2A00 (SIM_DESC sd, SIM_CPU *cpu)
1563 {
1564 int64_t tmp;
1565
1566 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1567 tmp = SEXT40 ((int16_t)(GPR (OP[1])) * (int16_t)(GPR (OP[2])));
1568
1569 if (PSW_FX)
1570 tmp = SEXT40( (tmp << 1) & MASK40);
1571
1572 if (PSW_ST && tmp > SEXT40(MAX32))
1573 tmp = (MAX32);
1574
1575 tmp += SEXT40 (ACC (OP[0]));
1576 if (PSW_ST)
1577 {
1578 if (tmp > SEXT40(MAX32))
1579 tmp = (MAX32);
1580 else if (tmp < SEXT40(MIN32))
1581 tmp = (MIN32);
1582 else
1583 tmp = (tmp & MASK40);
1584 }
1585 else
1586 tmp = (tmp & MASK40);
1587 SET_ACC (OP[0], tmp);
1588 trace_output_40 (sd, tmp);
1589 }
1590
1591 /* macsu */
1592 void
1593 OP_1A00 (SIM_DESC sd, SIM_CPU *cpu)
1594 {
1595 int64_t tmp;
1596
1597 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1598 tmp = SEXT40 ((int16_t) GPR (OP[1]) * GPR (OP[2]));
1599 if (PSW_FX)
1600 tmp = SEXT40 ((tmp << 1) & MASK40);
1601 tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
1602 SET_ACC (OP[0], tmp);
1603 trace_output_40 (sd, tmp);
1604 }
1605
1606 /* macu */
1607 void
1608 OP_3A00 (SIM_DESC sd, SIM_CPU *cpu)
1609 {
1610 uint64_t tmp;
1611 uint32_t src1;
1612 uint32_t src2;
1613
1614 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1615 src1 = (uint16_t) GPR (OP[1]);
1616 src2 = (uint16_t) GPR (OP[2]);
1617 tmp = src1 * src2;
1618 if (PSW_FX)
1619 tmp = (tmp << 1);
1620 tmp = ((ACC (OP[0]) + tmp) & MASK40);
1621 SET_ACC (OP[0], tmp);
1622 trace_output_40 (sd, tmp);
1623 }
1624
1625 /* max */
1626 void
1627 OP_2600 (SIM_DESC sd, SIM_CPU *cpu)
1628 {
1629 int16_t tmp;
1630 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1631 SET_PSW_F1 (PSW_F0);
1632 if ((int16_t) GPR (OP[1]) > (int16_t)GPR (OP[0]))
1633 {
1634 tmp = GPR (OP[1]);
1635 SET_PSW_F0 (1);
1636 }
1637 else
1638 {
1639 tmp = GPR (OP[0]);
1640 SET_PSW_F0 (0);
1641 }
1642 SET_GPR (OP[0], tmp);
1643 trace_output_16 (sd, tmp);
1644 }
1645
1646 /* max */
1647 void
1648 OP_3600 (SIM_DESC sd, SIM_CPU *cpu)
1649 {
1650 int64_t tmp;
1651
1652 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1653 SET_PSW_F1 (PSW_F0);
1654 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1655 if (tmp > SEXT40 (ACC (OP[0])))
1656 {
1657 tmp = (tmp & MASK40);
1658 SET_PSW_F0 (1);
1659 }
1660 else
1661 {
1662 tmp = ACC (OP[0]);
1663 SET_PSW_F0 (0);
1664 }
1665 SET_ACC (OP[0], tmp);
1666 trace_output_40 (sd, tmp);
1667 }
1668
1669 /* max */
1670 void
1671 OP_3602 (SIM_DESC sd, SIM_CPU *cpu)
1672 {
1673 int64_t tmp;
1674 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1675 SET_PSW_F1 (PSW_F0);
1676 if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
1677 {
1678 tmp = ACC (OP[1]);
1679 SET_PSW_F0 (1);
1680 }
1681 else
1682 {
1683 tmp = ACC (OP[0]);
1684 SET_PSW_F0 (0);
1685 }
1686 SET_ACC (OP[0], tmp);
1687 trace_output_40 (sd, tmp);
1688 }
1689
1690
1691 /* min */
1692 void
1693 OP_2601 (SIM_DESC sd, SIM_CPU *cpu)
1694 {
1695 int16_t tmp;
1696 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1697 SET_PSW_F1 (PSW_F0);
1698 if ((int16_t)GPR (OP[1]) < (int16_t)GPR (OP[0]))
1699 {
1700 tmp = GPR (OP[1]);
1701 SET_PSW_F0 (1);
1702 }
1703 else
1704 {
1705 tmp = GPR (OP[0]);
1706 SET_PSW_F0 (0);
1707 }
1708 SET_GPR (OP[0], tmp);
1709 trace_output_16 (sd, tmp);
1710 }
1711
1712 /* min */
1713 void
1714 OP_3601 (SIM_DESC sd, SIM_CPU *cpu)
1715 {
1716 int64_t tmp;
1717
1718 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1719 SET_PSW_F1 (PSW_F0);
1720 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1721 if (tmp < SEXT40(ACC (OP[0])))
1722 {
1723 tmp = (tmp & MASK40);
1724 SET_PSW_F0 (1);
1725 }
1726 else
1727 {
1728 tmp = ACC (OP[0]);
1729 SET_PSW_F0 (0);
1730 }
1731 SET_ACC (OP[0], tmp);
1732 trace_output_40 (sd, tmp);
1733 }
1734
1735 /* min */
1736 void
1737 OP_3603 (SIM_DESC sd, SIM_CPU *cpu)
1738 {
1739 int64_t tmp;
1740 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1741 SET_PSW_F1 (PSW_F0);
1742 if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
1743 {
1744 tmp = ACC (OP[1]);
1745 SET_PSW_F0 (1);
1746 }
1747 else
1748 {
1749 tmp = ACC (OP[0]);
1750 SET_PSW_F0 (0);
1751 }
1752 SET_ACC (OP[0], tmp);
1753 trace_output_40 (sd, tmp);
1754 }
1755
1756 /* msb */
1757 void
1758 OP_2800 (SIM_DESC sd, SIM_CPU *cpu)
1759 {
1760 int64_t tmp;
1761
1762 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1763 tmp = SEXT40 ((int16_t)(GPR (OP[1])) * (int16_t)(GPR (OP[2])));
1764
1765 if (PSW_FX)
1766 tmp = SEXT40 ((tmp << 1) & MASK40);
1767
1768 if (PSW_ST && tmp > SEXT40(MAX32))
1769 tmp = (MAX32);
1770
1771 tmp = SEXT40(ACC (OP[0])) - tmp;
1772 if (PSW_ST)
1773 {
1774 if (tmp > SEXT40(MAX32))
1775 tmp = (MAX32);
1776 else if (tmp < SEXT40(MIN32))
1777 tmp = (MIN32);
1778 else
1779 tmp = (tmp & MASK40);
1780 }
1781 else
1782 {
1783 tmp = (tmp & MASK40);
1784 }
1785 SET_ACC (OP[0], tmp);
1786 trace_output_40 (sd, tmp);
1787 }
1788
1789 /* msbsu */
1790 void
1791 OP_1800 (SIM_DESC sd, SIM_CPU *cpu)
1792 {
1793 int64_t tmp;
1794
1795 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1796 tmp = SEXT40 ((int16_t)GPR (OP[1]) * GPR (OP[2]));
1797 if (PSW_FX)
1798 tmp = SEXT40( (tmp << 1) & MASK40);
1799 tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
1800 SET_ACC (OP[0], tmp);
1801 trace_output_40 (sd, tmp);
1802 }
1803
1804 /* msbu */
1805 void
1806 OP_3800 (SIM_DESC sd, SIM_CPU *cpu)
1807 {
1808 uint64_t tmp;
1809 uint32_t src1;
1810 uint32_t src2;
1811
1812 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1813 src1 = (uint16_t) GPR (OP[1]);
1814 src2 = (uint16_t) GPR (OP[2]);
1815 tmp = src1 * src2;
1816 if (PSW_FX)
1817 tmp = (tmp << 1);
1818 tmp = ((ACC (OP[0]) - tmp) & MASK40);
1819 SET_ACC (OP[0], tmp);
1820 trace_output_40 (sd, tmp);
1821 }
1822
1823 /* mul */
1824 void
1825 OP_2E00 (SIM_DESC sd, SIM_CPU *cpu)
1826 {
1827 int16_t tmp;
1828 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1829 tmp = GPR (OP[0]) * GPR (OP[1]);
1830 SET_GPR (OP[0], tmp);
1831 trace_output_16 (sd, tmp);
1832 }
1833
1834 /* mulx */
1835 void
1836 OP_2C00 (SIM_DESC sd, SIM_CPU *cpu)
1837 {
1838 int64_t tmp;
1839
1840 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1841 tmp = SEXT40 ((int16_t)(GPR (OP[1])) * (int16_t)(GPR (OP[2])));
1842
1843 if (PSW_FX)
1844 tmp = SEXT40 ((tmp << 1) & MASK40);
1845
1846 if (PSW_ST && tmp > SEXT40(MAX32))
1847 tmp = (MAX32);
1848 else
1849 tmp = (tmp & MASK40);
1850 SET_ACC (OP[0], tmp);
1851 trace_output_40 (sd, tmp);
1852 }
1853
1854 /* mulxsu */
1855 void
1856 OP_1C00 (SIM_DESC sd, SIM_CPU *cpu)
1857 {
1858 int64_t tmp;
1859
1860 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1861 tmp = SEXT40 ((int16_t)(GPR (OP[1])) * GPR (OP[2]));
1862
1863 if (PSW_FX)
1864 tmp <<= 1;
1865 tmp = (tmp & MASK40);
1866 SET_ACC (OP[0], tmp);
1867 trace_output_40 (sd, tmp);
1868 }
1869
1870 /* mulxu */
1871 void
1872 OP_3C00 (SIM_DESC sd, SIM_CPU *cpu)
1873 {
1874 uint64_t tmp;
1875 uint32_t src1;
1876 uint32_t src2;
1877
1878 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1879 src1 = (uint16_t) GPR (OP[1]);
1880 src2 = (uint16_t) GPR (OP[2]);
1881 tmp = src1 * src2;
1882 if (PSW_FX)
1883 tmp <<= 1;
1884 tmp = (tmp & MASK40);
1885 SET_ACC (OP[0], tmp);
1886 trace_output_40 (sd, tmp);
1887 }
1888
1889 /* mv */
1890 void
1891 OP_4000 (SIM_DESC sd, SIM_CPU *cpu)
1892 {
1893 int16_t tmp;
1894 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1895 tmp = GPR (OP[1]);
1896 SET_GPR (OP[0], tmp);
1897 trace_output_16 (sd, tmp);
1898 }
1899
1900 /* mv2w */
1901 void
1902 OP_5000 (SIM_DESC sd, SIM_CPU *cpu)
1903 {
1904 int32_t tmp;
1905 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1906 tmp = GPR32 (OP[1]);
1907 SET_GPR32 (OP[0], tmp);
1908 trace_output_32 (sd, tmp);
1909 }
1910
1911 /* mv2wfac */
1912 void
1913 OP_3E00 (SIM_DESC sd, SIM_CPU *cpu)
1914 {
1915 int32_t tmp;
1916 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1917 tmp = ACC (OP[1]);
1918 SET_GPR32 (OP[0], tmp);
1919 trace_output_32 (sd, tmp);
1920 }
1921
1922 /* mv2wtac */
1923 void
1924 OP_3E01 (SIM_DESC sd, SIM_CPU *cpu)
1925 {
1926 int64_t tmp;
1927 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1928 tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
1929 SET_ACC (OP[1], tmp);
1930 trace_output_40 (sd, tmp);
1931 }
1932
1933 /* mvac */
1934 void
1935 OP_3E03 (SIM_DESC sd, SIM_CPU *cpu)
1936 {
1937 int64_t tmp;
1938 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1939 tmp = ACC (OP[1]);
1940 SET_ACC (OP[0], tmp);
1941 trace_output_40 (sd, tmp);
1942 }
1943
1944 /* mvb */
1945 void
1946 OP_5400 (SIM_DESC sd, SIM_CPU *cpu)
1947 {
1948 int16_t tmp;
1949 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1950 tmp = SEXT8 (GPR (OP[1]) & 0xff);
1951 SET_GPR (OP[0], tmp);
1952 trace_output_16 (sd, tmp);
1953 }
1954
1955 /* mvf0f */
1956 void
1957 OP_4400 (SIM_DESC sd, SIM_CPU *cpu)
1958 {
1959 int16_t tmp;
1960 trace_input ("mvf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1961 if (PSW_F0 == 0)
1962 {
1963 tmp = GPR (OP[1]);
1964 SET_GPR (OP[0], tmp);
1965 }
1966 else
1967 tmp = GPR (OP[0]);
1968 trace_output_16 (sd, tmp);
1969 }
1970
1971 /* mvf0t */
1972 void
1973 OP_4401 (SIM_DESC sd, SIM_CPU *cpu)
1974 {
1975 int16_t tmp;
1976 trace_input ("mvf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1977 if (PSW_F0)
1978 {
1979 tmp = GPR (OP[1]);
1980 SET_GPR (OP[0], tmp);
1981 }
1982 else
1983 tmp = GPR (OP[0]);
1984 trace_output_16 (sd, tmp);
1985 }
1986
1987 /* mvfacg */
1988 void
1989 OP_1E04 (SIM_DESC sd, SIM_CPU *cpu)
1990 {
1991 int16_t tmp;
1992 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1993 tmp = ((ACC (OP[1]) >> 32) & 0xff);
1994 SET_GPR (OP[0], tmp);
1995 trace_output_16 (sd, tmp);
1996 }
1997
1998 /* mvfachi */
1999 void
2000 OP_1E00 (SIM_DESC sd, SIM_CPU *cpu)
2001 {
2002 int16_t tmp;
2003 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2004 tmp = (ACC (OP[1]) >> 16);
2005 SET_GPR (OP[0], tmp);
2006 trace_output_16 (sd, tmp);
2007 }
2008
2009 /* mvfaclo */
2010 void
2011 OP_1E02 (SIM_DESC sd, SIM_CPU *cpu)
2012 {
2013 int16_t tmp;
2014 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2015 tmp = ACC (OP[1]);
2016 SET_GPR (OP[0], tmp);
2017 trace_output_16 (sd, tmp);
2018 }
2019
2020 /* mvfc */
2021 void
2022 OP_5200 (SIM_DESC sd, SIM_CPU *cpu)
2023 {
2024 int16_t tmp;
2025 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
2026 tmp = CREG (OP[1]);
2027 SET_GPR (OP[0], tmp);
2028 trace_output_16 (sd, tmp);
2029 }
2030
2031 /* mvtacg */
2032 void
2033 OP_1E41 (SIM_DESC sd, SIM_CPU *cpu)
2034 {
2035 int64_t tmp;
2036 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2037 tmp = ((ACC (OP[1]) & MASK32)
2038 | ((int64_t)(GPR (OP[0]) & 0xff) << 32));
2039 SET_ACC (OP[1], tmp);
2040 trace_output_40 (sd, tmp);
2041 }
2042
2043 /* mvtachi */
2044 void
2045 OP_1E01 (SIM_DESC sd, SIM_CPU *cpu)
2046 {
2047 uint64_t tmp;
2048 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2049 tmp = ACC (OP[1]) & 0xffff;
2050 tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
2051 SET_ACC (OP[1], tmp);
2052 trace_output_40 (sd, tmp);
2053 }
2054
2055 /* mvtaclo */
2056 void
2057 OP_1E21 (SIM_DESC sd, SIM_CPU *cpu)
2058 {
2059 int64_t tmp;
2060 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
2061 tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
2062 SET_ACC (OP[1], tmp);
2063 trace_output_40 (sd, tmp);
2064 }
2065
2066 /* mvtc */
2067 void
2068 OP_5600 (SIM_DESC sd, SIM_CPU *cpu)
2069 {
2070 int16_t tmp;
2071 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2072 tmp = GPR (OP[0]);
2073 tmp = SET_CREG (OP[1], tmp);
2074 trace_output_16 (sd, tmp);
2075 }
2076
2077 /* mvub */
2078 void
2079 OP_5401 (SIM_DESC sd, SIM_CPU *cpu)
2080 {
2081 int16_t tmp;
2082 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2083 tmp = (GPR (OP[1]) & 0xff);
2084 SET_GPR (OP[0], tmp);
2085 trace_output_16 (sd, tmp);
2086 }
2087
2088 /* neg */
2089 void
2090 OP_4605 (SIM_DESC sd, SIM_CPU *cpu)
2091 {
2092 int16_t tmp;
2093 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2094 tmp = - GPR (OP[0]);
2095 SET_GPR (OP[0], tmp);
2096 trace_output_16 (sd, tmp);
2097 }
2098
2099 /* neg */
2100 void
2101 OP_5605 (SIM_DESC sd, SIM_CPU *cpu)
2102 {
2103 int64_t tmp;
2104
2105 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
2106 tmp = -SEXT40(ACC (OP[0]));
2107 if (PSW_ST)
2108 {
2109 if (tmp > SEXT40(MAX32))
2110 tmp = (MAX32);
2111 else if (tmp < SEXT40(MIN32))
2112 tmp = (MIN32);
2113 else
2114 tmp = (tmp & MASK40);
2115 }
2116 else
2117 tmp = (tmp & MASK40);
2118 SET_ACC (OP[0], tmp);
2119 trace_output_40 (sd, tmp);
2120 }
2121
2122
2123 /* nop */
2124 void
2125 OP_5E00 (SIM_DESC sd, SIM_CPU *cpu)
2126 {
2127 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
2128
2129 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
2130 switch (State.ins_type)
2131 {
2132 default:
2133 ins_type_counters[ (int)INS_UNKNOWN ]++;
2134 break;
2135
2136 case INS_LEFT_PARALLEL:
2137 /* Don't count a parallel op that includes a NOP as a true parallel op */
2138 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
2139 ins_type_counters[ (int)INS_RIGHT ]++;
2140 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2141 break;
2142
2143 case INS_LEFT:
2144 case INS_LEFT_COND_EXE:
2145 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2146 break;
2147
2148 case INS_RIGHT_PARALLEL:
2149 /* Don't count a parallel op that includes a NOP as a true parallel op */
2150 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
2151 ins_type_counters[ (int)INS_LEFT ]++;
2152 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2153 break;
2154
2155 case INS_RIGHT:
2156 case INS_RIGHT_COND_EXE:
2157 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2158 break;
2159 }
2160
2161 trace_output_void (sd);
2162 }
2163
2164 /* not */
2165 void
2166 OP_4603 (SIM_DESC sd, SIM_CPU *cpu)
2167 {
2168 int16_t tmp;
2169 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2170 tmp = ~GPR (OP[0]);
2171 SET_GPR (OP[0], tmp);
2172 trace_output_16 (sd, tmp);
2173 }
2174
2175 /* or */
2176 void
2177 OP_800 (SIM_DESC sd, SIM_CPU *cpu)
2178 {
2179 int16_t tmp;
2180 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2181 tmp = (GPR (OP[0]) | GPR (OP[1]));
2182 SET_GPR (OP[0], tmp);
2183 trace_output_16 (sd, tmp);
2184 }
2185
2186 /* or3 */
2187 void
2188 OP_4000000 (SIM_DESC sd, SIM_CPU *cpu)
2189 {
2190 int16_t tmp;
2191 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2192 tmp = (GPR (OP[1]) | OP[2]);
2193 SET_GPR (OP[0], tmp);
2194 trace_output_16 (sd, tmp);
2195 }
2196
2197 /* rac */
2198 void
2199 OP_5201 (SIM_DESC sd, SIM_CPU *cpu)
2200 {
2201 int64_t tmp;
2202 int shift = SEXT3 (OP[2]);
2203
2204 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2205 if (OP[1] != 0)
2206 {
2207 sim_io_printf (sd,
2208 "ERROR at PC 0x%x: instruction only valid for A0\n",
2209 PC<<2);
2210 EXCEPTION (SIM_SIGILL);
2211 }
2212
2213 SET_PSW_F1 (PSW_F0);
2214 tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2215 if (shift >=0)
2216 tmp <<= shift;
2217 else
2218 tmp >>= -shift;
2219 tmp += 0x8000;
2220 tmp >>= 16; /* look at bits 0:43 */
2221 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2222 {
2223 tmp = 0x7fffffff;
2224 SET_PSW_F0 (1);
2225 }
2226 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2227 {
2228 tmp = 0x80000000;
2229 SET_PSW_F0 (1);
2230 }
2231 else
2232 {
2233 SET_PSW_F0 (0);
2234 }
2235 SET_GPR32 (OP[0], tmp);
2236 trace_output_32 (sd, tmp);
2237 }
2238
2239 /* rachi */
2240 void
2241 OP_4201 (SIM_DESC sd, SIM_CPU *cpu)
2242 {
2243 int64_t tmp;
2244 int shift = SEXT3 (OP[2]);
2245
2246 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2247 SET_PSW_F1 (PSW_F0);
2248 if (shift >=0)
2249 tmp = SEXT40 (ACC (OP[1])) << shift;
2250 else
2251 tmp = SEXT40 (ACC (OP[1])) >> -shift;
2252 tmp += 0x8000;
2253
2254 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2255 {
2256 tmp = 0x7fff;
2257 SET_PSW_F0 (1);
2258 }
2259 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2260 {
2261 tmp = 0x8000;
2262 SET_PSW_F0 (1);
2263 }
2264 else
2265 {
2266 tmp = (tmp >> 16);
2267 SET_PSW_F0 (0);
2268 }
2269 SET_GPR (OP[0], tmp);
2270 trace_output_16 (sd, tmp);
2271 }
2272
2273 /* rep */
2274 void
2275 OP_27000000 (SIM_DESC sd, SIM_CPU *cpu)
2276 {
2277 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2278 SET_RPT_S (PC + 1);
2279 SET_RPT_E (PC + OP[1]);
2280 SET_RPT_C (GPR (OP[0]));
2281 SET_PSW_RP (1);
2282 if (GPR (OP[0]) == 0)
2283 {
2284 sim_io_printf (sd, "ERROR: rep with count=0 is illegal.\n");
2285 EXCEPTION (SIM_SIGILL);
2286 }
2287 if (OP[1] < 4)
2288 {
2289 sim_io_printf (sd, "ERROR: rep must include at least 4 instructions.\n");
2290 EXCEPTION (SIM_SIGILL);
2291 }
2292 trace_output_void (sd);
2293 }
2294
2295 /* repi */
2296 void
2297 OP_2F000000 (SIM_DESC sd, SIM_CPU *cpu)
2298 {
2299 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2300 SET_RPT_S (PC + 1);
2301 SET_RPT_E (PC + OP[1]);
2302 SET_RPT_C (OP[0]);
2303 SET_PSW_RP (1);
2304 if (OP[0] == 0)
2305 {
2306 sim_io_printf (sd, "ERROR: repi with count=0 is illegal.\n");
2307 EXCEPTION (SIM_SIGILL);
2308 }
2309 if (OP[1] < 4)
2310 {
2311 sim_io_printf (sd, "ERROR: repi must include at least 4 instructions.\n");
2312 EXCEPTION (SIM_SIGILL);
2313 }
2314 trace_output_void (sd);
2315 }
2316
2317 /* rtd */
2318 void
2319 OP_5F60 (SIM_DESC sd, SIM_CPU *cpu)
2320 {
2321 trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
2322 SET_CREG (PSW_CR, DPSW);
2323 JMP(DPC);
2324 trace_output_void (sd);
2325 }
2326
2327 /* rte */
2328 void
2329 OP_5F40 (SIM_DESC sd, SIM_CPU *cpu)
2330 {
2331 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2332 SET_CREG (PSW_CR, BPSW);
2333 JMP(BPC);
2334 trace_output_void (sd);
2335 }
2336
2337 /* sac */
2338 void OP_5209 (SIM_DESC sd, SIM_CPU *cpu)
2339 {
2340 int64_t tmp;
2341
2342 trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2343
2344 tmp = SEXT40(ACC (OP[1]));
2345
2346 SET_PSW_F1 (PSW_F0);
2347
2348 if (tmp > SEXT40(MAX32))
2349 {
2350 tmp = (MAX32);
2351 SET_PSW_F0 (1);
2352 }
2353 else if (tmp < SEXT40(MIN32))
2354 {
2355 tmp = 0x80000000;
2356 SET_PSW_F0 (1);
2357 }
2358 else
2359 {
2360 tmp = (tmp & MASK32);
2361 SET_PSW_F0 (0);
2362 }
2363
2364 SET_GPR32 (OP[0], tmp);
2365
2366 trace_output_40 (sd, tmp);
2367 }
2368
2369 /* sachi */
2370 void
2371 OP_4209 (SIM_DESC sd, SIM_CPU *cpu)
2372 {
2373 int64_t tmp;
2374
2375 trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2376
2377 tmp = SEXT40(ACC (OP[1]));
2378
2379 SET_PSW_F1 (PSW_F0);
2380
2381 if (tmp > SEXT40(MAX32))
2382 {
2383 tmp = 0x7fff;
2384 SET_PSW_F0 (1);
2385 }
2386 else if (tmp < SEXT40(MIN32))
2387 {
2388 tmp = 0x8000;
2389 SET_PSW_F0 (1);
2390 }
2391 else
2392 {
2393 tmp >>= 16;
2394 SET_PSW_F0 (0);
2395 }
2396
2397 SET_GPR (OP[0], tmp);
2398
2399 trace_output_16 (sd, OP[0]);
2400 }
2401
2402 /* sadd */
2403 void
2404 OP_1223 (SIM_DESC sd, SIM_CPU *cpu)
2405 {
2406 int64_t tmp;
2407
2408 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2409 tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
2410 if (PSW_ST)
2411 {
2412 if (tmp > SEXT40(MAX32))
2413 tmp = (MAX32);
2414 else if (tmp < SEXT40(MIN32))
2415 tmp = (MIN32);
2416 else
2417 tmp = (tmp & MASK40);
2418 }
2419 else
2420 tmp = (tmp & MASK40);
2421 SET_ACC (OP[0], tmp);
2422 trace_output_40 (sd, tmp);
2423 }
2424
2425 /* setf0f */
2426 void
2427 OP_4611 (SIM_DESC sd, SIM_CPU *cpu)
2428 {
2429 int16_t tmp;
2430 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2431 tmp = ((PSW_F0 == 0) ? 1 : 0);
2432 SET_GPR (OP[0], tmp);
2433 trace_output_16 (sd, tmp);
2434 }
2435
2436 /* setf0t */
2437 void
2438 OP_4613 (SIM_DESC sd, SIM_CPU *cpu)
2439 {
2440 int16_t tmp;
2441 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2442 tmp = ((PSW_F0 == 1) ? 1 : 0);
2443 SET_GPR (OP[0], tmp);
2444 trace_output_16 (sd, tmp);
2445 }
2446
2447 /* slae */
2448 void
2449 OP_3220 (SIM_DESC sd, SIM_CPU *cpu)
2450 {
2451 int64_t tmp;
2452 int16_t reg;
2453
2454 trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
2455
2456 reg = SEXT16 (GPR (OP[1]));
2457
2458 if (reg >= 17 || reg <= -17)
2459 {
2460 sim_io_printf (sd, "ERROR: shift value %d too large.\n", reg);
2461 EXCEPTION (SIM_SIGILL);
2462 }
2463
2464 tmp = SEXT40 (ACC (OP[0]));
2465
2466 if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32)))
2467 {
2468 sim_io_printf (sd, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp >> 32) & 0xff), ((unsigned long) tmp) & 0xffffffff);
2469 EXCEPTION (SIM_SIGILL);
2470 }
2471
2472 if (reg >= 0 && reg <= 16)
2473 {
2474 tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1])));
2475 if (PSW_ST)
2476 {
2477 if (tmp > SEXT40(MAX32))
2478 tmp = (MAX32);
2479 else if (tmp < SEXT40(MIN32))
2480 tmp = (MIN32);
2481 else
2482 tmp = (tmp & MASK40);
2483 }
2484 else
2485 tmp = (tmp & MASK40);
2486 }
2487 else
2488 {
2489 tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1]));
2490 }
2491
2492 SET_ACC(OP[0], tmp);
2493
2494 trace_output_40 (sd, tmp);
2495 }
2496
2497 /* sleep */
2498 void
2499 OP_5FC0 (SIM_DESC sd, SIM_CPU *cpu)
2500 {
2501 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2502 SET_PSW_IE (1);
2503 trace_output_void (sd);
2504 }
2505
2506 /* sll */
2507 void
2508 OP_2200 (SIM_DESC sd, SIM_CPU *cpu)
2509 {
2510 int16_t tmp;
2511 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2512 tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
2513 SET_GPR (OP[0], tmp);
2514 trace_output_16 (sd, tmp);
2515 }
2516
2517 /* sll */
2518 void
2519 OP_3200 (SIM_DESC sd, SIM_CPU *cpu)
2520 {
2521 int64_t tmp;
2522 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2523 if ((GPR (OP[1]) & 31) <= 16)
2524 tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
2525 else
2526 {
2527 sim_io_printf (sd, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2528 EXCEPTION (SIM_SIGILL);
2529 }
2530
2531 if (PSW_ST)
2532 {
2533 if (tmp > SEXT40(MAX32))
2534 tmp = (MAX32);
2535 else if (tmp < SEXT40(MIN32))
2536 tmp = (MIN32);
2537 else
2538 tmp = (tmp & MASK40);
2539 }
2540 else
2541 tmp = (tmp & MASK40);
2542 SET_ACC (OP[0], tmp);
2543 trace_output_40 (sd, tmp);
2544 }
2545
2546 /* slli */
2547 void
2548 OP_2201 (SIM_DESC sd, SIM_CPU *cpu)
2549 {
2550 int16_t tmp;
2551 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2552 tmp = (GPR (OP[0]) << OP[1]);
2553 SET_GPR (OP[0], tmp);
2554 trace_output_16 (sd, tmp);
2555 }
2556
2557 /* slli */
2558 void
2559 OP_3201 (SIM_DESC sd, SIM_CPU *cpu)
2560 {
2561 int64_t tmp;
2562
2563 if (OP[1] == 0)
2564 OP[1] = 16;
2565
2566 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2567 tmp = SEXT40(ACC (OP[0])) << OP[1];
2568
2569 if (PSW_ST)
2570 {
2571 if (tmp > SEXT40(MAX32))
2572 tmp = (MAX32);
2573 else if (tmp < SEXT40(MIN32))
2574 tmp = (MIN32);
2575 else
2576 tmp = (tmp & MASK40);
2577 }
2578 else
2579 tmp = (tmp & MASK40);
2580 SET_ACC (OP[0], tmp);
2581 trace_output_40 (sd, tmp);
2582 }
2583
2584 /* slx */
2585 void
2586 OP_460B (SIM_DESC sd, SIM_CPU *cpu)
2587 {
2588 int16_t tmp;
2589 trace_input ("slx", OP_REG, OP_VOID, OP_VOID);
2590 tmp = ((GPR (OP[0]) << 1) | PSW_F0);
2591 SET_GPR (OP[0], tmp);
2592 trace_output_16 (sd, tmp);
2593 }
2594
2595 /* sra */
2596 void
2597 OP_2400 (SIM_DESC sd, SIM_CPU *cpu)
2598 {
2599 int16_t tmp;
2600 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2601 tmp = (((int16_t)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
2602 SET_GPR (OP[0], tmp);
2603 trace_output_16 (sd, tmp);
2604 }
2605
2606 /* sra */
2607 void
2608 OP_3400 (SIM_DESC sd, SIM_CPU *cpu)
2609 {
2610 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2611 if ((GPR (OP[1]) & 31) <= 16)
2612 {
2613 int64_t tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
2614 SET_ACC (OP[0], tmp);
2615 trace_output_40 (sd, tmp);
2616 }
2617 else
2618 {
2619 sim_io_printf (sd, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2620 EXCEPTION (SIM_SIGILL);
2621 }
2622 }
2623
2624 /* srai */
2625 void
2626 OP_2401 (SIM_DESC sd, SIM_CPU *cpu)
2627 {
2628 int16_t tmp;
2629 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2630 tmp = (((int16_t)(GPR (OP[0]))) >> OP[1]);
2631 SET_GPR (OP[0], tmp);
2632 trace_output_16 (sd, tmp);
2633 }
2634
2635 /* srai */
2636 void
2637 OP_3401 (SIM_DESC sd, SIM_CPU *cpu)
2638 {
2639 int64_t tmp;
2640 if (OP[1] == 0)
2641 OP[1] = 16;
2642
2643 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2644 tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
2645 SET_ACC (OP[0], tmp);
2646 trace_output_40 (sd, tmp);
2647 }
2648
2649 /* srl */
2650 void
2651 OP_2000 (SIM_DESC sd, SIM_CPU *cpu)
2652 {
2653 int16_t tmp;
2654 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2655 tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
2656 SET_GPR (OP[0], tmp);
2657 trace_output_16 (sd, tmp);
2658 }
2659
2660 /* srl */
2661 void
2662 OP_3000 (SIM_DESC sd, SIM_CPU *cpu)
2663 {
2664 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2665 if ((GPR (OP[1]) & 31) <= 16)
2666 {
2667 int64_t tmp = ((uint64_t)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
2668 SET_ACC (OP[0], tmp);
2669 trace_output_40 (sd, tmp);
2670 }
2671 else
2672 {
2673 sim_io_printf (sd, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2674 EXCEPTION (SIM_SIGILL);
2675 }
2676
2677 }
2678
2679 /* srli */
2680 void
2681 OP_2001 (SIM_DESC sd, SIM_CPU *cpu)
2682 {
2683 int16_t tmp;
2684 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2685 tmp = (GPR (OP[0]) >> OP[1]);
2686 SET_GPR (OP[0], tmp);
2687 trace_output_16 (sd, tmp);
2688 }
2689
2690 /* srli */
2691 void
2692 OP_3001 (SIM_DESC sd, SIM_CPU *cpu)
2693 {
2694 int64_t tmp;
2695 if (OP[1] == 0)
2696 OP[1] = 16;
2697
2698 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2699 tmp = ((uint64_t)(ACC (OP[0]) & MASK40) >> OP[1]);
2700 SET_ACC (OP[0], tmp);
2701 trace_output_40 (sd, tmp);
2702 }
2703
2704 /* srx */
2705 void
2706 OP_4609 (SIM_DESC sd, SIM_CPU *cpu)
2707 {
2708 uint16_t tmp;
2709 trace_input ("srx", OP_REG, OP_VOID, OP_VOID);
2710 tmp = PSW_F0 << 15;
2711 tmp = ((GPR (OP[0]) >> 1) | tmp);
2712 SET_GPR (OP[0], tmp);
2713 trace_output_16 (sd, tmp);
2714 }
2715
2716 /* st */
2717 void
2718 OP_34000000 (SIM_DESC sd, SIM_CPU *cpu)
2719 {
2720 uint16_t addr = OP[1] + GPR (OP[2]);
2721 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2722 if ((addr & 1))
2723 {
2724 trace_output_void (sd);
2725 EXCEPTION (SIM_SIGBUS);
2726 }
2727 SW (addr, GPR (OP[0]));
2728 trace_output_void (sd);
2729 }
2730
2731 /* st */
2732 void
2733 OP_6800 (SIM_DESC sd, SIM_CPU *cpu)
2734 {
2735 uint16_t addr = GPR (OP[1]);
2736 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2737 if ((addr & 1))
2738 {
2739 trace_output_void (sd);
2740 EXCEPTION (SIM_SIGBUS);
2741 }
2742 SW (addr, GPR (OP[0]));
2743 trace_output_void (sd);
2744 }
2745
2746 /* st */
2747 /* st Rsrc1,@-SP */
2748 void
2749 OP_6C1F (SIM_DESC sd, SIM_CPU *cpu)
2750 {
2751 uint16_t addr = GPR (OP[1]) - 2;
2752 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2753 if (OP[1] != 15)
2754 {
2755 sim_io_printf (sd, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2756 EXCEPTION (SIM_SIGILL);
2757 }
2758 if ((addr & 1))
2759 {
2760 trace_output_void (sd);
2761 EXCEPTION (SIM_SIGBUS);
2762 }
2763 SW (addr, GPR (OP[0]));
2764 SET_GPR (OP[1], addr);
2765 trace_output_void (sd);
2766 }
2767
2768 /* st */
2769 void
2770 OP_6801 (SIM_DESC sd, SIM_CPU *cpu)
2771 {
2772 uint16_t addr = GPR (OP[1]);
2773 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2774 if ((addr & 1))
2775 {
2776 trace_output_void (sd);
2777 EXCEPTION (SIM_SIGBUS);
2778 }
2779 SW (addr, GPR (OP[0]));
2780 INC_ADDR (OP[1], 2);
2781 trace_output_void (sd);
2782 }
2783
2784 /* st */
2785 void
2786 OP_6C01 (SIM_DESC sd, SIM_CPU *cpu)
2787 {
2788 uint16_t addr = GPR (OP[1]);
2789 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2790 if ( OP[1] == 15 )
2791 {
2792 sim_io_printf (sd, "ERROR: cannot post-decrement register r15 (SP).\n");
2793 EXCEPTION (SIM_SIGILL);
2794 }
2795 if ((addr & 1))
2796 {
2797 trace_output_void (sd);
2798 EXCEPTION (SIM_SIGBUS);
2799 }
2800 SW (addr, GPR (OP[0]));
2801 INC_ADDR (OP[1], -2);
2802 trace_output_void (sd);
2803 }
2804
2805 /* st */
2806 void
2807 OP_36010000 (SIM_DESC sd, SIM_CPU *cpu)
2808 {
2809 uint16_t addr = OP[1];
2810 trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
2811 if ((addr & 1))
2812 {
2813 trace_output_void (sd);
2814 EXCEPTION (SIM_SIGBUS);
2815 }
2816 SW (addr, GPR (OP[0]));
2817 trace_output_void (sd);
2818 }
2819
2820 /* st2w */
2821 void
2822 OP_35000000 (SIM_DESC sd, SIM_CPU *cpu)
2823 {
2824 uint16_t addr = GPR (OP[2])+ OP[1];
2825 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2826 if ((addr & 1))
2827 {
2828 trace_output_void (sd);
2829 EXCEPTION (SIM_SIGBUS);
2830 }
2831 SW (addr + 0, GPR (OP[0] + 0));
2832 SW (addr + 2, GPR (OP[0] + 1));
2833 trace_output_void (sd);
2834 }
2835
2836 /* st2w */
2837 void
2838 OP_6A00 (SIM_DESC sd, SIM_CPU *cpu)
2839 {
2840 uint16_t addr = GPR (OP[1]);
2841 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2842 if ((addr & 1))
2843 {
2844 trace_output_void (sd);
2845 EXCEPTION (SIM_SIGBUS);
2846 }
2847 SW (addr + 0, GPR (OP[0] + 0));
2848 SW (addr + 2, GPR (OP[0] + 1));
2849 trace_output_void (sd);
2850 }
2851
2852 /* st2w */
2853 void
2854 OP_6E1F (SIM_DESC sd, SIM_CPU *cpu)
2855 {
2856 uint16_t addr = GPR (OP[1]) - 4;
2857 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2858 if ( OP[1] != 15 )
2859 {
2860 sim_io_printf (sd, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2861 EXCEPTION (SIM_SIGILL);
2862 }
2863 if ((addr & 1))
2864 {
2865 trace_output_void (sd);
2866 EXCEPTION (SIM_SIGBUS);
2867 }
2868 SW (addr + 0, GPR (OP[0] + 0));
2869 SW (addr + 2, GPR (OP[0] + 1));
2870 SET_GPR (OP[1], addr);
2871 trace_output_void (sd);
2872 }
2873
2874 /* st2w */
2875 void
2876 OP_6A01 (SIM_DESC sd, SIM_CPU *cpu)
2877 {
2878 uint16_t addr = GPR (OP[1]);
2879 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2880 if ((addr & 1))
2881 {
2882 trace_output_void (sd);
2883 EXCEPTION (SIM_SIGBUS);
2884 }
2885 SW (addr + 0, GPR (OP[0] + 0));
2886 SW (addr + 2, GPR (OP[0] + 1));
2887 INC_ADDR (OP[1], 4);
2888 trace_output_void (sd);
2889 }
2890
2891 /* st2w */
2892 void
2893 OP_6E01 (SIM_DESC sd, SIM_CPU *cpu)
2894 {
2895 uint16_t addr = GPR (OP[1]);
2896 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2897 if ( OP[1] == 15 )
2898 {
2899 sim_io_printf (sd, "ERROR: cannot post-decrement register r15 (SP).\n");
2900 EXCEPTION (SIM_SIGILL);
2901 }
2902 if ((addr & 1))
2903 {
2904 trace_output_void (sd);
2905 EXCEPTION (SIM_SIGBUS);
2906 }
2907 SW (addr + 0, GPR (OP[0] + 0));
2908 SW (addr + 2, GPR (OP[0] + 1));
2909 INC_ADDR (OP[1], -4);
2910 trace_output_void (sd);
2911 }
2912
2913 /* st2w */
2914 void
2915 OP_37010000 (SIM_DESC sd, SIM_CPU *cpu)
2916 {
2917 uint16_t addr = OP[1];
2918 trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
2919 if ((addr & 1))
2920 {
2921 trace_output_void (sd);
2922 EXCEPTION (SIM_SIGBUS);
2923 }
2924 SW (addr + 0, GPR (OP[0] + 0));
2925 SW (addr + 2, GPR (OP[0] + 1));
2926 trace_output_void (sd);
2927 }
2928
2929 /* stb */
2930 void
2931 OP_3C000000 (SIM_DESC sd, SIM_CPU *cpu)
2932 {
2933 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2934 SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
2935 trace_output_void (sd);
2936 }
2937
2938 /* stb */
2939 void
2940 OP_7800 (SIM_DESC sd, SIM_CPU *cpu)
2941 {
2942 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2943 SB (GPR (OP[1]), GPR (OP[0]));
2944 trace_output_void (sd);
2945 }
2946
2947 /* stop */
2948 void
2949 OP_5FE0 (SIM_DESC sd, SIM_CPU *cpu)
2950 {
2951 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2952 trace_output_void (sd);
2953 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, 0);
2954 }
2955
2956 /* sub */
2957 void
2958 OP_0 (SIM_DESC sd, SIM_CPU *cpu)
2959 {
2960 uint16_t a = GPR (OP[0]);
2961 uint16_t b = GPR (OP[1]);
2962 uint16_t tmp = (a - b);
2963 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2964 /* see ../common/sim-alu.h for a more extensive discussion on how to
2965 compute the carry/overflow bits. */
2966 SET_PSW_C (a >= b);
2967 SET_GPR (OP[0], tmp);
2968 trace_output_16 (sd, tmp);
2969 }
2970
2971 /* sub */
2972 void
2973 OP_1001 (SIM_DESC sd, SIM_CPU *cpu)
2974 {
2975 int64_t tmp;
2976
2977 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2978 tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
2979 if (PSW_ST)
2980 {
2981 if (tmp > SEXT40(MAX32))
2982 tmp = (MAX32);
2983 else if (tmp < SEXT40(MIN32))
2984 tmp = (MIN32);
2985 else
2986 tmp = (tmp & MASK40);
2987 }
2988 else
2989 tmp = (tmp & MASK40);
2990 SET_ACC (OP[0], tmp);
2991
2992 trace_output_40 (sd, tmp);
2993 }
2994
2995 /* sub */
2996
2997 void
2998 OP_1003 (SIM_DESC sd, SIM_CPU *cpu)
2999 {
3000 int64_t tmp;
3001
3002 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
3003 tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
3004 if (PSW_ST)
3005 {
3006 if (tmp > SEXT40(MAX32))
3007 tmp = (MAX32);
3008 else if (tmp < SEXT40(MIN32))
3009 tmp = (MIN32);
3010 else
3011 tmp = (tmp & MASK40);
3012 }
3013 else
3014 tmp = (tmp & MASK40);
3015 SET_ACC (OP[0], tmp);
3016
3017 trace_output_40 (sd, tmp);
3018 }
3019
3020 /* sub2w */
3021 void
3022 OP_1000 (SIM_DESC sd, SIM_CPU *cpu)
3023 {
3024 uint32_t tmp, a, b;
3025
3026 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
3027 a = (uint32_t)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
3028 b = (uint32_t)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
3029 /* see ../common/sim-alu.h for a more extensive discussion on how to
3030 compute the carry/overflow bits */
3031 tmp = a - b;
3032 SET_PSW_C (a >= b);
3033 SET_GPR32 (OP[0], tmp);
3034 trace_output_32 (sd, tmp);
3035 }
3036
3037 /* subac3 */
3038 void
3039 OP_17000000 (SIM_DESC sd, SIM_CPU *cpu)
3040 {
3041 int64_t tmp;
3042
3043 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
3044 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
3045 SET_GPR32 (OP[0], tmp);
3046 trace_output_32 (sd, tmp);
3047 }
3048
3049 /* subac3 */
3050 void
3051 OP_17000002 (SIM_DESC sd, SIM_CPU *cpu)
3052 {
3053 int64_t tmp;
3054
3055 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
3056 tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
3057 SET_GPR32 (OP[0], tmp);
3058 trace_output_32 (sd, tmp);
3059 }
3060
3061 /* subac3s */
3062 void
3063 OP_17001000 (SIM_DESC sd, SIM_CPU *cpu)
3064 {
3065 int64_t tmp;
3066
3067 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
3068 SET_PSW_F1 (PSW_F0);
3069 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
3070 if (tmp > SEXT40(MAX32))
3071 {
3072 tmp = (MAX32);
3073 SET_PSW_F0 (1);
3074 }
3075 else if (tmp < SEXT40(MIN32))
3076 {
3077 tmp = (MIN32);
3078 SET_PSW_F0 (1);
3079 }
3080 else
3081 {
3082 SET_PSW_F0 (0);
3083 }
3084 SET_GPR32 (OP[0], tmp);
3085 trace_output_32 (sd, tmp);
3086 }
3087
3088 /* subac3s */
3089 void
3090 OP_17001002 (SIM_DESC sd, SIM_CPU *cpu)
3091 {
3092 int64_t tmp;
3093
3094 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
3095 SET_PSW_F1 (PSW_F0);
3096 tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
3097 if (tmp > SEXT40(MAX32))
3098 {
3099 tmp = (MAX32);
3100 SET_PSW_F0 (1);
3101 }
3102 else if (tmp < SEXT40(MIN32))
3103 {
3104 tmp = (MIN32);
3105 SET_PSW_F0 (1);
3106 }
3107 else
3108 {
3109 SET_PSW_F0 (0);
3110 }
3111 SET_GPR32 (OP[0], tmp);
3112 trace_output_32 (sd, tmp);
3113 }
3114
3115 /* subi */
3116 void
3117 OP_1 (SIM_DESC sd, SIM_CPU *cpu)
3118 {
3119 unsigned tmp;
3120 if (OP[1] == 0)
3121 OP[1] = 16;
3122
3123 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
3124 /* see ../common/sim-alu.h for a more extensive discussion on how to
3125 compute the carry/overflow bits. */
3126 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
3127 tmp = ((unsigned)(uint16_t) GPR (OP[0])
3128 + (unsigned)(uint16_t) ( - OP[1]));
3129 SET_PSW_C (tmp >= (1 << 16));
3130 SET_GPR (OP[0], tmp);
3131 trace_output_16 (sd, tmp);
3132 }
3133
3134 /* trap */
3135 void
3136 OP_5F00 (SIM_DESC sd, SIM_CPU *cpu)
3137 {
3138 host_callback *cb = STATE_CALLBACK (sd);
3139
3140 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
3141 trace_output_void (sd);
3142
3143 switch (OP[0])
3144 {
3145 default:
3146 #if (DEBUG & DEBUG_TRAP) == 0
3147 {
3148 uint16_t vec = OP[0] + TRAP_VECTOR_START;
3149 SET_BPC (PC + 1);
3150 SET_BPSW (PSW);
3151 SET_PSW (PSW & PSW_SM_BIT);
3152 JMP (vec);
3153 break;
3154 }
3155 #else /* if debugging use trap to print registers */
3156 {
3157 int i;
3158 static int first_time = 1;
3159
3160 if (first_time)
3161 {
3162 first_time = 0;
3163 sim_io_printf (sd, "Trap # PC ");
3164 for (i = 0; i < 16; i++)
3165 sim_io_printf (sd, " %sr%d", (i > 9) ? "" : " ", i);
3166 sim_io_printf (sd, " a0 a1 f0 f1 c\n");
3167 }
3168
3169 sim_io_printf (sd, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
3170
3171 for (i = 0; i < 16; i++)
3172 sim_io_printf (sd, " %.4x", (int) GPR (i));
3173
3174 for (i = 0; i < 2; i++)
3175 sim_io_printf (sd, " %.2x%.8lx",
3176 ((int)(ACC (i) >> 32) & 0xff),
3177 ((unsigned long) ACC (i)) & 0xffffffff);
3178
3179 sim_io_printf (sd, " %d %d %d\n",
3180 PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
3181 sim_io_flush_stdout (sd);
3182 break;
3183 }
3184 #endif
3185 case 15: /* new system call trap */
3186 /* Trap 15 is used for simulating low-level I/O */
3187 {
3188 uint32_t result = 0;
3189 errno = 0;
3190
3191 /* Registers passed to trap 0 */
3192
3193 #define FUNC GPR (4) /* function number */
3194 #define PARM1 GPR (0) /* optional parm 1 */
3195 #define PARM2 GPR (1) /* optional parm 2 */
3196 #define PARM3 GPR (2) /* optional parm 3 */
3197 #define PARM4 GPR (3) /* optional parm 3 */
3198
3199 /* Registers set by trap 0 */
3200
3201 #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
3202 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3203 #define RETERR(X) SET_GPR (4, (X)) /* return error code */
3204
3205 /* Turn a pointer in a register into a pointer into real memory. */
3206
3207 #define MEMPTR(x) ((char *)(dmem_addr (sd, cpu, x)))
3208
3209 switch (FUNC)
3210 {
3211 #if !defined(__GO32__) && !defined(_WIN32)
3212 case TARGET_NEWLIB_D10V_SYS_fork:
3213 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
3214 RETVAL (fork ());
3215 trace_output_16 (sd, result);
3216 break;
3217
3218 #define getpid() 47
3219 case TARGET_NEWLIB_D10V_SYS_getpid:
3220 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3221 RETVAL (getpid ());
3222 trace_output_16 (sd, result);
3223 break;
3224
3225 case TARGET_NEWLIB_D10V_SYS_kill:
3226 trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
3227 if (PARM1 == getpid ())
3228 {
3229 trace_output_void (sd);
3230 sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, PARM2);
3231 }
3232 else
3233 {
3234 int os_sig = -1;
3235 switch (PARM2)
3236 {
3237 #ifdef SIGHUP
3238 case 1: os_sig = SIGHUP; break;
3239 #endif
3240 #ifdef SIGINT
3241 case 2: os_sig = SIGINT; break;
3242 #endif
3243 #ifdef SIGQUIT
3244 case 3: os_sig = SIGQUIT; break;
3245 #endif
3246 #ifdef SIGILL
3247 case 4: os_sig = SIGILL; break;
3248 #endif
3249 #ifdef SIGTRAP
3250 case 5: os_sig = SIGTRAP; break;
3251 #endif
3252 #ifdef SIGABRT
3253 case 6: os_sig = SIGABRT; break;
3254 #elif defined(SIGIOT)
3255 case 6: os_sig = SIGIOT; break;
3256 #endif
3257 #ifdef SIGEMT
3258 case 7: os_sig = SIGEMT; break;
3259 #endif
3260 #ifdef SIGFPE
3261 case 8: os_sig = SIGFPE; break;
3262 #endif
3263 #ifdef SIGKILL
3264 case 9: os_sig = SIGKILL; break;
3265 #endif
3266 #ifdef SIGBUS
3267 case 10: os_sig = SIGBUS; break;
3268 #endif
3269 #ifdef SIGSEGV
3270 case 11: os_sig = SIGSEGV; break;
3271 #endif
3272 #ifdef SIGSYS
3273 case 12: os_sig = SIGSYS; break;
3274 #endif
3275 #ifdef SIGPIPE
3276 case 13: os_sig = SIGPIPE; break;
3277 #endif
3278 #ifdef SIGALRM
3279 case 14: os_sig = SIGALRM; break;
3280 #endif
3281 #ifdef SIGTERM
3282 case 15: os_sig = SIGTERM; break;
3283 #endif
3284 #ifdef SIGURG
3285 case 16: os_sig = SIGURG; break;
3286 #endif
3287 #ifdef SIGSTOP
3288 case 17: os_sig = SIGSTOP; break;
3289 #endif
3290 #ifdef SIGTSTP
3291 case 18: os_sig = SIGTSTP; break;
3292 #endif
3293 #ifdef SIGCONT
3294 case 19: os_sig = SIGCONT; break;
3295 #endif
3296 #ifdef SIGCHLD
3297 case 20: os_sig = SIGCHLD; break;
3298 #elif defined(SIGCLD)
3299 case 20: os_sig = SIGCLD; break;
3300 #endif
3301 #ifdef SIGTTIN
3302 case 21: os_sig = SIGTTIN; break;
3303 #endif
3304 #ifdef SIGTTOU
3305 case 22: os_sig = SIGTTOU; break;
3306 #endif
3307 #ifdef SIGIO
3308 case 23: os_sig = SIGIO; break;
3309 #elif defined (SIGPOLL)
3310 case 23: os_sig = SIGPOLL; break;
3311 #endif
3312 #ifdef SIGXCPU
3313 case 24: os_sig = SIGXCPU; break;
3314 #endif
3315 #ifdef SIGXFSZ
3316 case 25: os_sig = SIGXFSZ; break;
3317 #endif
3318 #ifdef SIGVTALRM
3319 case 26: os_sig = SIGVTALRM; break;
3320 #endif
3321 #ifdef SIGPROF
3322 case 27: os_sig = SIGPROF; break;
3323 #endif
3324 #ifdef SIGWINCH
3325 case 28: os_sig = SIGWINCH; break;
3326 #endif
3327 #ifdef SIGLOST
3328 case 29: os_sig = SIGLOST; break;
3329 #endif
3330 #ifdef SIGUSR1
3331 case 30: os_sig = SIGUSR1; break;
3332 #endif
3333 #ifdef SIGUSR2
3334 case 31: os_sig = SIGUSR2; break;
3335 #endif
3336 }
3337
3338 if (os_sig == -1)
3339 {
3340 trace_output_void (sd);
3341 sim_io_printf (sd, "Unknown signal %d\n", PARM2);
3342 sim_io_flush_stdout (sd);
3343 EXCEPTION (SIM_SIGILL);
3344 }
3345 else
3346 {
3347 RETVAL (kill (PARM1, PARM2));
3348 trace_output_16 (sd, result);
3349 }
3350 }
3351 break;
3352
3353 case TARGET_NEWLIB_D10V_SYS_execve:
3354 trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
3355 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
3356 (char **)MEMPTR (PARM3)));
3357 trace_output_16 (sd, result);
3358 break;
3359
3360 case TARGET_NEWLIB_D10V_SYS_execv:
3361 trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
3362 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
3363 trace_output_16 (sd, result);
3364 break;
3365
3366 case TARGET_NEWLIB_D10V_SYS_pipe:
3367 {
3368 reg_t buf;
3369 int host_fd[2];
3370
3371 trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
3372 buf = PARM1;
3373 RETVAL (pipe (host_fd));
3374 SW (buf, host_fd[0]);
3375 buf += sizeof(uint16_t);
3376 SW (buf, host_fd[1]);
3377 trace_output_16 (sd, result);
3378 }
3379 break;
3380
3381 #if 0
3382 case TARGET_NEWLIB_D10V_SYS_wait:
3383 {
3384 int status;
3385 trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
3386 RETVAL (wait (&status));
3387 if (PARM1)
3388 SW (PARM1, status);
3389 trace_output_16 (sd, result);
3390 }
3391 break;
3392 #endif
3393 #else
3394 case TARGET_NEWLIB_D10V_SYS_getpid:
3395 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3396 RETVAL (1);
3397 trace_output_16 (sd, result);
3398 break;
3399
3400 case TARGET_NEWLIB_D10V_SYS_kill:
3401 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
3402 trace_output_void (sd);
3403 sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, PARM2);
3404 break;
3405 #endif
3406
3407 case TARGET_NEWLIB_D10V_SYS_read:
3408 trace_input ("<read>", OP_R0, OP_R1, OP_R2);
3409 RETVAL (cb->read (cb, PARM1, MEMPTR (PARM2), PARM3));
3410 trace_output_16 (sd, result);
3411 break;
3412
3413 case TARGET_NEWLIB_D10V_SYS_write:
3414 trace_input ("<write>", OP_R0, OP_R1, OP_R2);
3415 if (PARM1 == 1)
3416 RETVAL ((int)cb->write_stdout (cb, MEMPTR (PARM2), PARM3));
3417 else
3418 RETVAL ((int)cb->write (cb, PARM1, MEMPTR (PARM2), PARM3));
3419 trace_output_16 (sd, result);
3420 break;
3421
3422 case TARGET_NEWLIB_D10V_SYS_lseek:
3423 trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
3424 RETVAL32 (cb->lseek (cb, PARM1,
3425 ((((unsigned long) PARM2) << 16)
3426 || (unsigned long) PARM3),
3427 PARM4));
3428 trace_output_32 (sd, result);
3429 break;
3430
3431 case TARGET_NEWLIB_D10V_SYS_close:
3432 trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
3433 RETVAL (cb->close (cb, PARM1));
3434 trace_output_16 (sd, result);
3435 break;
3436
3437 case TARGET_NEWLIB_D10V_SYS_open:
3438 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
3439 RETVAL (cb->open (cb, MEMPTR (PARM1), PARM2));
3440 trace_output_16 (sd, result);
3441 break;
3442
3443 case TARGET_NEWLIB_D10V_SYS_exit:
3444 trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
3445 trace_output_void (sd);
3446 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (0));
3447 break;
3448
3449 case TARGET_NEWLIB_D10V_SYS_stat:
3450 trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
3451 /* stat system call */
3452 {
3453 struct stat host_stat;
3454 reg_t buf;
3455
3456 RETVAL (stat (MEMPTR (PARM1), &host_stat));
3457
3458 buf = PARM2;
3459
3460 /* The hard-coded offsets and sizes were determined by using
3461 * the D10V compiler on a test program that used struct stat.
3462 */
3463 SW (buf, host_stat.st_dev);
3464 SW (buf+2, host_stat.st_ino);
3465 SW (buf+4, host_stat.st_mode);
3466 SW (buf+6, host_stat.st_nlink);
3467 SW (buf+8, host_stat.st_uid);
3468 SW (buf+10, host_stat.st_gid);
3469 SW (buf+12, host_stat.st_rdev);
3470 SLW (buf+16, host_stat.st_size);
3471 SLW (buf+20, host_stat.st_atime);
3472 SLW (buf+28, host_stat.st_mtime);
3473 SLW (buf+36, host_stat.st_ctime);
3474 }
3475 trace_output_16 (sd, result);
3476 break;
3477
3478 case TARGET_NEWLIB_D10V_SYS_chown:
3479 trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3480 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
3481 trace_output_16 (sd, result);
3482 break;
3483
3484 case TARGET_NEWLIB_D10V_SYS_chmod:
3485 trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3486 RETVAL (chmod (MEMPTR (PARM1), PARM2));
3487 trace_output_16 (sd, result);
3488 break;
3489
3490 #if 0
3491 case TARGET_NEWLIB_D10V_SYS_utime:
3492 trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3493 /* Cast the second argument to void *, to avoid type mismatch
3494 if a prototype is present. */
3495 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
3496 trace_output_16 (sd, result);
3497 break;
3498 #endif
3499
3500 #if 0
3501 case TARGET_NEWLIB_D10V_SYS_time:
3502 trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3503 RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
3504 trace_output_32 (sd, result);
3505 break;
3506 #endif
3507
3508 default:
3509 cb->error (cb, "Unknown syscall %d", FUNC);
3510 }
3511 if ((uint16_t) result == (uint16_t) -1)
3512 RETERR (cb->get_errno (cb));
3513 else
3514 RETERR (0);
3515 break;
3516 }
3517 }
3518 }
3519
3520 /* tst0i */
3521 void
3522 OP_7000000 (SIM_DESC sd, SIM_CPU *cpu)
3523 {
3524 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3525 SET_PSW_F1 (PSW_F0);;
3526 SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
3527 trace_output_flag (sd);
3528 }
3529
3530 /* tst1i */
3531 void
3532 OP_F000000 (SIM_DESC sd, SIM_CPU *cpu)
3533 {
3534 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3535 SET_PSW_F1 (PSW_F0);
3536 SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
3537 trace_output_flag (sd);
3538 }
3539
3540 /* wait */
3541 void
3542 OP_5F80 (SIM_DESC sd, SIM_CPU *cpu)
3543 {
3544 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3545 SET_PSW_IE (1);
3546 trace_output_void (sd);
3547 }
3548
3549 /* xor */
3550 void
3551 OP_A00 (SIM_DESC sd, SIM_CPU *cpu)
3552 {
3553 int16_t tmp;
3554 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3555 tmp = (GPR (OP[0]) ^ GPR (OP[1]));
3556 SET_GPR (OP[0], tmp);
3557 trace_output_16 (sd, tmp);
3558 }
3559
3560 /* xor3 */
3561 void
3562 OP_5000000 (SIM_DESC sd, SIM_CPU *cpu)
3563 {
3564 int16_t tmp;
3565 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3566 tmp = (GPR (OP[1]) ^ OP[2]);
3567 SET_GPR (OP[0], tmp);
3568 trace_output_16 (sd, tmp);
3569 }
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