]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/d10v/simops.c
ed3e570762eacdfde86cc038f93eee7c43d22bed
16 #include "targ-vals.h"
18 extern char * strrchr ();
51 PSW_MASK
= ( PSW_SM_BIT
62 /* The following bits in the PSW _can't_ be set by instructions such
64 PSW_HW_MASK
= ( PSW_MASK
| PSW_DM_BIT
)
68 move_to_cr ( int cr
, reg_t mask
, reg_t val
, int psw_hw_p
)
70 /* A MASK bit is set when the corresponding bit in the CR should
72 /* This assumes that (VAL & MASK) == 0 */
80 if (( mask
& PSW_SM_BIT
) == 0 )
82 int new_psw_sm
= ( val
& PSW_SM_BIT
) != 0 ;
84 SET_HELD_SP ( PSW_SM
, GPR ( SP_IDX
));
85 if ( PSW_SM
!= new_psw_sm
)
87 SET_GPR ( SP_IDX
, HELD_SP ( new_psw_sm
));
89 if (( mask
& ( PSW_ST_BIT
| PSW_FX_BIT
)) == 0 )
91 if ( val
& PSW_ST_BIT
&& !( val
& PSW_FX_BIT
))
93 (* d10v_callback
-> printf_filtered
)
95 "ERROR at PC 0x%x: ST can only be set when FX is set. \n " ,
97 State
. exception
= SIGILL
;
100 /* keep an up-to-date psw around for tracing */
101 State
. trace
. psw
= ( State
. trace
. psw
& mask
) | val
;
105 /* Just like PSW, mask things like DM out. */
118 /* only issue an update if the register is being changed */
119 if (( State
. cregs
[ cr
] & ~ mask
) != val
)
120 SLOT_PEND_MASK ( State
. cregs
[ cr
], mask
, val
);
125 static void trace_input_func ( char * name
,
130 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
132 #ifndef SIZE_INSTRUCTION
133 #define SIZE_INSTRUCTION 8
136 #ifndef SIZE_OPERANDS
137 #define SIZE_OPERANDS 18
141 #define SIZE_VALUES 13
144 #ifndef SIZE_LOCATION
145 #define SIZE_LOCATION 20
152 #ifndef SIZE_LINE_NUMBER
153 #define SIZE_LINE_NUMBER 4
157 trace_input_func ( name
, in1
, in2
, in3
)
170 const char * filename
;
171 const char * functionname
;
172 unsigned int linenumber
;
175 if (( d10v_debug
& DEBUG_TRACE
) == 0 )
178 switch ( State
. ins_type
)
181 case INS_UNKNOWN
: type
= " ?" ; break ;
182 case INS_LEFT
: type
= " L" ; break ;
183 case INS_RIGHT
: type
= " R" ; break ;
184 case INS_LEFT_PARALLEL
: type
= "*L" ; break ;
185 case INS_RIGHT_PARALLEL
: type
= "*R" ; break ;
186 case INS_LEFT_COND_TEST
: type
= "?L" ; break ;
187 case INS_RIGHT_COND_TEST
: type
= "?R" ; break ;
188 case INS_LEFT_COND_EXE
: type
= "&L" ; break ;
189 case INS_RIGHT_COND_EXE
: type
= "&R" ; break ;
190 case INS_LONG
: type
= " B" ; break ;
193 if (( d10v_debug
& DEBUG_LINE_NUMBER
) == 0 )
194 (* d10v_callback
-> printf_filtered
) ( d10v_callback
,
196 SIZE_PC
, ( unsigned ) PC
,
198 SIZE_INSTRUCTION
, name
);
203 byte_pc
= decode_pc ();
204 if ( text
&& byte_pc
>= text_start
&& byte_pc
< text_end
)
206 filename
= ( const char *) 0 ;
207 functionname
= ( const char *) 0 ;
209 if ( bfd_find_nearest_line ( prog_bfd
, text
, ( struct bfd_symbol
**) 0 , byte_pc
- text_start
,
210 & filename
, & functionname
, & linenumber
))
215 sprintf ( p
, "#%-*d " , SIZE_LINE_NUMBER
, linenumber
);
220 sprintf ( p
, "%-*s " , SIZE_LINE_NUMBER
+ 1 , "---" );
221 p
+= SIZE_LINE_NUMBER
+ 2 ;
226 sprintf ( p
, "%s " , functionname
);
231 char * q
= strrchr ( filename
, '/' );
232 sprintf ( p
, "%s " , ( q
) ? q
+ 1 : filename
);
241 (* d10v_callback
-> printf_filtered
) ( d10v_callback
,
242 "0x%.*x %s: %-*.*s %-*s " ,
243 SIZE_PC
, ( unsigned ) PC
,
245 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
246 SIZE_INSTRUCTION
, name
);
254 for ( i
= 0 ; i
< 3 ; i
++)
268 sprintf ( p
, "%sr%d" , comma
, OP
[ i
]);
276 sprintf ( p
, "%scr%d" , comma
, OP
[ i
]);
282 case OP_ACCUM_OUTPUT
:
283 case OP_ACCUM_REVERSE
:
284 sprintf ( p
, "%sa%d" , comma
, OP
[ i
]);
290 sprintf ( p
, "%s%d" , comma
, OP
[ i
]);
296 sprintf ( p
, "%s%d" , comma
, SEXT8 ( OP
[ i
]));
302 sprintf ( p
, "%s%d" , comma
, SEXT4 ( OP
[ i
]));
308 sprintf ( p
, "%s%d" , comma
, SEXT3 ( OP
[ i
]));
314 sprintf ( p
, "%s@r%d" , comma
, OP
[ i
]);
320 sprintf ( p
, "%s@(%d,r%d)" , comma
, ( int16
) OP
[ i
], OP
[ i
+ 1 ]);
326 sprintf ( p
, "%s@%d" , comma
, OP
[ i
]);
332 sprintf ( p
, "%s@r%d+" , comma
, OP
[ i
]);
338 sprintf ( p
, "%s@r%d-" , comma
, OP
[ i
]);
344 sprintf ( p
, "%s@-r%d" , comma
, OP
[ i
]);
352 sprintf ( p
, "%sf0" , comma
);
355 sprintf ( p
, "%sf1" , comma
);
358 sprintf ( p
, "%sc" , comma
);
366 if (( d10v_debug
& DEBUG_VALUES
) == 0 )
370 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%s" , buf
);
375 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%-*s" , SIZE_OPERANDS
, buf
);
378 for ( i
= 0 ; i
< 3 ; i
++)
384 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*s" , SIZE_VALUES
, "" );
390 case OP_ACCUM_OUTPUT
:
392 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*s" , SIZE_VALUES
, "---" );
400 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*s0x%.4x" , SIZE_VALUES
- 6 , "" ,
401 ( uint16
) GPR ( OP
[ i
]));
405 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*s0x%.4x" , SIZE_VALUES
- 6 , "" , ( uint16
) OP
[ i
]);
409 tmp
= ( long )(((( uint32
) GPR ( OP
[ i
])) << 16 ) | (( uint32
) GPR ( OP
[ i
] + 1 )));
410 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*s0x%.8lx" , SIZE_VALUES
- 10 , "" , tmp
);
415 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*s0x%.4x" , SIZE_VALUES
- 6 , "" ,
416 ( uint16
) CREG ( OP
[ i
]));
420 case OP_ACCUM_REVERSE
:
421 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*s0x%.2x%.8lx" , SIZE_VALUES
- 12 , "" ,
422 (( int )( ACC ( OP
[ i
]) >> 32 ) & 0xff ),
423 (( unsigned long ) ACC ( OP
[ i
])) & 0xffffffff );
427 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*s0x%.4x" , SIZE_VALUES
- 6 , "" ,
432 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*s0x%.4x" , SIZE_VALUES
- 6 , "" ,
433 ( uint16
) SEXT4 ( OP
[ i
]));
437 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*s0x%.4x" , SIZE_VALUES
- 6 , "" ,
438 ( uint16
) SEXT8 ( OP
[ i
]));
442 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*s0x%.4x" , SIZE_VALUES
- 6 , "" ,
443 ( uint16
) SEXT3 ( OP
[ i
]));
448 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*sF0 = %d" , SIZE_VALUES
- 6 , "" ,
452 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*sF1 = %d" , SIZE_VALUES
- 6 , "" ,
456 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*sC = %d" , SIZE_VALUES
- 5 , "" ,
462 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*s0x%.4x" , SIZE_VALUES
- 6 , "" ,
464 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*s0x%.4x" , SIZE_VALUES
- 6 , "" ,
465 ( uint16
) GPR ( OP
[ i
+ 1 ]));
470 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*s0x%.4x" , SIZE_VALUES
- 6 , "" ,
475 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*s0x%.4x" , SIZE_VALUES
- 6 , "" ,
480 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "%*s0x%.4x" , SIZE_VALUES
- 6 , "" ,
488 (* d10v_callback
-> flush_stdout
) ( d10v_callback
);
492 do_trace_output_flush ( void )
494 (* d10v_callback
-> flush_stdout
) ( d10v_callback
);
498 do_trace_output_finish ( void )
500 (* d10v_callback
-> printf_filtered
) ( d10v_callback
,
501 " F0=%d F1=%d C=%d \n " ,
502 ( State
. trace
. psw
& PSW_F0_BIT
) != 0 ,
503 ( State
. trace
. psw
& PSW_F1_BIT
) != 0 ,
504 ( State
. trace
. psw
& PSW_C_BIT
) != 0 );
505 (* d10v_callback
-> flush_stdout
) ( d10v_callback
);
509 trace_output_40 ( uint64 val
)
511 if (( d10v_debug
& ( DEBUG_TRACE
| DEBUG_VALUES
)) == ( DEBUG_TRACE
| DEBUG_VALUES
))
513 (* d10v_callback
-> printf_filtered
) ( d10v_callback
,
514 " :: %*s0x%.2x%.8lx" ,
517 (( int )( val
>> 32 ) & 0xff ),
518 (( unsigned long ) val
) & 0xffffffff );
519 do_trace_output_finish ();
524 trace_output_32 ( uint32 val
)
526 if (( d10v_debug
& ( DEBUG_TRACE
| DEBUG_VALUES
)) == ( DEBUG_TRACE
| DEBUG_VALUES
))
528 (* d10v_callback
-> printf_filtered
) ( d10v_callback
,
533 do_trace_output_finish ();
538 trace_output_16 ( uint16 val
)
540 if (( d10v_debug
& ( DEBUG_TRACE
| DEBUG_VALUES
)) == ( DEBUG_TRACE
| DEBUG_VALUES
))
542 (* d10v_callback
-> printf_filtered
) ( d10v_callback
,
547 do_trace_output_finish ();
554 if (( d10v_debug
& ( DEBUG_TRACE
| DEBUG_VALUES
)) == ( DEBUG_TRACE
| DEBUG_VALUES
))
556 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, " \n " );
557 do_trace_output_flush ();
564 if (( d10v_debug
& ( DEBUG_TRACE
| DEBUG_VALUES
)) == ( DEBUG_TRACE
| DEBUG_VALUES
))
566 (* d10v_callback
-> printf_filtered
) ( d10v_callback
,
570 do_trace_output_finish ();
578 #define trace_input(NAME, IN1, IN2, IN3)
579 #define trace_output(RESULT)
587 trace_input ( "abs" , OP_REG
, OP_VOID
, OP_VOID
);
597 SET_GPR ( OP
[ 0 ], tmp
);
598 trace_output_16 ( tmp
);
606 trace_input ( "abs" , OP_ACCUM
, OP_VOID
, OP_VOID
);
609 tmp
= SEXT40 ( ACC ( OP
[ 0 ]));
615 if ( tmp
> SEXT40 ( MAX32
))
617 else if ( tmp
< SEXT40 ( MIN32
))
620 tmp
= ( tmp
& MASK40
);
623 tmp
= ( tmp
& MASK40
);
628 tmp
= ( tmp
& MASK40
);
631 SET_ACC ( OP
[ 0 ], tmp
);
632 trace_output_40 ( tmp
);
639 uint16 a
= GPR ( OP
[ 0 ]);
640 uint16 b
= GPR ( OP
[ 1 ]);
641 uint16 tmp
= ( a
+ b
);
642 trace_input ( "add" , OP_REG
, OP_REG
, OP_VOID
);
644 SET_GPR ( OP
[ 0 ], tmp
);
645 trace_output_16 ( tmp
);
653 tmp
= SEXT40 ( ACC ( OP
[ 0 ])) + ( SEXT16 ( GPR ( OP
[ 1 ])) << 16 | GPR ( OP
[ 1 ] + 1 ));
655 trace_input ( "add" , OP_ACCUM
, OP_REG
, OP_VOID
);
658 if ( tmp
> SEXT40 ( MAX32
))
660 else if ( tmp
< SEXT40 ( MIN32
))
663 tmp
= ( tmp
& MASK40
);
666 tmp
= ( tmp
& MASK40
);
667 SET_ACC ( OP
[ 0 ], tmp
);
668 trace_output_40 ( tmp
);
676 tmp
= SEXT40 ( ACC ( OP
[ 0 ])) + SEXT40 ( ACC ( OP
[ 1 ]));
678 trace_input ( "add" , OP_ACCUM
, OP_ACCUM
, OP_VOID
);
681 if ( tmp
> SEXT40 ( MAX32
))
683 else if ( tmp
< SEXT40 ( MIN32
))
686 tmp
= ( tmp
& MASK40
);
689 tmp
= ( tmp
& MASK40
);
690 SET_ACC ( OP
[ 0 ], tmp
);
691 trace_output_40 ( tmp
);
699 uint32 a
= ( GPR ( OP
[ 0 ])) << 16 | GPR ( OP
[ 0 ] + 1 );
700 uint32 b
= ( GPR ( OP
[ 1 ])) << 16 | GPR ( OP
[ 1 ] + 1 );
701 trace_input ( "add2w" , OP_DREG
, OP_DREG
, OP_VOID
);
704 SET_GPR ( OP
[ 0 ] + 0 , ( tmp
>> 16 ));
705 SET_GPR ( OP
[ 0 ] + 1 , ( tmp
& 0xFFFF ));
706 trace_output_32 ( tmp
);
713 uint16 a
= GPR ( OP
[ 1 ]);
715 uint16 tmp
= ( a
+ b
);
716 trace_input ( "add3" , OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
718 SET_GPR ( OP
[ 0 ], tmp
);
719 trace_output_16 ( tmp
);
727 tmp
= SEXT40 ( ACC ( OP
[ 2 ])) + SEXT40 (( GPR ( OP
[ 1 ]) << 16 ) | GPR ( OP
[ 1 ] + 1 ));
729 trace_input ( "addac3" , OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
730 SET_GPR ( OP
[ 0 ] + 0 , (( tmp
>> 16 ) & 0xffff ));
731 SET_GPR ( OP
[ 0 ] + 1 , ( tmp
& 0xffff ));
732 trace_output_32 ( tmp
);
740 tmp
= SEXT40 ( ACC ( OP
[ 1 ])) + SEXT40 ( ACC ( OP
[ 2 ]));
742 trace_input ( "addac3" , OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
743 SET_GPR ( OP
[ 0 ] + 0 , ( tmp
>> 16 ) & 0xffff );
744 SET_GPR ( OP
[ 0 ] + 1 , tmp
& 0xffff );
745 trace_output_32 ( tmp
);
755 trace_input ( "addac3s" , OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
756 tmp
= SEXT40 ( ACC ( OP
[ 2 ])) + SEXT40 (( GPR ( OP
[ 1 ]) << 16 ) | GPR ( OP
[ 1 ] + 1 ));
757 if ( tmp
> SEXT40 ( MAX32
))
762 else if ( tmp
< SEXT40 ( MIN32
))
771 SET_GPR ( OP
[ 0 ] + 0 , ( tmp
>> 16 ) & 0xffff );
772 SET_GPR ( OP
[ 0 ] + 1 , ( tmp
& 0xffff ));
773 trace_output_32 ( tmp
);
783 trace_input ( "addac3s" , OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
784 tmp
= SEXT40 ( ACC ( OP
[ 1 ])) + SEXT40 ( ACC ( OP
[ 2 ]));
785 if ( tmp
> SEXT40 ( MAX32
))
790 else if ( tmp
< SEXT40 ( MIN32
))
799 SET_GPR ( OP
[ 0 ] + 0 , ( tmp
>> 16 ) & 0xffff );
800 SET_GPR ( OP
[ 0 ] + 1 , ( tmp
& 0xffff ));
801 trace_output_32 ( tmp
);
808 uint16 a
= GPR ( OP
[ 0 ]);
815 trace_input ( "addi" , OP_REG
, OP_CONSTANT16
, OP_VOID
);
817 SET_GPR ( OP
[ 0 ], tmp
);
818 trace_output_16 ( tmp
);
825 uint16 tmp
= GPR ( OP
[ 0 ]) & GPR ( OP
[ 1 ]);
826 trace_input ( "and" , OP_REG
, OP_REG
, OP_VOID
);
827 SET_GPR ( OP
[ 0 ], tmp
);
828 trace_output_16 ( tmp
);
835 uint16 tmp
= GPR ( OP
[ 1 ]) & OP
[ 2 ];
836 trace_input ( "and3" , OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
837 SET_GPR ( OP
[ 0 ], tmp
);
838 trace_output_16 ( tmp
);
846 trace_input ( "bclri" , OP_REG
, OP_CONSTANT16
, OP_VOID
);
847 tmp
= ( GPR ( OP
[ 0 ]) &~( 0x8000 >> OP
[ 1 ]));
848 SET_GPR ( OP
[ 0 ], tmp
);
849 trace_output_16 ( tmp
);
856 trace_input ( "bl.s" , OP_CONSTANT8
, OP_R0
, OP_R1
);
857 SET_GPR ( 13 , PC
+ 1 );
858 JMP ( PC
+ SEXT8 ( OP
[ 0 ]));
859 trace_output_void ();
866 trace_input ( "bl.l" , OP_CONSTANT16
, OP_R0
, OP_R1
);
867 SET_GPR ( 13 , ( PC
+ 1 ));
869 trace_output_void ();
877 trace_input ( "bnoti" , OP_REG
, OP_CONSTANT16
, OP_VOID
);
878 tmp
= ( GPR ( OP
[ 0 ]) ^ ( 0x8000 >> OP
[ 1 ]));
879 SET_GPR ( OP
[ 0 ], tmp
);
880 trace_output_16 ( tmp
);
887 trace_input ( "bra.s" , OP_CONSTANT8
, OP_VOID
, OP_VOID
);
888 JMP ( PC
+ SEXT8 ( OP
[ 0 ]));
889 trace_output_void ();
896 trace_input ( "bra.l" , OP_CONSTANT16
, OP_VOID
, OP_VOID
);
898 trace_output_void ();
905 trace_input ( "brf0f.s" , OP_CONSTANT8
, OP_VOID
, OP_VOID
);
907 JMP ( PC
+ SEXT8 ( OP
[ 0 ]));
908 trace_output_flag ();
915 trace_input ( "brf0f.l" , OP_CONSTANT16
, OP_VOID
, OP_VOID
);
918 trace_output_flag ();
925 trace_input ( "brf0t.s" , OP_CONSTANT8
, OP_VOID
, OP_VOID
);
927 JMP ( PC
+ SEXT8 ( OP
[ 0 ]));
928 trace_output_flag ();
935 trace_input ( "brf0t.l" , OP_CONSTANT16
, OP_VOID
, OP_VOID
);
938 trace_output_flag ();
946 trace_input ( "bseti" , OP_REG
, OP_CONSTANT16
, OP_VOID
);
947 tmp
= ( GPR ( OP
[ 0 ]) | ( 0x8000 >> OP
[ 1 ]));
948 SET_GPR ( OP
[ 0 ], tmp
);
949 trace_output_16 ( tmp
);
956 trace_input ( "btsti" , OP_REG
, OP_CONSTANT16
, OP_VOID
);
958 SET_PSW_F0 (( GPR ( OP
[ 0 ]) & ( 0x8000 >> OP
[ 1 ])) ? 1 : 0 );
959 trace_output_flag ();
966 trace_input ( "clrac" , OP_ACCUM_OUTPUT
, OP_VOID
, OP_VOID
);
975 trace_input ( "cmp" , OP_REG
, OP_REG
, OP_VOID
);
977 SET_PSW_F0 ((( int16
)( GPR ( OP
[ 0 ])) < ( int16
)( GPR ( OP
[ 1 ]))) ? 1 : 0 );
978 trace_output_flag ();
985 trace_input ( "cmp" , OP_ACCUM
, OP_ACCUM
, OP_VOID
);
987 SET_PSW_F0 (( SEXT40 ( ACC ( OP
[ 0 ])) < SEXT40 ( ACC ( OP
[ 1 ]))) ? 1 : 0 );
988 trace_output_flag ();
995 trace_input ( "cmpeq" , OP_REG
, OP_REG
, OP_VOID
);
997 SET_PSW_F0 (( GPR ( OP
[ 0 ]) == GPR ( OP
[ 1 ])) ? 1 : 0 );
998 trace_output_flag ();
1005 trace_input ( "cmpeq" , OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1006 SET_PSW_F1 ( PSW_F0
);
1007 SET_PSW_F0 ((( ACC ( OP
[ 0 ]) & MASK40
) == ( ACC ( OP
[ 1 ]) & MASK40
)) ? 1 : 0 );
1008 trace_output_flag ();
1015 trace_input ( "cmpeqi.s" , OP_REG
, OP_CONSTANT4
, OP_VOID
);
1016 SET_PSW_F1 ( PSW_F0
);
1017 SET_PSW_F0 (( GPR ( OP
[ 0 ]) == ( reg_t
) SEXT4 ( OP
[ 1 ])) ? 1 : 0 );
1018 trace_output_flag ();
1025 trace_input ( "cmpeqi.l" , OP_REG
, OP_CONSTANT16
, OP_VOID
);
1026 SET_PSW_F1 ( PSW_F0
);
1027 SET_PSW_F0 (( GPR ( OP
[ 0 ]) == ( reg_t
) OP
[ 1 ]) ? 1 : 0 );
1028 trace_output_flag ();
1035 trace_input ( "cmpi.s" , OP_REG
, OP_CONSTANT4
, OP_VOID
);
1036 SET_PSW_F1 ( PSW_F0
);
1037 SET_PSW_F0 ((( int16
)( GPR ( OP
[ 0 ])) < ( int16
) SEXT4 ( OP
[ 1 ])) ? 1 : 0 );
1038 trace_output_flag ();
1045 trace_input ( "cmpi.l" , OP_REG
, OP_CONSTANT16
, OP_VOID
);
1046 SET_PSW_F1 ( PSW_F0
);
1047 SET_PSW_F0 ((( int16
)( GPR ( OP
[ 0 ])) < ( int16
)( OP
[ 1 ])) ? 1 : 0 );
1048 trace_output_flag ();
1055 trace_input ( "cmpu" , OP_REG
, OP_REG
, OP_VOID
);
1056 SET_PSW_F1 ( PSW_F0
);
1057 SET_PSW_F0 (( GPR ( OP
[ 0 ]) < GPR ( OP
[ 1 ])) ? 1 : 0 );
1058 trace_output_flag ();
1065 trace_input ( "cmpui" , OP_REG
, OP_CONSTANT16
, OP_VOID
);
1066 SET_PSW_F1 ( PSW_F0
);
1067 SET_PSW_F0 (( GPR ( OP
[ 0 ]) < ( reg_t
) OP
[ 1 ]) ? 1 : 0 );
1068 trace_output_flag ();
1077 trace_input ( "cpfg" , OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
1081 else if ( OP
[ 1 ] == 1 )
1090 trace_output_flag ();
1099 trace_input ( "cpfg" , OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
1103 else if ( OP
[ 1 ] == 1 )
1112 trace_output_flag ();
1119 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1121 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1122 The conditional below is for either of the instruction pairs
1123 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1124 where the dbt instruction should be interpreted.
1126 The module `sim-break' provides a more effective mechanism for
1127 detecting GDB planted breakpoints. The code below may,
1128 eventually, be changed to use that mechanism. */
1130 if ( State
. ins_type
== INS_LEFT
1131 || State
. ins_type
== INS_RIGHT
)
1133 trace_input ( "dbt" , OP_VOID
, OP_VOID
, OP_VOID
);
1136 SET_HW_PSW ( PSW_DM_BIT
| ( PSW
& ( PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
1137 JMP ( DBT_VECTOR_START
);
1138 trace_output_void ();
1142 State
. exception
= SIGTRAP
;
1150 uint16 foo
, tmp
, tmpf
;
1154 trace_input ( "divs" , OP_DREG
, OP_REG
, OP_VOID
);
1155 foo
= ( GPR ( OP
[ 0 ]) << 1 ) | ( GPR ( OP
[ 0 ] + 1 ) >> 15 );
1156 tmp
= ( int16
) foo
- ( int16
)( GPR ( OP
[ 1 ]));
1157 tmpf
= ( foo
>= GPR ( OP
[ 1 ])) ? 1 : 0 ;
1158 hi
= (( tmpf
== 1 ) ? tmp
: foo
);
1159 lo
= (( GPR ( OP
[ 0 ] + 1 ) << 1 ) | tmpf
);
1160 SET_GPR ( OP
[ 0 ] + 0 , hi
);
1161 SET_GPR ( OP
[ 0 ] + 1 , lo
);
1162 trace_output_32 ((( uint32
) hi
<< 16 ) | lo
);
1169 trace_input ( "exef0f" , OP_VOID
, OP_VOID
, OP_VOID
);
1170 State
. exe
= ( PSW_F0
== 0 );
1171 trace_output_flag ();
1178 trace_input ( "exef0t" , OP_VOID
, OP_VOID
, OP_VOID
);
1179 State
. exe
= ( PSW_F0
!= 0 );
1180 trace_output_flag ();
1187 trace_input ( "exef1f" , OP_VOID
, OP_VOID
, OP_VOID
);
1188 State
. exe
= ( PSW_F1
== 0 );
1189 trace_output_flag ();
1196 trace_input ( "exef1t" , OP_VOID
, OP_VOID
, OP_VOID
);
1197 State
. exe
= ( PSW_F1
!= 0 );
1198 trace_output_flag ();
1205 trace_input ( "exefaf" , OP_VOID
, OP_VOID
, OP_VOID
);
1206 State
. exe
= ( PSW_F0
== 0 ) & ( PSW_F1
== 0 );
1207 trace_output_flag ();
1214 trace_input ( "exefat" , OP_VOID
, OP_VOID
, OP_VOID
);
1215 State
. exe
= ( PSW_F0
== 0 ) & ( PSW_F1
!= 0 );
1216 trace_output_flag ();
1223 trace_input ( "exetaf" , OP_VOID
, OP_VOID
, OP_VOID
);
1224 State
. exe
= ( PSW_F0
!= 0 ) & ( PSW_F1
== 0 );
1225 trace_output_flag ();
1232 trace_input ( "exetat" , OP_VOID
, OP_VOID
, OP_VOID
);
1233 State
. exe
= ( PSW_F0
!= 0 ) & ( PSW_F1
!= 0 );
1234 trace_output_flag ();
1244 trace_input ( "exp" , OP_REG_OUTPUT
, OP_DREG
, OP_VOID
);
1245 if ((( int16
) GPR ( OP
[ 1 ])) >= 0 )
1246 tmp
= ( GPR ( OP
[ 1 ]) << 16 ) | GPR ( OP
[ 1 ] + 1 );
1248 tmp
= ~(( GPR ( OP
[ 1 ]) << 16 ) | GPR ( OP
[ 1 ] + 1 ));
1255 SET_GPR ( OP
[ 0 ], ( i
- 1 ));
1256 trace_output_16 ( i
- 1 );
1261 SET_GPR ( OP
[ 0 ], 16 );
1262 trace_output_16 ( 16 );
1272 trace_input ( "exp" , OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1273 tmp
= SEXT40 ( ACC ( OP
[ 1 ]));
1275 tmp
= ~ tmp
& MASK40
;
1277 foo
= 0x4000000000 LL
;
1282 SET_GPR ( OP
[ 0 ], i
- 9 );
1283 trace_output_16 ( i
- 9 );
1288 SET_GPR ( OP
[ 0 ], 16 );
1289 trace_output_16 ( 16 );
1296 trace_input ( "jl" , OP_REG
, OP_R0
, OP_R1
);
1297 SET_GPR ( 13 , PC
+ 1 );
1299 trace_output_void ();
1306 trace_input ( "jmp" , OP_REG
,
1307 ( OP
[ 0 ] == 13 ) ? OP_R0
: OP_VOID
,
1308 ( OP
[ 0 ] == 13 ) ? OP_R1
: OP_VOID
);
1311 trace_output_void ();
1319 uint16 addr
= OP
[ 1 ] + GPR ( OP
[ 2 ]);
1320 trace_input ( "ld" , OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1323 State
. exception
= SIG_D10V_BUS
;
1324 State
. pc_changed
= 1 ; /* Don't increment the PC. */
1325 trace_output_void ();
1329 SET_GPR ( OP
[ 0 ], tmp
);
1330 trace_output_16 ( tmp
);
1338 uint16 addr
= GPR ( OP
[ 1 ]);
1339 trace_input ( "ld" , OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1342 State
. exception
= SIG_D10V_BUS
;
1343 State
. pc_changed
= 1 ; /* Don't increment the PC. */
1344 trace_output_void ();
1348 SET_GPR ( OP
[ 0 ], tmp
);
1350 INC_ADDR ( OP
[ 1 ], - 2 );
1351 trace_output_16 ( tmp
);
1359 uint16 addr
= GPR ( OP
[ 1 ]);
1360 trace_input ( "ld" , OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1363 State
. exception
= SIG_D10V_BUS
;
1364 State
. pc_changed
= 1 ; /* Don't increment the PC. */
1365 trace_output_void ();
1369 SET_GPR ( OP
[ 0 ], tmp
);
1371 INC_ADDR ( OP
[ 1 ], 2 );
1372 trace_output_16 ( tmp
);
1380 uint16 addr
= GPR ( OP
[ 1 ]);
1381 trace_input ( "ld" , OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1384 State
. exception
= SIG_D10V_BUS
;
1385 State
. pc_changed
= 1 ; /* Don't increment the PC. */
1386 trace_output_void ();
1390 SET_GPR ( OP
[ 0 ], tmp
);
1391 trace_output_16 ( tmp
);
1399 uint16 addr
= OP
[ 1 ];
1400 trace_input ( "ld" , OP_REG_OUTPUT
, OP_MEMREF3
, OP_VOID
);
1403 State
. exception
= SIG_D10V_BUS
;
1404 State
. pc_changed
= 1 ; /* Don't increment the PC. */
1405 trace_output_void ();
1409 SET_GPR ( OP
[ 0 ], tmp
);
1410 trace_output_16 ( tmp
);
1418 uint16 addr
= OP
[ 1 ] + GPR ( OP
[ 2 ]);
1419 trace_input ( "ld2w" , OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1422 State
. exception
= SIG_D10V_BUS
;
1423 State
. pc_changed
= 1 ; /* Don't increment the PC. */
1424 trace_output_void ();
1428 SET_GPR32 ( OP
[ 0 ], tmp
);
1429 trace_output_32 ( tmp
);
1436 uint16 addr
= GPR ( OP
[ 1 ]);
1438 trace_input ( "ld2w" , OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1441 State
. exception
= SIG_D10V_BUS
;
1442 State
. pc_changed
= 1 ; /* Don't increment the PC. */
1443 trace_output_void ();
1447 SET_GPR32 ( OP
[ 0 ], tmp
);
1448 if ( OP
[ 0 ] != OP
[ 1 ] && (( OP
[ 0 ] + 1 ) != OP
[ 1 ]))
1449 INC_ADDR ( OP
[ 1 ], - 4 );
1450 trace_output_32 ( tmp
);
1458 uint16 addr
= GPR ( OP
[ 1 ]);
1459 trace_input ( "ld2w" , OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1462 State
. exception
= SIG_D10V_BUS
;
1463 State
. pc_changed
= 1 ; /* Don't increment the PC. */
1464 trace_output_void ();
1468 SET_GPR32 ( OP
[ 0 ], tmp
);
1469 if ( OP
[ 0 ] != OP
[ 1 ] && (( OP
[ 0 ] + 1 ) != OP
[ 1 ]))
1470 INC_ADDR ( OP
[ 1 ], 4 );
1471 trace_output_32 ( tmp
);
1478 uint16 addr
= GPR ( OP
[ 1 ]);
1480 trace_input ( "ld2w" , OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1483 State
. exception
= SIG_D10V_BUS
;
1484 State
. pc_changed
= 1 ; /* Don't increment the PC. */
1485 trace_output_void ();
1489 SET_GPR32 ( OP
[ 0 ], tmp
);
1490 trace_output_32 ( tmp
);
1498 uint16 addr
= OP
[ 1 ];
1499 trace_input ( "ld2w" , OP_REG_OUTPUT
, OP_MEMREF3
, OP_VOID
);
1502 State
. exception
= SIG_D10V_BUS
;
1503 State
. pc_changed
= 1 ; /* Don't increment the PC. */
1504 trace_output_void ();
1508 SET_GPR32 ( OP
[ 0 ], tmp
);
1509 trace_output_32 ( tmp
);
1517 trace_input ( "ldb" , OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1518 tmp
= SEXT8 ( RB ( OP
[ 1 ] + GPR ( OP
[ 2 ])));
1519 SET_GPR ( OP
[ 0 ], tmp
);
1520 trace_output_16 ( tmp
);
1528 trace_input ( "ldb" , OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1529 tmp
= SEXT8 ( RB ( GPR ( OP
[ 1 ])));
1530 SET_GPR ( OP
[ 0 ], tmp
);
1531 trace_output_16 ( tmp
);
1539 trace_input ( "ldi.s" , OP_REG_OUTPUT
, OP_CONSTANT4
, OP_VOID
);
1540 tmp
= SEXT4 ( OP
[ 1 ]);
1541 SET_GPR ( OP
[ 0 ], tmp
);
1542 trace_output_16 ( tmp
);
1550 trace_input ( "ldi.l" , OP_REG_OUTPUT
, OP_CONSTANT16
, OP_VOID
);
1552 SET_GPR ( OP
[ 0 ], tmp
);
1553 trace_output_16 ( tmp
);
1561 trace_input ( "ldub" , OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1562 tmp
= RB ( OP
[ 1 ] + GPR ( OP
[ 2 ]));
1563 SET_GPR ( OP
[ 0 ], tmp
);
1564 trace_output_16 ( tmp
);
1572 trace_input ( "ldub" , OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1573 tmp
= RB ( GPR ( OP
[ 1 ]));
1574 SET_GPR ( OP
[ 0 ], tmp
);
1575 trace_output_16 ( tmp
);
1584 trace_input ( "mac" , OP_ACCUM
, OP_REG
, OP_REG
);
1585 tmp
= SEXT40 (( int16
)( GPR ( OP
[ 1 ])) * ( int16
)( GPR ( OP
[ 2 ])));
1588 tmp
= SEXT40 ( ( tmp
<< 1 ) & MASK40
);
1590 if ( PSW_ST
&& tmp
> SEXT40 ( MAX32
))
1593 tmp
+= SEXT40 ( ACC ( OP
[ 0 ]));
1596 if ( tmp
> SEXT40 ( MAX32
))
1598 else if ( tmp
< SEXT40 ( MIN32
))
1601 tmp
= ( tmp
& MASK40
);
1604 tmp
= ( tmp
& MASK40
);
1605 SET_ACC ( OP
[ 0 ], tmp
);
1606 trace_output_40 ( tmp
);
1615 trace_input ( "macsu" , OP_ACCUM
, OP_REG
, OP_REG
);
1616 tmp
= SEXT40 (( int16
) GPR ( OP
[ 1 ]) * GPR ( OP
[ 2 ]));
1618 tmp
= SEXT40 (( tmp
<< 1 ) & MASK40
);
1619 tmp
= (( SEXT40 ( ACC ( OP
[ 0 ])) + tmp
) & MASK40
);
1620 SET_ACC ( OP
[ 0 ], tmp
);
1621 trace_output_40 ( tmp
);
1632 trace_input ( "macu" , OP_ACCUM
, OP_REG
, OP_REG
);
1633 src1
= ( uint16
) GPR ( OP
[ 1 ]);
1634 src2
= ( uint16
) GPR ( OP
[ 2 ]);
1638 tmp
= (( ACC ( OP
[ 0 ]) + tmp
) & MASK40
);
1639 SET_ACC ( OP
[ 0 ], tmp
);
1640 trace_output_40 ( tmp
);
1648 trace_input ( "max" , OP_REG
, OP_REG
, OP_VOID
);
1649 SET_PSW_F1 ( PSW_F0
);
1650 if (( int16
) GPR ( OP
[ 1 ]) > ( int16
) GPR ( OP
[ 0 ]))
1660 SET_GPR ( OP
[ 0 ], tmp
);
1661 trace_output_16 ( tmp
);
1670 trace_input ( "max" , OP_ACCUM
, OP_DREG
, OP_VOID
);
1671 SET_PSW_F1 ( PSW_F0
);
1672 tmp
= SEXT16 ( GPR ( OP
[ 1 ])) << 16 | GPR ( OP
[ 1 ] + 1 );
1673 if ( tmp
> SEXT40 ( ACC ( OP
[ 0 ])))
1675 tmp
= ( tmp
& MASK40
);
1683 SET_ACC ( OP
[ 0 ], tmp
);
1684 trace_output_40 ( tmp
);
1692 trace_input ( "max" , OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1693 SET_PSW_F1 ( PSW_F0
);
1694 if ( SEXT40 ( ACC ( OP
[ 1 ])) > SEXT40 ( ACC ( OP
[ 0 ])))
1704 SET_ACC ( OP
[ 0 ], tmp
);
1705 trace_output_40 ( tmp
);
1714 trace_input ( "min" , OP_REG
, OP_REG
, OP_VOID
);
1715 SET_PSW_F1 ( PSW_F0
);
1716 if (( int16
) GPR ( OP
[ 1 ]) < ( int16
) GPR ( OP
[ 0 ]))
1726 SET_GPR ( OP
[ 0 ], tmp
);
1727 trace_output_16 ( tmp
);
1736 trace_input ( "min" , OP_ACCUM
, OP_DREG
, OP_VOID
);
1737 SET_PSW_F1 ( PSW_F0
);
1738 tmp
= SEXT16 ( GPR ( OP
[ 1 ])) << 16 | GPR ( OP
[ 1 ] + 1 );
1739 if ( tmp
< SEXT40 ( ACC ( OP
[ 0 ])))
1741 tmp
= ( tmp
& MASK40
);
1749 SET_ACC ( OP
[ 0 ], tmp
);
1750 trace_output_40 ( tmp
);
1758 trace_input ( "min" , OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1759 SET_PSW_F1 ( PSW_F0
);
1760 if ( SEXT40 ( ACC ( OP
[ 1 ])) < SEXT40 ( ACC ( OP
[ 0 ])))
1770 SET_ACC ( OP
[ 0 ], tmp
);
1771 trace_output_40 ( tmp
);
1780 trace_input ( "msb" , OP_ACCUM
, OP_REG
, OP_REG
);
1781 tmp
= SEXT40 (( int16
)( GPR ( OP
[ 1 ])) * ( int16
)( GPR ( OP
[ 2 ])));
1784 tmp
= SEXT40 (( tmp
<< 1 ) & MASK40
);
1786 if ( PSW_ST
&& tmp
> SEXT40 ( MAX32
))
1789 tmp
= SEXT40 ( ACC ( OP
[ 0 ])) - tmp
;
1792 if ( tmp
> SEXT40 ( MAX32
))
1794 else if ( tmp
< SEXT40 ( MIN32
))
1797 tmp
= ( tmp
& MASK40
);
1801 tmp
= ( tmp
& MASK40
);
1803 SET_ACC ( OP
[ 0 ], tmp
);
1804 trace_output_40 ( tmp
);
1813 trace_input ( "msbsu" , OP_ACCUM
, OP_REG
, OP_REG
);
1814 tmp
= SEXT40 (( int16
) GPR ( OP
[ 1 ]) * GPR ( OP
[ 2 ]));
1816 tmp
= SEXT40 ( ( tmp
<< 1 ) & MASK40
);
1817 tmp
= (( SEXT40 ( ACC ( OP
[ 0 ])) - tmp
) & MASK40
);
1818 SET_ACC ( OP
[ 0 ], tmp
);
1819 trace_output_40 ( tmp
);
1830 trace_input ( "msbu" , OP_ACCUM
, OP_REG
, OP_REG
);
1831 src1
= ( uint16
) GPR ( OP
[ 1 ]);
1832 src2
= ( uint16
) GPR ( OP
[ 2 ]);
1836 tmp
= (( ACC ( OP
[ 0 ]) - tmp
) & MASK40
);
1837 SET_ACC ( OP
[ 0 ], tmp
);
1838 trace_output_40 ( tmp
);
1846 trace_input ( "mul" , OP_REG
, OP_REG
, OP_VOID
);
1847 tmp
= GPR ( OP
[ 0 ]) * GPR ( OP
[ 1 ]);
1848 SET_GPR ( OP
[ 0 ], tmp
);
1849 trace_output_16 ( tmp
);
1858 trace_input ( "mulx" , OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1859 tmp
= SEXT40 (( int16
)( GPR ( OP
[ 1 ])) * ( int16
)( GPR ( OP
[ 2 ])));
1862 tmp
= SEXT40 (( tmp
<< 1 ) & MASK40
);
1864 if ( PSW_ST
&& tmp
> SEXT40 ( MAX32
))
1867 tmp
= ( tmp
& MASK40
);
1868 SET_ACC ( OP
[ 0 ], tmp
);
1869 trace_output_40 ( tmp
);
1878 trace_input ( "mulxsu" , OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1879 tmp
= SEXT40 (( int16
)( GPR ( OP
[ 1 ])) * GPR ( OP
[ 2 ]));
1883 tmp
= ( tmp
& MASK40
);
1884 SET_ACC ( OP
[ 0 ], tmp
);
1885 trace_output_40 ( tmp
);
1896 trace_input ( "mulxu" , OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1897 src1
= ( uint16
) GPR ( OP
[ 1 ]);
1898 src2
= ( uint16
) GPR ( OP
[ 2 ]);
1902 tmp
= ( tmp
& MASK40
);
1903 SET_ACC ( OP
[ 0 ], tmp
);
1904 trace_output_40 ( tmp
);
1912 trace_input ( "mv" , OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1914 SET_GPR ( OP
[ 0 ], tmp
);
1915 trace_output_16 ( tmp
);
1923 trace_input ( "mv2w" , OP_DREG_OUTPUT
, OP_DREG
, OP_VOID
);
1924 tmp
= GPR32 ( OP
[ 1 ]);
1925 SET_GPR32 ( OP
[ 0 ], tmp
);
1926 trace_output_32 ( tmp
);
1934 trace_input ( "mv2wfac" , OP_DREG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1936 SET_GPR32 ( OP
[ 0 ], tmp
);
1937 trace_output_32 ( tmp
);
1945 trace_input ( "mv2wtac" , OP_DREG
, OP_ACCUM_OUTPUT
, OP_VOID
);
1946 tmp
= (( SEXT16 ( GPR ( OP
[ 0 ])) << 16 | GPR ( OP
[ 0 ] + 1 )) & MASK40
);
1947 SET_ACC ( OP
[ 1 ], tmp
);
1948 trace_output_40 ( tmp
);
1956 trace_input ( "mvac" , OP_ACCUM_OUTPUT
, OP_ACCUM
, OP_VOID
);
1958 SET_ACC ( OP
[ 0 ], tmp
);
1959 trace_output_40 ( tmp
);
1967 trace_input ( "mvb" , OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1968 tmp
= SEXT8 ( GPR ( OP
[ 1 ]) & 0xff );
1969 SET_GPR ( OP
[ 0 ], tmp
);
1970 trace_output_16 ( tmp
);
1978 trace_input ( "mvf0f" , OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1982 SET_GPR ( OP
[ 0 ], tmp
);
1986 trace_output_16 ( tmp
);
1994 trace_input ( "mvf0t" , OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1998 SET_GPR ( OP
[ 0 ], tmp
);
2002 trace_output_16 ( tmp
);
2010 trace_input ( "mvfacg" , OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2011 tmp
= (( ACC ( OP
[ 1 ]) >> 32 ) & 0xff );
2012 SET_GPR ( OP
[ 0 ], tmp
);
2013 trace_output_16 ( tmp
);
2021 trace_input ( "mvfachi" , OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2022 tmp
= ( ACC ( OP
[ 1 ]) >> 16 );
2023 SET_GPR ( OP
[ 0 ], tmp
);
2024 trace_output_16 ( tmp
);
2032 trace_input ( "mvfaclo" , OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2034 SET_GPR ( OP
[ 0 ], tmp
);
2035 trace_output_16 ( tmp
);
2043 trace_input ( "mvfc" , OP_REG_OUTPUT
, OP_CR
, OP_VOID
);
2045 SET_GPR ( OP
[ 0 ], tmp
);
2046 trace_output_16 ( tmp
);
2054 trace_input ( "mvtacg" , OP_REG
, OP_ACCUM
, OP_VOID
);
2055 tmp
= (( ACC ( OP
[ 1 ]) & MASK32
)
2056 | (( int64
)( GPR ( OP
[ 0 ]) & 0xff ) << 32 ));
2057 SET_ACC ( OP
[ 1 ], tmp
);
2058 trace_output_40 ( tmp
);
2066 trace_input ( "mvtachi" , OP_REG
, OP_ACCUM
, OP_VOID
);
2067 tmp
= ACC ( OP
[ 1 ]) & 0xffff ;
2068 tmp
= (( SEXT16 ( GPR ( OP
[ 0 ])) << 16 | tmp
) & MASK40
);
2069 SET_ACC ( OP
[ 1 ], tmp
);
2070 trace_output_40 ( tmp
);
2078 trace_input ( "mvtaclo" , OP_REG
, OP_ACCUM
, OP_VOID
);
2079 tmp
= (( SEXT16 ( GPR ( OP
[ 0 ]))) & MASK40
);
2080 SET_ACC ( OP
[ 1 ], tmp
);
2081 trace_output_40 ( tmp
);
2089 trace_input ( "mvtc" , OP_REG
, OP_CR_OUTPUT
, OP_VOID
);
2091 tmp
= SET_CREG ( OP
[ 1 ], tmp
);
2092 trace_output_16 ( tmp
);
2100 trace_input ( "mvub" , OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
2101 tmp
= ( GPR ( OP
[ 1 ]) & 0xff );
2102 SET_GPR ( OP
[ 0 ], tmp
);
2103 trace_output_16 ( tmp
);
2111 trace_input ( "neg" , OP_REG
, OP_VOID
, OP_VOID
);
2112 tmp
= - GPR ( OP
[ 0 ]);
2113 SET_GPR ( OP
[ 0 ], tmp
);
2114 trace_output_16 ( tmp
);
2123 trace_input ( "neg" , OP_ACCUM
, OP_VOID
, OP_VOID
);
2124 tmp
= - SEXT40 ( ACC ( OP
[ 0 ]));
2127 if ( tmp
> SEXT40 ( MAX32
))
2129 else if ( tmp
< SEXT40 ( MIN32
))
2132 tmp
= ( tmp
& MASK40
);
2135 tmp
= ( tmp
& MASK40
);
2136 SET_ACC ( OP
[ 0 ], tmp
);
2137 trace_output_40 ( tmp
);
2145 trace_input ( "nop" , OP_VOID
, OP_VOID
, OP_VOID
);
2147 ins_type_counters
[ ( int ) State
. ins_type
]--; /* don't count nops as normal instructions */
2148 switch ( State
. ins_type
)
2151 ins_type_counters
[ ( int ) INS_UNKNOWN
]++;
2154 case INS_LEFT_PARALLEL
:
2155 /* Don't count a parallel op that includes a NOP as a true parallel op */
2156 ins_type_counters
[ ( int ) INS_RIGHT_PARALLEL
]--;
2157 ins_type_counters
[ ( int ) INS_RIGHT
]++;
2158 ins_type_counters
[ ( int ) INS_LEFT_NOPS
]++;
2162 case INS_LEFT_COND_EXE
:
2163 ins_type_counters
[ ( int ) INS_LEFT_NOPS
]++;
2166 case INS_RIGHT_PARALLEL
:
2167 /* Don't count a parallel op that includes a NOP as a true parallel op */
2168 ins_type_counters
[ ( int ) INS_LEFT_PARALLEL
]--;
2169 ins_type_counters
[ ( int ) INS_LEFT
]++;
2170 ins_type_counters
[ ( int ) INS_RIGHT_NOPS
]++;
2174 case INS_RIGHT_COND_EXE
:
2175 ins_type_counters
[ ( int ) INS_RIGHT_NOPS
]++;
2179 trace_output_void ();
2187 trace_input ( "not" , OP_REG
, OP_VOID
, OP_VOID
);
2189 SET_GPR ( OP
[ 0 ], tmp
);
2190 trace_output_16 ( tmp
);
2198 trace_input ( "or" , OP_REG
, OP_REG
, OP_VOID
);
2199 tmp
= ( GPR ( OP
[ 0 ]) | GPR ( OP
[ 1 ]));
2200 SET_GPR ( OP
[ 0 ], tmp
);
2201 trace_output_16 ( tmp
);
2209 trace_input ( "or3" , OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
2210 tmp
= ( GPR ( OP
[ 1 ]) | OP
[ 2 ]);
2211 SET_GPR ( OP
[ 0 ], tmp
);
2212 trace_output_16 ( tmp
);
2220 int shift
= SEXT3 ( OP
[ 2 ]);
2222 trace_input ( "rac" , OP_DREG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
2225 (* d10v_callback
-> printf_filtered
) ( d10v_callback
,
2226 "ERROR at PC 0x%x: instruction only valid for A0 \n " ,
2228 State
. exception
= SIGILL
;
2231 SET_PSW_F1 ( PSW_F0
);
2232 tmp
= SEXT56 (( ACC ( 0 ) << 16 ) | ( ACC ( 1 ) & 0xffff ));
2238 tmp
>>= 16 ; /* look at bits 0:43 */
2239 if ( tmp
> SEXT44 ( SIGNED64 ( 0x0007fffffff )))
2244 else if ( tmp
< SEXT44 ( SIGNED64 ( 0xfff80000000 )))
2253 SET_GPR32 ( OP
[ 0 ], tmp
);
2254 trace_output_32 ( tmp
);
2262 int shift
= SEXT3 ( OP
[ 2 ]);
2264 trace_input ( "rachi" , OP_REG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
2265 SET_PSW_F1 ( PSW_F0
);
2267 tmp
= SEXT40 ( ACC ( OP
[ 1 ])) << shift
;
2269 tmp
= SEXT40 ( ACC ( OP
[ 1 ])) >> - shift
;
2272 if ( tmp
> SEXT44 ( SIGNED64 ( 0x0007fffffff )))
2277 else if ( tmp
< SEXT44 ( SIGNED64 ( 0xfff80000000 )))
2287 SET_GPR ( OP
[ 0 ], tmp
);
2288 trace_output_16 ( tmp
);
2295 trace_input ( "rep" , OP_REG
, OP_CONSTANT16
, OP_VOID
);
2297 SET_RPT_E ( PC
+ OP
[ 1 ]);
2298 SET_RPT_C ( GPR ( OP
[ 0 ]));
2300 if ( GPR ( OP
[ 0 ]) == 0 )
2302 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "ERROR: rep with count=0 is illegal. \n " );
2303 State
. exception
= SIGILL
;
2307 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "ERROR: rep must include at least 4 instructions. \n " );
2308 State
. exception
= SIGILL
;
2310 trace_output_void ();
2317 trace_input ( "repi" , OP_CONSTANT16
, OP_CONSTANT16
, OP_VOID
);
2319 SET_RPT_E ( PC
+ OP
[ 1 ]);
2324 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "ERROR: repi with count=0 is illegal. \n " );
2325 State
. exception
= SIGILL
;
2329 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "ERROR: repi must include at least 4 instructions. \n " );
2330 State
. exception
= SIGILL
;
2332 trace_output_void ();
2339 trace_input ( "rtd" , OP_VOID
, OP_VOID
, OP_VOID
);
2340 SET_CREG ( PSW_CR
, DPSW
);
2342 trace_output_void ();
2349 trace_input ( "rte" , OP_VOID
, OP_VOID
, OP_VOID
);
2350 SET_CREG ( PSW_CR
, BPSW
);
2352 trace_output_void ();
2360 trace_input ( "sac" , OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2362 tmp
= SEXT40 ( ACC ( OP
[ 1 ]));
2364 SET_PSW_F1 ( PSW_F0
);
2366 if ( tmp
> SEXT40 ( MAX32
))
2371 else if ( tmp
< SEXT40 ( MIN32
))
2378 tmp
= ( tmp
& MASK32
);
2382 SET_GPR32 ( OP
[ 0 ], tmp
);
2384 trace_output_40 ( tmp
);
2393 trace_input ( "sachi" , OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2395 tmp
= SEXT40 ( ACC ( OP
[ 1 ]));
2397 SET_PSW_F1 ( PSW_F0
);
2399 if ( tmp
> SEXT40 ( MAX32
))
2404 else if ( tmp
< SEXT40 ( MIN32
))
2415 SET_GPR ( OP
[ 0 ], tmp
);
2417 trace_output_16 ( OP
[ 0 ]);
2426 trace_input ( "sadd" , OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2427 tmp
= SEXT40 ( ACC ( OP
[ 0 ])) + ( SEXT40 ( ACC ( OP
[ 1 ])) >> 16 );
2430 if ( tmp
> SEXT40 ( MAX32
))
2432 else if ( tmp
< SEXT40 ( MIN32
))
2435 tmp
= ( tmp
& MASK40
);
2438 tmp
= ( tmp
& MASK40
);
2439 SET_ACC ( OP
[ 0 ], tmp
);
2440 trace_output_40 ( tmp
);
2448 trace_input ( "setf0f" , OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2449 tmp
= (( PSW_F0
== 0 ) ? 1 : 0 );
2450 SET_GPR ( OP
[ 0 ], tmp
);
2451 trace_output_16 ( tmp
);
2459 trace_input ( "setf0t" , OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2460 tmp
= (( PSW_F0
== 1 ) ? 1 : 0 );
2461 SET_GPR ( OP
[ 0 ], tmp
);
2462 trace_output_16 ( tmp
);
2472 trace_input ( "slae" , OP_ACCUM
, OP_REG
, OP_VOID
);
2474 reg
= SEXT16 ( GPR ( OP
[ 1 ]));
2476 if ( reg
>= 17 || reg
<= - 17 )
2478 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "ERROR: shift value %d too large. \n " , reg
);
2479 State
. exception
= SIGILL
;
2483 tmp
= SEXT40 ( ACC ( OP
[ 0 ]));
2485 if ( PSW_ST
&& ( tmp
< SEXT40 ( MIN32
) || tmp
> SEXT40 ( MAX32
)))
2487 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "ERROR: accumulator value 0x%.2x%.8lx out of range \n " , (( int )( tmp
>> 32 ) & 0xff ), (( unsigned long ) tmp
) & 0xffffffff );
2488 State
. exception
= SIGILL
;
2492 if ( reg
>= 0 && reg
<= 16 )
2494 tmp
= SEXT56 (( SEXT56 ( tmp
)) << ( GPR ( OP
[ 1 ])));
2497 if ( tmp
> SEXT40 ( MAX32
))
2499 else if ( tmp
< SEXT40 ( MIN32
))
2502 tmp
= ( tmp
& MASK40
);
2505 tmp
= ( tmp
& MASK40
);
2509 tmp
= ( SEXT40 ( ACC ( OP
[ 0 ]))) >> (- GPR ( OP
[ 1 ]));
2512 SET_ACC ( OP
[ 0 ], tmp
);
2514 trace_output_40 ( tmp
);
2521 trace_input ( "sleep" , OP_VOID
, OP_VOID
, OP_VOID
);
2523 trace_output_void ();
2531 trace_input ( "sll" , OP_REG
, OP_REG
, OP_VOID
);
2532 tmp
= ( GPR ( OP
[ 0 ]) << ( GPR ( OP
[ 1 ]) & 0xf ));
2533 SET_GPR ( OP
[ 0 ], tmp
);
2534 trace_output_16 ( tmp
);
2542 trace_input ( "sll" , OP_ACCUM
, OP_REG
, OP_VOID
);
2543 if (( GPR ( OP
[ 1 ]) & 31 ) <= 16 )
2544 tmp
= SEXT40 ( ACC ( OP
[ 0 ])) << ( GPR ( OP
[ 1 ]) & 31 );
2547 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "ERROR: shift value %d too large. \n " , GPR ( OP
[ 1 ]) & 31 );
2548 State
. exception
= SIGILL
;
2554 if ( tmp
> SEXT40 ( MAX32
))
2556 else if ( tmp
< SEXT40 ( MIN32
))
2559 tmp
= ( tmp
& MASK40
);
2562 tmp
= ( tmp
& MASK40
);
2563 SET_ACC ( OP
[ 0 ], tmp
);
2564 trace_output_40 ( tmp
);
2572 trace_input ( "slli" , OP_REG
, OP_CONSTANT16
, OP_VOID
);
2573 tmp
= ( GPR ( OP
[ 0 ]) << OP
[ 1 ]);
2574 SET_GPR ( OP
[ 0 ], tmp
);
2575 trace_output_16 ( tmp
);
2587 trace_input ( "slli" , OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2588 tmp
= SEXT40 ( ACC ( OP
[ 0 ])) << OP
[ 1 ];
2592 if ( tmp
> SEXT40 ( MAX32
))
2594 else if ( tmp
< SEXT40 ( MIN32
))
2597 tmp
= ( tmp
& MASK40
);
2600 tmp
= ( tmp
& MASK40
);
2601 SET_ACC ( OP
[ 0 ], tmp
);
2602 trace_output_40 ( tmp
);
2610 trace_input ( "slx" , OP_REG
, OP_VOID
, OP_VOID
);
2611 tmp
= (( GPR ( OP
[ 0 ]) << 1 ) | PSW_F0
);
2612 SET_GPR ( OP
[ 0 ], tmp
);
2613 trace_output_16 ( tmp
);
2621 trace_input ( "sra" , OP_REG
, OP_REG
, OP_VOID
);
2622 tmp
= ((( int16
)( GPR ( OP
[ 0 ]))) >> ( GPR ( OP
[ 1 ]) & 0xf ));
2623 SET_GPR ( OP
[ 0 ], tmp
);
2624 trace_output_16 ( tmp
);
2631 trace_input ( "sra" , OP_ACCUM
, OP_REG
, OP_VOID
);
2632 if (( GPR ( OP
[ 1 ]) & 31 ) <= 16 )
2634 int64 tmp
= (( SEXT40 ( ACC ( OP
[ 0 ])) >> ( GPR ( OP
[ 1 ]) & 31 )) & MASK40
);
2635 SET_ACC ( OP
[ 0 ], tmp
);
2636 trace_output_40 ( tmp
);
2640 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "ERROR: shift value %d too large. \n " , GPR ( OP
[ 1 ]) & 31 );
2641 State
. exception
= SIGILL
;
2651 trace_input ( "srai" , OP_REG
, OP_CONSTANT16
, OP_VOID
);
2652 tmp
= ((( int16
)( GPR ( OP
[ 0 ]))) >> OP
[ 1 ]);
2653 SET_GPR ( OP
[ 0 ], tmp
);
2654 trace_output_16 ( tmp
);
2665 trace_input ( "srai" , OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2666 tmp
= (( SEXT40 ( ACC ( OP
[ 0 ])) >> OP
[ 1 ]) & MASK40
);
2667 SET_ACC ( OP
[ 0 ], tmp
);
2668 trace_output_40 ( tmp
);
2676 trace_input ( "srl" , OP_REG
, OP_REG
, OP_VOID
);
2677 tmp
= ( GPR ( OP
[ 0 ]) >> ( GPR ( OP
[ 1 ]) & 0xf ));
2678 SET_GPR ( OP
[ 0 ], tmp
);
2679 trace_output_16 ( tmp
);
2686 trace_input ( "srl" , OP_ACCUM
, OP_REG
, OP_VOID
);
2687 if (( GPR ( OP
[ 1 ]) & 31 ) <= 16 )
2689 int64 tmp
= (( uint64
)(( ACC ( OP
[ 0 ]) & MASK40
) >> ( GPR ( OP
[ 1 ]) & 31 )));
2690 SET_ACC ( OP
[ 0 ], tmp
);
2691 trace_output_40 ( tmp
);
2695 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "ERROR: shift value %d too large. \n " , GPR ( OP
[ 1 ]) & 31 );
2696 State
. exception
= SIGILL
;
2707 trace_input ( "srli" , OP_REG
, OP_CONSTANT16
, OP_VOID
);
2708 tmp
= ( GPR ( OP
[ 0 ]) >> OP
[ 1 ]);
2709 SET_GPR ( OP
[ 0 ], tmp
);
2710 trace_output_16 ( tmp
);
2721 trace_input ( "srli" , OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2722 tmp
= (( uint64
)( ACC ( OP
[ 0 ]) & MASK40
) >> OP
[ 1 ]);
2723 SET_ACC ( OP
[ 0 ], tmp
);
2724 trace_output_40 ( tmp
);
2732 trace_input ( "srx" , OP_REG
, OP_VOID
, OP_VOID
);
2734 tmp
= (( GPR ( OP
[ 0 ]) >> 1 ) | tmp
);
2735 SET_GPR ( OP
[ 0 ], tmp
);
2736 trace_output_16 ( tmp
);
2743 uint16 addr
= OP
[ 1 ] + GPR ( OP
[ 2 ]);
2744 trace_input ( "st" , OP_REG
, OP_MEMREF2
, OP_VOID
);
2747 State
. exception
= SIG_D10V_BUS
;
2748 State
. pc_changed
= 1 ; /* Don't increment the PC. */
2749 trace_output_void ();
2752 SW ( addr
, GPR ( OP
[ 0 ]));
2753 trace_output_void ();
2760 uint16 addr
= GPR ( OP
[ 1 ]);
2761 trace_input ( "st" , OP_REG
, OP_MEMREF
, OP_VOID
);
2764 State
. exception
= SIG_D10V_BUS
;
2765 State
. pc_changed
= 1 ; /* Don't increment the PC. */
2766 trace_output_void ();
2769 SW ( addr
, GPR ( OP
[ 0 ]));
2770 trace_output_void ();
2778 uint16 addr
= GPR ( OP
[ 1 ]) - 2 ;
2779 trace_input ( "st" , OP_REG
, OP_PREDEC
, OP_VOID
);
2782 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP). \n " );
2783 State
. exception
= SIGILL
;
2788 State
. exception
= SIG_D10V_BUS
;
2789 State
. pc_changed
= 1 ; /* Don't increment the PC. */
2790 trace_output_void ();
2793 SW ( addr
, GPR ( OP
[ 0 ]));
2794 SET_GPR ( OP
[ 1 ], addr
);
2795 trace_output_void ();
2802 uint16 addr
= GPR ( OP
[ 1 ]);
2803 trace_input ( "st" , OP_REG
, OP_POSTINC
, OP_VOID
);
2806 State
. exception
= SIG_D10V_BUS
;
2807 State
. pc_changed
= 1 ; /* Don't increment the PC. */
2808 trace_output_void ();
2811 SW ( addr
, GPR ( OP
[ 0 ]));
2812 INC_ADDR ( OP
[ 1 ], 2 );
2813 trace_output_void ();
2820 uint16 addr
= GPR ( OP
[ 1 ]);
2821 trace_input ( "st" , OP_REG
, OP_POSTDEC
, OP_VOID
);
2824 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "ERROR: cannot post-decrement register r15 (SP). \n " );
2825 State
. exception
= SIGILL
;
2830 State
. exception
= SIG_D10V_BUS
;
2831 State
. pc_changed
= 1 ; /* Don't increment the PC. */
2832 trace_output_void ();
2835 SW ( addr
, GPR ( OP
[ 0 ]));
2836 INC_ADDR ( OP
[ 1 ], - 2 );
2837 trace_output_void ();
2844 uint16 addr
= OP
[ 1 ];
2845 trace_input ( "st" , OP_REG
, OP_MEMREF3
, OP_VOID
);
2848 State
. exception
= SIG_D10V_BUS
;
2849 State
. pc_changed
= 1 ; /* Don't increment the PC. */
2850 trace_output_void ();
2853 SW ( addr
, GPR ( OP
[ 0 ]));
2854 trace_output_void ();
2861 uint16 addr
= GPR ( OP
[ 2 ])+ OP
[ 1 ];
2862 trace_input ( "st2w" , OP_DREG
, OP_MEMREF2
, OP_VOID
);
2865 State
. exception
= SIG_D10V_BUS
;
2866 State
. pc_changed
= 1 ; /* Don't increment the PC. */
2867 trace_output_void ();
2870 SW ( addr
+ 0 , GPR ( OP
[ 0 ] + 0 ));
2871 SW ( addr
+ 2 , GPR ( OP
[ 0 ] + 1 ));
2872 trace_output_void ();
2879 uint16 addr
= GPR ( OP
[ 1 ]);
2880 trace_input ( "st2w" , OP_DREG
, OP_MEMREF
, OP_VOID
);
2883 State
. exception
= SIG_D10V_BUS
;
2884 State
. pc_changed
= 1 ; /* Don't increment the PC. */
2885 trace_output_void ();
2888 SW ( addr
+ 0 , GPR ( OP
[ 0 ] + 0 ));
2889 SW ( addr
+ 2 , GPR ( OP
[ 0 ] + 1 ));
2890 trace_output_void ();
2897 uint16 addr
= GPR ( OP
[ 1 ]) - 4 ;
2898 trace_input ( "st2w" , OP_DREG
, OP_PREDEC
, OP_VOID
);
2901 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP). \n " );
2902 State
. exception
= SIGILL
;
2907 State
. exception
= SIG_D10V_BUS
;
2908 State
. pc_changed
= 1 ; /* Don't increment the PC. */
2909 trace_output_void ();
2912 SW ( addr
+ 0 , GPR ( OP
[ 0 ] + 0 ));
2913 SW ( addr
+ 2 , GPR ( OP
[ 0 ] + 1 ));
2914 SET_GPR ( OP
[ 1 ], addr
);
2915 trace_output_void ();
2922 uint16 addr
= GPR ( OP
[ 1 ]);
2923 trace_input ( "st2w" , OP_DREG
, OP_POSTINC
, OP_VOID
);
2926 State
. exception
= SIG_D10V_BUS
;
2927 State
. pc_changed
= 1 ; /* Don't increment the PC. */
2928 trace_output_void ();
2931 SW ( addr
+ 0 , GPR ( OP
[ 0 ] + 0 ));
2932 SW ( addr
+ 2 , GPR ( OP
[ 0 ] + 1 ));
2933 INC_ADDR ( OP
[ 1 ], 4 );
2934 trace_output_void ();
2941 uint16 addr
= GPR ( OP
[ 1 ]);
2942 trace_input ( "st2w" , OP_DREG
, OP_POSTDEC
, OP_VOID
);
2945 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "ERROR: cannot post-decrement register r15 (SP). \n " );
2946 State
. exception
= SIGILL
;
2951 State
. exception
= SIG_D10V_BUS
;
2952 State
. pc_changed
= 1 ; /* Don't increment the PC. */
2953 trace_output_void ();
2956 SW ( addr
+ 0 , GPR ( OP
[ 0 ] + 0 ));
2957 SW ( addr
+ 2 , GPR ( OP
[ 0 ] + 1 ));
2958 INC_ADDR ( OP
[ 1 ], - 4 );
2959 trace_output_void ();
2966 uint16 addr
= OP
[ 1 ];
2967 trace_input ( "st2w" , OP_DREG
, OP_MEMREF3
, OP_VOID
);
2970 State
. exception
= SIG_D10V_BUS
;
2971 State
. pc_changed
= 1 ; /* Don't increment the PC. */
2972 trace_output_void ();
2975 SW ( addr
+ 0 , GPR ( OP
[ 0 ] + 0 ));
2976 SW ( addr
+ 2 , GPR ( OP
[ 0 ] + 1 ));
2977 trace_output_void ();
2984 trace_input ( "stb" , OP_REG
, OP_MEMREF2
, OP_VOID
);
2985 SB ( GPR ( OP
[ 2 ]) + OP
[ 1 ], GPR ( OP
[ 0 ]));
2986 trace_output_void ();
2993 trace_input ( "stb" , OP_REG
, OP_MEMREF
, OP_VOID
);
2994 SB ( GPR ( OP
[ 1 ]), GPR ( OP
[ 0 ]));
2995 trace_output_void ();
3002 trace_input ( "stop" , OP_VOID
, OP_VOID
, OP_VOID
);
3003 State
. exception
= SIG_D10V_STOP
;
3004 trace_output_void ();
3011 uint16 a
= GPR ( OP
[ 0 ]);
3012 uint16 b
= GPR ( OP
[ 1 ]);
3013 uint16 tmp
= ( a
- b
);
3014 trace_input ( "sub" , OP_REG
, OP_REG
, OP_VOID
);
3015 /* see ../common/sim-alu.h for a more extensive discussion on how to
3016 compute the carry/overflow bits. */
3018 SET_GPR ( OP
[ 0 ], tmp
);
3019 trace_output_16 ( tmp
);
3028 trace_input ( "sub" , OP_ACCUM
, OP_DREG
, OP_VOID
);
3029 tmp
= SEXT40 ( ACC ( OP
[ 0 ])) - ( SEXT16 ( GPR ( OP
[ 1 ])) << 16 | GPR ( OP
[ 1 ] + 1 ));
3032 if ( tmp
> SEXT40 ( MAX32
))
3034 else if ( tmp
< SEXT40 ( MIN32
))
3037 tmp
= ( tmp
& MASK40
);
3040 tmp
= ( tmp
& MASK40
);
3041 SET_ACC ( OP
[ 0 ], tmp
);
3043 trace_output_40 ( tmp
);
3053 trace_input ( "sub" , OP_ACCUM
, OP_ACCUM
, OP_VOID
);
3054 tmp
= SEXT40 ( ACC ( OP
[ 0 ])) - SEXT40 ( ACC ( OP
[ 1 ]));
3057 if ( tmp
> SEXT40 ( MAX32
))
3059 else if ( tmp
< SEXT40 ( MIN32
))
3062 tmp
= ( tmp
& MASK40
);
3065 tmp
= ( tmp
& MASK40
);
3066 SET_ACC ( OP
[ 0 ], tmp
);
3068 trace_output_40 ( tmp
);
3077 trace_input ( "sub2w" , OP_DREG
, OP_DREG
, OP_VOID
);
3078 a
= ( uint32
)(( GPR ( OP
[ 0 ]) << 16 ) | GPR ( OP
[ 0 ] + 1 ));
3079 b
= ( uint32
)(( GPR ( OP
[ 1 ]) << 16 ) | GPR ( OP
[ 1 ] + 1 ));
3080 /* see ../common/sim-alu.h for a more extensive discussion on how to
3081 compute the carry/overflow bits */
3084 SET_GPR32 ( OP
[ 0 ], tmp
);
3085 trace_output_32 ( tmp
);
3094 trace_input ( "subac3" , OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
3095 tmp
= SEXT40 (( GPR ( OP
[ 1 ]) << 16 ) | GPR ( OP
[ 1 ] + 1 )) - SEXT40 ( ACC ( OP
[ 2 ]));
3096 SET_GPR32 ( OP
[ 0 ], tmp
);
3097 trace_output_32 ( tmp
);
3106 trace_input ( "subac3" , OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
3107 tmp
= SEXT40 ( ACC ( OP
[ 1 ])) - SEXT40 ( ACC ( OP
[ 2 ]));
3108 SET_GPR32 ( OP
[ 0 ], tmp
);
3109 trace_output_32 ( tmp
);
3118 trace_input ( "subac3s" , OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
3119 SET_PSW_F1 ( PSW_F0
);
3120 tmp
= SEXT40 (( GPR ( OP
[ 1 ]) << 16 ) | GPR ( OP
[ 1 ] + 1 )) - SEXT40 ( ACC ( OP
[ 2 ]));
3121 if ( tmp
> SEXT40 ( MAX32
))
3126 else if ( tmp
< SEXT40 ( MIN32
))
3135 SET_GPR32 ( OP
[ 0 ], tmp
);
3136 trace_output_32 ( tmp
);
3145 trace_input ( "subac3s" , OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
3146 SET_PSW_F1 ( PSW_F0
);
3147 tmp
= SEXT40 ( ACC ( OP
[ 1 ])) - SEXT40 ( ACC ( OP
[ 2 ]));
3148 if ( tmp
> SEXT40 ( MAX32
))
3153 else if ( tmp
< SEXT40 ( MIN32
))
3162 SET_GPR32 ( OP
[ 0 ], tmp
);
3163 trace_output_32 ( tmp
);
3174 trace_input ( "subi" , OP_REG
, OP_CONSTANT16
, OP_VOID
);
3175 /* see ../common/sim-alu.h for a more extensive discussion on how to
3176 compute the carry/overflow bits. */
3177 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
3178 tmp
= (( unsigned )( unsigned16
) GPR ( OP
[ 0 ])
3179 + ( unsigned )( unsigned16
) ( - OP
[ 1 ]));
3180 SET_PSW_C ( tmp
>= ( 1 << 16 ));
3181 SET_GPR ( OP
[ 0 ], tmp
);
3182 trace_output_16 ( tmp
);
3189 trace_input ( "trap" , OP_CONSTANT4
, OP_VOID
, OP_VOID
);
3190 trace_output_void ();
3195 #if (DEBUG & DEBUG_TRAP) == 0
3197 uint16 vec
= OP
[ 0 ] + TRAP_VECTOR_START
;
3200 SET_PSW ( PSW
& PSW_SM_BIT
);
3204 #else /* if debugging use trap to print registers */
3207 static int first_time
= 1 ;
3212 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "Trap # PC " );
3213 for ( i
= 0 ; i
< 16 ; i
++)
3214 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, " %sr%d" , ( i
> 9 ) ? "" : " " , i
);
3215 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, " a0 a1 f0 f1 c \n " );
3218 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "Trap %2d 0x%.4x:" , ( int ) OP
[ 0 ], ( int ) PC
);
3220 for ( i
= 0 ; i
< 16 ; i
++)
3221 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, " %.4x" , ( int ) GPR ( i
));
3223 for ( i
= 0 ; i
< 2 ; i
++)
3224 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, " %.2x%.8lx" ,
3225 (( int )( ACC ( i
) >> 32 ) & 0xff ),
3226 (( unsigned long ) ACC ( i
)) & 0xffffffff );
3228 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, " %d %d %d \n " ,
3229 PSW_F0
!= 0 , PSW_F1
!= 0 , PSW_C
!= 0 );
3230 (* d10v_callback
-> flush_stdout
) ( d10v_callback
);
3234 case 15 : /* new system call trap */
3235 /* Trap 15 is used for simulating low-level I/O */
3237 unsigned32 result
= 0 ;
3240 /* Registers passed to trap 0 */
3242 #define FUNC GPR (4) /* function number */
3243 #define PARM1 GPR (0) /* optional parm 1 */
3244 #define PARM2 GPR (1) /* optional parm 2 */
3245 #define PARM3 GPR (2) /* optional parm 3 */
3246 #define PARM4 GPR (3) /* optional parm 3 */
3248 /* Registers set by trap 0 */
3250 #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
3251 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3252 #define RETERR(X) SET_GPR (4, (X)) /* return error code */
3254 /* Turn a pointer in a register into a pointer into real memory. */
3256 #define MEMPTR(x) ((char *)(dmem_addr(x)))
3260 #if !defined(__GO32__) && !defined(_WIN32)
3261 case TARGET_SYS_fork
:
3262 trace_input ( "<fork>" , OP_VOID
, OP_VOID
, OP_VOID
);
3264 trace_output_16 ( result
);
3268 case TARGET_SYS_getpid
:
3269 trace_input ( "<getpid>" , OP_VOID
, OP_VOID
, OP_VOID
);
3271 trace_output_16 ( result
);
3274 case TARGET_SYS_kill
:
3275 trace_input ( "<kill>" , OP_R0
, OP_R1
, OP_VOID
);
3276 if ( PARM1
== getpid ())
3278 trace_output_void ();
3279 State
. exception
= PARM2
;
3287 case 1 : os_sig
= SIGHUP
; break ;
3290 case 2 : os_sig
= SIGINT
; break ;
3293 case 3 : os_sig
= SIGQUIT
; break ;
3296 case 4 : os_sig
= SIGILL
; break ;
3299 case 5 : os_sig
= SIGTRAP
; break ;
3302 case 6 : os_sig
= SIGABRT
; break ;
3303 #elif defined(SIGIOT)
3304 case 6 : os_sig
= SIGIOT
; break ;
3307 case 7 : os_sig
= SIGEMT
; break ;
3310 case 8 : os_sig
= SIGFPE
; break ;
3313 case 9 : os_sig
= SIGKILL
; break ;
3316 case 10 : os_sig
= SIGBUS
; break ;
3319 case 11 : os_sig
= SIGSEGV
; break ;
3322 case 12 : os_sig
= SIGSYS
; break ;
3325 case 13 : os_sig
= SIGPIPE
; break ;
3328 case 14 : os_sig
= SIGALRM
; break ;
3331 case 15 : os_sig
= SIGTERM
; break ;
3334 case 16 : os_sig
= SIGURG
; break ;
3337 case 17 : os_sig
= SIGSTOP
; break ;
3340 case 18 : os_sig
= SIGTSTP
; break ;
3343 case 19 : os_sig
= SIGCONT
; break ;
3346 case 20 : os_sig
= SIGCHLD
; break ;
3347 #elif defined(SIGCLD)
3348 case 20 : os_sig
= SIGCLD
; break ;
3351 case 21 : os_sig
= SIGTTIN
; break ;
3354 case 22 : os_sig
= SIGTTOU
; break ;
3357 case 23 : os_sig
= SIGIO
; break ;
3358 #elif defined (SIGPOLL)
3359 case 23 : os_sig
= SIGPOLL
; break ;
3362 case 24 : os_sig
= SIGXCPU
; break ;
3365 case 25 : os_sig
= SIGXFSZ
; break ;
3368 case 26 : os_sig
= SIGVTALRM
; break ;
3371 case 27 : os_sig
= SIGPROF
; break ;
3374 case 28 : os_sig
= SIGWINCH
; break ;
3377 case 29 : os_sig
= SIGLOST
; break ;
3380 case 30 : os_sig
= SIGUSR1
; break ;
3383 case 31 : os_sig
= SIGUSR2
; break ;
3389 trace_output_void ();
3390 (* d10v_callback
-> printf_filtered
) ( d10v_callback
, "Unknown signal %d \n " , PARM2
);
3391 (* d10v_callback
-> flush_stdout
) ( d10v_callback
);
3392 State
. exception
= SIGILL
;
3396 RETVAL ( kill ( PARM1
, PARM2
));
3397 trace_output_16 ( result
);
3402 case TARGET_SYS_execve
:
3403 trace_input ( "<execve>" , OP_R0
, OP_R1
, OP_R2
);
3404 RETVAL ( execve ( MEMPTR ( PARM1
), ( char **) MEMPTR ( PARM2
),
3405 ( char **) MEMPTR ( PARM3
)));
3406 trace_output_16 ( result
);
3409 #ifdef TARGET_SYS_execv
3410 case TARGET_SYS_execv
:
3411 trace_input ( "<execv>" , OP_R0
, OP_R1
, OP_VOID
);
3412 RETVAL ( execve ( MEMPTR ( PARM1
), ( char **) MEMPTR ( PARM2
), NULL
));
3413 trace_output_16 ( result
);
3417 case TARGET_SYS_pipe
:
3422 trace_input ( "<pipe>" , OP_R0
, OP_VOID
, OP_VOID
);
3424 RETVAL ( pipe ( host_fd
));
3425 SW ( buf
, host_fd
[ 0 ]);
3426 buf
+= sizeof ( uint16
);
3427 SW ( buf
, host_fd
[ 1 ]);
3428 trace_output_16 ( result
);
3433 #ifdef TARGET_SYS_wait
3434 case TARGET_SYS_wait
:
3437 trace_input ( "<wait>" , OP_R0
, OP_VOID
, OP_VOID
);
3438 RETVAL ( wait (& status
));
3441 trace_output_16 ( result
);
3447 case TARGET_SYS_getpid
:
3448 trace_input ( "<getpid>" , OP_VOID
, OP_VOID
, OP_VOID
);
3450 trace_output_16 ( result
);
3453 case TARGET_SYS_kill
:
3454 trace_input ( "<kill>" , OP_REG
, OP_REG
, OP_VOID
);
3455 trace_output_void ();
3456 State
. exception
= PARM2
;
3460 case TARGET_SYS_read
:
3461 trace_input ( "<read>" , OP_R0
, OP_R1
, OP_R2
);
3462 RETVAL ( d10v_callback
-> read ( d10v_callback
, PARM1
, MEMPTR ( PARM2
),
3464 trace_output_16 ( result
);
3467 case TARGET_SYS_write
:
3468 trace_input ( "<write>" , OP_R0
, OP_R1
, OP_R2
);
3470 RETVAL (( int ) d10v_callback
-> write_stdout ( d10v_callback
,
3471 MEMPTR ( PARM2
), PARM3
));
3473 RETVAL (( int ) d10v_callback
-> write ( d10v_callback
, PARM1
,
3474 MEMPTR ( PARM2
), PARM3
));
3475 trace_output_16 ( result
);
3478 case TARGET_SYS_lseek
:
3479 trace_input ( "<lseek>" , OP_R0
, OP_R1
, OP_R2
);
3480 RETVAL32 ( d10v_callback
-> lseek ( d10v_callback
, PARM1
,
3481 (((( unsigned long ) PARM2
) << 16 )
3482 || ( unsigned long ) PARM3
),
3484 trace_output_32 ( result
);
3487 case TARGET_SYS_close
:
3488 trace_input ( "<close>" , OP_R0
, OP_VOID
, OP_VOID
);
3489 RETVAL ( d10v_callback
-> close ( d10v_callback
, PARM1
));
3490 trace_output_16 ( result
);
3493 case TARGET_SYS_open
:
3494 trace_input ( "<open>" , OP_R0
, OP_R1
, OP_R2
);
3495 RETVAL ( d10v_callback
-> open ( d10v_callback
, MEMPTR ( PARM1
), PARM2
));
3496 trace_output_16 ( result
);
3499 case TARGET_SYS_exit
:
3500 trace_input ( "<exit>" , OP_R0
, OP_VOID
, OP_VOID
);
3501 State
. exception
= SIG_D10V_EXIT
;
3502 trace_output_void ();
3505 #ifdef TARGET_SYS_stat
3506 case TARGET_SYS_stat
:
3507 trace_input ( "<stat>" , OP_R0
, OP_R1
, OP_VOID
);
3508 /* stat system call */
3510 struct stat host_stat
;
3513 RETVAL ( stat ( MEMPTR ( PARM1
), & host_stat
));
3517 /* The hard-coded offsets and sizes were determined by using
3518 * the D10V compiler on a test program that used struct stat.
3520 SW ( buf
, host_stat
. st_dev
);
3521 SW ( buf
+ 2 , host_stat
. st_ino
);
3522 SW ( buf
+ 4 , host_stat
. st_mode
);
3523 SW ( buf
+ 6 , host_stat
. st_nlink
);
3524 SW ( buf
+ 8 , host_stat
. st_uid
);
3525 SW ( buf
+ 10 , host_stat
. st_gid
);
3526 SW ( buf
+ 12 , host_stat
. st_rdev
);
3527 SLW ( buf
+ 16 , host_stat
. st_size
);
3528 SLW ( buf
+ 20 , host_stat
. st_atime
);
3529 SLW ( buf
+ 28 , host_stat
. st_mtime
);
3530 SLW ( buf
+ 36 , host_stat
. st_ctime
);
3532 trace_output_16 ( result
);
3536 case TARGET_SYS_chown
:
3537 trace_input ( "<chown>" , OP_R0
, OP_R1
, OP_R2
);
3538 RETVAL ( chown ( MEMPTR ( PARM1
), PARM2
, PARM3
));
3539 trace_output_16 ( result
);
3542 case TARGET_SYS_chmod
:
3543 trace_input ( "<chmod>" , OP_R0
, OP_R1
, OP_R2
);
3544 RETVAL ( chmod ( MEMPTR ( PARM1
), PARM2
));
3545 trace_output_16 ( result
);
3549 #ifdef TARGET_SYS_utime
3550 case TARGET_SYS_utime
:
3551 trace_input ( "<utime>" , OP_R0
, OP_R1
, OP_R2
);
3552 /* Cast the second argument to void *, to avoid type mismatch
3553 if a prototype is present. */
3554 RETVAL ( utime ( MEMPTR ( PARM1
), ( void *) MEMPTR ( PARM2
)));
3555 trace_output_16 ( result
);
3561 #ifdef TARGET_SYS_time
3562 case TARGET_SYS_time
:
3563 trace_input ( "<time>" , OP_R0
, OP_R1
, OP_R2
);
3564 RETVAL32 ( time ( PARM1
? MEMPTR ( PARM1
) : NULL
));
3565 trace_output_32 ( result
);
3571 d10v_callback
-> error ( d10v_callback
, "Unknown syscall %d" , FUNC
);
3573 if (( uint16
) result
== ( uint16
) - 1 )
3574 RETERR ( d10v_callback
-> get_errno ( d10v_callback
));
3586 trace_input ( "tst0i" , OP_REG
, OP_CONSTANT16
, OP_VOID
);
3587 SET_PSW_F1 ( PSW_F0
);;
3588 SET_PSW_F0 (( GPR ( OP
[ 0 ]) & OP
[ 1 ]) ? 1 : 0 );
3589 trace_output_flag ();
3596 trace_input ( "tst1i" , OP_REG
, OP_CONSTANT16
, OP_VOID
);
3597 SET_PSW_F1 ( PSW_F0
);
3598 SET_PSW_F0 ((~( GPR ( OP
[ 0 ])) & OP
[ 1 ]) ? 1 : 0 );
3599 trace_output_flag ();
3606 trace_input ( "wait" , OP_VOID
, OP_VOID
, OP_VOID
);
3608 trace_output_void ();
3616 trace_input ( "xor" , OP_REG
, OP_REG
, OP_VOID
);
3617 tmp
= ( GPR ( OP
[ 0 ]) ^ GPR ( OP
[ 1 ]));
3618 SET_GPR ( OP
[ 0 ], tmp
);
3619 trace_output_16 ( tmp
);
3627 trace_input ( "xor3" , OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
3628 tmp
= ( GPR ( OP
[ 1 ]) ^ OP
[ 2 ]);
3629 SET_GPR ( OP
[ 0 ], tmp
);
3630 trace_output_16 ( tmp
);