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Enhance debug support
[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
1 #include <signal.h>
2 #include <errno.h>
3 #include <sys/types.h>
4 #include <sys/stat.h>
5 #include <unistd.h>
6
7 #include "d10v_sim.h"
8 #include "simops.h"
9 #include "sys/syscall.h"
10
11 enum op_types {
12 OP_VOID,
13 OP_REG,
14 OP_REG_OUTPUT,
15 OP_DREG,
16 OP_DREG_OUTPUT,
17 OP_ACCUM,
18 OP_ACCUM_OUTPUT,
19 OP_ACCUM_REVERSE,
20 OP_CR,
21 OP_CR_OUTPUT,
22 OP_CR_REVERSE,
23 OP_FLAG,
24 OP_CONSTANT16,
25 OP_CONSTANT3,
26 OP_CONSTANT4,
27 OP_MEMREF,
28 OP_MEMREF2,
29 OP_POSTDEC,
30 OP_POSTINC,
31 OP_PREDEC
32 };
33
34 #if (DEBUG & DEBUG_TRACE) != 0
35 static void trace_input PARAMS ((char *name,
36 enum op_types in1,
37 enum op_types in2,
38 enum op_types in3));
39
40 static void trace_output PARAMS ((enum op_types result));
41
42 #ifndef SIZE_INSTRUCTION
43 #define SIZE_INSTRUCTION 10
44 #endif
45
46 #ifndef SIZE_OPERANDS
47 #define SIZE_OPERANDS 24
48 #endif
49
50 #ifndef SIZE_VALUES
51 #define SIZE_VALUES 13
52 #endif
53
54 static void
55 trace_input (name, in1, in2, in3)
56 char *name;
57 enum op_types in1;
58 enum op_types in2;
59 enum op_types in3;
60 {
61 char *comma;
62 enum op_types in[3];
63 int i;
64 char buf[80];
65 char *p;
66 long tmp;
67 char *type;
68
69 switch (State.ins_type)
70 {
71 default:
72 case INS_UNKNOWN: type = " ?"; break;
73 case INS_LEFT: type = " L"; break;
74 case INS_RIGHT: type = " R"; break;
75 case INS_LEFT_PARALLEL: type = "*L"; break;
76 case INS_RIGHT_PARALLEL: type = "*R"; break;
77 case INS_LONG: type = " B"; break;
78 }
79
80 printf ("0x%.6x %s: %-*s", (unsigned)PC, type, SIZE_INSTRUCTION, name);
81
82 in[0] = in1;
83 in[1] = in2;
84 in[2] = in3;
85 comma = "";
86 p = buf;
87 for (i = 0; i < 3; i++)
88 {
89 switch (in[i])
90 {
91 case OP_VOID:
92 break;
93
94 case OP_REG:
95 case OP_REG_OUTPUT:
96 case OP_DREG:
97 case OP_DREG_OUTPUT:
98 sprintf (p, "%sr%d", comma, OP[i]);
99 p += strlen (p);
100 comma = ",";
101 break;
102
103 case OP_CR:
104 case OP_CR_OUTPUT:
105 case OP_CR_REVERSE:
106 sprintf (p, "%scr%d", comma, OP[i]);
107 p += strlen (p);
108 comma = ",";
109 break;
110
111 case OP_ACCUM:
112 case OP_ACCUM_OUTPUT:
113 case OP_ACCUM_REVERSE:
114 sprintf (p, "%sa%d", comma, OP[i]);
115 p += strlen (p);
116 comma = ",";
117 break;
118
119 case OP_CONSTANT16:
120 sprintf (p, "%s%d", comma, OP[i]);
121 p += strlen (p);
122 comma = ",";
123 break;
124
125 case OP_CONSTANT4:
126 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
127 p += strlen (p);
128 comma = ",";
129 break;
130
131 case OP_CONSTANT3:
132 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
133 p += strlen (p);
134 comma = ",";
135 break;
136
137 case OP_MEMREF:
138 sprintf (p, "%s@r%d", comma, OP[i]);
139 p += strlen (p);
140 comma = ",";
141 break;
142
143 case OP_MEMREF2:
144 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
145 p += strlen (p);
146 comma = ",";
147 break;
148
149 case OP_POSTINC:
150 sprintf (p, "%s@r%d+", comma, OP[i]);
151 p += strlen (p);
152 comma = ",";
153 break;
154
155 case OP_POSTDEC:
156 sprintf (p, "%s@r%d-", comma, OP[i]);
157 p += strlen (p);
158 comma = ",";
159 break;
160
161 case OP_PREDEC:
162 sprintf (p, "%s@-r%d", comma, OP[i]);
163 p += strlen (p);
164 comma = ",";
165 break;
166
167 case OP_FLAG:
168 if (OP[i] == 0)
169 sprintf (p, "%sf0", comma);
170
171 else if (OP[i] == 1)
172 sprintf (p, "%sf1", comma);
173
174 else
175 sprintf (p, "%scarry", comma);
176
177 p += strlen (p);
178 comma = ",";
179 break;
180 }
181 }
182
183 #if (DEBUG & DEBUG_VALUES) == 0
184 *p++ = '\n';
185 *p = '\0';
186 fputs (buf, stdout);
187
188 #else /* DEBUG_VALUES */
189 *p = '\0';
190 printf ("%-*s", SIZE_OPERANDS, buf);
191
192 p = buf;
193 for (i = 0; i < 3; i++)
194 {
195 buf[0] = '\0';
196 switch (in[i])
197 {
198 case OP_VOID:
199 printf ("%*s", SIZE_VALUES, "");
200 break;
201
202 case OP_REG_OUTPUT:
203 case OP_DREG_OUTPUT:
204 case OP_CR_OUTPUT:
205 case OP_ACCUM_OUTPUT:
206 printf ("%*s", SIZE_VALUES, "---");
207 break;
208
209 case OP_REG:
210 case OP_MEMREF:
211 case OP_POSTDEC:
212 case OP_POSTINC:
213 case OP_PREDEC:
214 printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)State.regs[OP[i]]);
215 break;
216
217 case OP_DREG:
218 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
219 printf ("%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
220 break;
221
222 case OP_CR:
223 case OP_CR_REVERSE:
224 printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)State.cregs[OP[i]]);
225 break;
226
227 case OP_ACCUM:
228 case OP_ACCUM_REVERSE:
229 printf ("%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
230 ((int)(State.a[OP[i]] >> 32) & 0xff),
231 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
232 break;
233
234 case OP_CONSTANT16:
235 printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)OP[i]);
236 break;
237
238 case OP_CONSTANT4:
239 printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)SEXT4(OP[i]));
240 break;
241
242 case OP_CONSTANT3:
243 printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)SEXT3(OP[i]));
244 break;
245
246 case OP_FLAG:
247 if (OP[i] == 0)
248 printf ("%*sF0 = %d", SIZE_VALUES-6, "", State.F0 != 0);
249
250 else if (OP[i] == 1)
251 printf ("%*sF1 = %d", SIZE_VALUES-6, "", State.F1 != 0);
252
253 else
254 printf ("%*sC = %d", SIZE_VALUES-5, "", State.C != 0);
255
256 break;
257
258 case OP_MEMREF2:
259 printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)OP[i]);
260 printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)State.regs[OP[++i]]);
261 break;
262 }
263 }
264 #endif
265 }
266
267 static void
268 trace_output (result)
269 enum op_types result;
270 {
271 #if (DEBUG & DEBUG_VALUES) != 0
272 long tmp;
273
274 switch (result)
275 {
276 default:
277 putchar ('\n');
278 break;
279
280 case OP_REG:
281 case OP_REG_OUTPUT:
282 printf (" :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", (uint16)State.regs[OP[0]],
283 State.F0 != 0, State.F1 != 0, State.C != 0);
284 break;
285
286 case OP_DREG:
287 case OP_DREG_OUTPUT:
288 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
289 printf (" :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
290 State.F0 != 0, State.F1 != 0, State.C != 0);
291 break;
292
293 case OP_CR:
294 case OP_CR_OUTPUT:
295 printf (" :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", (uint16)State.cregs[OP[0]],
296 State.F0 != 0, State.F1 != 0, State.C != 0);
297 break;
298
299 case OP_CR_REVERSE:
300 printf (" :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", (uint16)State.cregs[OP[1]],
301 State.F0 != 0, State.F1 != 0, State.C != 0);
302 break;
303
304 case OP_ACCUM:
305 case OP_ACCUM_OUTPUT:
306 printf (" :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
307 ((int)(State.a[OP[0]] >> 32) & 0xff),
308 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
309 State.F0 != 0, State.F1 != 0, State.C != 0);
310 break;
311
312 case OP_ACCUM_REVERSE:
313 printf (" :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
314 ((int)(State.a[OP[1]] >> 32) & 0xff),
315 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
316 State.F0 != 0, State.F1 != 0, State.C != 0);
317 break;
318
319 case OP_FLAG:
320 printf (" :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
321 State.F0 != 0, State.F1 != 0, State.C != 0);
322 break;
323 }
324
325 fflush (stdout);
326 #endif
327 }
328
329 #else
330 #define trace_input(NAME, IN1, IN2, IN3)
331 #define trace_output(RESULT)
332 #endif
333
334 /* abs */
335 void
336 OP_4607 ()
337 {
338 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
339 State.F1 = State.F0;
340 if ((int16)(State.regs[OP[0]]) < 0)
341 {
342 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
343 State.F0 = 1;
344 }
345 else
346 State.F0 = 0;
347 trace_output (OP_REG);
348 }
349
350 /* abs */
351 void
352 OP_5607 ()
353 {
354 int64 tmp;
355
356 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
357 State.F1 = State.F0;
358 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
359
360 if (State.a[OP[0]] < 0 )
361 {
362 tmp = -State.a[OP[0]];
363 if (State.ST)
364 {
365 if (tmp > MAX32)
366 State.a[OP[0]] = MAX32;
367 else if (tmp < MIN32)
368 State.a[OP[0]] = MIN32;
369 else
370 State.a[OP[0]] = tmp & MASK40;
371 }
372 else
373 State.a[OP[0]] = tmp & MASK40;
374 State.F0 = 1;
375 }
376 else
377 State.F0 = 0;
378 trace_output (OP_ACCUM);
379 }
380
381 /* add */
382 void
383 OP_200 ()
384 {
385 uint16 tmp = State.regs[OP[0]];
386 trace_input ("add", OP_REG, OP_REG, OP_VOID);
387 State.regs[OP[0]] += State.regs[OP[1]];
388 if ( tmp > State.regs[OP[0]])
389 State.C = 1;
390 else
391 State.C = 0;
392 trace_output (OP_REG);
393 }
394
395 /* add */
396 void
397 OP_1201 ()
398 {
399 int64 tmp;
400 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
401
402 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
403 if (State.ST)
404 {
405 if ( tmp > MAX32)
406 State.a[OP[0]] = MAX32;
407 else if ( tmp < MIN32)
408 State.a[OP[0]] = MIN32;
409 else
410 State.a[OP[0]] = tmp & MASK40;
411 }
412 else
413 State.a[OP[0]] = tmp & MASK40;
414 trace_output (OP_ACCUM);
415 }
416
417 /* add */
418 void
419 OP_1203 ()
420 {
421 int64 tmp;
422 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
423
424 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
425 if (State.ST)
426 {
427 if (tmp > MAX32)
428 State.a[OP[0]] = MAX32;
429 else if ( tmp < MIN32)
430 State.a[OP[0]] = MIN32;
431 else
432 State.a[OP[0]] = tmp & MASK40;
433 }
434 else
435 State.a[OP[0]] = tmp & MASK40;
436 trace_output (OP_ACCUM);
437 }
438
439 /* add2w */
440 void
441 OP_1200 ()
442 {
443 uint32 tmp;
444 uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
445 uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
446
447 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
448 tmp = tmp1 + tmp2;
449 if ( (tmp < tmp1) || (tmp < tmp2) )
450 State.C = 1;
451 else
452 State.C = 0;
453 State.regs[OP[0]] = tmp >> 16;
454 State.regs[OP[0]+1] = tmp & 0xFFFF;
455 trace_output (OP_DREG);
456 }
457
458 /* add3 */
459 void
460 OP_1000000 ()
461 {
462 uint16 tmp = State.regs[OP[0]];
463 State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
464
465 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
466 if ( tmp > State.regs[OP[0]])
467 State.C = 1;
468 else
469 State.C = 0;
470 trace_output (OP_REG);
471 }
472
473 /* addac3 */
474 void
475 OP_17000200 ()
476 {
477 int64 tmp;
478 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
479
480 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
481 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
482 State.regs[OP[0]+1] = tmp & 0xffff;
483 trace_output (OP_DREG);
484 }
485
486 /* addac3 */
487 void
488 OP_17000202 ()
489 {
490 int64 tmp;
491 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
492
493 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
494 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
495 State.regs[OP[0]+1] = tmp & 0xffff;
496 trace_output (OP_DREG);
497 }
498
499 /* addac3s */
500 void
501 OP_17001200 ()
502 {
503 int64 tmp;
504 State.F1 = State.F0;
505
506 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
507 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
508 if ( tmp > MAX32)
509 {
510 State.regs[OP[0]] = 0x7fff;
511 State.regs[OP[0]+1] = 0xffff;
512 State.F0 = 1;
513 }
514 else if (tmp < MIN32)
515 {
516 State.regs[OP[0]] = 0x8000;
517 State.regs[OP[0]+1] = 0;
518 State.F0 = 1;
519 }
520 else
521 {
522 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
523 State.regs[OP[0]+1] = tmp & 0xffff;
524 State.F0 = 0;
525 }
526 trace_output (OP_DREG);
527 }
528
529 /* addac3s */
530 void
531 OP_17001202 ()
532 {
533 int64 tmp;
534 State.F1 = State.F0;
535
536 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
537 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
538 if ( tmp > MAX32)
539 {
540 State.regs[OP[0]] = 0x7fff;
541 State.regs[OP[0]+1] = 0xffff;
542 State.F0 = 1;
543 }
544 else if (tmp < MIN32)
545 {
546 State.regs[OP[0]] = 0x8000;
547 State.regs[OP[0]+1] = 0;
548 State.F0 = 1;
549 }
550 else
551 {
552 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
553 State.regs[OP[0]+1] = tmp & 0xffff;
554 State.F0 = 0;
555 }
556 trace_output (OP_DREG);
557 }
558
559 /* addi */
560 void
561 OP_201 ()
562 {
563 if (OP[1] == 0)
564 OP[1] = 16;
565 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
566 State.regs[OP[0]] += OP[1];
567 trace_output (OP_REG);
568 }
569
570 /* and */
571 void
572 OP_C00 ()
573 {
574 trace_input ("and", OP_REG, OP_REG, OP_VOID);
575 State.regs[OP[0]] &= State.regs[OP[1]];
576 trace_output (OP_REG);
577 }
578
579 /* and3 */
580 void
581 OP_6000000 ()
582 {
583 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
584 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
585 trace_output (OP_REG);
586 }
587
588 /* bclri */
589 void
590 OP_C01 ()
591 {
592 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
593 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
594 trace_output (OP_REG);
595 }
596
597 /* bl.s */
598 void
599 OP_4900 ()
600 {
601 trace_input ("bl.s", OP_CONSTANT16, OP_VOID, OP_VOID);
602 State.regs[13] = PC+1;
603 PC += SEXT8 (OP[0]);
604 trace_output (OP_VOID);
605 }
606
607 /* bl.l */
608 void
609 OP_24800000 ()
610 {
611 trace_input ("bl.l", OP_CONSTANT16, OP_VOID, OP_VOID);
612 State.regs[13] = PC+1;
613 PC += OP[0];
614 trace_output (OP_VOID);
615 }
616
617 /* bnoti */
618 void
619 OP_A01 ()
620 {
621 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
622 State.regs[OP[0]] ^= 0x8000 >> OP[1];
623 trace_output (OP_REG);
624 }
625
626 /* bra.s */
627 void
628 OP_4800 ()
629 {
630 trace_input ("bra.s", OP_CONSTANT16, OP_VOID, OP_VOID);
631 PC += SEXT8 (OP[0]);
632 trace_output (OP_VOID);
633 }
634
635 /* bra.l */
636 void
637 OP_24000000 ()
638 {
639 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
640 PC += OP[0];
641 trace_output (OP_VOID);
642 }
643
644 /* brf0f.s */
645 void
646 OP_4A00 ()
647 {
648 trace_input ("brf0f.s", OP_CONSTANT16, OP_VOID, OP_VOID);
649 if (State.F0 == 0)
650 PC += SEXT8 (OP[0]);
651 trace_output (OP_FLAG);
652 }
653
654 /* brf0f.l */
655 void
656 OP_25000000 ()
657 {
658 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
659 if (State.F0 == 0)
660 PC += OP[0];
661 trace_output (OP_FLAG);
662 }
663
664 /* brf0t.s */
665 void
666 OP_4B00 ()
667 {
668 trace_input ("brf0t.s", OP_CONSTANT16, OP_VOID, OP_VOID);
669 if (State.F0)
670 PC += SEXT8 (OP[0]);
671 trace_output (OP_FLAG);
672 }
673
674 /* brf0t.l */
675 void
676 OP_25800000 ()
677 {
678 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
679 if (State.F0)
680 PC += OP[0];
681 trace_output (OP_FLAG);
682 }
683
684 /* bseti */
685 void
686 OP_801 ()
687 {
688 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
689 State.regs[OP[0]] |= 0x8000 >> OP[1];
690 trace_output (OP_REG);
691 }
692
693 /* btsti */
694 void
695 OP_E01 ()
696 {
697 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
698 State.F1 = State.F0;
699 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
700 trace_output (OP_FLAG);
701 }
702
703 /* clrac */
704 void
705 OP_5601 ()
706 {
707 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
708 State.a[OP[0]] = 0;
709 trace_output (OP_ACCUM);
710 }
711
712 /* cmp */
713 void
714 OP_600 ()
715 {
716 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
717 State.F1 = State.F0;
718 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
719 trace_output (OP_FLAG);
720 }
721
722 /* cmp */
723 void
724 OP_1603 ()
725 {
726 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
727 State.F1 = State.F0;
728 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
729 trace_output (OP_FLAG);
730 }
731
732 /* cmpeq */
733 void
734 OP_400 ()
735 {
736 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
737 State.F1 = State.F0;
738 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
739 trace_output (OP_FLAG);
740 }
741
742 /* cmpeq */
743 void
744 OP_1403 ()
745 {
746 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
747 State.F1 = State.F0;
748 State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
749 trace_output (OP_FLAG);
750 }
751
752 /* cmpeqi.s */
753 void
754 OP_401 ()
755 {
756 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT16, OP_VOID);
757 State.F1 = State.F0;
758 State.F0 = (State.regs[OP[0]] == SEXT4(OP[1])) ? 1 : 0;
759 trace_output (OP_FLAG);
760 }
761
762 /* cmpeqi.l */
763 void
764 OP_2000000 ()
765 {
766 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
767 State.F1 = State.F0;
768 State.F0 = (State.regs[OP[0]] == OP[1]) ? 1 : 0;
769 trace_output (OP_FLAG);
770 }
771
772 /* cmpi.s */
773 void
774 OP_601 ()
775 {
776 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
777 State.F1 = State.F0;
778 State.F0 = ((int16)(State.regs[OP[0]]) < SEXT4(OP[1])) ? 1 : 0;
779 trace_output (OP_FLAG);
780 }
781
782 /* cmpi.l */
783 void
784 OP_3000000 ()
785 {
786 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
787 State.F1 = State.F0;
788 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
789 trace_output (OP_FLAG);
790 }
791
792 /* cmpu */
793 void
794 OP_4600 ()
795 {
796 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
797 State.F1 = State.F0;
798 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
799 trace_output (OP_FLAG);
800 }
801
802 /* cmpui */
803 void
804 OP_23000000 ()
805 {
806 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
807 State.F1 = State.F0;
808 State.F0 = (State.regs[OP[0]] < OP[1]) ? 1 : 0;
809 trace_output (OP_FLAG);
810 }
811
812 /* cpfg */
813 void
814 OP_4E09 ()
815 {
816 uint8 *src, *dst;
817
818 trace_input ("cpfg", OP_FLAG, OP_VOID, OP_VOID);
819 if (OP[0] == 0)
820 dst = &State.F0;
821 else
822 dst = &State.F1;
823
824 if (OP[1] == 0)
825 src = &State.F0;
826 else if (OP[1] == 1)
827 src = &State.F1;
828 else
829 src = &State.C;
830
831 *dst = *src;
832 trace_output (OP_FLAG);
833 }
834
835 /* dbt */
836 void
837 OP_5F20 ()
838 {
839 printf("***** DBT ***** PC=%x\n",PC);
840 State.exception = SIGTRAP;
841 }
842
843 /* divs */
844 void
845 OP_14002800 ()
846 {
847 uint16 foo, tmp, tmpf;
848
849 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
850 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
851 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
852 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
853 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
854 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
855 trace_output (OP_DREG);
856 }
857
858 /* exef0f */
859 void
860 OP_4E04 ()
861 {
862 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
863 State.exe = (State.F0) ? 0 : 1;
864 trace_output (OP_FLAG);
865 }
866
867 /* exef0t */
868 void
869 OP_4E24 ()
870 {
871 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
872 State.exe = State.F0;
873 trace_output (OP_FLAG);
874 }
875
876 /* exef1f */
877 void
878 OP_4E40 ()
879 {
880 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
881 State.exe = (State.F1) ? 0 : 1;
882 trace_output (OP_FLAG);
883 }
884
885 /* exef1t */
886 void
887 OP_4E42 ()
888 {
889 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
890 State.exe = State.F1;
891 trace_output (OP_FLAG);
892 }
893
894 /* exefaf */
895 void
896 OP_4E00 ()
897 {
898 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
899 State.exe = (State.F0 | State.F1) ? 0 : 1;
900 trace_output (OP_FLAG);
901 }
902
903 /* exefat */
904 void
905 OP_4E02 ()
906 {
907 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
908 State.exe = (State.F0) ? 0 : (State.F1);
909 trace_output (OP_FLAG);
910 }
911
912 /* exetaf */
913 void
914 OP_4E20 ()
915 {
916 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
917 State.exe = (State.F1) ? 0 : (State.F0);
918 trace_output (OP_FLAG);
919 }
920
921 /* exetat */
922 void
923 OP_4E22 ()
924 {
925 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
926 State.exe = (State.F0) ? (State.F1) : 0;
927 trace_output (OP_FLAG);
928 }
929
930 /* exp */
931 void
932 OP_15002A00 ()
933 {
934 uint32 tmp, foo;
935 int i;
936
937 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
938 if (((int16)State.regs[OP[1]]) >= 0)
939 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
940 else
941 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
942
943 foo = 0x40000000;
944 for (i=1;i<17;i++)
945 {
946 if (tmp & foo)
947 {
948 State.regs[OP[0]] = i-1;
949 trace_output (OP_REG);
950 return;
951 }
952 foo >>= 1;
953 }
954 State.regs[OP[0]] = 16;
955 trace_output (OP_REG);
956 }
957
958 /* exp */
959 void
960 OP_15002A02 ()
961 {
962 int64 tmp, foo;
963 int i;
964
965 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
966 if (SEXT40(State.a[OP[1]]) >= 0)
967 tmp = State.a[OP[1]];
968 else
969 tmp = ~(State.a[OP[1]]);
970
971 foo = 0x4000000000LL;
972 for (i=1;i<25;i++)
973 {
974 if (tmp & foo)
975 {
976 State.regs[OP[0]] = i-9;
977 trace_output (OP_REG);
978 return;
979 }
980 foo >>= 1;
981 }
982 State.regs[OP[0]] = 16;
983 trace_output (OP_REG);
984 }
985
986 /* jl */
987 void
988 OP_4D00 ()
989 {
990 trace_input ("jl", OP_REG, OP_VOID, OP_VOID);
991 State.regs[13] = PC+1;
992 PC = State.regs[OP[0]];
993 trace_output (OP_VOID);
994 }
995
996 /* jmp */
997 void
998 OP_4C00 ()
999 {
1000 trace_input ("jmp", OP_REG, OP_VOID, OP_VOID);
1001 PC = State.regs[OP[0]];
1002 trace_output (OP_VOID);
1003 }
1004
1005 /* ld */
1006 void
1007 OP_30000000 ()
1008 {
1009 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1010 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1011 trace_output (OP_REG);
1012 }
1013
1014 /* ld */
1015 void
1016 OP_6401 ()
1017 {
1018 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1019 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1020 INC_ADDR(State.regs[OP[1]],-2);
1021 trace_output (OP_REG);
1022 }
1023
1024 /* ld */
1025 void
1026 OP_6001 ()
1027 {
1028 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1029 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1030 INC_ADDR(State.regs[OP[1]],2);
1031 trace_output (OP_REG);
1032 }
1033
1034 /* ld */
1035 void
1036 OP_6000 ()
1037 {
1038 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1039 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1040 trace_output (OP_REG);
1041 }
1042
1043 /* ld2w */
1044 void
1045 OP_31000000 ()
1046 {
1047 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1048 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1049 State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2);
1050 trace_output (OP_DREG);
1051 }
1052
1053 /* ld2w */
1054 void
1055 OP_6601 ()
1056 {
1057 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1058 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1059 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1060 INC_ADDR(State.regs[OP[1]],-4);
1061 trace_output (OP_DREG);
1062 }
1063
1064 /* ld2w */
1065 void
1066 OP_6201 ()
1067 {
1068 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1069 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1070 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1071 INC_ADDR(State.regs[OP[1]],4);
1072 trace_output (OP_REG);
1073 }
1074
1075 /* ld2w */
1076 void
1077 OP_6200 ()
1078 {
1079 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1080 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1081 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1082 trace_output (OP_REG);
1083 }
1084
1085 /* ldb */
1086 void
1087 OP_38000000 ()
1088 {
1089 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1090 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1091 SEXT8 (State.regs[OP[0]]);
1092 trace_output (OP_REG);
1093 }
1094
1095 /* ldb */
1096 void
1097 OP_7000 ()
1098 {
1099 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1100 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1101 SEXT8 (State.regs[OP[0]]);
1102 trace_output (OP_REG);
1103 }
1104
1105 /* ldi.s */
1106 void
1107 OP_4001 ()
1108 {
1109 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1110 State.regs[OP[0]] = SEXT4(OP[1]);
1111 trace_output (OP_REG);
1112 }
1113
1114 /* ldi.l */
1115 void
1116 OP_20000000 ()
1117 {
1118 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1119 State.regs[OP[0]] = OP[1];
1120 trace_output (OP_REG);
1121 }
1122
1123 /* ldub */
1124 void
1125 OP_39000000 ()
1126 {
1127 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1128 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1129 trace_output (OP_REG);
1130 }
1131
1132 /* ldub */
1133 void
1134 OP_7200 ()
1135 {
1136 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1137 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1138 trace_output (OP_REG);
1139 }
1140
1141 /* mac */
1142 void
1143 OP_2A00 ()
1144 {
1145 int64 tmp;
1146
1147 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1148 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1149
1150 if (State.FX)
1151 tmp = SEXT40( (tmp << 1) & MASK40);
1152
1153 if (State.ST && tmp > MAX32)
1154 tmp = MAX32;
1155
1156 tmp += SEXT40(State.a[OP[0]]);
1157 if (State.ST)
1158 {
1159 if (tmp > MAX32)
1160 State.a[OP[0]] = MAX32;
1161 else if (tmp < MIN32)
1162 State.a[OP[0]] = MIN32;
1163 else
1164 State.a[OP[0]] = tmp & MASK40;
1165 }
1166 else
1167 State.a[OP[0]] = tmp & MASK40;
1168 trace_output (OP_ACCUM);
1169 }
1170
1171 /* macsu */
1172 void
1173 OP_1A00 ()
1174 {
1175 int64 tmp;
1176
1177 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1178 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1179 if (State.FX)
1180 tmp = SEXT40( (tmp << 1) & MASK40);
1181
1182 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1183 trace_output (OP_ACCUM);
1184 }
1185
1186 /* macu */
1187 void
1188 OP_3A00 ()
1189 {
1190 int64 tmp;
1191
1192 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1193 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1194 if (State.FX)
1195 tmp = SEXT40( (tmp << 1) & MASK40);
1196 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1197 trace_output (OP_ACCUM);
1198 }
1199
1200 /* max */
1201 void
1202 OP_2600 ()
1203 {
1204 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1205 State.F1 = State.F0;
1206 if (State.regs[OP[1]] > State.regs[OP[0]])
1207 {
1208 State.regs[OP[0]] = State.regs[OP[1]];
1209 State.F0 = 1;
1210 }
1211 else
1212 State.F0 = 0;
1213 trace_output (OP_REG);
1214 }
1215
1216 /* max */
1217 void
1218 OP_3600 ()
1219 {
1220 int64 tmp;
1221
1222 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1223 State.F1 = State.F0;
1224 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1225 if (tmp > SEXT40(State.a[OP[0]]))
1226 {
1227 State.a[OP[0]] = tmp & MASK40;
1228 State.F0 = 1;
1229 }
1230 else
1231 State.F0 = 0;
1232 trace_output (OP_ACCUM);
1233 }
1234
1235 /* max */
1236 void
1237 OP_3602 ()
1238 {
1239 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1240 State.F1 = State.F0;
1241 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1242 {
1243 State.a[OP[0]] = State.a[OP[1]];
1244 State.F0 = 1;
1245 }
1246 else
1247 State.F0 = 0;
1248 trace_output (OP_ACCUM);
1249 }
1250
1251
1252 /* min */
1253 void
1254 OP_2601 ()
1255 {
1256 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1257 State.F1 = State.F0;
1258 if (State.regs[OP[1]] < State.regs[OP[0]])
1259 {
1260 State.regs[OP[0]] = State.regs[OP[1]];
1261 State.F0 = 1;
1262 }
1263 else
1264 State.F0 = 0;
1265 trace_output (OP_REG);
1266 }
1267
1268 /* min */
1269 void
1270 OP_3601 ()
1271 {
1272 int64 tmp;
1273
1274 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1275 State.F1 = State.F0;
1276 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1277 if (tmp < SEXT40(State.a[OP[0]]))
1278 {
1279 State.a[OP[0]] = tmp & MASK40;
1280 State.F0 = 1;
1281 }
1282 else
1283 State.F0 = 0;
1284 trace_output (OP_ACCUM);
1285 }
1286
1287 /* min */
1288 void
1289 OP_3603 ()
1290 {
1291 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1292 State.F1 = State.F0;
1293 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1294 {
1295 State.a[OP[0]] = State.a[OP[1]];
1296 State.F0 = 1;
1297 }
1298 else
1299 State.F0 = 0;
1300 trace_output (OP_ACCUM);
1301 }
1302
1303 /* msb */
1304 void
1305 OP_2800 ()
1306 {
1307 int64 tmp;
1308
1309 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1310 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1311
1312 if (State.FX)
1313 tmp = SEXT40 ((tmp << 1) & MASK40);
1314
1315 if (State.ST && tmp > MAX32)
1316 tmp = MAX32;
1317
1318 tmp = SEXT40(State.a[OP[0]]) - tmp;
1319 if (State.ST)
1320 {
1321 if (tmp > MAX32)
1322 State.a[OP[0]] = MAX32;
1323 else if (tmp < MIN32)
1324 State.a[OP[0]] = MIN32;
1325 else
1326 State.a[OP[0]] = tmp & MASK40;
1327 }
1328 else
1329 State.a[OP[0]] = tmp & MASK40;
1330 trace_output (OP_ACCUM);
1331 }
1332
1333 /* msbsu */
1334 void
1335 OP_1800 ()
1336 {
1337 int64 tmp;
1338
1339 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1340 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1341 if (State.FX)
1342 tmp = SEXT40( (tmp << 1) & MASK40);
1343
1344 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1345 trace_output (OP_ACCUM);
1346 }
1347
1348 /* msbu */
1349 void
1350 OP_3800 ()
1351 {
1352 int64 tmp;
1353
1354 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1355 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1356 if (State.FX)
1357 tmp = SEXT40( (tmp << 1) & MASK40);
1358
1359 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1360 trace_output (OP_ACCUM);
1361 }
1362
1363 /* mul */
1364 void
1365 OP_2E00 ()
1366 {
1367 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1368 State.regs[OP[0]] *= State.regs[OP[1]];
1369 trace_output (OP_REG);
1370 }
1371
1372 /* mulx */
1373 void
1374 OP_2C00 ()
1375 {
1376 int64 tmp;
1377
1378 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1379 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1380
1381 if (State.FX)
1382 tmp = SEXT40 ((tmp << 1) & MASK40);
1383
1384 if (State.ST && tmp > MAX32)
1385 State.a[OP[0]] = MAX32;
1386 else
1387 State.a[OP[0]] = tmp & MASK40;
1388 trace_output (OP_ACCUM);
1389 }
1390
1391 /* mulxsu */
1392 void
1393 OP_1C00 ()
1394 {
1395 int64 tmp;
1396
1397 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1398 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1399
1400 if (State.FX)
1401 tmp <<= 1;
1402
1403 State.a[OP[0]] = tmp & MASK40;
1404 trace_output (OP_ACCUM);
1405 }
1406
1407 /* mulxu */
1408 void
1409 OP_3C00 ()
1410 {
1411 int64 tmp;
1412
1413 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1414 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1415
1416 if (State.FX)
1417 tmp <<= 1;
1418
1419 State.a[OP[0]] = tmp & MASK40;
1420 trace_output (OP_ACCUM);
1421 }
1422
1423 /* mv */
1424 void
1425 OP_4000 ()
1426 {
1427 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1428 State.regs[OP[0]] = State.regs[OP[1]];
1429 trace_output (OP_REG);
1430 }
1431
1432 /* mv2w */
1433 void
1434 OP_5000 ()
1435 {
1436 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1437 State.regs[OP[0]] = State.regs[OP[1]];
1438 State.regs[OP[0]+1] = State.regs[OP[1]+1];
1439 trace_output (OP_DREG);
1440 }
1441
1442 /* mv2wfac */
1443 void
1444 OP_3E00 ()
1445 {
1446 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1447 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1448 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
1449 trace_output (OP_DREG);
1450 }
1451
1452 /* mv2wtac */
1453 void
1454 OP_3E01 ()
1455 {
1456 trace_input ("mv2wtac", OP_ACCUM_OUTPUT, OP_DREG, OP_VOID);
1457 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
1458 trace_output (OP_ACCUM);
1459 }
1460
1461 /* mvac */
1462 void
1463 OP_3E03 ()
1464 {
1465 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1466 State.a[OP[0]] = State.a[OP[1]];
1467 trace_output (OP_ACCUM);
1468 }
1469
1470 /* mvb */
1471 void
1472 OP_5400 ()
1473 {
1474 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1475 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
1476 trace_output (OP_REG);
1477 }
1478
1479 /* mvf0f */
1480 void
1481 OP_4400 ()
1482 {
1483 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1484 if (State.F0 == 0)
1485 State.regs[OP[0]] = State.regs[OP[1]];
1486 trace_output (OP_REG);
1487 }
1488
1489 /* mvf0t */
1490 void
1491 OP_4401 ()
1492 {
1493 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1494 if (State.F0)
1495 State.regs[OP[0]] = State.regs[OP[1]];
1496 trace_output (OP_REG);
1497 }
1498
1499 /* mvfacg */
1500 void
1501 OP_1E04 ()
1502 {
1503 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1504 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
1505 trace_output (OP_ACCUM);
1506 }
1507
1508 /* mvfachi */
1509 void
1510 OP_1E00 ()
1511 {
1512 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1513 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1514 trace_output (OP_REG);
1515 }
1516
1517 /* mvfaclo */
1518 void
1519 OP_1E02 ()
1520 {
1521 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1522 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
1523 trace_output (OP_REG);
1524 }
1525
1526 /* mvfc */
1527 void
1528 OP_5200 ()
1529 {
1530 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1531 if (OP[1] == 0)
1532 {
1533 /* PSW is treated specially */
1534 PSW = 0;
1535 if (State.SM) PSW |= 0x8000;
1536 if (State.EA) PSW |= 0x2000;
1537 if (State.DB) PSW |= 0x1000;
1538 if (State.IE) PSW |= 0x400;
1539 if (State.RP) PSW |= 0x200;
1540 if (State.MD) PSW |= 0x100;
1541 if (State.FX) PSW |= 0x80;
1542 if (State.ST) PSW |= 0x40;
1543 if (State.F0) PSW |= 8;
1544 if (State.F1) PSW |= 4;
1545 if (State.C) PSW |= 1;
1546 }
1547 State.regs[OP[0]] = State.cregs[OP[1]];
1548 trace_output (OP_REG);
1549 }
1550
1551 /* mvtacg */
1552 void
1553 OP_1E41 ()
1554 {
1555 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1556 State.a[OP[1]] &= MASK32;
1557 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
1558 trace_output (OP_ACCUM_REVERSE);
1559 }
1560
1561 /* mvtachi */
1562 void
1563 OP_1E01 ()
1564 {
1565 uint16 tmp;
1566
1567 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1568 tmp = State.a[OP[1]] & 0xffff;
1569 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
1570 trace_output (OP_ACCUM_REVERSE);
1571 }
1572
1573 /* mvtaclo */
1574 void
1575 OP_1E21 ()
1576 {
1577 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1578 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
1579 trace_output (OP_ACCUM_REVERSE);
1580 }
1581
1582 /* mvtc */
1583 void
1584 OP_5600 ()
1585 {
1586 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1587 State.cregs[OP[1]] = State.regs[OP[0]];
1588 if (OP[1] == 0)
1589 {
1590 /* PSW is treated specially */
1591 State.SM = (PSW & 0x8000) ? 1 : 0;
1592 State.EA = (PSW & 0x2000) ? 1 : 0;
1593 State.DB = (PSW & 0x1000) ? 1 : 0;
1594 State.IE = (PSW & 0x400) ? 1 : 0;
1595 State.RP = (PSW & 0x200) ? 1 : 0;
1596 State.MD = (PSW & 0x100) ? 1 : 0;
1597 State.FX = (PSW & 0x80) ? 1 : 0;
1598 State.ST = (PSW & 0x40) ? 1 : 0;
1599 State.F0 = (PSW & 8) ? 1 : 0;
1600 State.F1 = (PSW & 4) ? 1 : 0;
1601 State.C = PSW & 1;
1602 if (State.ST && !State.FX)
1603 {
1604 fprintf (stderr,"ERROR at PC 0x%x: ST can only be set when FX is set.\n",PC<<2);
1605 State.exception = SIGILL;
1606 }
1607 }
1608 trace_output (OP_CR_REVERSE);
1609 }
1610
1611 /* mvub */
1612 void
1613 OP_5401 ()
1614 {
1615 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1616 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
1617 trace_output (OP_REG);
1618 }
1619
1620 /* neg */
1621 void
1622 OP_4605 ()
1623 {
1624 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
1625 State.regs[OP[0]] = 0 - State.regs[OP[0]];
1626 trace_output (OP_REG);
1627 }
1628
1629 /* neg */
1630 void
1631 OP_5605 ()
1632 {
1633 int64 tmp;
1634
1635 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
1636 tmp = -SEXT40(State.a[OP[0]]);
1637 if (State.ST)
1638 {
1639 if ( tmp > MAX32)
1640 State.a[OP[0]] = MAX32;
1641 else if (tmp < MIN32)
1642 State.a[OP[0]] = MIN32;
1643 else
1644 State.a[OP[0]] = tmp & MASK40;
1645 }
1646 else
1647 State.a[OP[0]] = tmp & MASK40;
1648 trace_output (OP_ACCUM);
1649 }
1650
1651
1652 /* nop */
1653 void
1654 OP_5E00 ()
1655 {
1656 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1657 trace_output (OP_VOID);
1658 }
1659
1660 /* not */
1661 void
1662 OP_4603 ()
1663 {
1664 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
1665 State.regs[OP[0]] = ~(State.regs[OP[0]]);
1666 trace_output (OP_REG);
1667 }
1668
1669 /* or */
1670 void
1671 OP_800 ()
1672 {
1673 trace_input ("or", OP_REG, OP_REG, OP_VOID);
1674 State.regs[OP[0]] |= State.regs[OP[1]];
1675 trace_output (OP_REG);
1676 }
1677
1678 /* or3 */
1679 void
1680 OP_4000000 ()
1681 {
1682 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
1683 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
1684 trace_output (OP_REG);
1685 }
1686
1687 /* rac */
1688 void
1689 OP_5201 ()
1690 {
1691 int64 tmp;
1692 int shift = SEXT3 (OP[2]);
1693
1694 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1695 if (OP[1] != 0)
1696 {
1697 fprintf (stderr,"ERROR at PC 0x%x: instruction only valid for A0\n",PC<<2);
1698 State.exception = SIGILL;
1699 }
1700
1701 State.F1 = State.F0;
1702 if (shift >=0)
1703 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1704 else
1705 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
1706 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
1707 if (tmp > MAX32)
1708 {
1709 State.regs[OP[0]] = 0x7fff;
1710 State.regs[OP[0]+1] = 0xffff;
1711 State.F0 = 1;
1712 }
1713 else if (tmp < MIN32)
1714 {
1715 State.regs[OP[0]] = 0x8000;
1716 State.regs[OP[0]+1] = 0;
1717 State.F0 = 1;
1718 }
1719 else
1720 {
1721 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1722 State.regs[OP[0]+1] = tmp & 0xffff;
1723 State.F0 = 0;
1724 }
1725 trace_output (OP_DREG);
1726 }
1727
1728 /* rachi */
1729 void
1730 OP_4201 ()
1731 {
1732 int64 tmp;
1733 int shift = SEXT3 (OP[2]);
1734
1735 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1736 State.F1 = State.F0;
1737 if (shift >=0)
1738 tmp = SEXT44 (State.a[1]) << shift;
1739 else
1740 tmp = SEXT44 (State.a[1]) >> -shift;
1741 tmp += 0x8000;
1742
1743 if (tmp > MAX32)
1744 {
1745 State.regs[OP[0]] = 0x7fff;
1746 State.F0 = 1;
1747 }
1748 else if (tmp < 0xfff80000000LL)
1749 {
1750 State.regs[OP[0]] = 0x8000;
1751 State.F0 = 1;
1752 }
1753 else
1754 {
1755 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1756 State.F0 = 0;
1757 }
1758 trace_output (OP_REG);
1759 }
1760
1761 /* rep */
1762 void
1763 OP_27000000 ()
1764 {
1765 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
1766 RPT_S = PC + 1;
1767 RPT_E = PC + OP[1];
1768 RPT_C = State.regs[OP[0]];
1769 State.RP = 1;
1770 if (RPT_C == 0)
1771 {
1772 fprintf (stderr, "ERROR: rep with count=0 is illegal.\n");
1773 State.exception = SIGILL;
1774 }
1775 if (OP[1] < 4)
1776 {
1777 fprintf (stderr, "ERROR: rep must include at least 4 instructions.\n");
1778 State.exception = SIGILL;
1779 }
1780 trace_output (OP_VOID);
1781 }
1782
1783 /* repi */
1784 void
1785 OP_2F000000 ()
1786 {
1787 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
1788 RPT_S = PC + 1;
1789 RPT_E = PC + OP[1];
1790 RPT_C = OP[0];
1791 State.RP = 1;
1792 if (RPT_C == 0)
1793 {
1794 fprintf (stderr, "ERROR: repi with count=0 is illegal.\n");
1795 State.exception = SIGILL;
1796 }
1797 if (OP[1] < 4)
1798 {
1799 fprintf (stderr, "ERROR: repi must include at least 4 instructions.\n");
1800 State.exception = SIGILL;
1801 }
1802 trace_output (OP_VOID);
1803 }
1804
1805 /* rtd */
1806 void
1807 OP_5F60 ()
1808 {
1809 fprintf(stderr, "ERROR: rtd - NOT IMPLEMENTED\n");
1810 State.exception = SIGILL;
1811 }
1812
1813 /* rte */
1814 void
1815 OP_5F40 ()
1816 {
1817 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
1818 PC = BPC;
1819 PSW = BPSW;
1820 trace_output (OP_VOID);
1821 }
1822
1823 /* sadd */
1824 void
1825 OP_1223 ()
1826 {
1827 int64 tmp;
1828
1829 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
1830 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
1831 if (State.ST)
1832 {
1833 if (tmp > MAX32)
1834 State.a[OP[0]] = MAX32;
1835 else if (tmp < MIN32)
1836 State.a[OP[0]] = MIN32;
1837 else
1838 State.a[OP[0]] = tmp & MASK40;
1839 }
1840 else
1841 State.a[OP[0]] = tmp & MASK40;
1842 trace_output (OP_ACCUM);
1843 }
1844
1845 /* setf0f */
1846 void
1847 OP_4611 ()
1848 {
1849 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
1850 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
1851 trace_output (OP_REG);
1852 }
1853
1854 /* setf0t */
1855 void
1856 OP_4613 ()
1857 {
1858 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
1859 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
1860 trace_output (OP_REG);
1861 }
1862
1863 /* sleep */
1864 void
1865 OP_5FC0 ()
1866 {
1867 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
1868 State.IE = 1;
1869 trace_output (OP_VOID);
1870 }
1871
1872 /* sll */
1873 void
1874 OP_2200 ()
1875 {
1876 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
1877 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
1878 trace_output (OP_REG);
1879 }
1880
1881 /* sll */
1882 void
1883 OP_3200 ()
1884 {
1885 int64 tmp;
1886 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
1887 if (State.regs[OP[1]] & 31 <= 16)
1888 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
1889
1890 if (State.ST)
1891 {
1892 if (tmp > MAX32)
1893 State.a[OP[0]] = MAX32;
1894 else if (tmp < 0xffffff80000000LL)
1895 State.a[OP[0]] = MIN32;
1896 else
1897 State.a[OP[0]] = tmp & MASK40;
1898 }
1899 else
1900 State.a[OP[0]] = tmp & MASK40;
1901 trace_output (OP_ACCUM);
1902 }
1903
1904 /* slli */
1905 void
1906 OP_2201 ()
1907 {
1908 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
1909 State.regs[OP[0]] <<= OP[1];
1910 trace_output (OP_REG);
1911 }
1912
1913 /* slli */
1914 void
1915 OP_3201 ()
1916 {
1917 int64 tmp;
1918
1919 if (OP[1] == 0)
1920 OP[1] = 16;
1921
1922 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
1923 tmp = SEXT40(State.a[OP[0]]) << OP[1];
1924
1925 if (State.ST)
1926 {
1927 if (tmp > MAX32)
1928 State.a[OP[0]] = MAX32;
1929 else if (tmp < 0xffffff80000000LL)
1930 State.a[OP[0]] = MIN32;
1931 else
1932 State.a[OP[0]] = tmp & MASK40;
1933 }
1934 else
1935 State.a[OP[0]] = tmp & MASK40;
1936 trace_output (OP_ACCUM);
1937 }
1938
1939 /* slx */
1940 void
1941 OP_460B ()
1942 {
1943 uint16 tmp;
1944
1945 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
1946 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
1947 trace_output (OP_REG);
1948 }
1949
1950 /* sra */
1951 void
1952 OP_2400 ()
1953 {
1954 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
1955 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
1956 trace_output (OP_REG);
1957 }
1958
1959 /* sra */
1960 void
1961 OP_3400 ()
1962 {
1963 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
1964 if (State.regs[OP[1]] & 31 <= 16)
1965 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
1966 trace_output (OP_ACCUM);
1967 }
1968
1969 /* srai */
1970 void
1971 OP_2401 ()
1972 {
1973 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
1974 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
1975 trace_output (OP_REG);
1976 }
1977
1978 /* srai */
1979 void
1980 OP_3401 ()
1981 {
1982 if (OP[1] == 0)
1983 OP[1] = 16;
1984
1985 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
1986 State.a[OP[0]] >>= OP[1];
1987 trace_output (OP_ACCUM);
1988 }
1989
1990 /* srl */
1991 void
1992 OP_2000 ()
1993 {
1994 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
1995 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
1996 trace_output (OP_REG);
1997 }
1998
1999 /* srl */
2000 void
2001 OP_3000 ()
2002 {
2003 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2004 if (State.regs[OP[1]] & 31 <= 16)
2005 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
2006 trace_output (OP_ACCUM);
2007 }
2008
2009 /* srli */
2010 void
2011 OP_2001 ()
2012 {
2013 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2014 State.regs[OP[0]] >>= OP[1];
2015 trace_output (OP_REG);
2016 }
2017
2018 /* srli */
2019 void
2020 OP_3001 ()
2021 {
2022 if (OP[1] == 0)
2023 OP[1] = 16;
2024
2025 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2026 State.a[OP[0]] >>= OP[1];
2027 trace_output (OP_ACCUM);
2028 }
2029
2030 /* srx */
2031 void
2032 OP_4609 ()
2033 {
2034 uint16 tmp;
2035
2036 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2037 tmp = State.F0 << 15;
2038 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
2039 trace_output (OP_REG);
2040 }
2041
2042 /* st */
2043 void
2044 OP_34000000 ()
2045 {
2046 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2047 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
2048 trace_output (OP_VOID);
2049 }
2050
2051 /* st */
2052 void
2053 OP_6800 ()
2054 {
2055 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2056 SW (State.regs[OP[1]], State.regs[OP[0]]);
2057 trace_output (OP_VOID);
2058 }
2059
2060 /* st */
2061 void
2062 OP_6C1F ()
2063 {
2064 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2065 if ( OP[1] != 15 )
2066 {
2067 fprintf (stderr,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2068 State.exception = SIGILL;
2069 return;
2070 }
2071 State.regs[OP[1]] -= 2;
2072 SW (State.regs[OP[1]], State.regs[OP[0]]);
2073 trace_output (OP_VOID);
2074 }
2075
2076 /* st */
2077 void
2078 OP_6801 ()
2079 {
2080 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2081 SW (State.regs[OP[1]], State.regs[OP[0]]);
2082 INC_ADDR (State.regs[OP[1]],2);
2083 trace_output (OP_VOID);
2084 }
2085
2086 /* st */
2087 void
2088 OP_6C01 ()
2089 {
2090 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2091 SW (State.regs[OP[1]], State.regs[OP[0]]);
2092 INC_ADDR (State.regs[OP[1]],-2);
2093 trace_output (OP_VOID);
2094 }
2095
2096 /* st2w */
2097 void
2098 OP_35000000 ()
2099 {
2100 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2101 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2102 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
2103 trace_output (OP_VOID);
2104 }
2105
2106 /* st2w */
2107 void
2108 OP_6A00 ()
2109 {
2110 trace_input ("st2w", OP_REG, OP_MEMREF, OP_VOID);
2111 SW (State.regs[OP[1]], State.regs[OP[0]]);
2112 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2113 trace_output (OP_VOID);
2114 }
2115
2116 /* st2w */
2117 void
2118 OP_6E1F ()
2119 {
2120 trace_input ("st2w", OP_REG, OP_PREDEC, OP_VOID);
2121 if ( OP[1] != 15 )
2122 {
2123 fprintf (stderr,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2124 State.exception = SIGILL;
2125 return;
2126 }
2127 State.regs[OP[1]] -= 4;
2128 SW (State.regs[OP[1]], State.regs[OP[0]]);
2129 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2130 trace_output (OP_VOID);
2131 }
2132
2133 /* st2w */
2134 void
2135 OP_6A01 ()
2136 {
2137 trace_input ("st2w", OP_REG, OP_POSTDEC, OP_VOID);
2138 SW (State.regs[OP[1]], State.regs[OP[0]]);
2139 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2140 INC_ADDR (State.regs[OP[1]],4);
2141 trace_output (OP_VOID);
2142 }
2143
2144 /* st2w */
2145 void
2146 OP_6E01 ()
2147 {
2148 trace_input ("st2w", OP_REG, OP_POSTINC, OP_VOID);
2149 SW (State.regs[OP[1]], State.regs[OP[0]]);
2150 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2151 INC_ADDR (State.regs[OP[1]],-4);
2152 trace_output (OP_VOID);
2153 }
2154
2155 /* stb */
2156 void
2157 OP_3C000000 ()
2158 {
2159 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2160 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2161 trace_output (OP_VOID);
2162 }
2163
2164 /* stb */
2165 void
2166 OP_7800 ()
2167 {
2168 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2169 SB (State.regs[OP[1]], State.regs[OP[0]]);
2170 trace_output (OP_VOID);
2171 }
2172
2173 /* stop */
2174 void
2175 OP_5FE0 ()
2176 {
2177 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2178 State.exception = SIGQUIT;
2179 trace_output (OP_VOID);
2180 }
2181
2182 /* sub */
2183 void
2184 OP_0 ()
2185 {
2186 int32 tmp;
2187
2188 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2189 tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
2190 State.C = (tmp & 0xffff0000) ? 1 : 0;
2191 State.regs[OP[0]] = tmp & 0xffff;
2192 trace_output (OP_REG);
2193 }
2194
2195 /* sub */
2196 void
2197 OP_1001 ()
2198 {
2199 int64 tmp;
2200
2201 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2202 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2203 if (State.ST)
2204 {
2205 if ( tmp > MAX32)
2206 State.a[OP[0]] = MAX32;
2207 else if ( tmp < MIN32)
2208 State.a[OP[0]] = MIN32;
2209 else
2210 State.a[OP[0]] = tmp & MASK40;
2211 }
2212 else
2213 State.a[OP[0]] = tmp & MASK40;
2214
2215 trace_output (OP_ACCUM);
2216 }
2217
2218 /* sub */
2219
2220 void
2221 OP_1003 ()
2222 {
2223 int64 tmp;
2224
2225 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2226 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2227 if (State.ST)
2228 {
2229 if (tmp > MAX32)
2230 State.a[OP[0]] = MAX32;
2231 else if ( tmp < MIN32)
2232 State.a[OP[0]] = MIN32;
2233 else
2234 State.a[OP[0]] = tmp & MASK40;
2235 }
2236 else
2237 State.a[OP[0]] = tmp & MASK40;
2238
2239 trace_output (OP_ACCUM);
2240 }
2241
2242 /* sub2w */
2243 void
2244 OP_1000 ()
2245 {
2246 int64 tmp;
2247 int32 a,b;
2248
2249 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2250 a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2251 b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2252 tmp = a-b;
2253 State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;
2254 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2255 State.regs[OP[0]+1] = tmp & 0xffff;
2256 trace_output (OP_DREG);
2257 }
2258
2259 /* subac3 */
2260 void
2261 OP_17000000 ()
2262 {
2263 int64 tmp;
2264
2265 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2266 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2267 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2268 State.regs[OP[0]+1] = tmp & 0xffff;
2269 trace_output (OP_DREG);
2270 }
2271
2272 /* subac3 */
2273 void
2274 OP_17000002 ()
2275 {
2276 int64 tmp;
2277
2278 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2279 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2280 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2281 State.regs[OP[0]+1] = tmp & 0xffff;
2282 trace_output (OP_DREG);
2283 }
2284
2285 /* subac3s */
2286 void
2287 OP_17001000 ()
2288 {
2289 int64 tmp;
2290
2291 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2292 State.F1 = State.F0;
2293 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2294 if ( tmp > MAX32)
2295 {
2296 State.regs[OP[0]] = 0x7fff;
2297 State.regs[OP[0]+1] = 0xffff;
2298 State.F0 = 1;
2299 }
2300 else if (tmp < MIN32)
2301 {
2302 State.regs[OP[0]] = 0x8000;
2303 State.regs[OP[0]+1] = 0;
2304 State.F0 = 1;
2305 }
2306 else
2307 {
2308 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2309 State.regs[OP[0]+1] = tmp & 0xffff;
2310 State.F0 = 0;
2311 }
2312 trace_output (OP_DREG);
2313 }
2314
2315 /* subac3s */
2316 void
2317 OP_17001002 ()
2318 {
2319 int64 tmp;
2320
2321 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2322 State.F1 = State.F0;
2323 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2324 if ( tmp > MAX32)
2325 {
2326 State.regs[OP[0]] = 0x7fff;
2327 State.regs[OP[0]+1] = 0xffff;
2328 State.F0 = 1;
2329 }
2330 else if (tmp < MIN32)
2331 {
2332 State.regs[OP[0]] = 0x8000;
2333 State.regs[OP[0]+1] = 0;
2334 State.F0 = 1;
2335 }
2336 else
2337 {
2338 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2339 State.regs[OP[0]+1] = tmp & 0xffff;
2340 State.F0 = 0;
2341 }
2342 trace_output (OP_DREG);
2343 }
2344
2345 /* subi */
2346 void
2347 OP_1 ()
2348 {
2349 int32 tmp;
2350 if (OP[1] == 0)
2351 OP[1] = 16;
2352
2353 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2354 tmp = (int16)State.regs[OP[0]] - OP[1];
2355 State.C = (tmp & 0xffff0000) ? 1 : 0;
2356 State.regs[OP[0]] = tmp & 0xffff;
2357 trace_output (OP_REG);
2358 }
2359
2360 /* trap */
2361 void
2362 OP_5F00 ()
2363 {
2364 trace_input ("trap", OP_CONSTANT16, OP_REG, OP_VOID);
2365 trace_output (OP_VOID);
2366
2367 switch (OP[0])
2368 {
2369 default:
2370 fprintf (stderr, "Unknown trap code %d\n", OP[0]);
2371 State.exception = SIGILL;
2372
2373 case 0:
2374 /* Trap 0 is used for simulating low-level I/O */
2375 {
2376 int save_errno = errno;
2377 errno = 0;
2378
2379 /* Registers passed to trap 0 */
2380
2381 #define FUNC State.regs[2] /* function number, return value */
2382 #define PARM1 State.regs[3] /* optional parm 1 */
2383 #define PARM2 State.regs[4] /* optional parm 2 */
2384 #define PARM3 State.regs[5] /* optional parm 3 */
2385
2386 /* Registers set by trap 0 */
2387
2388 #define RETVAL State.regs[2] /* return value */
2389 #define RETERR State.regs[3] /* return error code */
2390
2391 /* Turn a pointer in a register into a pointer into real memory. */
2392
2393 #define MEMPTR(x) ((char *)((x) + State.imem))
2394
2395 switch (FUNC)
2396 {
2397 #if !defined(__GO32__) && !defined(_WIN32)
2398 #ifdef SYS_fork
2399 case SYS_fork:
2400 RETVAL = fork ();
2401 break;
2402 #endif
2403 #ifdef SYS_execve
2404 case SYS_execve:
2405 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2406 (char **)MEMPTR (PARM3));
2407 break;
2408 #endif
2409 #ifdef SYS_execv
2410 case SYS_execv:
2411 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2412 break;
2413 #endif
2414 #ifdef SYS_pipe
2415 case SYS_pipe:
2416 {
2417 reg_t buf;
2418 int host_fd[2];
2419
2420 buf = PARM1;
2421 RETVAL = pipe (host_fd);
2422 SW (buf, host_fd[0]);
2423 buf += sizeof(uint16);
2424 SW (buf, host_fd[1]);
2425 }
2426 break;
2427 #endif
2428 #ifdef SYS_wait
2429 case SYS_wait:
2430 {
2431 int status;
2432
2433 RETVAL = wait (&status);
2434 SW (PARM1, status);
2435 }
2436 break;
2437 #endif
2438 #endif
2439
2440 #ifdef SYS_read
2441 case SYS_read:
2442 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2443 PARM3);
2444 break;
2445 #endif
2446 #ifdef SYS_write
2447 case SYS_write:
2448 if (PARM1 == 1)
2449 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2450 MEMPTR (PARM2), PARM3);
2451 else
2452 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2453 MEMPTR (PARM2), PARM3);
2454 break;
2455 #endif
2456 #ifdef SYS_lseek
2457 case SYS_lseek:
2458 RETVAL = d10v_callback->lseek (d10v_callback, PARM1, PARM2, PARM3);
2459 break;
2460 #endif
2461 #ifdef SYS_close
2462 case SYS_close:
2463 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2464 break;
2465 #endif
2466 #ifdef SYS_open
2467 case SYS_open:
2468 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2469 break;
2470 #endif
2471 #ifdef SYS_exit
2472 case SYS_exit:
2473 /* EXIT - caller can look in PARM1 to work out the
2474 reason */
2475 State.exception = SIGQUIT;
2476 break;
2477 #endif
2478
2479 #ifdef SYS_stat
2480 case SYS_stat:
2481 /* stat system call */
2482 {
2483 struct stat host_stat;
2484 reg_t buf;
2485
2486 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2487
2488 buf = PARM2;
2489
2490 /* The hard-coded offsets and sizes were determined by using
2491 * the D10V compiler on a test program that used struct stat.
2492 */
2493 SW (buf, host_stat.st_dev);
2494 SW (buf+2, host_stat.st_ino);
2495 SW (buf+4, host_stat.st_mode);
2496 SW (buf+6, host_stat.st_nlink);
2497 SW (buf+8, host_stat.st_uid);
2498 SW (buf+10, host_stat.st_gid);
2499 SW (buf+12, host_stat.st_rdev);
2500 SLW (buf+16, host_stat.st_size);
2501 SLW (buf+20, host_stat.st_atime);
2502 SLW (buf+28, host_stat.st_mtime);
2503 SLW (buf+36, host_stat.st_ctime);
2504 }
2505 break;
2506 #endif
2507
2508 #ifdef SYS_chown
2509 case SYS_chown:
2510 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2511 break;
2512 #endif
2513 #ifdef SYS_chmod
2514 case SYS_chmod:
2515 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2516 break;
2517 #endif
2518 #ifdef SYS_utime
2519 case SYS_utime:
2520 /* Cast the second argument to void *, to avoid type mismatch
2521 if a prototype is present. */
2522 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2523 break;
2524 #endif
2525 default:
2526 abort ();
2527 }
2528 RETERR = errno;
2529 errno = save_errno;
2530 break;
2531 }
2532
2533 case 1:
2534 /* Trap 1 prints a string */
2535 {
2536 char *fstr = State.regs[2] + State.imem;
2537 fputs (fstr, stdout);
2538 break;
2539 }
2540
2541 case 2:
2542 /* Trap 2 calls printf */
2543 {
2544 char *fstr = State.regs[2] + State.imem;
2545 printf (fstr, (int16)State.regs[3], (int16)State.regs[4], (int16)State.regs[5]);
2546 break;
2547 }
2548
2549 case 3:
2550 /* Trap 3 writes a character */
2551 putchar (State.regs[2]);
2552 break;
2553 }
2554 }
2555
2556 /* tst0i */
2557 void
2558 OP_7000000 ()
2559 {
2560 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
2561 State.F1 = State.F0;
2562 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
2563 trace_output (OP_FLAG);
2564 }
2565
2566 /* tst1i */
2567 void
2568 OP_F000000 ()
2569 {
2570 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
2571 State.F1 = State.F0;
2572 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
2573 trace_output (OP_FLAG);
2574 }
2575
2576 /* wait */
2577 void
2578 OP_5F80 ()
2579 {
2580 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
2581 State.IE = 1;
2582 trace_output (OP_VOID);
2583 }
2584
2585 /* xor */
2586 void
2587 OP_A00 ()
2588 {
2589 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
2590 State.regs[OP[0]] ^= State.regs[OP[1]];
2591 trace_output (OP_REG);
2592 }
2593
2594 /* xor3 */
2595 void
2596 OP_5000000 ()
2597 {
2598 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2599 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
2600 trace_output (OP_REG);
2601 }
2602
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