sim/erc32/ChangeLog

   1 Mon Jun  3 12:33:38 1996  Ian Lance Taylor  <ian@cygnus.com>
   2
   3         * Makefile.in (end.h): Use explicit ./ when running end.
   4
   5 Sun May 19 21:05:31 1996  Rob Savoye  <rob@chinadoll.cygnus.com>
   6
   7         * func.c(bfd_load): Don't try to print the filename if the pfbd is
   8         NULL.
   9         * interf.c(sim_load): Pass the whole string, not just the first
  10         byte.
  11
  12 Version 2.1 26-02-96
  13 --------------------
  14
  15 * Fixed bug in "go" command.
  16
  17 version 2.0 05-02-96
  18 --------------------
  19
  20 * Fixed bug in interrupt force register (erc32.c).
  21
  22 * Change file load function to use bfd_openr.
  23
  24 * SIS should now be endian independent.
  25
  26 version 1.8 24-11-95
  27 --------------------
  28
  29 * Fixed FPU timing - some sequences of FPU instructions did not calculate
  30   the resource dependencies right.
  31
  32 * Corrected STDFQ when qne = 0 (again!). The ftt is set to sequence_error
  33   but no FPU trap is generated.
  34
  35 version 1.7.1 31-10-95
  36 --------------------
  37
  38 * Corrected STDFQ when qne = 0. Now, a trap is immidiately generated but
  39   the FPU stays in execute mode.
  40
  41 * Corrected JMPL and RETT timing (these instructions takes two cycles).
  42
  43
  44 version 1.7 25-10-95
  45 --------------------
  46
  47 * Interrupt during annuled instruction corrupted return address - fixed.
  48
  49
  50 version 1.6.2 25-10-95
  51 --------------------
  52
  53 * Added -DFAST_UART to Makefile
  54
  55
  56 version 1.6.1 24-10-95
  57 --------------------
  58
  59 * Fixed bug in STDFQ which caused bus error
  60
  61
  62 version 1.6 02-10-95
  63 --------------------
  64
  65 * Modified srt0.s to include code that initiates registers in IU and FPU
  66   and initializes the data segment. The simulator 'load' command does not
  67   longer initialize the data segment!
  68
  69 * Corrected MEC timer operation; scalers now divide the frequency by
  70   (scaler_value + 1).
  71
  72 * MEC breakpoints are not checked during store operation
  73
  74
  75 version 1.5 14-09-95
  76 --------------------
  77
  78 * Fixed some bugs in the cycle counting for IU & FPU instructions.
  79
  80 * Fixed bug that allowed an annuled instruction to cause memory exception.
  81
  82 * The *ws parameter in mem.c should now contain the number of waitstates
  83   required by the memory access (was total number of cycles).
  84
  85 * The supplied srt0.s now clears the BSS (thanks Joel).
  86
  87 version 1.4 22-08-95
  88 --------------------
  89
  90 * Added a '-g' switch to enable/disable the GNU readline(), which cause
  91 some problems on solaris 2.x machines.
  92
  93 * Enabled MEC watchpoint and breakpoint function to mem.c. Performance
  94 may suffer a bit ...
  95
  96 NOTE: The UARTs are now connected to /dev/ttypc and /dev/ttypd.
  97
  98 version 1.3 26-07-95
  99 --------------------
 100
 101 * Fixed bug in mulscc instruction (how could that ever have worked?)
 102
 103 * Fixed bug in UART B (flushed characters on UART A), thanks Paul.
 104
 105 version 1.2 13-07-95
 106 --------------------
 107
 108 * Fixed bug in interrupt handling (wrong interrupt selected when more that
 109 one interrupt pending)
 110
 111 * Fixed updating of condition codes during logical instructions (carry and
 112 overflow were not reset)
 113
 114 * Fixed bug in WRTBR (tt field was wrongly over-written)
 115
 116 version 1.1 07-07-95
 117 --------------------
 118
 119 * Fixed several bugs in the interrupt handler and callback routines.
 120 (reported by Paul Warren, Alsys)