sim/erc32/float.c

   1 /*
   2  * This file is part of SIS.
   3  *
   4  * SIS, SPARC instruction simulator. Copyright (C) 1995 Jiri Gaisler, European
   5  * Space Agency
   6  *
   7  * This program is free software; you can redistribute it and/or modify it under
   8  * the terms of the GNU General Public License as published by the Free
   9  * Software Foundation; either version 2 of the License, or (at your option)
  10  * any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc., 675
  19  * Mass Ave, Cambridge, MA 02139, USA.
  20  *
  21  *
  22  * This file implements the interface between the host and the simulated
  23  * FPU. IEEE trap handling is done as follows:
  24  * 1. In the host, all IEEE traps are masked
  25  * 2. After each simulated FPU instruction, check if any exception occured
  26  *    by reading the exception bits from the host FPU status register
  27  *    (get_accex()).
  28  * 3. Propagate any exceptions to the simulated FSR.
  29  * 4. Clear host exception bits
  30  *
  31  *
  32  * This can also be done using ieee_flags() library routine on sun.
  33  */
  34
  35 #include "sis.h"
  36
  37 /* This host dependent routine should return the accrued exceptions */
  38 int
  39 get_accex()
  40 {
  41 #ifdef sparc
  42     return ((_get_fsr_raw() >> 5) & 0x1F);
  43 #elif i386
  44     uint32 accx;
  45
  46     accx = _get_sw() & 0x3f;
  47     accx = ((accx & 1) << 4) | ((accx & 2) >> 1) | ((accx & 4) >> 1) |
  48            (accx & 8) | ((accx & 16) >> 2) | ((accx & 32) >> 5);
  49     return(accx);
  50 #else
  51     return(0);
  52 #warning no fpu trap support for this target
  53 #endif
  54
  55 }
  56
  57 /* How to clear the accrued exceptions */
  58 int
  59 clear_accex()
  60 {
  61 #ifdef sparc
  62     set_fsr((_get_fsr_raw() & ~0x3e0));
  63 #elif i386
  64     asm("
  65 .text
  66         fnclex
  67
  68     ");
  69 #else
  70 #warning no fpu trap support for this target
  71 #endif
  72 }
  73
  74 /* How to map SPARC FSR onto the host */
  75 int
  76 set_fsr(fsr)
  77 uint32 fsr;
  78 {
  79 #ifdef sparc
  80         _set_fsr_raw(fsr & ~0x0f800000);
  81 #elif i386
  82      uint32 rawfsr;
  83
  84      fsr >>= 30;
  85      switch (fsr) {
  86         case 0:
  87         case 2: break;
  88         case 1: fsr = 3;
  89         case 3: fsr = 1;
  90     }
  91     rawfsr = _get_cw();
  92     rawfsr |= (fsr << 10) | 0x3ff;
  93     __setfpucw(rawfsr);
  94 #else
  95 #warning no fpu trap support for this target
  96 #endif
  97 }
  98
  99
 100 /* Host dependent support functions */
 101
 102 #ifdef sparc
 103
 104     asm("
 105
 106 .text
 107         .align 4
 108         .global __set_fsr_raw,_set_fsr_raw
 109 __set_fsr_raw:
 110 _set_fsr_raw:
 111         save %sp,-104,%sp
 112         st %i0,[%fp+68]
 113         ld [%fp+68], %fsr
 114         mov 0,%i0
 115         ret
 116         restore
 117
 118         .align 4
 119         .global __get_fsr_raw
 120         .global _get_fsr_raw
 121 __get_fsr_raw:
 122 _get_fsr_raw:
 123         save %sp,-104,%sp
 124         st %fsr,[%fp+68]
 125         ld [%fp+68], %i0
 126         ret
 127         restore
 128
 129     ");
 130
 131 #elif i386
 132         /* both these align statements were 16, not 8 */
 133
 134     asm("
 135
 136 .text
 137         .align 8
 138 .globl _get_sw,__get_sw
 139 __get_sw:
 140 _get_sw:
 141         pushl %ebp
 142         movl %esp,%ebp
 143         movl $0,%eax
 144         fnstsw %ax
 145         movl %ebp,%esp
 146         popl %ebp
 147         ret
 148
 149         .align 8
 150 .globl _get_cw,__get_cw
 151 __get_cw:
 152 _get_cw:
 153         pushl %ebp
 154         movl %esp,%ebp
 155         subw $2,%esp
 156         fnstcw -2(%ebp)
 157         movw -2(%ebp),%eax
 158         movl %ebp,%esp
 159         popl %ebp
 160         ret
 161
 162
 163     ");
 164
 165
 166 #else
 167 #warning no fpu trap support for this target
 168 #endif
 169