sim/fr30/cpu.h

   1 /* CPU family header for fr30bf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_FR30BF_H
  26 #define CPU_FR30BF_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 1
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 1
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[16];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* coprocessor registers */
  48   SI h_cr[16];
  49 #define GET_H_CR(a1) CPU (h_cr)[a1]
  50 #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
  51   /* dedicated registers */
  52   SI h_dr[6];
  53 #define GET_H_DR(index) fr30bf_h_dr_get_handler (current_cpu, index)
  54 #define SET_H_DR(index, x) \
  55 do { \
  56 fr30bf_h_dr_set_handler (current_cpu, (index), (x));\
  57 } while (0)
  58   /* processor status */
  59   USI h_ps;
  60 #define GET_H_PS() fr30bf_h_ps_get_handler (current_cpu)
  61 #define SET_H_PS(x) \
  62 do { \
  63 fr30bf_h_ps_set_handler (current_cpu, (x));\
  64 } while (0)
  65   /* General Register 13 explicitly required */
  66   SI h_r13;
  67 #define GET_H_R13() CPU (h_r13)
  68 #define SET_H_R13(x) (CPU (h_r13) = (x))
  69   /* General Register 14 explicitly required */
  70   SI h_r14;
  71 #define GET_H_R14() CPU (h_r14)
  72 #define SET_H_R14(x) (CPU (h_r14) = (x))
  73   /* General Register 15 explicitly required */
  74   SI h_r15;
  75 #define GET_H_R15() CPU (h_r15)
  76 #define SET_H_R15(x) (CPU (h_r15) = (x))
  77   /* negative         bit */
  78   BI h_nbit;
  79 #define GET_H_NBIT() CPU (h_nbit)
  80 #define SET_H_NBIT(x) (CPU (h_nbit) = (x))
  81   /* zero             bit */
  82   BI h_zbit;
  83 #define GET_H_ZBIT() CPU (h_zbit)
  84 #define SET_H_ZBIT(x) (CPU (h_zbit) = (x))
  85   /* overflow         bit */
  86   BI h_vbit;
  87 #define GET_H_VBIT() CPU (h_vbit)
  88 #define SET_H_VBIT(x) (CPU (h_vbit) = (x))
  89   /* carry            bit */
  90   BI h_cbit;
  91 #define GET_H_CBIT() CPU (h_cbit)
  92 #define SET_H_CBIT(x) (CPU (h_cbit) = (x))
  93   /* interrupt enable bit */
  94   BI h_ibit;
  95 #define GET_H_IBIT() CPU (h_ibit)
  96 #define SET_H_IBIT(x) (CPU (h_ibit) = (x))
  97   /* stack bit */
  98   BI h_sbit;
  99 #define GET_H_SBIT() fr30bf_h_sbit_get_handler (current_cpu)
 100 #define SET_H_SBIT(x) \
 101 do { \
 102 fr30bf_h_sbit_set_handler (current_cpu, (x));\
 103 } while (0)
 104   /* trace trap       bit */
 105   BI h_tbit;
 106 #define GET_H_TBIT() CPU (h_tbit)
 107 #define SET_H_TBIT(x) (CPU (h_tbit) = (x))
 108   /* division 0       bit */
 109   BI h_d0bit;
 110 #define GET_H_D0BIT() CPU (h_d0bit)
 111 #define SET_H_D0BIT(x) (CPU (h_d0bit) = (x))
 112   /* division 1       bit */
 113   BI h_d1bit;
 114 #define GET_H_D1BIT() CPU (h_d1bit)
 115 #define SET_H_D1BIT(x) (CPU (h_d1bit) = (x))
 116   /* condition code bits */
 117   UQI h_ccr;
 118 #define GET_H_CCR() fr30bf_h_ccr_get_handler (current_cpu)
 119 #define SET_H_CCR(x) \
 120 do { \
 121 fr30bf_h_ccr_set_handler (current_cpu, (x));\
 122 } while (0)
 123   /* system condition bits */
 124   UQI h_scr;
 125 #define GET_H_SCR() fr30bf_h_scr_get_handler (current_cpu)
 126 #define SET_H_SCR(x) \
 127 do { \
 128 fr30bf_h_scr_set_handler (current_cpu, (x));\
 129 } while (0)
 130   /* interrupt level mask */
 131   UQI h_ilm;
 132 #define GET_H_ILM() fr30bf_h_ilm_get_handler (current_cpu)
 133 #define SET_H_ILM(x) \
 134 do { \
 135 fr30bf_h_ilm_set_handler (current_cpu, (x));\
 136 } while (0)
 137   } hardware;
 138 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
 139 } FR30BF_CPU_DATA;
 140
 141 /* Cover fns for register access.  */
 142 USI fr30bf_h_pc_get (SIM_CPU *);
 143 void fr30bf_h_pc_set (SIM_CPU *, USI);
 144 SI fr30bf_h_gr_get (SIM_CPU *, UINT);
 145 void fr30bf_h_gr_set (SIM_CPU *, UINT, SI);
 146 SI fr30bf_h_cr_get (SIM_CPU *, UINT);
 147 void fr30bf_h_cr_set (SIM_CPU *, UINT, SI);
 148 SI fr30bf_h_dr_get (SIM_CPU *, UINT);
 149 void fr30bf_h_dr_set (SIM_CPU *, UINT, SI);
 150 USI fr30bf_h_ps_get (SIM_CPU *);
 151 void fr30bf_h_ps_set (SIM_CPU *, USI);
 152 SI fr30bf_h_r13_get (SIM_CPU *);
 153 void fr30bf_h_r13_set (SIM_CPU *, SI);
 154 SI fr30bf_h_r14_get (SIM_CPU *);
 155 void fr30bf_h_r14_set (SIM_CPU *, SI);
 156 SI fr30bf_h_r15_get (SIM_CPU *);
 157 void fr30bf_h_r15_set (SIM_CPU *, SI);
 158 BI fr30bf_h_nbit_get (SIM_CPU *);
 159 void fr30bf_h_nbit_set (SIM_CPU *, BI);
 160 BI fr30bf_h_zbit_get (SIM_CPU *);
 161 void fr30bf_h_zbit_set (SIM_CPU *, BI);
 162 BI fr30bf_h_vbit_get (SIM_CPU *);
 163 void fr30bf_h_vbit_set (SIM_CPU *, BI);
 164 BI fr30bf_h_cbit_get (SIM_CPU *);
 165 void fr30bf_h_cbit_set (SIM_CPU *, BI);
 166 BI fr30bf_h_ibit_get (SIM_CPU *);
 167 void fr30bf_h_ibit_set (SIM_CPU *, BI);
 168 BI fr30bf_h_sbit_get (SIM_CPU *);
 169 void fr30bf_h_sbit_set (SIM_CPU *, BI);
 170 BI fr30bf_h_tbit_get (SIM_CPU *);
 171 void fr30bf_h_tbit_set (SIM_CPU *, BI);
 172 BI fr30bf_h_d0bit_get (SIM_CPU *);
 173 void fr30bf_h_d0bit_set (SIM_CPU *, BI);
 174 BI fr30bf_h_d1bit_get (SIM_CPU *);
 175 void fr30bf_h_d1bit_set (SIM_CPU *, BI);
 176 UQI fr30bf_h_ccr_get (SIM_CPU *);
 177 void fr30bf_h_ccr_set (SIM_CPU *, UQI);
 178 UQI fr30bf_h_scr_get (SIM_CPU *);
 179 void fr30bf_h_scr_set (SIM_CPU *, UQI);
 180 UQI fr30bf_h_ilm_get (SIM_CPU *);
 181 void fr30bf_h_ilm_set (SIM_CPU *, UQI);
 182
 183 /* These must be hand-written.  */
 184 extern CPUREG_FETCH_FN fr30bf_fetch_register;
 185 extern CPUREG_STORE_FN fr30bf_store_register;
 186
 187 typedef struct {
 188   UINT load_regs;
 189   UINT load_regs_pending;
 190 } MODEL_FR30_1_DATA;
 191
 192 union sem_fields {
 193     struct { /* empty sformat for unspecified field list */
 194       int empty;
 195     } fmt_empty;
 196     struct { /* e.g. add $Rj,$Ri */
 197       SI * i_Ri;
 198       SI * i_Rj;
 199       unsigned char in_Ri;
 200       unsigned char in_Rj;
 201       unsigned char out_Ri;
 202     } fmt_add;
 203     struct { /* e.g. add $u4,$Ri */
 204       UINT f_u4;
 205       SI * i_Ri;
 206       unsigned char in_Ri;
 207       unsigned char out_Ri;
 208     } fmt_addi;
 209     struct { /* e.g. add2 $m4,$Ri */
 210       SI f_m4;
 211       SI * i_Ri;
 212       unsigned char in_Ri;
 213       unsigned char out_Ri;
 214     } fmt_add2;
 215     struct { /* e.g. addc $Rj,$Ri */
 216       SI * i_Ri;
 217       SI * i_Rj;
 218       unsigned char in_Ri;
 219       unsigned char in_Rj;
 220       unsigned char out_Ri;
 221     } fmt_addc;
 222     struct { /* e.g. addn $Rj,$Ri */
 223       SI * i_Ri;
 224       SI * i_Rj;
 225       unsigned char in_Ri;
 226       unsigned char in_Rj;
 227       unsigned char out_Ri;
 228     } fmt_addn;
 229     struct { /* e.g. addn $u4,$Ri */
 230       UINT f_u4;
 231       SI * i_Ri;
 232       unsigned char in_Ri;
 233       unsigned char out_Ri;
 234     } fmt_addni;
 235     struct { /* e.g. addn2 $m4,$Ri */
 236       SI f_m4;
 237       SI * i_Ri;
 238       unsigned char in_Ri;
 239       unsigned char out_Ri;
 240     } fmt_addn2;
 241     struct { /* e.g. cmp $Rj,$Ri */
 242       SI * i_Ri;
 243       SI * i_Rj;
 244       unsigned char in_Ri;
 245       unsigned char in_Rj;
 246     } fmt_cmp;
 247     struct { /* e.g. cmp $u4,$Ri */
 248       UINT f_u4;
 249       SI * i_Ri;
 250       unsigned char in_Ri;
 251     } fmt_cmpi;
 252     struct { /* e.g. cmp2 $m4,$Ri */
 253       SI f_m4;
 254       SI * i_Ri;
 255       unsigned char in_Ri;
 256     } fmt_cmp2;
 257     struct { /* e.g. and $Rj,$Ri */
 258       SI * i_Ri;
 259       SI * i_Rj;
 260       unsigned char in_Ri;
 261       unsigned char in_Rj;
 262       unsigned char out_Ri;
 263     } fmt_and;
 264     struct { /* e.g. and $Rj,@$Ri */
 265       SI * i_Ri;
 266       SI * i_Rj;
 267       unsigned char in_Ri;
 268       unsigned char in_Rj;
 269     } fmt_andm;
 270     struct { /* e.g. andh $Rj,@$Ri */
 271       SI * i_Ri;
 272       SI * i_Rj;
 273       unsigned char in_Ri;
 274       unsigned char in_Rj;
 275     } fmt_andh;
 276     struct { /* e.g. andb $Rj,@$Ri */
 277       SI * i_Ri;
 278       SI * i_Rj;
 279       unsigned char in_Ri;
 280       unsigned char in_Rj;
 281     } fmt_andb;
 282     struct { /* e.g. bandl $u4,@$Ri */
 283       UINT f_u4;
 284       SI * i_Ri;
 285       unsigned char in_Ri;
 286     } fmt_bandl;
 287     struct { /* e.g. btstl $u4,@$Ri */
 288       UINT f_u4;
 289       SI * i_Ri;
 290       unsigned char in_Ri;
 291     } fmt_btstl;
 292     struct { /* e.g. mul $Rj,$Ri */
 293       SI * i_Ri;
 294       SI * i_Rj;
 295       unsigned char in_Ri;
 296       unsigned char in_Rj;
 297     } fmt_mul;
 298     struct { /* e.g. mulu $Rj,$Ri */
 299       SI * i_Ri;
 300       SI * i_Rj;
 301       unsigned char in_Ri;
 302       unsigned char in_Rj;
 303     } fmt_mulu;
 304     struct { /* e.g. mulh $Rj,$Ri */
 305       SI * i_Ri;
 306       SI * i_Rj;
 307       unsigned char in_Ri;
 308       unsigned char in_Rj;
 309     } fmt_mulh;
 310     struct { /* e.g. div0s $Ri */
 311       SI * i_Ri;
 312       unsigned char in_Ri;
 313     } fmt_div0s;
 314     struct { /* e.g. div0u $Ri */
 315       int empty;
 316     } fmt_div0u;
 317     struct { /* e.g. div1 $Ri */
 318       SI * i_Ri;
 319       unsigned char in_Ri;
 320     } fmt_div1;
 321     struct { /* e.g. div2 $Ri */
 322       SI * i_Ri;
 323       unsigned char in_Ri;
 324     } fmt_div2;
 325     struct { /* e.g. div3 */
 326       int empty;
 327     } fmt_div3;
 328     struct { /* e.g. div4s */
 329       int empty;
 330     } fmt_div4s;
 331     struct { /* e.g. lsl $Rj,$Ri */
 332       SI * i_Ri;
 333       SI * i_Rj;
 334       unsigned char in_Ri;
 335       unsigned char in_Rj;
 336       unsigned char out_Ri;
 337     } fmt_lsl;
 338     struct { /* e.g. lsl $u4,$Ri */
 339       UINT f_u4;
 340       SI * i_Ri;
 341       unsigned char in_Ri;
 342       unsigned char out_Ri;
 343     } fmt_lsli;
 344     struct { /* e.g. ldi:8 $i8,$Ri */
 345       UINT f_i8;
 346       SI * i_Ri;
 347       unsigned char out_Ri;
 348     } fmt_ldi8;
 349     struct { /* e.g. ldi:20 $i20,$Ri */
 350       UINT f_i20;
 351       SI * i_Ri;
 352       unsigned char out_Ri;
 353     } fmt_ldi20;
 354     struct { /* e.g. ldi:32 $i32,$Ri */
 355       UINT f_i32;
 356       SI * i_Ri;
 357       unsigned char out_Ri;
 358     } fmt_ldi32;
 359     struct { /* e.g. ld @$Rj,$Ri */
 360       SI * i_Rj;
 361       SI * i_Ri;
 362       unsigned char in_Rj;
 363       unsigned char out_Ri;
 364     } fmt_ld;
 365     struct { /* e.g. ld @($R13,$Rj),$Ri */
 366       SI * i_Rj;
 367       SI * i_Ri;
 368       unsigned char in_Rj;
 369       unsigned char in_h_gr_13;
 370       unsigned char out_Ri;
 371     } fmt_ldr13;
 372     struct { /* e.g. ld @($R14,$disp10),$Ri */
 373       SI f_disp10;
 374       SI * i_Ri;
 375       unsigned char in_h_gr_14;
 376       unsigned char out_Ri;
 377     } fmt_ldr14;
 378     struct { /* e.g. lduh @($R14,$disp9),$Ri */
 379       SI f_disp9;
 380       SI * i_Ri;
 381       unsigned char in_h_gr_14;
 382       unsigned char out_Ri;
 383     } fmt_ldr14uh;
 384     struct { /* e.g. ldub @($R14,$disp8),$Ri */
 385       INT f_disp8;
 386       SI * i_Ri;
 387       unsigned char in_h_gr_14;
 388       unsigned char out_Ri;
 389     } fmt_ldr14ub;
 390     struct { /* e.g. ld @($R15,$udisp6),$Ri */
 391       USI f_udisp6;
 392       SI * i_Ri;
 393       unsigned char in_h_gr_15;
 394       unsigned char out_Ri;
 395     } fmt_ldr15;
 396     struct { /* e.g. ld @$R15+,$Ri */
 397       UINT f_Ri;
 398       SI * i_Ri;
 399       unsigned char in_h_gr_15;
 400       unsigned char out_Ri;
 401       unsigned char out_h_gr_15;
 402     } fmt_ldr15gr;
 403     struct { /* e.g. ld @$R15+,$Rs2 */
 404       UINT f_Rs2;
 405       unsigned char in_h_gr_15;
 406       unsigned char out_h_gr_15;
 407     } fmt_ldr15dr;
 408     struct { /* e.g. ld @$R15+,$ps */
 409       int empty;
 410       unsigned char in_h_gr_15;
 411       unsigned char out_h_gr_15;
 412     } fmt_ldr15ps;
 413     struct { /* e.g. st $Ri,@$Rj */
 414       SI * i_Ri;
 415       SI * i_Rj;
 416       unsigned char in_Ri;
 417       unsigned char in_Rj;
 418     } fmt_st;
 419     struct { /* e.g. st $Ri,@($R13,$Rj) */
 420       SI * i_Ri;
 421       SI * i_Rj;
 422       unsigned char in_Ri;
 423       unsigned char in_Rj;
 424       unsigned char in_h_gr_13;
 425     } fmt_str13;
 426     struct { /* e.g. st $Ri,@($R14,$disp10) */
 427       SI f_disp10;
 428       SI * i_Ri;
 429       unsigned char in_Ri;
 430       unsigned char in_h_gr_14;
 431     } fmt_str14;
 432     struct { /* e.g. sth $Ri,@($R14,$disp9) */
 433       SI f_disp9;
 434       SI * i_Ri;
 435       unsigned char in_Ri;
 436       unsigned char in_h_gr_14;
 437     } fmt_str14h;
 438     struct { /* e.g. stb $Ri,@($R14,$disp8) */
 439       INT f_disp8;
 440       SI * i_Ri;
 441       unsigned char in_Ri;
 442       unsigned char in_h_gr_14;
 443     } fmt_str14b;
 444     struct { /* e.g. st $Ri,@($R15,$udisp6) */
 445       USI f_udisp6;
 446       SI * i_Ri;
 447       unsigned char in_Ri;
 448       unsigned char in_h_gr_15;
 449     } fmt_str15;
 450     struct { /* e.g. st $Ri,@-$R15 */
 451       SI * i_Ri;
 452       unsigned char in_Ri;
 453       unsigned char in_h_gr_15;
 454       unsigned char out_h_gr_15;
 455     } fmt_str15gr;
 456     struct { /* e.g. st $Rs2,@-$R15 */
 457       UINT f_Rs2;
 458       unsigned char in_h_gr_15;
 459       unsigned char out_h_gr_15;
 460     } fmt_str15dr;
 461     struct { /* e.g. st $ps,@-$R15 */
 462       int empty;
 463       unsigned char in_h_gr_15;
 464       unsigned char out_h_gr_15;
 465     } fmt_str15ps;
 466     struct { /* e.g. mov $Rj,$Ri */
 467       SI * i_Rj;
 468       SI * i_Ri;
 469       unsigned char in_Rj;
 470       unsigned char out_Ri;
 471     } fmt_mov;
 472     struct { /* e.g. mov $Rs1,$Ri */
 473       UINT f_Rs1;
 474       SI * i_Ri;
 475       unsigned char out_Ri;
 476     } fmt_movdr;
 477     struct { /* e.g. mov $ps,$Ri */
 478       SI * i_Ri;
 479       unsigned char out_Ri;
 480     } fmt_movps;
 481     struct { /* e.g. mov $Ri,$Rs1 */
 482       UINT f_Rs1;
 483       SI * i_Ri;
 484       unsigned char in_Ri;
 485     } fmt_mov2dr;
 486     struct { /* e.g. mov $Ri,$ps */
 487       SI * i_Ri;
 488       unsigned char in_Ri;
 489     } fmt_mov2ps;
 490     struct { /* e.g. bno:d $label9 */
 491       int empty;
 492     } fmt_bnod;
 493     struct { /* e.g. dmov $R13,@$dir10 */
 494       USI f_dir10;
 495       unsigned char in_h_gr_13;
 496     } fmt_dmovr13;
 497     struct { /* e.g. dmovh $R13,@$dir9 */
 498       USI f_dir9;
 499       unsigned char in_h_gr_13;
 500     } fmt_dmovr13h;
 501     struct { /* e.g. dmovb $R13,@$dir8 */
 502       UINT f_dir8;
 503       unsigned char in_h_gr_13;
 504     } fmt_dmovr13b;
 505     struct { /* e.g. dmov @$R13+,@$dir10 */
 506       USI f_dir10;
 507       unsigned char in_h_gr_13;
 508       unsigned char out_h_gr_13;
 509     } fmt_dmovr13pi;
 510     struct { /* e.g. dmovh @$R13+,@$dir9 */
 511       USI f_dir9;
 512       unsigned char in_h_gr_13;
 513       unsigned char out_h_gr_13;
 514     } fmt_dmovr13pih;
 515     struct { /* e.g. dmovb @$R13+,@$dir8 */
 516       UINT f_dir8;
 517       unsigned char in_h_gr_13;
 518       unsigned char out_h_gr_13;
 519     } fmt_dmovr13pib;
 520     struct { /* e.g. dmov @$R15+,@$dir10 */
 521       USI f_dir10;
 522       unsigned char in_h_gr_15;
 523       unsigned char out_h_gr_15;
 524     } fmt_dmovr15pi;
 525     struct { /* e.g. dmov @$dir10,$R13 */
 526       USI f_dir10;
 527       unsigned char out_h_gr_13;
 528     } fmt_dmov2r13;
 529     struct { /* e.g. dmovh @$dir9,$R13 */
 530       USI f_dir9;
 531       unsigned char out_h_gr_13;
 532     } fmt_dmov2r13h;
 533     struct { /* e.g. dmovb @$dir8,$R13 */
 534       UINT f_dir8;
 535       unsigned char out_h_gr_13;
 536     } fmt_dmov2r13b;
 537     struct { /* e.g. dmov @$dir10,@$R13+ */
 538       USI f_dir10;
 539       unsigned char in_h_gr_13;
 540       unsigned char out_h_gr_13;
 541     } fmt_dmov2r13pi;
 542     struct { /* e.g. dmovh @$dir9,@$R13+ */
 543       USI f_dir9;
 544       unsigned char in_h_gr_13;
 545       unsigned char out_h_gr_13;
 546     } fmt_dmov2r13pih;
 547     struct { /* e.g. dmovb @$dir8,@$R13+ */
 548       UINT f_dir8;
 549       unsigned char in_h_gr_13;
 550       unsigned char out_h_gr_13;
 551     } fmt_dmov2r13pib;
 552     struct { /* e.g. dmov @$dir10,@-$R15 */
 553       USI f_dir10;
 554       unsigned char in_h_gr_15;
 555       unsigned char out_h_gr_15;
 556     } fmt_dmov2r15pd;
 557     struct { /* e.g. ldres @$Ri+,$u4 */
 558       SI * i_Ri;
 559       unsigned char in_Ri;
 560       unsigned char out_Ri;
 561     } fmt_ldres;
 562     struct { /* e.g. copop $u4c,$ccc,$CRj,$CRi */
 563       int empty;
 564     } fmt_copop;
 565     struct { /* e.g. andccr $u8 */
 566       UINT f_u8;
 567     } fmt_andccr;
 568     struct { /* e.g. stilm $u8 */
 569       UINT f_u8;
 570     } fmt_stilm;
 571     struct { /* e.g. addsp $s10 */
 572       SI f_s10;
 573       unsigned char in_h_gr_15;
 574       unsigned char out_h_gr_15;
 575     } fmt_addsp;
 576     struct { /* e.g. extsb $Ri */
 577       SI * i_Ri;
 578       unsigned char in_Ri;
 579       unsigned char out_Ri;
 580     } fmt_extsb;
 581     struct { /* e.g. extub $Ri */
 582       SI * i_Ri;
 583       unsigned char in_Ri;
 584       unsigned char out_Ri;
 585     } fmt_extub;
 586     struct { /* e.g. extsh $Ri */
 587       SI * i_Ri;
 588       unsigned char in_Ri;
 589       unsigned char out_Ri;
 590     } fmt_extsh;
 591     struct { /* e.g. extuh $Ri */
 592       SI * i_Ri;
 593       unsigned char in_Ri;
 594       unsigned char out_Ri;
 595     } fmt_extuh;
 596     struct { /* e.g. ldm0 ($reglist_low_ld) */
 597       UINT f_reglist_low_ld;
 598       unsigned char in_h_gr_15;
 599       unsigned char out_h_gr_0;
 600       unsigned char out_h_gr_1;
 601       unsigned char out_h_gr_15;
 602       unsigned char out_h_gr_2;
 603       unsigned char out_h_gr_3;
 604       unsigned char out_h_gr_4;
 605       unsigned char out_h_gr_5;
 606       unsigned char out_h_gr_6;
 607       unsigned char out_h_gr_7;
 608     } fmt_ldm0;
 609     struct { /* e.g. ldm1 ($reglist_hi_ld) */
 610       UINT f_reglist_hi_ld;
 611       unsigned char in_h_gr_15;
 612       unsigned char out_h_gr_10;
 613       unsigned char out_h_gr_11;
 614       unsigned char out_h_gr_12;
 615       unsigned char out_h_gr_13;
 616       unsigned char out_h_gr_14;
 617       unsigned char out_h_gr_15;
 618       unsigned char out_h_gr_8;
 619       unsigned char out_h_gr_9;
 620     } fmt_ldm1;
 621     struct { /* e.g. stm0 ($reglist_low_st) */
 622       UINT f_reglist_low_st;
 623       unsigned char in_h_gr_0;
 624       unsigned char in_h_gr_1;
 625       unsigned char in_h_gr_15;
 626       unsigned char in_h_gr_2;
 627       unsigned char in_h_gr_3;
 628       unsigned char in_h_gr_4;
 629       unsigned char in_h_gr_5;
 630       unsigned char in_h_gr_6;
 631       unsigned char in_h_gr_7;
 632       unsigned char out_h_gr_15;
 633     } fmt_stm0;
 634     struct { /* e.g. stm1 ($reglist_hi_st) */
 635       UINT f_reglist_hi_st;
 636       unsigned char in_h_gr_10;
 637       unsigned char in_h_gr_11;
 638       unsigned char in_h_gr_12;
 639       unsigned char in_h_gr_13;
 640       unsigned char in_h_gr_14;
 641       unsigned char in_h_gr_15;
 642       unsigned char in_h_gr_8;
 643       unsigned char in_h_gr_9;
 644       unsigned char out_h_gr_15;
 645     } fmt_stm1;
 646     struct { /* e.g. enter $u10 */
 647       USI f_u10;
 648       unsigned char in_h_gr_14;
 649       unsigned char in_h_gr_15;
 650       unsigned char out_h_gr_14;
 651       unsigned char out_h_gr_15;
 652     } fmt_enter;
 653     struct { /* e.g. leave */
 654       int empty;
 655       unsigned char in_h_gr_14;
 656       unsigned char in_h_gr_15;
 657       unsigned char out_h_gr_14;
 658       unsigned char out_h_gr_15;
 659     } fmt_leave;
 660     struct { /* e.g. xchb @$Rj,$Ri */
 661       SI * i_Ri;
 662       SI * i_Rj;
 663       unsigned char in_Ri;
 664       unsigned char in_Rj;
 665       unsigned char out_Ri;
 666     } fmt_xchb;
 667   /* cti insns, kept separately so addr_cache is in fixed place */
 668   struct {
 669     union {
 670     struct { /* e.g. jmp @$Ri */
 671       SI * i_Ri;
 672       unsigned char in_Ri;
 673     } fmt_jmp;
 674     struct { /* e.g. call @$Ri */
 675       SI * i_Ri;
 676       unsigned char in_Ri;
 677     } fmt_callr;
 678     struct { /* e.g. call $label12 */
 679       IADDR i_label12;
 680     } fmt_call;
 681     struct { /* e.g. ret */
 682       int empty;
 683     } fmt_ret;
 684     struct { /* e.g. int $u8 */
 685       UINT f_u8;
 686     } fmt_int;
 687     struct { /* e.g. inte */
 688       int empty;
 689     } fmt_inte;
 690     struct { /* e.g. reti */
 691       int empty;
 692     } fmt_reti;
 693     struct { /* e.g. bra:d $label9 */
 694       IADDR i_label9;
 695     } fmt_brad;
 696     struct { /* e.g. beq:d $label9 */
 697       IADDR i_label9;
 698     } fmt_beqd;
 699     struct { /* e.g. bc:d $label9 */
 700       IADDR i_label9;
 701     } fmt_bcd;
 702     struct { /* e.g. bn:d $label9 */
 703       IADDR i_label9;
 704     } fmt_bnd;
 705     struct { /* e.g. bv:d $label9 */
 706       IADDR i_label9;
 707     } fmt_bvd;
 708     struct { /* e.g. blt:d $label9 */
 709       IADDR i_label9;
 710     } fmt_bltd;
 711     struct { /* e.g. ble:d $label9 */
 712       IADDR i_label9;
 713     } fmt_bled;
 714     struct { /* e.g. bls:d $label9 */
 715       IADDR i_label9;
 716     } fmt_blsd;
 717     } fields;
 718 #if WITH_SCACHE_PBB
 719     SEM_PC addr_cache;
 720 #endif
 721   } cti;
 722 #if WITH_SCACHE_PBB
 723   /* Writeback handler.  */
 724   struct {
 725     /* Pointer to argbuf entry for insn whose results need writing back.  */
 726     const struct argbuf *abuf;
 727   } write;
 728   /* x-before handler */
 729   struct {
 730     /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 731     int first_p;
 732   } before;
 733   /* x-after handler */
 734   struct {
 735     int empty;
 736   } after;
 737   /* This entry is used to terminate each pbb.  */
 738   struct {
 739     /* Number of insns in pbb.  */
 740     int insn_count;
 741     /* Next pbb to execute.  */
 742     SCACHE *next;
 743   } chain;
 744 #endif
 745 };
 746
 747 /* The ARGBUF struct.  */
 748 struct argbuf {
 749   /* These are the baseclass definitions.  */
 750   IADDR addr;
 751   const IDESC *idesc;
 752   char trace_p;
 753   char profile_p;
 754   /* cpu specific data follows */
 755   union sem semantic;
 756   int written;
 757   union sem_fields fields;
 758 };
 759
 760 /* A cached insn.
 761
 762    ??? SCACHE used to contain more than just argbuf.  We could delete the
 763    type entirely and always just use ARGBUF, but for future concerns and as
 764    a level of abstraction it is left in.  */
 765
 766 struct scache {
 767   struct argbuf argbuf;
 768 };
 769
 770 /* Macros to simplify extraction, reading and semantic code.
 771    These define and assign the local vars that contain the insn's fields.  */
 772
 773 #define EXTRACT_IFMT_EMPTY_VARS \
 774   /* Instruction fields.  */ \
 775   unsigned int length;
 776 #define EXTRACT_IFMT_EMPTY_CODE \
 777   length = 0; \
 778
 779 #define EXTRACT_IFMT_ADD_VARS \
 780   /* Instruction fields.  */ \
 781   UINT f_op1; \
 782   UINT f_op2; \
 783   UINT f_Rj; \
 784   UINT f_Ri; \
 785   unsigned int length;
 786 #define EXTRACT_IFMT_ADD_CODE \
 787   length = 2; \
 788   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 789   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 790   f_Rj = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 791   f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 792
 793 #define EXTRACT_IFMT_ADDI_VARS \
 794   /* Instruction fields.  */ \
 795   UINT f_op1; \
 796   UINT f_op2; \
 797   UINT f_u4; \
 798   UINT f_Ri; \
 799   unsigned int length;
 800 #define EXTRACT_IFMT_ADDI_CODE \
 801   length = 2; \
 802   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 803   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 804   f_u4 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 805   f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 806
 807 #define EXTRACT_IFMT_ADD2_VARS \
 808   /* Instruction fields.  */ \
 809   UINT f_op1; \
 810   UINT f_op2; \
 811   SI f_m4; \
 812   UINT f_Ri; \
 813   unsigned int length;
 814 #define EXTRACT_IFMT_ADD2_CODE \
 815   length = 2; \
 816   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 817   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 818   f_m4 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 4)) | (((-1) << (4)))); \
 819   f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 820
 821 #define EXTRACT_IFMT_DIV0S_VARS \
 822   /* Instruction fields.  */ \
 823   UINT f_op1; \
 824   UINT f_op2; \
 825   UINT f_op3; \
 826   UINT f_Ri; \
 827   unsigned int length;
 828 #define EXTRACT_IFMT_DIV0S_CODE \
 829   length = 2; \
 830   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 831   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 832   f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 833   f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 834
 835 #define EXTRACT_IFMT_DIV3_VARS \
 836   /* Instruction fields.  */ \
 837   UINT f_op1; \
 838   UINT f_op2; \
 839   UINT f_op3; \
 840   UINT f_op4; \
 841   unsigned int length;
 842 #define EXTRACT_IFMT_DIV3_CODE \
 843   length = 2; \
 844   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 845   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 846   f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 847   f_op4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 848
 849 #define EXTRACT_IFMT_LDI8_VARS \
 850   /* Instruction fields.  */ \
 851   UINT f_op1; \
 852   UINT f_i8; \
 853   UINT f_Ri; \
 854   unsigned int length;
 855 #define EXTRACT_IFMT_LDI8_CODE \
 856   length = 2; \
 857   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 858   f_i8 = EXTRACT_MSB0_UINT (insn, 16, 4, 8); \
 859   f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 860
 861 #define EXTRACT_IFMT_LDI20_VARS \
 862   /* Instruction fields.  */ \
 863   UINT f_op1; \
 864   UINT f_i20_4; \
 865   UINT f_i20_16; \
 866   UINT f_i20; \
 867   UINT f_op2; \
 868   UINT f_Ri; \
 869   /* Contents of trailing part of insn.  */ \
 870   UINT word_1; \
 871   unsigned int length;
 872 #define EXTRACT_IFMT_LDI20_CODE \
 873   length = 4; \
 874   word_1 = GETIMEMUHI (current_cpu, pc + 2); \
 875   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 876   f_i20_4 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 877   f_i20_16 = (0|(EXTRACT_MSB0_UINT (word_1, 16, 0, 16) << 0)); \
 878 {\
 879   f_i20 = ((((f_i20_4) << (16))) | (f_i20_16));\
 880 }\
 881   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 882   f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 883
 884 #define EXTRACT_IFMT_LDI32_VARS \
 885   /* Instruction fields.  */ \
 886   UINT f_op1; \
 887   UINT f_i32; \
 888   UINT f_op2; \
 889   UINT f_op3; \
 890   UINT f_Ri; \
 891   /* Contents of trailing part of insn.  */ \
 892   UINT word_1; \
 893   UINT word_2; \
 894   unsigned int length;
 895 #define EXTRACT_IFMT_LDI32_CODE \
 896   length = 6; \
 897   word_1 = GETIMEMUHI (current_cpu, pc + 2); \
 898   word_2 = GETIMEMUHI (current_cpu, pc + 4); \
 899   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 900   f_i32 = (0|(EXTRACT_MSB0_UINT (word_2, 16, 0, 16) << 0)|(EXTRACT_MSB0_UINT (word_1, 16, 0, 16) << 16)); \
 901   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 902   f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 903   f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 904
 905 #define EXTRACT_IFMT_LDR14_VARS \
 906   /* Instruction fields.  */ \
 907   UINT f_op1; \
 908   SI f_disp10; \
 909   UINT f_Ri; \
 910   unsigned int length;
 911 #define EXTRACT_IFMT_LDR14_CODE \
 912   length = 2; \
 913   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 914   f_disp10 = ((EXTRACT_MSB0_INT (insn, 16, 4, 8)) << (2)); \
 915   f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 916
 917 #define EXTRACT_IFMT_LDR14UH_VARS \
 918   /* Instruction fields.  */ \
 919   UINT f_op1; \
 920   SI f_disp9; \
 921   UINT f_Ri; \
 922   unsigned int length;
 923 #define EXTRACT_IFMT_LDR14UH_CODE \
 924   length = 2; \
 925   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 926   f_disp9 = ((EXTRACT_MSB0_INT (insn, 16, 4, 8)) << (1)); \
 927   f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 928
 929 #define EXTRACT_IFMT_LDR14UB_VARS \
 930   /* Instruction fields.  */ \
 931   UINT f_op1; \
 932   INT f_disp8; \
 933   UINT f_Ri; \
 934   unsigned int length;
 935 #define EXTRACT_IFMT_LDR14UB_CODE \
 936   length = 2; \
 937   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 938   f_disp8 = EXTRACT_MSB0_INT (insn, 16, 4, 8); \
 939   f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 940
 941 #define EXTRACT_IFMT_LDR15_VARS \
 942   /* Instruction fields.  */ \
 943   UINT f_op1; \
 944   UINT f_op2; \
 945   USI f_udisp6; \
 946   UINT f_Ri; \
 947   unsigned int length;
 948 #define EXTRACT_IFMT_LDR15_CODE \
 949   length = 2; \
 950   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 951   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 952   f_udisp6 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 4)) << (2)); \
 953   f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 954
 955 #define EXTRACT_IFMT_LDR15DR_VARS \
 956   /* Instruction fields.  */ \
 957   UINT f_op1; \
 958   UINT f_op2; \
 959   UINT f_op3; \
 960   UINT f_Rs2; \
 961   unsigned int length;
 962 #define EXTRACT_IFMT_LDR15DR_CODE \
 963   length = 2; \
 964   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 965   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 966   f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 967   f_Rs2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 968
 969 #define EXTRACT_IFMT_MOVDR_VARS \
 970   /* Instruction fields.  */ \
 971   UINT f_op1; \
 972   UINT f_op2; \
 973   UINT f_Rs1; \
 974   UINT f_Ri; \
 975   unsigned int length;
 976 #define EXTRACT_IFMT_MOVDR_CODE \
 977   length = 2; \
 978   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 979   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 980   f_Rs1 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 981   f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 982
 983 #define EXTRACT_IFMT_CALL_VARS \
 984   /* Instruction fields.  */ \
 985   UINT f_op1; \
 986   UINT f_op5; \
 987   SI f_rel12; \
 988   unsigned int length;
 989 #define EXTRACT_IFMT_CALL_CODE \
 990   length = 2; \
 991   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 992   f_op5 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
 993   f_rel12 = ((((EXTRACT_MSB0_INT (insn, 16, 5, 11)) << (1))) + (((pc) + (2)))); \
 994
 995 #define EXTRACT_IFMT_INT_VARS \
 996   /* Instruction fields.  */ \
 997   UINT f_op1; \
 998   UINT f_op2; \
 999   UINT f_u8; \
1000   unsigned int length;
1001 #define EXTRACT_IFMT_INT_CODE \
1002   length = 2; \
1003   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
1004   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
1005   f_u8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
1006
1007 #define EXTRACT_IFMT_BRAD_VARS \
1008   /* Instruction fields.  */ \
1009   UINT f_op1; \
1010   UINT f_cc; \
1011   SI f_rel9; \
1012   unsigned int length;
1013 #define EXTRACT_IFMT_BRAD_CODE \
1014   length = 2; \
1015   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
1016   f_cc = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
1017   f_rel9 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (2)))); \
1018
1019 #define EXTRACT_IFMT_DMOVR13_VARS \
1020   /* Instruction fields.  */ \
1021   UINT f_op1; \
1022   UINT f_op2; \
1023   USI f_dir10; \
1024   unsigned int length;
1025 #define EXTRACT_IFMT_DMOVR13_CODE \
1026   length = 2; \
1027   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
1028   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
1029   f_dir10 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); \
1030
1031 #define EXTRACT_IFMT_DMOVR13H_VARS \
1032   /* Instruction fields.  */ \
1033   UINT f_op1; \
1034   UINT f_op2; \
1035   USI f_dir9; \
1036   unsigned int length;
1037 #define EXTRACT_IFMT_DMOVR13H_CODE \
1038   length = 2; \
1039   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
1040   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
1041   f_dir9 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (1)); \
1042
1043 #define EXTRACT_IFMT_DMOVR13B_VARS \
1044   /* Instruction fields.  */ \
1045   UINT f_op1; \
1046   UINT f_op2; \
1047   UINT f_dir8; \
1048   unsigned int length;
1049 #define EXTRACT_IFMT_DMOVR13B_CODE \
1050   length = 2; \
1051   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
1052   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
1053   f_dir8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
1054
1055 #define EXTRACT_IFMT_COPOP_VARS \
1056   /* Instruction fields.  */ \
1057   UINT f_op1; \
1058   UINT f_ccc; \
1059   UINT f_op2; \
1060   UINT f_op3; \
1061   UINT f_CRj; \
1062   UINT f_u4c; \
1063   UINT f_CRi; \
1064   /* Contents of trailing part of insn.  */ \
1065   UINT word_1; \
1066   unsigned int length;
1067 #define EXTRACT_IFMT_COPOP_CODE \
1068   length = 4; \
1069   word_1 = GETIMEMUHI (current_cpu, pc + 2); \
1070   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
1071   f_ccc = (0|(EXTRACT_MSB0_UINT (word_1, 16, 0, 8) << 0)); \
1072   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
1073   f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
1074   f_CRj = (0|(EXTRACT_MSB0_UINT (word_1, 16, 8, 4) << 0)); \
1075   f_u4c = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
1076   f_CRi = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 16) << 0)); \
1077
1078 #define EXTRACT_IFMT_COPLD_VARS \
1079   /* Instruction fields.  */ \
1080   UINT f_op1; \
1081   UINT f_ccc; \
1082   UINT f_op2; \
1083   UINT f_op3; \
1084   UINT f_Rjc; \
1085   UINT f_u4c; \
1086   UINT f_CRi; \
1087   /* Contents of trailing part of insn.  */ \
1088   UINT word_1; \
1089   unsigned int length;
1090 #define EXTRACT_IFMT_COPLD_CODE \
1091   length = 4; \
1092   word_1 = GETIMEMUHI (current_cpu, pc + 2); \
1093   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
1094   f_ccc = (0|(EXTRACT_MSB0_UINT (word_1, 16, 0, 8) << 0)); \
1095   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
1096   f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
1097   f_Rjc = (0|(EXTRACT_MSB0_UINT (word_1, 16, 8, 4) << 0)); \
1098   f_u4c = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
1099   f_CRi = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 16) << 0)); \
1100
1101 #define EXTRACT_IFMT_COPST_VARS \
1102   /* Instruction fields.  */ \
1103   UINT f_op1; \
1104   UINT f_ccc; \
1105   UINT f_op2; \
1106   UINT f_op3; \
1107   UINT f_CRj; \
1108   UINT f_u4c; \
1109   UINT f_Ric; \
1110   /* Contents of trailing part of insn.  */ \
1111   UINT word_1; \
1112   unsigned int length;
1113 #define EXTRACT_IFMT_COPST_CODE \
1114   length = 4; \
1115   word_1 = GETIMEMUHI (current_cpu, pc + 2); \
1116   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
1117   f_ccc = (0|(EXTRACT_MSB0_UINT (word_1, 16, 0, 8) << 0)); \
1118   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
1119   f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
1120   f_CRj = (0|(EXTRACT_MSB0_UINT (word_1, 16, 8, 4) << 0)); \
1121   f_u4c = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
1122   f_Ric = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 16) << 0)); \
1123
1124 #define EXTRACT_IFMT_ADDSP_VARS \
1125   /* Instruction fields.  */ \
1126   UINT f_op1; \
1127   UINT f_op2; \
1128   SI f_s10; \
1129   unsigned int length;
1130 #define EXTRACT_IFMT_ADDSP_CODE \
1131   length = 2; \
1132   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
1133   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
1134   f_s10 = ((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2)); \
1135
1136 #define EXTRACT_IFMT_LDM0_VARS \
1137   /* Instruction fields.  */ \
1138   UINT f_op1; \
1139   UINT f_op2; \
1140   UINT f_reglist_low_ld; \
1141   unsigned int length;
1142 #define EXTRACT_IFMT_LDM0_CODE \
1143   length = 2; \
1144   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
1145   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
1146   f_reglist_low_ld = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
1147
1148 #define EXTRACT_IFMT_LDM1_VARS \
1149   /* Instruction fields.  */ \
1150   UINT f_op1; \
1151   UINT f_op2; \
1152   UINT f_reglist_hi_ld; \
1153   unsigned int length;
1154 #define EXTRACT_IFMT_LDM1_CODE \
1155   length = 2; \
1156   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
1157   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
1158   f_reglist_hi_ld = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
1159
1160 #define EXTRACT_IFMT_STM0_VARS \
1161   /* Instruction fields.  */ \
1162   UINT f_op1; \
1163   UINT f_op2; \
1164   UINT f_reglist_low_st; \
1165   unsigned int length;
1166 #define EXTRACT_IFMT_STM0_CODE \
1167   length = 2; \
1168   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
1169   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
1170   f_reglist_low_st = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
1171
1172 #define EXTRACT_IFMT_STM1_VARS \
1173   /* Instruction fields.  */ \
1174   UINT f_op1; \
1175   UINT f_op2; \
1176   UINT f_reglist_hi_st; \
1177   unsigned int length;
1178 #define EXTRACT_IFMT_STM1_CODE \
1179   length = 2; \
1180   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
1181   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
1182   f_reglist_hi_st = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
1183
1184 #define EXTRACT_IFMT_ENTER_VARS \
1185   /* Instruction fields.  */ \
1186   UINT f_op1; \
1187   UINT f_op2; \
1188   USI f_u10; \
1189   unsigned int length;
1190 #define EXTRACT_IFMT_ENTER_CODE \
1191   length = 2; \
1192   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
1193   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
1194   f_u10 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); \
1195
1196 /* Collection of various things for the trace handler to use.  */
1197
1198 typedef struct trace_record {
1199   IADDR pc;
1200   /* FIXME:wip */
1201 } TRACE_RECORD;
1202
1203 #endif /* CPU_FR30BF_H */