]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/frv/profile-fr400.c
1 /* frv simulator fr400 dependent profiling code.
3 Copyright (C) 2001-2021 Free Software Foundation, Inc.
6 This file is part of the GNU simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 /* This must come before any other includes. */
25 #define WANT_CPU_FRVBF
30 #if WITH_PROFILE_MODEL_P
33 #include "profile-fr400.h"
35 /* These functions get and set flags representing the use of
36 registers/resources. */
37 static void set_use_not_fp_load (SIM_CPU
*, INT
);
38 static void set_use_not_media_p4 (SIM_CPU
*, INT
);
39 static void set_use_not_media_p6 (SIM_CPU
*, INT
);
41 static void set_acc_use_not_media_p2 (SIM_CPU
*, INT
);
42 static void set_acc_use_not_media_p4 (SIM_CPU
*, INT
);
45 fr400_reset_gr_flags (SIM_CPU
*cpu
, INT fr
)
47 set_use_not_gr_complex (cpu
, fr
);
51 fr400_reset_fr_flags (SIM_CPU
*cpu
, INT fr
)
53 set_use_not_fp_load (cpu
, fr
);
54 set_use_not_media_p4 (cpu
, fr
);
55 set_use_not_media_p6 (cpu
, fr
);
59 fr400_reset_acc_flags (SIM_CPU
*cpu
, INT acc
)
61 set_acc_use_not_media_p2 (cpu
, acc
);
62 set_acc_use_not_media_p4 (cpu
, acc
);
66 set_use_is_fp_load (SIM_CPU
*cpu
, INT fr
, INT fr_double
)
68 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
71 fr400_reset_fr_flags (cpu
, fr
);
72 d
->cur_fp_load
|= (((DI
)1) << fr
);
76 fr400_reset_fr_flags (cpu
, fr_double
);
77 d
->cur_fp_load
|= (((DI
)1) << fr_double
);
80 fr400_reset_fr_flags (cpu
, fr_double
+ 1);
81 d
->cur_fp_load
|= (((DI
)1) << (fr_double
+ 1));
88 set_use_not_fp_load (SIM_CPU
*cpu
, INT fr
)
90 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
92 d
->cur_fp_load
&= ~(((DI
)1) << fr
);
96 use_is_fp_load (SIM_CPU
*cpu
, INT fr
)
98 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
100 return (d
->prev_fp_load
>> fr
) & 1;
105 set_acc_use_is_media_p2 (SIM_CPU
*cpu
, INT acc
)
107 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
110 fr400_reset_acc_flags (cpu
, acc
);
111 d
->cur_acc_p2
|= (((DI
)1) << acc
);
116 set_acc_use_not_media_p2 (SIM_CPU
*cpu
, INT acc
)
118 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
120 d
->cur_acc_p2
&= ~(((DI
)1) << acc
);
124 acc_use_is_media_p2 (SIM_CPU
*cpu
, INT acc
)
126 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
128 return d
->cur_acc_p2
& (((DI
)1) << acc
);
133 set_use_is_media_p4 (SIM_CPU
*cpu
, INT fr
)
135 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
138 fr400_reset_fr_flags (cpu
, fr
);
139 d
->cur_fr_p4
|= (((DI
)1) << fr
);
144 set_use_not_media_p4 (SIM_CPU
*cpu
, INT fr
)
146 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
148 d
->cur_fr_p4
&= ~(((DI
)1) << fr
);
152 use_is_media_p4 (SIM_CPU
*cpu
, INT fr
)
154 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
156 return d
->cur_fr_p4
& (((DI
)1) << fr
);
161 set_acc_use_is_media_p4 (SIM_CPU
*cpu
, INT acc
)
163 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
166 fr400_reset_acc_flags (cpu
, acc
);
167 d
->cur_acc_p4
|= (((DI
)1) << acc
);
172 set_acc_use_not_media_p4 (SIM_CPU
*cpu
, INT acc
)
174 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
176 d
->cur_acc_p4
&= ~(((DI
)1) << acc
);
180 acc_use_is_media_p4 (SIM_CPU
*cpu
, INT acc
)
182 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
184 return d
->cur_acc_p4
& (((DI
)1) << acc
);
189 set_use_is_media_p6 (SIM_CPU
*cpu
, INT fr
)
191 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
194 fr400_reset_fr_flags (cpu
, fr
);
195 d
->cur_fr_p6
|= (((DI
)1) << fr
);
200 set_use_not_media_p6 (SIM_CPU
*cpu
, INT fr
)
202 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
204 d
->cur_fr_p6
&= ~(((DI
)1) << fr
);
208 use_is_media_p6 (SIM_CPU
*cpu
, INT fr
)
210 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
212 return d
->cur_fr_p6
& (((DI
)1) << fr
);
216 /* Initialize cycle counting for an insn.
217 FIRST_P is non-zero if this is the first insn in a set of parallel
220 fr400_model_insn_before (SIM_CPU
*cpu
, int first_p
)
224 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
225 FRV_PROFILE_STATE
*ps
= CPU_PROFILE_STATE (cpu
);
226 ps
->cur_gr_complex
= ps
->prev_gr_complex
;
227 d
->cur_fp_load
= d
->prev_fp_load
;
228 d
->cur_fr_p4
= d
->prev_fr_p4
;
229 d
->cur_fr_p6
= d
->prev_fr_p6
;
230 d
->cur_acc_p2
= d
->prev_acc_p2
;
231 d
->cur_acc_p4
= d
->prev_acc_p4
;
235 /* Record the cycles computed for an insn.
236 LAST_P is non-zero if this is the last insn in a set of parallel insns,
237 and we update the total cycle count.
238 CYCLES is the cycle count of the insn. */
240 fr400_model_insn_after (SIM_CPU
*cpu
, int last_p
, int cycles
)
244 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
245 FRV_PROFILE_STATE
*ps
= CPU_PROFILE_STATE (cpu
);
246 ps
->prev_gr_complex
= ps
->cur_gr_complex
;
247 d
->prev_fp_load
= d
->cur_fp_load
;
248 d
->prev_fr_p4
= d
->cur_fr_p4
;
249 d
->prev_fr_p6
= d
->cur_fr_p6
;
250 d
->prev_acc_p2
= d
->cur_acc_p2
;
251 d
->prev_acc_p4
= d
->cur_acc_p4
;
256 frvbf_model_fr400_u_exec (SIM_CPU
*cpu
, const IDESC
*idesc
,
257 int unit_num
, int referenced
)
259 return idesc
->timing
->units
[unit_num
].done
;
263 frvbf_model_fr400_u_integer (SIM_CPU
*cpu
, const IDESC
*idesc
,
264 int unit_num
, int referenced
,
265 INT in_GRi
, INT in_GRj
, INT out_GRk
,
268 /* Modelling for this unit is the same as for fr500. */
269 return frvbf_model_fr500_u_integer (cpu
, idesc
, unit_num
, referenced
,
270 in_GRi
, in_GRj
, out_GRk
, out_ICCi_1
);
274 frvbf_model_fr400_u_imul (SIM_CPU
*cpu
, const IDESC
*idesc
,
275 int unit_num
, int referenced
,
276 INT in_GRi
, INT in_GRj
, INT out_GRk
, INT out_ICCi_1
)
278 /* Modelling for this unit is the same as for fr500. */
279 return frvbf_model_fr500_u_imul (cpu
, idesc
, unit_num
, referenced
,
280 in_GRi
, in_GRj
, out_GRk
, out_ICCi_1
);
284 frvbf_model_fr400_u_idiv (SIM_CPU
*cpu
, const IDESC
*idesc
,
285 int unit_num
, int referenced
,
286 INT in_GRi
, INT in_GRj
, INT out_GRk
, INT out_ICCi_1
)
292 /* icc0-icc4 are the upper 4 fields of the CCR. */
296 vliw
= CPU_VLIW (cpu
);
297 slot
= vliw
->next_slot
- 1;
298 slot
= (*vliw
->current_vliw
)[slot
] - UNIT_I0
;
300 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
302 /* The entire VLIW insn must wait if there is a dependency on a register
303 which is not ready yet.
304 The latency of the registers may be less than previously recorded,
305 depending on how they were used previously.
306 See Table 13-8 in the LSI. */
307 if (in_GRi
!= out_GRk
&& in_GRi
>= 0)
309 if (use_is_gr_complex (cpu
, in_GRi
))
310 decrease_GR_busy (cpu
, in_GRi
, 1);
312 if (in_GRj
!= out_GRk
&& in_GRj
!= in_GRi
&& in_GRj
>= 0)
314 if (use_is_gr_complex (cpu
, in_GRj
))
315 decrease_GR_busy (cpu
, in_GRj
, 1);
317 vliw_wait_for_GR (cpu
, in_GRi
);
318 vliw_wait_for_GR (cpu
, in_GRj
);
319 vliw_wait_for_GR (cpu
, out_GRk
);
320 vliw_wait_for_CCR (cpu
, out_ICCi_1
);
321 vliw_wait_for_idiv_resource (cpu
, slot
);
322 handle_resource_wait (cpu
);
323 load_wait_for_GR (cpu
, in_GRi
);
324 load_wait_for_GR (cpu
, in_GRj
);
325 load_wait_for_GR (cpu
, out_GRk
);
326 trace_vliw_wait_cycles (cpu
);
330 /* GRk has a latency of 19 cycles! */
331 cycles
= idesc
->timing
->units
[unit_num
].done
;
332 update_GR_latency (cpu
, out_GRk
, cycles
+ 19);
333 set_use_is_gr_complex (cpu
, out_GRk
);
335 /* ICCi_1 has a latency of 18 cycles. */
336 update_CCR_latency (cpu
, out_ICCi_1
, cycles
+ 18);
338 /* the idiv resource has a latency of 18 cycles! */
339 update_idiv_resource_latency (cpu
, slot
, cycles
+ 18);
345 frvbf_model_fr400_u_branch (SIM_CPU
*cpu
, const IDESC
*idesc
,
346 int unit_num
, int referenced
,
347 INT in_GRi
, INT in_GRj
,
348 INT in_ICCi_2
, INT in_ICCi_3
)
350 #define BRANCH_PREDICTED(ps) ((ps)->branch_hint & 2)
351 FRV_PROFILE_STATE
*ps
;
354 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
356 /* Modelling for this unit is the same as for fr500 in pass 1. */
357 return frvbf_model_fr500_u_branch (cpu
, idesc
, unit_num
, referenced
,
358 in_GRi
, in_GRj
, in_ICCi_2
, in_ICCi_3
);
361 cycles
= idesc
->timing
->units
[unit_num
].done
;
363 /* Compute the branch penalty, based on the the prediction and the out
364 come. When counting branches taken or not taken, don't consider branches
365 after the first taken branch in a vliw insn. */
366 ps
= CPU_PROFILE_STATE (cpu
);
367 if (! ps
->vliw_branch_taken
)
370 /* (1 << 4): The pc is the 5th element in inputs, outputs.
371 ??? can be cleaned up */
372 PROFILE_DATA
*p
= CPU_PROFILE_DATA (cpu
);
373 int taken
= (referenced
& (1 << 4)) != 0;
376 ++PROFILE_MODEL_TAKEN_COUNT (p
);
377 ps
->vliw_branch_taken
= 1;
378 if (BRANCH_PREDICTED (ps
))
385 ++PROFILE_MODEL_UNTAKEN_COUNT (p
);
386 if (BRANCH_PREDICTED (ps
))
393 /* Additional 1 cycle penalty if the branch address is not 8 byte
395 if (ps
->branch_address
& 7)
397 update_branch_penalty (cpu
, penalty
);
398 PROFILE_MODEL_CTI_STALL_CYCLES (p
) += penalty
;
406 frvbf_model_fr400_u_trap (SIM_CPU
*cpu
, const IDESC
*idesc
,
407 int unit_num
, int referenced
,
408 INT in_GRi
, INT in_GRj
,
409 INT in_ICCi_2
, INT in_FCCi_2
)
411 /* Modelling for this unit is the same as for fr500. */
412 return frvbf_model_fr500_u_trap (cpu
, idesc
, unit_num
, referenced
,
413 in_GRi
, in_GRj
, in_ICCi_2
, in_FCCi_2
);
417 frvbf_model_fr400_u_check (SIM_CPU
*cpu
, const IDESC
*idesc
,
418 int unit_num
, int referenced
,
419 INT in_ICCi_3
, INT in_FCCi_3
)
421 /* Modelling for this unit is the same as for fr500. */
422 return frvbf_model_fr500_u_check (cpu
, idesc
, unit_num
, referenced
,
423 in_ICCi_3
, in_FCCi_3
);
427 frvbf_model_fr400_u_set_hilo (SIM_CPU
*cpu
, const IDESC
*idesc
,
428 int unit_num
, int referenced
,
429 INT out_GRkhi
, INT out_GRklo
)
431 /* Modelling for this unit is the same as for fr500. */
432 return frvbf_model_fr500_u_set_hilo (cpu
, idesc
, unit_num
, referenced
,
433 out_GRkhi
, out_GRklo
);
437 frvbf_model_fr400_u_gr_load (SIM_CPU
*cpu
, const IDESC
*idesc
,
438 int unit_num
, int referenced
,
439 INT in_GRi
, INT in_GRj
,
440 INT out_GRk
, INT out_GRdoublek
)
442 /* Modelling for this unit is the same as for fr500. */
443 return frvbf_model_fr500_u_gr_load (cpu
, idesc
, unit_num
, referenced
,
444 in_GRi
, in_GRj
, out_GRk
, out_GRdoublek
);
448 frvbf_model_fr400_u_gr_store (SIM_CPU
*cpu
, const IDESC
*idesc
,
449 int unit_num
, int referenced
,
450 INT in_GRi
, INT in_GRj
,
451 INT in_GRk
, INT in_GRdoublek
)
453 /* Modelling for this unit is the same as for fr500. */
454 return frvbf_model_fr500_u_gr_store (cpu
, idesc
, unit_num
, referenced
,
455 in_GRi
, in_GRj
, in_GRk
, in_GRdoublek
);
459 frvbf_model_fr400_u_fr_load (SIM_CPU
*cpu
, const IDESC
*idesc
,
460 int unit_num
, int referenced
,
461 INT in_GRi
, INT in_GRj
,
462 INT out_FRk
, INT out_FRdoublek
)
466 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
468 /* Pass 1 is the same as for fr500. */
469 return frvbf_model_fr500_u_fr_load (cpu
, idesc
, unit_num
, referenced
,
470 in_GRi
, in_GRj
, out_FRk
,
474 cycles
= idesc
->timing
->units
[unit_num
].done
;
476 /* The latency of FRk for a load will depend on how long it takes to retrieve
477 the the data from the cache or memory. */
478 update_FR_latency_for_load (cpu
, out_FRk
, cycles
);
479 update_FRdouble_latency_for_load (cpu
, out_FRdoublek
, cycles
);
481 set_use_is_fp_load (cpu
, out_FRk
, out_FRdoublek
);
487 frvbf_model_fr400_u_fr_store (SIM_CPU
*cpu
, const IDESC
*idesc
,
488 int unit_num
, int referenced
,
489 INT in_GRi
, INT in_GRj
,
490 INT in_FRk
, INT in_FRdoublek
)
494 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
496 /* The entire VLIW insn must wait if there is a dependency on a register
497 which is not ready yet.
498 The latency of the registers may be less than previously recorded,
499 depending on how they were used previously.
500 See Table 13-8 in the LSI. */
503 if (use_is_gr_complex (cpu
, in_GRi
))
504 decrease_GR_busy (cpu
, in_GRi
, 1);
506 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
508 if (use_is_gr_complex (cpu
, in_GRj
))
509 decrease_GR_busy (cpu
, in_GRj
, 1);
513 if (use_is_media_p4 (cpu
, in_FRk
) || use_is_media_p6 (cpu
, in_FRk
))
514 decrease_FR_busy (cpu
, in_FRk
, 1);
516 enforce_full_fr_latency (cpu
, in_FRk
);
518 vliw_wait_for_GR (cpu
, in_GRi
);
519 vliw_wait_for_GR (cpu
, in_GRj
);
520 vliw_wait_for_FR (cpu
, in_FRk
);
521 vliw_wait_for_FRdouble (cpu
, in_FRdoublek
);
522 handle_resource_wait (cpu
);
523 load_wait_for_GR (cpu
, in_GRi
);
524 load_wait_for_GR (cpu
, in_GRj
);
525 load_wait_for_FR (cpu
, in_FRk
);
526 load_wait_for_FRdouble (cpu
, in_FRdoublek
);
527 trace_vliw_wait_cycles (cpu
);
531 cycles
= idesc
->timing
->units
[unit_num
].done
;
537 frvbf_model_fr400_u_swap (SIM_CPU
*cpu
, const IDESC
*idesc
,
538 int unit_num
, int referenced
,
539 INT in_GRi
, INT in_GRj
, INT out_GRk
)
541 /* Modelling for this unit is the same as for fr500. */
542 return frvbf_model_fr500_u_swap (cpu
, idesc
, unit_num
, referenced
,
543 in_GRi
, in_GRj
, out_GRk
);
547 frvbf_model_fr400_u_fr2gr (SIM_CPU
*cpu
, const IDESC
*idesc
,
548 int unit_num
, int referenced
,
549 INT in_FRk
, INT out_GRj
)
553 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
555 /* The entire VLIW insn must wait if there is a dependency on a register
556 which is not ready yet.
557 The latency of the registers may be less than previously recorded,
558 depending on how they were used previously.
559 See Table 13-8 in the LSI. */
562 if (use_is_media_p4 (cpu
, in_FRk
) || use_is_media_p6 (cpu
, in_FRk
))
563 decrease_FR_busy (cpu
, in_FRk
, 1);
565 enforce_full_fr_latency (cpu
, in_FRk
);
567 vliw_wait_for_FR (cpu
, in_FRk
);
568 vliw_wait_for_GR (cpu
, out_GRj
);
569 handle_resource_wait (cpu
);
570 load_wait_for_FR (cpu
, in_FRk
);
571 load_wait_for_GR (cpu
, out_GRj
);
572 trace_vliw_wait_cycles (cpu
);
576 /* The latency of GRj is 2 cycles. */
577 cycles
= idesc
->timing
->units
[unit_num
].done
;
578 update_GR_latency (cpu
, out_GRj
, cycles
+ 2);
579 set_use_is_gr_complex (cpu
, out_GRj
);
585 frvbf_model_fr400_u_spr2gr (SIM_CPU
*cpu
, const IDESC
*idesc
,
586 int unit_num
, int referenced
,
587 INT in_spr
, INT out_GRj
)
589 /* Modelling for this unit is the same as for fr500. */
590 return frvbf_model_fr500_u_spr2gr (cpu
, idesc
, unit_num
, referenced
,
595 frvbf_model_fr400_u_gr2fr (SIM_CPU
*cpu
, const IDESC
*idesc
,
596 int unit_num
, int referenced
,
597 INT in_GRj
, INT out_FRk
)
601 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
603 /* Pass 1 is the same as for fr500. */
604 frvbf_model_fr500_u_gr2fr (cpu
, idesc
, unit_num
, referenced
,
608 /* The latency of FRk is 1 cycles. */
609 cycles
= idesc
->timing
->units
[unit_num
].done
;
610 update_FR_latency (cpu
, out_FRk
, cycles
+ 1);
616 frvbf_model_fr400_u_gr2spr (SIM_CPU
*cpu
, const IDESC
*idesc
,
617 int unit_num
, int referenced
,
618 INT in_GRj
, INT out_spr
)
620 /* Modelling for this unit is the same as for fr500. */
621 return frvbf_model_fr500_u_gr2spr (cpu
, idesc
, unit_num
, referenced
,
626 frvbf_model_fr400_u_media_1 (SIM_CPU
*cpu
, const IDESC
*idesc
,
627 int unit_num
, int referenced
,
628 INT in_FRi
, INT in_FRj
,
632 FRV_PROFILE_STATE
*ps
;
633 const CGEN_INSN
*insn
;
634 int busy_adjustment
[] = {0, 0};
637 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
640 /* The preprocessing can execute right away. */
641 cycles
= idesc
->timing
->units
[unit_num
].done
;
643 ps
= CPU_PROFILE_STATE (cpu
);
646 /* The latency of the registers may be less than previously recorded,
647 depending on how they were used previously.
648 See Table 13-8 in the LSI. */
651 if (use_is_fp_load (cpu
, in_FRi
))
653 busy_adjustment
[0] = 1;
654 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
657 enforce_full_fr_latency (cpu
, in_FRi
);
659 if (in_FRj
>= 0 && in_FRj
!= in_FRi
)
661 if (use_is_fp_load (cpu
, in_FRj
))
663 busy_adjustment
[1] = 1;
664 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[1]);
667 enforce_full_fr_latency (cpu
, in_FRj
);
670 /* The post processing must wait if there is a dependency on a FR
671 which is not ready yet. */
672 ps
->post_wait
= cycles
;
673 post_wait_for_FR (cpu
, in_FRi
);
674 post_wait_for_FR (cpu
, in_FRj
);
675 post_wait_for_FR (cpu
, out_FRk
);
677 /* Restore the busy cycles of the registers we used. */
680 fr
[in_FRi
] += busy_adjustment
[0];
682 fr
[in_FRj
] += busy_adjustment
[1];
684 /* The latency of the output register will be at least the latency of the
685 other inputs. Once initiated, post-processing has no latency. */
688 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
689 update_FR_ptime (cpu
, out_FRk
, 0);
696 frvbf_model_fr400_u_media_1_quad (SIM_CPU
*cpu
, const IDESC
*idesc
,
697 int unit_num
, int referenced
,
698 INT in_FRi
, INT in_FRj
,
705 FRV_PROFILE_STATE
*ps
;
706 int busy_adjustment
[] = {0, 0, 0, 0};
709 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
712 /* The preprocessing can execute right away. */
713 cycles
= idesc
->timing
->units
[unit_num
].done
;
715 ps
= CPU_PROFILE_STATE (cpu
);
716 dual_FRi
= DUAL_REG (in_FRi
);
717 dual_FRj
= DUAL_REG (in_FRj
);
718 dual_FRk
= DUAL_REG (out_FRk
);
720 /* The latency of the registers may be less than previously recorded,
721 depending on how they were used previously.
722 See Table 13-8 in the LSI. */
723 if (use_is_fp_load (cpu
, in_FRi
))
725 busy_adjustment
[0] = 1;
726 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
729 enforce_full_fr_latency (cpu
, in_FRi
);
730 if (dual_FRi
>= 0 && use_is_fp_load (cpu
, dual_FRi
))
732 busy_adjustment
[1] = 1;
733 decrease_FR_busy (cpu
, dual_FRi
, busy_adjustment
[1]);
736 enforce_full_fr_latency (cpu
, dual_FRi
);
737 if (in_FRj
!= in_FRi
)
739 if (use_is_fp_load (cpu
, in_FRj
))
741 busy_adjustment
[2] = 1;
742 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[2]);
745 enforce_full_fr_latency (cpu
, in_FRj
);
746 if (dual_FRj
>= 0 && use_is_fp_load (cpu
, dual_FRj
))
748 busy_adjustment
[3] = 1;
749 decrease_FR_busy (cpu
, dual_FRj
, busy_adjustment
[3]);
752 enforce_full_fr_latency (cpu
, dual_FRj
);
755 /* The post processing must wait if there is a dependency on a FR
756 which is not ready yet. */
757 ps
->post_wait
= cycles
;
758 post_wait_for_FR (cpu
, in_FRi
);
759 post_wait_for_FR (cpu
, dual_FRi
);
760 post_wait_for_FR (cpu
, in_FRj
);
761 post_wait_for_FR (cpu
, dual_FRj
);
762 post_wait_for_FR (cpu
, out_FRk
);
763 post_wait_for_FR (cpu
, dual_FRk
);
765 /* Restore the busy cycles of the registers we used. */
767 fr
[in_FRi
] += busy_adjustment
[0];
769 fr
[dual_FRi
] += busy_adjustment
[1];
770 fr
[in_FRj
] += busy_adjustment
[2];
772 fr
[dual_FRj
] += busy_adjustment
[3];
774 /* The latency of the output register will be at least the latency of the
776 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
778 /* Once initiated, post-processing has no latency. */
779 update_FR_ptime (cpu
, out_FRk
, 0);
783 update_FR_latency (cpu
, dual_FRk
, ps
->post_wait
);
784 update_FR_ptime (cpu
, dual_FRk
, 0);
791 frvbf_model_fr400_u_media_hilo (SIM_CPU
*cpu
, const IDESC
*idesc
,
792 int unit_num
, int referenced
,
793 INT out_FRkhi
, INT out_FRklo
)
796 FRV_PROFILE_STATE
*ps
;
798 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
801 /* The preprocessing can execute right away. */
802 cycles
= idesc
->timing
->units
[unit_num
].done
;
804 ps
= CPU_PROFILE_STATE (cpu
);
806 /* The post processing must wait if there is a dependency on a FR
807 which is not ready yet. */
808 ps
->post_wait
= cycles
;
809 post_wait_for_FR (cpu
, out_FRkhi
);
810 post_wait_for_FR (cpu
, out_FRklo
);
812 /* The latency of the output register will be at least the latency of the
813 other inputs. Once initiated, post-processing has no latency. */
816 update_FR_latency (cpu
, out_FRkhi
, ps
->post_wait
);
817 update_FR_ptime (cpu
, out_FRkhi
, 0);
821 update_FR_latency (cpu
, out_FRklo
, ps
->post_wait
);
822 update_FR_ptime (cpu
, out_FRklo
, 0);
829 frvbf_model_fr400_u_media_2 (SIM_CPU
*cpu
, const IDESC
*idesc
,
830 int unit_num
, int referenced
,
831 INT in_FRi
, INT in_FRj
,
832 INT out_ACC40Sk
, INT out_ACC40Uk
)
837 FRV_PROFILE_STATE
*ps
;
838 int busy_adjustment
[] = {0, 0, 0, 0, 0, 0};
842 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
845 /* The preprocessing can execute right away. */
846 cycles
= idesc
->timing
->units
[unit_num
].done
;
848 ps
= CPU_PROFILE_STATE (cpu
);
849 dual_ACC40Sk
= DUAL_REG (out_ACC40Sk
);
850 dual_ACC40Uk
= DUAL_REG (out_ACC40Uk
);
852 /* The latency of the registers may be less than previously recorded,
853 depending on how they were used previously.
854 See Table 13-8 in the LSI. */
857 if (use_is_fp_load (cpu
, in_FRi
))
859 busy_adjustment
[0] = 1;
860 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
863 enforce_full_fr_latency (cpu
, in_FRi
);
865 if (in_FRj
>= 0 && in_FRj
!= in_FRi
)
867 if (use_is_fp_load (cpu
, in_FRj
))
869 busy_adjustment
[1] = 1;
870 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[1]);
873 enforce_full_fr_latency (cpu
, in_FRj
);
875 if (out_ACC40Sk
>= 0)
877 if (acc_use_is_media_p2 (cpu
, out_ACC40Sk
))
879 busy_adjustment
[2] = 1;
880 decrease_ACC_busy (cpu
, out_ACC40Sk
, busy_adjustment
[2]);
883 if (dual_ACC40Sk
>= 0)
885 if (acc_use_is_media_p2 (cpu
, dual_ACC40Sk
))
887 busy_adjustment
[3] = 1;
888 decrease_ACC_busy (cpu
, dual_ACC40Sk
, busy_adjustment
[3]);
891 if (out_ACC40Uk
>= 0)
893 if (acc_use_is_media_p2 (cpu
, out_ACC40Uk
))
895 busy_adjustment
[4] = 1;
896 decrease_ACC_busy (cpu
, out_ACC40Uk
, busy_adjustment
[4]);
899 if (dual_ACC40Uk
>= 0)
901 if (acc_use_is_media_p2 (cpu
, dual_ACC40Uk
))
903 busy_adjustment
[5] = 1;
904 decrease_ACC_busy (cpu
, dual_ACC40Uk
, busy_adjustment
[5]);
908 /* The post processing must wait if there is a dependency on a FR
909 which is not ready yet. */
910 ps
->post_wait
= cycles
;
911 post_wait_for_FR (cpu
, in_FRi
);
912 post_wait_for_FR (cpu
, in_FRj
);
913 post_wait_for_ACC (cpu
, out_ACC40Sk
);
914 post_wait_for_ACC (cpu
, dual_ACC40Sk
);
915 post_wait_for_ACC (cpu
, out_ACC40Uk
);
916 post_wait_for_ACC (cpu
, dual_ACC40Uk
);
918 /* Restore the busy cycles of the registers we used. */
921 fr
[in_FRi
] += busy_adjustment
[0];
922 fr
[in_FRj
] += busy_adjustment
[1];
923 if (out_ACC40Sk
>= 0)
924 acc
[out_ACC40Sk
] += busy_adjustment
[2];
925 if (dual_ACC40Sk
>= 0)
926 acc
[dual_ACC40Sk
] += busy_adjustment
[3];
927 if (out_ACC40Uk
>= 0)
928 acc
[out_ACC40Uk
] += busy_adjustment
[4];
929 if (dual_ACC40Uk
>= 0)
930 acc
[dual_ACC40Uk
] += busy_adjustment
[5];
932 /* The latency of the output register will be at least the latency of the
933 other inputs. Once initiated, post-processing will take 1 cycles. */
934 if (out_ACC40Sk
>= 0)
936 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
937 set_acc_use_is_media_p2 (cpu
, out_ACC40Sk
);
939 if (dual_ACC40Sk
>= 0)
941 update_ACC_latency (cpu
, dual_ACC40Sk
, ps
->post_wait
+ 1);
942 set_acc_use_is_media_p2 (cpu
, dual_ACC40Sk
);
944 if (out_ACC40Uk
>= 0)
946 update_ACC_latency (cpu
, out_ACC40Uk
, ps
->post_wait
+ 1);
947 set_acc_use_is_media_p2 (cpu
, out_ACC40Uk
);
949 if (dual_ACC40Uk
>= 0)
951 update_ACC_latency (cpu
, dual_ACC40Uk
, ps
->post_wait
+ 1);
952 set_acc_use_is_media_p2 (cpu
, dual_ACC40Uk
);
959 frvbf_model_fr400_u_media_2_quad (SIM_CPU
*cpu
, const IDESC
*idesc
,
960 int unit_num
, int referenced
,
961 INT in_FRi
, INT in_FRj
,
962 INT out_ACC40Sk
, INT out_ACC40Uk
)
973 FRV_PROFILE_STATE
*ps
;
974 int busy_adjustment
[] = {0, 0, 0, 0, 0, 0, 0 ,0};
978 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
981 /* The preprocessing can execute right away. */
982 cycles
= idesc
->timing
->units
[unit_num
].done
;
984 dual_FRi
= DUAL_REG (in_FRi
);
985 dual_FRj
= DUAL_REG (in_FRj
);
986 ACC40Sk_1
= DUAL_REG (out_ACC40Sk
);
987 ACC40Sk_2
= DUAL_REG (ACC40Sk_1
);
988 ACC40Sk_3
= DUAL_REG (ACC40Sk_2
);
989 ACC40Uk_1
= DUAL_REG (out_ACC40Uk
);
990 ACC40Uk_2
= DUAL_REG (ACC40Uk_1
);
991 ACC40Uk_3
= DUAL_REG (ACC40Uk_2
);
993 ps
= CPU_PROFILE_STATE (cpu
);
994 /* The latency of the registers may be less than previously recorded,
995 depending on how they were used previously.
996 See Table 13-8 in the LSI. */
997 if (use_is_fp_load (cpu
, in_FRi
))
999 busy_adjustment
[0] = 1;
1000 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
1003 enforce_full_fr_latency (cpu
, in_FRi
);
1004 if (dual_FRi
>= 0 && use_is_fp_load (cpu
, dual_FRi
))
1006 busy_adjustment
[1] = 1;
1007 decrease_FR_busy (cpu
, dual_FRi
, busy_adjustment
[1]);
1010 enforce_full_fr_latency (cpu
, dual_FRi
);
1011 if (in_FRj
!= in_FRi
)
1013 if (use_is_fp_load (cpu
, in_FRj
))
1015 busy_adjustment
[2] = 1;
1016 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[2]);
1019 enforce_full_fr_latency (cpu
, in_FRj
);
1020 if (dual_FRj
>= 0 && use_is_fp_load (cpu
, dual_FRj
))
1022 busy_adjustment
[3] = 1;
1023 decrease_FR_busy (cpu
, dual_FRj
, busy_adjustment
[3]);
1026 enforce_full_fr_latency (cpu
, dual_FRj
);
1028 if (out_ACC40Sk
>= 0)
1030 if (acc_use_is_media_p2 (cpu
, out_ACC40Sk
))
1032 busy_adjustment
[4] = 1;
1033 decrease_ACC_busy (cpu
, out_ACC40Sk
, busy_adjustment
[4]);
1037 if (acc_use_is_media_p2 (cpu
, ACC40Sk_1
))
1039 busy_adjustment
[5] = 1;
1040 decrease_ACC_busy (cpu
, ACC40Sk_1
, busy_adjustment
[5]);
1045 if (acc_use_is_media_p2 (cpu
, ACC40Sk_2
))
1047 busy_adjustment
[6] = 1;
1048 decrease_ACC_busy (cpu
, ACC40Sk_2
, busy_adjustment
[6]);
1053 if (acc_use_is_media_p2 (cpu
, ACC40Sk_3
))
1055 busy_adjustment
[7] = 1;
1056 decrease_ACC_busy (cpu
, ACC40Sk_3
, busy_adjustment
[7]);
1060 else if (out_ACC40Uk
>= 0)
1062 if (acc_use_is_media_p2 (cpu
, out_ACC40Uk
))
1064 busy_adjustment
[4] = 1;
1065 decrease_ACC_busy (cpu
, out_ACC40Uk
, busy_adjustment
[4]);
1069 if (acc_use_is_media_p2 (cpu
, ACC40Uk_1
))
1071 busy_adjustment
[5] = 1;
1072 decrease_ACC_busy (cpu
, ACC40Uk_1
, busy_adjustment
[5]);
1077 if (acc_use_is_media_p2 (cpu
, ACC40Uk_2
))
1079 busy_adjustment
[6] = 1;
1080 decrease_ACC_busy (cpu
, ACC40Uk_2
, busy_adjustment
[6]);
1085 if (acc_use_is_media_p2 (cpu
, ACC40Uk_3
))
1087 busy_adjustment
[7] = 1;
1088 decrease_ACC_busy (cpu
, ACC40Uk_3
, busy_adjustment
[7]);
1093 /* The post processing must wait if there is a dependency on a FR
1094 which is not ready yet. */
1095 ps
->post_wait
= cycles
;
1096 post_wait_for_FR (cpu
, in_FRi
);
1097 post_wait_for_FR (cpu
, dual_FRi
);
1098 post_wait_for_FR (cpu
, in_FRj
);
1099 post_wait_for_FR (cpu
, dual_FRj
);
1100 post_wait_for_ACC (cpu
, out_ACC40Sk
);
1101 post_wait_for_ACC (cpu
, ACC40Sk_1
);
1102 post_wait_for_ACC (cpu
, ACC40Sk_2
);
1103 post_wait_for_ACC (cpu
, ACC40Sk_3
);
1104 post_wait_for_ACC (cpu
, out_ACC40Uk
);
1105 post_wait_for_ACC (cpu
, ACC40Uk_1
);
1106 post_wait_for_ACC (cpu
, ACC40Uk_2
);
1107 post_wait_for_ACC (cpu
, ACC40Uk_3
);
1109 /* Restore the busy cycles of the registers we used. */
1112 fr
[in_FRi
] += busy_adjustment
[0];
1114 fr
[dual_FRi
] += busy_adjustment
[1];
1115 fr
[in_FRj
] += busy_adjustment
[2];
1117 fr
[dual_FRj
] += busy_adjustment
[3];
1118 if (out_ACC40Sk
>= 0)
1120 acc
[out_ACC40Sk
] += busy_adjustment
[4];
1122 acc
[ACC40Sk_1
] += busy_adjustment
[5];
1124 acc
[ACC40Sk_2
] += busy_adjustment
[6];
1126 acc
[ACC40Sk_3
] += busy_adjustment
[7];
1128 else if (out_ACC40Uk
>= 0)
1130 acc
[out_ACC40Uk
] += busy_adjustment
[4];
1132 acc
[ACC40Uk_1
] += busy_adjustment
[5];
1134 acc
[ACC40Uk_2
] += busy_adjustment
[6];
1136 acc
[ACC40Uk_3
] += busy_adjustment
[7];
1139 /* The latency of the output register will be at least the latency of the
1140 other inputs. Once initiated, post-processing will take 1 cycle. */
1141 if (out_ACC40Sk
>= 0)
1143 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
1145 set_acc_use_is_media_p2 (cpu
, out_ACC40Sk
);
1148 update_ACC_latency (cpu
, ACC40Sk_1
, ps
->post_wait
+ 1);
1150 set_acc_use_is_media_p2 (cpu
, ACC40Sk_1
);
1154 update_ACC_latency (cpu
, ACC40Sk_2
, ps
->post_wait
+ 1);
1156 set_acc_use_is_media_p2 (cpu
, ACC40Sk_2
);
1160 update_ACC_latency (cpu
, ACC40Sk_3
, ps
->post_wait
+ 1);
1162 set_acc_use_is_media_p2 (cpu
, ACC40Sk_3
);
1165 else if (out_ACC40Uk
>= 0)
1167 update_ACC_latency (cpu
, out_ACC40Uk
, ps
->post_wait
+ 1);
1169 set_acc_use_is_media_p2 (cpu
, out_ACC40Uk
);
1172 update_ACC_latency (cpu
, ACC40Uk_1
, ps
->post_wait
+ 1);
1174 set_acc_use_is_media_p2 (cpu
, ACC40Uk_1
);
1178 update_ACC_latency (cpu
, ACC40Uk_2
, ps
->post_wait
+ 1);
1180 set_acc_use_is_media_p2 (cpu
, ACC40Uk_2
);
1184 update_ACC_latency (cpu
, ACC40Uk_3
, ps
->post_wait
+ 1);
1186 set_acc_use_is_media_p2 (cpu
, ACC40Uk_3
);
1194 frvbf_model_fr400_u_media_2_acc (SIM_CPU
*cpu
, const IDESC
*idesc
,
1195 int unit_num
, int referenced
,
1196 INT in_ACC40Si
, INT out_ACC40Sk
)
1200 FRV_PROFILE_STATE
*ps
;
1201 int busy_adjustment
[] = {0, 0, 0};
1204 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1207 /* The preprocessing can execute right away. */
1208 cycles
= idesc
->timing
->units
[unit_num
].done
;
1210 ACC40Si_1
= DUAL_REG (in_ACC40Si
);
1212 ps
= CPU_PROFILE_STATE (cpu
);
1213 /* The latency of the registers may be less than previously recorded,
1214 depending on how they were used previously.
1215 See Table 13-8 in the LSI. */
1216 if (acc_use_is_media_p2 (cpu
, in_ACC40Si
))
1218 busy_adjustment
[0] = 1;
1219 decrease_ACC_busy (cpu
, in_ACC40Si
, busy_adjustment
[0]);
1221 if (ACC40Si_1
>= 0 && acc_use_is_media_p2 (cpu
, ACC40Si_1
))
1223 busy_adjustment
[1] = 1;
1224 decrease_ACC_busy (cpu
, ACC40Si_1
, busy_adjustment
[1]);
1226 if (out_ACC40Sk
!= in_ACC40Si
&& out_ACC40Sk
!= ACC40Si_1
1227 && acc_use_is_media_p2 (cpu
, out_ACC40Sk
))
1229 busy_adjustment
[2] = 1;
1230 decrease_ACC_busy (cpu
, out_ACC40Sk
, busy_adjustment
[2]);
1233 /* The post processing must wait if there is a dependency on a register
1234 which is not ready yet. */
1235 ps
->post_wait
= cycles
;
1236 post_wait_for_ACC (cpu
, in_ACC40Si
);
1237 post_wait_for_ACC (cpu
, ACC40Si_1
);
1238 post_wait_for_ACC (cpu
, out_ACC40Sk
);
1240 /* Restore the busy cycles of the registers we used. */
1242 acc
[in_ACC40Si
] += busy_adjustment
[0];
1244 acc
[ACC40Si_1
] += busy_adjustment
[1];
1245 acc
[out_ACC40Sk
] += busy_adjustment
[2];
1247 /* The latency of the output register will be at least the latency of the
1248 other inputs. Once initiated, post-processing will take 1 cycle. */
1249 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
1250 set_acc_use_is_media_p2 (cpu
, out_ACC40Sk
);
1256 frvbf_model_fr400_u_media_2_acc_dual (SIM_CPU
*cpu
, const IDESC
*idesc
,
1257 int unit_num
, int referenced
,
1258 INT in_ACC40Si
, INT out_ACC40Sk
)
1265 FRV_PROFILE_STATE
*ps
;
1266 int busy_adjustment
[] = {0, 0, 0, 0, 0, 0};
1269 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1272 /* The preprocessing can execute right away. */
1273 cycles
= idesc
->timing
->units
[unit_num
].done
;
1275 ACC40Si_1
= DUAL_REG (in_ACC40Si
);
1276 ACC40Si_2
= DUAL_REG (ACC40Si_1
);
1277 ACC40Si_3
= DUAL_REG (ACC40Si_2
);
1278 ACC40Sk_1
= DUAL_REG (out_ACC40Sk
);
1280 ps
= CPU_PROFILE_STATE (cpu
);
1281 /* The latency of the registers may be less than previously recorded,
1282 depending on how they were used previously.
1283 See Table 13-8 in the LSI. */
1284 if (acc_use_is_media_p2 (cpu
, in_ACC40Si
))
1286 busy_adjustment
[0] = 1;
1287 decrease_ACC_busy (cpu
, in_ACC40Si
, busy_adjustment
[0]);
1289 if (ACC40Si_1
>= 0 && acc_use_is_media_p2 (cpu
, ACC40Si_1
))
1291 busy_adjustment
[1] = 1;
1292 decrease_ACC_busy (cpu
, ACC40Si_1
, busy_adjustment
[1]);
1294 if (ACC40Si_2
>= 0 && acc_use_is_media_p2 (cpu
, ACC40Si_2
))
1296 busy_adjustment
[2] = 1;
1297 decrease_ACC_busy (cpu
, ACC40Si_2
, busy_adjustment
[2]);
1299 if (ACC40Si_3
>= 0 && acc_use_is_media_p2 (cpu
, ACC40Si_3
))
1301 busy_adjustment
[3] = 1;
1302 decrease_ACC_busy (cpu
, ACC40Si_3
, busy_adjustment
[3]);
1304 if (out_ACC40Sk
!= in_ACC40Si
&& out_ACC40Sk
!= ACC40Si_1
1305 && out_ACC40Sk
!= ACC40Si_2
&& out_ACC40Sk
!= ACC40Si_3
)
1307 if (acc_use_is_media_p2 (cpu
, out_ACC40Sk
))
1309 busy_adjustment
[4] = 1;
1310 decrease_ACC_busy (cpu
, out_ACC40Sk
, busy_adjustment
[4]);
1313 if (ACC40Sk_1
!= in_ACC40Si
&& ACC40Sk_1
!= ACC40Si_1
1314 && ACC40Sk_1
!= ACC40Si_2
&& ACC40Sk_1
!= ACC40Si_3
)
1316 if (acc_use_is_media_p2 (cpu
, ACC40Sk_1
))
1318 busy_adjustment
[5] = 1;
1319 decrease_ACC_busy (cpu
, ACC40Sk_1
, busy_adjustment
[5]);
1323 /* The post processing must wait if there is a dependency on a register
1324 which is not ready yet. */
1325 ps
->post_wait
= cycles
;
1326 post_wait_for_ACC (cpu
, in_ACC40Si
);
1327 post_wait_for_ACC (cpu
, ACC40Si_1
);
1328 post_wait_for_ACC (cpu
, ACC40Si_2
);
1329 post_wait_for_ACC (cpu
, ACC40Si_3
);
1330 post_wait_for_ACC (cpu
, out_ACC40Sk
);
1331 post_wait_for_ACC (cpu
, ACC40Sk_1
);
1333 /* Restore the busy cycles of the registers we used. */
1335 acc
[in_ACC40Si
] += busy_adjustment
[0];
1337 acc
[ACC40Si_1
] += busy_adjustment
[1];
1339 acc
[ACC40Si_2
] += busy_adjustment
[2];
1341 acc
[ACC40Si_3
] += busy_adjustment
[3];
1342 acc
[out_ACC40Sk
] += busy_adjustment
[4];
1344 acc
[ACC40Sk_1
] += busy_adjustment
[5];
1346 /* The latency of the output register will be at least the latency of the
1347 other inputs. Once initiated, post-processing will take 1 cycle. */
1348 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
1349 set_acc_use_is_media_p2 (cpu
, out_ACC40Sk
);
1352 update_ACC_latency (cpu
, ACC40Sk_1
, ps
->post_wait
+ 1);
1353 set_acc_use_is_media_p2 (cpu
, ACC40Sk_1
);
1360 frvbf_model_fr400_u_media_2_add_sub (SIM_CPU
*cpu
, const IDESC
*idesc
,
1361 int unit_num
, int referenced
,
1362 INT in_ACC40Si
, INT out_ACC40Sk
)
1367 FRV_PROFILE_STATE
*ps
;
1368 int busy_adjustment
[] = {0, 0, 0, 0};
1371 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1374 /* The preprocessing can execute right away. */
1375 cycles
= idesc
->timing
->units
[unit_num
].done
;
1377 ACC40Si_1
= DUAL_REG (in_ACC40Si
);
1378 ACC40Sk_1
= DUAL_REG (out_ACC40Sk
);
1380 ps
= CPU_PROFILE_STATE (cpu
);
1381 /* The latency of the registers may be less than previously recorded,
1382 depending on how they were used previously.
1383 See Table 13-8 in the LSI. */
1384 if (acc_use_is_media_p2 (cpu
, in_ACC40Si
))
1386 busy_adjustment
[0] = 1;
1387 decrease_ACC_busy (cpu
, in_ACC40Si
, busy_adjustment
[0]);
1389 if (ACC40Si_1
>= 0 && acc_use_is_media_p2 (cpu
, ACC40Si_1
))
1391 busy_adjustment
[1] = 1;
1392 decrease_ACC_busy (cpu
, ACC40Si_1
, busy_adjustment
[1]);
1394 if (out_ACC40Sk
!= in_ACC40Si
&& out_ACC40Sk
!= ACC40Si_1
)
1396 if (acc_use_is_media_p2 (cpu
, out_ACC40Sk
))
1398 busy_adjustment
[2] = 1;
1399 decrease_ACC_busy (cpu
, out_ACC40Sk
, busy_adjustment
[2]);
1402 if (ACC40Sk_1
!= in_ACC40Si
&& ACC40Sk_1
!= ACC40Si_1
)
1404 if (acc_use_is_media_p2 (cpu
, ACC40Sk_1
))
1406 busy_adjustment
[3] = 1;
1407 decrease_ACC_busy (cpu
, ACC40Sk_1
, busy_adjustment
[3]);
1411 /* The post processing must wait if there is a dependency on a register
1412 which is not ready yet. */
1413 ps
->post_wait
= cycles
;
1414 post_wait_for_ACC (cpu
, in_ACC40Si
);
1415 post_wait_for_ACC (cpu
, ACC40Si_1
);
1416 post_wait_for_ACC (cpu
, out_ACC40Sk
);
1417 post_wait_for_ACC (cpu
, ACC40Sk_1
);
1419 /* Restore the busy cycles of the registers we used. */
1421 acc
[in_ACC40Si
] += busy_adjustment
[0];
1423 acc
[ACC40Si_1
] += busy_adjustment
[1];
1424 acc
[out_ACC40Sk
] += busy_adjustment
[2];
1426 acc
[ACC40Sk_1
] += busy_adjustment
[3];
1428 /* The latency of the output register will be at least the latency of the
1429 other inputs. Once initiated, post-processing will take 1 cycle. */
1430 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
1431 set_acc_use_is_media_p2 (cpu
, out_ACC40Sk
);
1434 update_ACC_latency (cpu
, ACC40Sk_1
, ps
->post_wait
+ 1);
1435 set_acc_use_is_media_p2 (cpu
, ACC40Sk_1
);
1442 frvbf_model_fr400_u_media_2_add_sub_dual (SIM_CPU
*cpu
, const IDESC
*idesc
,
1443 int unit_num
, int referenced
,
1444 INT in_ACC40Si
, INT out_ACC40Sk
)
1453 FRV_PROFILE_STATE
*ps
;
1454 int busy_adjustment
[] = {0, 0, 0, 0, 0, 0, 0, 0};
1457 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1460 /* The preprocessing can execute right away. */
1461 cycles
= idesc
->timing
->units
[unit_num
].done
;
1463 ACC40Si_1
= DUAL_REG (in_ACC40Si
);
1464 ACC40Si_2
= DUAL_REG (ACC40Si_1
);
1465 ACC40Si_3
= DUAL_REG (ACC40Si_2
);
1466 ACC40Sk_1
= DUAL_REG (out_ACC40Sk
);
1467 ACC40Sk_2
= DUAL_REG (ACC40Sk_1
);
1468 ACC40Sk_3
= DUAL_REG (ACC40Sk_2
);
1470 ps
= CPU_PROFILE_STATE (cpu
);
1471 /* The latency of the registers may be less than previously recorded,
1472 depending on how they were used previously.
1473 See Table 13-8 in the LSI. */
1474 if (acc_use_is_media_p2 (cpu
, in_ACC40Si
))
1476 busy_adjustment
[0] = 1;
1477 decrease_ACC_busy (cpu
, in_ACC40Si
, busy_adjustment
[0]);
1479 if (ACC40Si_1
>= 0 && acc_use_is_media_p2 (cpu
, ACC40Si_1
))
1481 busy_adjustment
[1] = 1;
1482 decrease_ACC_busy (cpu
, ACC40Si_1
, busy_adjustment
[1]);
1484 if (ACC40Si_2
>= 0 && acc_use_is_media_p2 (cpu
, ACC40Si_2
))
1486 busy_adjustment
[2] = 1;
1487 decrease_ACC_busy (cpu
, ACC40Si_2
, busy_adjustment
[2]);
1489 if (ACC40Si_3
>= 0 && acc_use_is_media_p2 (cpu
, ACC40Si_3
))
1491 busy_adjustment
[3] = 1;
1492 decrease_ACC_busy (cpu
, ACC40Si_3
, busy_adjustment
[3]);
1494 if (out_ACC40Sk
!= in_ACC40Si
&& out_ACC40Sk
!= ACC40Si_1
1495 && out_ACC40Sk
!= ACC40Si_2
&& out_ACC40Sk
!= ACC40Si_3
)
1497 if (acc_use_is_media_p2 (cpu
, out_ACC40Sk
))
1499 busy_adjustment
[4] = 1;
1500 decrease_ACC_busy (cpu
, out_ACC40Sk
, busy_adjustment
[4]);
1503 if (ACC40Sk_1
!= in_ACC40Si
&& ACC40Sk_1
!= ACC40Si_1
1504 && ACC40Sk_1
!= ACC40Si_2
&& ACC40Sk_1
!= ACC40Si_3
)
1506 if (acc_use_is_media_p2 (cpu
, ACC40Sk_1
))
1508 busy_adjustment
[5] = 1;
1509 decrease_ACC_busy (cpu
, ACC40Sk_1
, busy_adjustment
[5]);
1512 if (ACC40Sk_2
!= in_ACC40Si
&& ACC40Sk_2
!= ACC40Si_1
1513 && ACC40Sk_2
!= ACC40Si_2
&& ACC40Sk_2
!= ACC40Si_3
)
1515 if (acc_use_is_media_p2 (cpu
, ACC40Sk_2
))
1517 busy_adjustment
[6] = 1;
1518 decrease_ACC_busy (cpu
, ACC40Sk_2
, busy_adjustment
[6]);
1521 if (ACC40Sk_3
!= in_ACC40Si
&& ACC40Sk_3
!= ACC40Si_1
1522 && ACC40Sk_3
!= ACC40Si_2
&& ACC40Sk_3
!= ACC40Si_3
)
1524 if (acc_use_is_media_p2 (cpu
, ACC40Sk_3
))
1526 busy_adjustment
[7] = 1;
1527 decrease_ACC_busy (cpu
, ACC40Sk_3
, busy_adjustment
[7]);
1531 /* The post processing must wait if there is a dependency on a register
1532 which is not ready yet. */
1533 ps
->post_wait
= cycles
;
1534 post_wait_for_ACC (cpu
, in_ACC40Si
);
1535 post_wait_for_ACC (cpu
, ACC40Si_1
);
1536 post_wait_for_ACC (cpu
, ACC40Si_2
);
1537 post_wait_for_ACC (cpu
, ACC40Si_3
);
1538 post_wait_for_ACC (cpu
, out_ACC40Sk
);
1539 post_wait_for_ACC (cpu
, ACC40Sk_1
);
1540 post_wait_for_ACC (cpu
, ACC40Sk_2
);
1541 post_wait_for_ACC (cpu
, ACC40Sk_3
);
1543 /* Restore the busy cycles of the registers we used. */
1545 acc
[in_ACC40Si
] += busy_adjustment
[0];
1547 acc
[ACC40Si_1
] += busy_adjustment
[1];
1549 acc
[ACC40Si_2
] += busy_adjustment
[2];
1551 acc
[ACC40Si_3
] += busy_adjustment
[3];
1552 acc
[out_ACC40Sk
] += busy_adjustment
[4];
1554 acc
[ACC40Sk_1
] += busy_adjustment
[5];
1556 acc
[ACC40Sk_2
] += busy_adjustment
[6];
1558 acc
[ACC40Sk_3
] += busy_adjustment
[7];
1560 /* The latency of the output register will be at least the latency of the
1561 other inputs. Once initiated, post-processing will take 1 cycle. */
1562 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
1563 set_acc_use_is_media_p2 (cpu
, out_ACC40Sk
);
1566 update_ACC_latency (cpu
, ACC40Sk_1
, ps
->post_wait
+ 1);
1567 set_acc_use_is_media_p2 (cpu
, ACC40Sk_1
);
1571 update_ACC_latency (cpu
, ACC40Sk_2
, ps
->post_wait
+ 1);
1572 set_acc_use_is_media_p2 (cpu
, ACC40Sk_2
);
1576 update_ACC_latency (cpu
, ACC40Sk_3
, ps
->post_wait
+ 1);
1577 set_acc_use_is_media_p2 (cpu
, ACC40Sk_3
);
1584 frvbf_model_fr400_u_media_3 (SIM_CPU
*cpu
, const IDESC
*idesc
,
1585 int unit_num
, int referenced
,
1586 INT in_FRi
, INT in_FRj
,
1589 /* Modelling is the same as media unit 1. */
1590 return frvbf_model_fr400_u_media_1 (cpu
, idesc
, unit_num
, referenced
,
1591 in_FRi
, in_FRj
, out_FRk
);
1595 frvbf_model_fr400_u_media_3_dual (SIM_CPU
*cpu
, const IDESC
*idesc
,
1596 int unit_num
, int referenced
,
1597 INT in_FRi
, INT out_FRk
)
1601 FRV_PROFILE_STATE
*ps
;
1602 int busy_adjustment
[] = {0, 0};
1605 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1608 /* The preprocessing can execute right away. */
1609 cycles
= idesc
->timing
->units
[unit_num
].done
;
1611 ps
= CPU_PROFILE_STATE (cpu
);
1612 dual_FRi
= DUAL_REG (in_FRi
);
1614 /* The latency of the registers may be less than previously recorded,
1615 depending on how they were used previously.
1616 See Table 13-8 in the LSI. */
1617 if (use_is_fp_load (cpu
, in_FRi
))
1619 busy_adjustment
[0] = 1;
1620 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
1623 enforce_full_fr_latency (cpu
, in_FRi
);
1624 if (dual_FRi
>= 0 && use_is_fp_load (cpu
, dual_FRi
))
1626 busy_adjustment
[1] = 1;
1627 decrease_FR_busy (cpu
, dual_FRi
, busy_adjustment
[1]);
1630 enforce_full_fr_latency (cpu
, dual_FRi
);
1632 /* The post processing must wait if there is a dependency on a FR
1633 which is not ready yet. */
1634 ps
->post_wait
= cycles
;
1635 post_wait_for_FR (cpu
, in_FRi
);
1636 post_wait_for_FR (cpu
, dual_FRi
);
1637 post_wait_for_FR (cpu
, out_FRk
);
1639 /* Restore the busy cycles of the registers we used. */
1641 fr
[in_FRi
] += busy_adjustment
[0];
1643 fr
[dual_FRi
] += busy_adjustment
[1];
1645 /* The latency of the output register will be at least the latency of the
1647 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1649 /* Once initiated, post-processing has no latency. */
1650 update_FR_ptime (cpu
, out_FRk
, 0);
1656 frvbf_model_fr400_u_media_3_quad (SIM_CPU
*cpu
, const IDESC
*idesc
,
1657 int unit_num
, int referenced
,
1658 INT in_FRi
, INT in_FRj
,
1661 /* Modelling is the same as media unit 1. */
1662 return frvbf_model_fr400_u_media_1_quad (cpu
, idesc
, unit_num
, referenced
,
1663 in_FRi
, in_FRj
, out_FRk
);
1667 frvbf_model_fr400_u_media_4 (SIM_CPU
*cpu
, const IDESC
*idesc
,
1668 int unit_num
, int referenced
,
1669 INT in_ACC40Si
, INT in_FRj
,
1670 INT out_ACC40Sk
, INT out_FRk
)
1673 FRV_PROFILE_STATE
*ps
;
1674 const CGEN_INSN
*insn
;
1675 int busy_adjustment
[] = {0};
1678 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1681 /* The preprocessing can execute right away. */
1682 cycles
= idesc
->timing
->units
[unit_num
].done
;
1684 ps
= CPU_PROFILE_STATE (cpu
);
1685 insn
= idesc
->idata
;
1687 /* The latency of the registers may be less than previously recorded,
1688 depending on how they were used previously.
1689 See Table 13-8 in the LSI. */
1692 if (use_is_fp_load (cpu
, in_FRj
))
1694 busy_adjustment
[0] = 1;
1695 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[0]);
1698 enforce_full_fr_latency (cpu
, in_FRj
);
1701 /* The post processing must wait if there is a dependency on a FR
1702 which is not ready yet. */
1703 ps
->post_wait
= cycles
;
1704 post_wait_for_ACC (cpu
, in_ACC40Si
);
1705 post_wait_for_ACC (cpu
, out_ACC40Sk
);
1706 post_wait_for_FR (cpu
, in_FRj
);
1707 post_wait_for_FR (cpu
, out_FRk
);
1709 /* Restore the busy cycles of the registers we used. */
1712 /* The latency of the output register will be at least the latency of the
1713 other inputs. Once initiated, post-processing will take 1 cycle. */
1716 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1717 update_FR_ptime (cpu
, out_FRk
, 1);
1718 /* Mark this use of the register as media unit 4. */
1719 set_use_is_media_p4 (cpu
, out_FRk
);
1721 else if (out_ACC40Sk
>= 0)
1723 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
);
1724 update_ACC_ptime (cpu
, out_ACC40Sk
, 1);
1725 /* Mark this use of the register as media unit 4. */
1726 set_acc_use_is_media_p4 (cpu
, out_ACC40Sk
);
1733 frvbf_model_fr400_u_media_4_accg (SIM_CPU
*cpu
, const IDESC
*idesc
,
1734 int unit_num
, int referenced
,
1735 INT in_ACCGi
, INT in_FRinti
,
1736 INT out_ACCGk
, INT out_FRintk
)
1738 /* Modelling is the same as media-4 unit except use accumulator guards
1739 as input instead of accumulators. */
1740 return frvbf_model_fr400_u_media_4 (cpu
, idesc
, unit_num
, referenced
,
1741 in_ACCGi
, in_FRinti
,
1742 out_ACCGk
, out_FRintk
);
1746 frvbf_model_fr400_u_media_4_acc_dual (SIM_CPU
*cpu
, const IDESC
*idesc
,
1747 int unit_num
, int referenced
,
1748 INT in_ACC40Si
, INT out_FRk
)
1751 FRV_PROFILE_STATE
*ps
;
1752 const CGEN_INSN
*insn
;
1756 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1759 /* The preprocessing can execute right away. */
1760 cycles
= idesc
->timing
->units
[unit_num
].done
;
1762 ps
= CPU_PROFILE_STATE (cpu
);
1763 ACC40Si_1
= DUAL_REG (in_ACC40Si
);
1764 FRk_1
= DUAL_REG (out_FRk
);
1766 insn
= idesc
->idata
;
1768 /* The post processing must wait if there is a dependency on a FR
1769 which is not ready yet. */
1770 ps
->post_wait
= cycles
;
1771 post_wait_for_ACC (cpu
, in_ACC40Si
);
1772 post_wait_for_ACC (cpu
, ACC40Si_1
);
1773 post_wait_for_FR (cpu
, out_FRk
);
1774 post_wait_for_FR (cpu
, FRk_1
);
1776 /* The latency of the output register will be at least the latency of the
1777 other inputs. Once initiated, post-processing will take 1 cycle. */
1780 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1781 update_FR_ptime (cpu
, out_FRk
, 1);
1782 /* Mark this use of the register as media unit 4. */
1783 set_use_is_media_p4 (cpu
, out_FRk
);
1787 update_FR_latency (cpu
, FRk_1
, ps
->post_wait
);
1788 update_FR_ptime (cpu
, FRk_1
, 1);
1789 /* Mark this use of the register as media unit 4. */
1790 set_use_is_media_p4 (cpu
, FRk_1
);
1797 frvbf_model_fr400_u_media_6 (SIM_CPU
*cpu
, const IDESC
*idesc
,
1798 int unit_num
, int referenced
,
1799 INT in_FRi
, INT out_FRk
)
1802 FRV_PROFILE_STATE
*ps
;
1803 const CGEN_INSN
*insn
;
1804 int busy_adjustment
[] = {0};
1807 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1810 /* The preprocessing can execute right away. */
1811 cycles
= idesc
->timing
->units
[unit_num
].done
;
1813 ps
= CPU_PROFILE_STATE (cpu
);
1814 insn
= idesc
->idata
;
1816 /* The latency of the registers may be less than previously recorded,
1817 depending on how they were used previously.
1818 See Table 13-8 in the LSI. */
1821 if (use_is_fp_load (cpu
, in_FRi
))
1823 busy_adjustment
[0] = 1;
1824 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
1827 enforce_full_fr_latency (cpu
, in_FRi
);
1830 /* The post processing must wait if there is a dependency on a FR
1831 which is not ready yet. */
1832 ps
->post_wait
= cycles
;
1833 post_wait_for_FR (cpu
, in_FRi
);
1834 post_wait_for_FR (cpu
, out_FRk
);
1836 /* Restore the busy cycles of the registers we used. */
1839 fr
[in_FRi
] += busy_adjustment
[0];
1841 /* The latency of the output register will be at least the latency of the
1842 other inputs. Once initiated, post-processing will take 1 cycle. */
1845 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1846 update_FR_ptime (cpu
, out_FRk
, 1);
1848 /* Mark this use of the register as media unit 1. */
1849 set_use_is_media_p6 (cpu
, out_FRk
);
1856 frvbf_model_fr400_u_media_7 (SIM_CPU
*cpu
, const IDESC
*idesc
,
1857 int unit_num
, int referenced
,
1858 INT in_FRinti
, INT in_FRintj
,
1862 FRV_PROFILE_STATE
*ps
;
1863 int busy_adjustment
[] = {0, 0};
1866 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1869 /* The preprocessing can execute right away. */
1870 cycles
= idesc
->timing
->units
[unit_num
].done
;
1872 /* The post processing must wait if there is a dependency on a FR
1873 which is not ready yet. */
1874 ps
= CPU_PROFILE_STATE (cpu
);
1876 /* The latency of the registers may be less than previously recorded,
1877 depending on how they were used previously.
1878 See Table 13-8 in the LSI. */
1881 if (use_is_fp_load (cpu
, in_FRinti
))
1883 busy_adjustment
[0] = 1;
1884 decrease_FR_busy (cpu
, in_FRinti
, busy_adjustment
[0]);
1887 enforce_full_fr_latency (cpu
, in_FRinti
);
1889 if (in_FRintj
>= 0 && in_FRintj
!= in_FRinti
)
1891 if (use_is_fp_load (cpu
, in_FRintj
))
1893 busy_adjustment
[1] = 1;
1894 decrease_FR_busy (cpu
, in_FRintj
, busy_adjustment
[1]);
1897 enforce_full_fr_latency (cpu
, in_FRintj
);
1900 ps
->post_wait
= cycles
;
1901 post_wait_for_FR (cpu
, in_FRinti
);
1902 post_wait_for_FR (cpu
, in_FRintj
);
1903 post_wait_for_CCR (cpu
, out_FCCk
);
1905 /* Restore the busy cycles of the registers we used. */
1908 fr
[in_FRinti
] += busy_adjustment
[0];
1910 fr
[in_FRintj
] += busy_adjustment
[1];
1912 /* The latency of FCCi_2 will be the latency of the other inputs plus 1
1914 update_CCR_latency (cpu
, out_FCCk
, ps
->post_wait
+ 1);
1920 frvbf_model_fr400_u_media_dual_expand (SIM_CPU
*cpu
, const IDESC
*idesc
,
1921 int unit_num
, int referenced
,
1925 /* Insns using this unit are media-3 class insns, with a dual FRk output. */
1928 FRV_PROFILE_STATE
*ps
;
1929 int busy_adjustment
[] = {0};
1932 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1935 /* The preprocessing can execute right away. */
1936 cycles
= idesc
->timing
->units
[unit_num
].done
;
1938 /* If the previous use of the registers was a media op,
1939 then their latency will be less than previously recorded.
1940 See Table 13-13 in the LSI. */
1941 dual_FRk
= DUAL_REG (out_FRk
);
1942 ps
= CPU_PROFILE_STATE (cpu
);
1943 if (use_is_fp_load (cpu
, in_FRi
))
1945 busy_adjustment
[0] = 1;
1946 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
1949 enforce_full_fr_latency (cpu
, in_FRi
);
1951 /* The post processing must wait if there is a dependency on a FR
1952 which is not ready yet. */
1953 ps
->post_wait
= cycles
;
1954 post_wait_for_FR (cpu
, in_FRi
);
1955 post_wait_for_FR (cpu
, out_FRk
);
1956 post_wait_for_FR (cpu
, dual_FRk
);
1958 /* Restore the busy cycles of the registers we used. */
1960 fr
[in_FRi
] += busy_adjustment
[0];
1962 /* The latency of the output register will be at least the latency of the
1963 other inputs. Once initiated, post-processing has no latency. */
1964 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1965 update_FR_ptime (cpu
, out_FRk
, 0);
1969 update_FR_latency (cpu
, dual_FRk
, ps
->post_wait
);
1970 update_FR_ptime (cpu
, dual_FRk
, 0);
1977 frvbf_model_fr400_u_media_dual_htob (SIM_CPU
*cpu
, const IDESC
*idesc
,
1978 int unit_num
, int referenced
,
1982 /* Insns using this unit are media-3 class insns, with a dual FRj input. */
1985 FRV_PROFILE_STATE
*ps
;
1986 int busy_adjustment
[] = {0, 0};
1989 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1992 /* The preprocessing can execute right away. */
1993 cycles
= idesc
->timing
->units
[unit_num
].done
;
1995 /* If the previous use of the registers was a media op,
1996 then their latency will be less than previously recorded.
1997 See Table 13-13 in the LSI. */
1998 dual_FRj
= DUAL_REG (in_FRj
);
1999 ps
= CPU_PROFILE_STATE (cpu
);
2000 if (use_is_fp_load (cpu
, in_FRj
))
2002 busy_adjustment
[0] = 1;
2003 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[0]);
2006 enforce_full_fr_latency (cpu
, in_FRj
);
2009 if (use_is_fp_load (cpu
, dual_FRj
))
2011 busy_adjustment
[1] = 1;
2012 decrease_FR_busy (cpu
, dual_FRj
, busy_adjustment
[1]);
2015 enforce_full_fr_latency (cpu
, dual_FRj
);
2018 /* The post processing must wait if there is a dependency on a FR
2019 which is not ready yet. */
2020 ps
->post_wait
= cycles
;
2021 post_wait_for_FR (cpu
, in_FRj
);
2022 post_wait_for_FR (cpu
, dual_FRj
);
2023 post_wait_for_FR (cpu
, out_FRk
);
2025 /* Restore the busy cycles of the registers we used. */
2027 fr
[in_FRj
] += busy_adjustment
[0];
2029 fr
[dual_FRj
] += busy_adjustment
[1];
2031 /* The latency of the output register will be at least the latency of the
2033 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
2035 /* Once initiated, post-processing has no latency. */
2036 update_FR_ptime (cpu
, out_FRk
, 0);
2042 frvbf_model_fr400_u_ici (SIM_CPU
*cpu
, const IDESC
*idesc
,
2043 int unit_num
, int referenced
,
2044 INT in_GRi
, INT in_GRj
)
2046 /* Modelling for this unit is the same as for fr500. */
2047 return frvbf_model_fr500_u_ici (cpu
, idesc
, unit_num
, referenced
,
2052 frvbf_model_fr400_u_dci (SIM_CPU
*cpu
, const IDESC
*idesc
,
2053 int unit_num
, int referenced
,
2054 INT in_GRi
, INT in_GRj
)
2056 /* Modelling for this unit is the same as for fr500. */
2057 return frvbf_model_fr500_u_dci (cpu
, idesc
, unit_num
, referenced
,
2062 frvbf_model_fr400_u_dcf (SIM_CPU
*cpu
, const IDESC
*idesc
,
2063 int unit_num
, int referenced
,
2064 INT in_GRi
, INT in_GRj
)
2066 /* Modelling for this unit is the same as for fr500. */
2067 return frvbf_model_fr500_u_dcf (cpu
, idesc
, unit_num
, referenced
,
2072 frvbf_model_fr400_u_icpl (SIM_CPU
*cpu
, const IDESC
*idesc
,
2073 int unit_num
, int referenced
,
2074 INT in_GRi
, INT in_GRj
)
2076 /* Modelling for this unit is the same as for fr500. */
2077 return frvbf_model_fr500_u_icpl (cpu
, idesc
, unit_num
, referenced
,
2082 frvbf_model_fr400_u_dcpl (SIM_CPU
*cpu
, const IDESC
*idesc
,
2083 int unit_num
, int referenced
,
2084 INT in_GRi
, INT in_GRj
)
2086 /* Modelling for this unit is the same as for fr500. */
2087 return frvbf_model_fr500_u_dcpl (cpu
, idesc
, unit_num
, referenced
,
2092 frvbf_model_fr400_u_icul (SIM_CPU
*cpu
, const IDESC
*idesc
,
2093 int unit_num
, int referenced
,
2094 INT in_GRi
, INT in_GRj
)
2096 /* Modelling for this unit is the same as for fr500. */
2097 return frvbf_model_fr500_u_icul (cpu
, idesc
, unit_num
, referenced
,
2102 frvbf_model_fr400_u_dcul (SIM_CPU
*cpu
, const IDESC
*idesc
,
2103 int unit_num
, int referenced
,
2104 INT in_GRi
, INT in_GRj
)
2106 /* Modelling for this unit is the same as for fr500. */
2107 return frvbf_model_fr500_u_dcul (cpu
, idesc
, unit_num
, referenced
,
2112 frvbf_model_fr400_u_barrier (SIM_CPU
*cpu
, const IDESC
*idesc
,
2113 int unit_num
, int referenced
)
2115 /* Modelling for this unit is the same as for fr500. */
2116 return frvbf_model_fr500_u_barrier (cpu
, idesc
, unit_num
, referenced
);
2120 frvbf_model_fr400_u_membar (SIM_CPU
*cpu
, const IDESC
*idesc
,
2121 int unit_num
, int referenced
)
2123 /* Modelling for this unit is the same as for fr500. */
2124 return frvbf_model_fr500_u_membar (cpu
, idesc
, unit_num
, referenced
);
2127 #endif /* WITH_PROFILE_MODEL_P */