]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/frv/profile-fr500.c
1 /* frv simulator fr500 dependent profiling code.
3 Copyright (C) 1998, 1999, 2000, 2001, 2003, 2007
4 Free Software Foundation, Inc.
7 This file is part of the GNU simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 #define WANT_CPU_FRVBF
30 #if WITH_PROFILE_MODEL_P
33 #include "profile-fr500.h"
35 /* Initialize cycle counting for an insn.
36 FIRST_P is non-zero if this is the first insn in a set of parallel
39 fr500_model_insn_before (SIM_CPU
*cpu
, int first_p
)
43 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
44 FRV_PROFILE_STATE
*ps
= CPU_PROFILE_STATE (cpu
);
45 ps
->cur_gr_complex
= ps
->prev_gr_complex
;
46 d
->cur_fpop
= d
->prev_fpop
;
47 d
->cur_media
= d
->prev_media
;
48 d
->cur_cc_complex
= d
->prev_cc_complex
;
52 /* Record the cycles computed for an insn.
53 LAST_P is non-zero if this is the last insn in a set of parallel insns,
54 and we update the total cycle count.
55 CYCLES is the cycle count of the insn. */
57 fr500_model_insn_after (SIM_CPU
*cpu
, int last_p
, int cycles
)
61 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
62 FRV_PROFILE_STATE
*ps
= CPU_PROFILE_STATE (cpu
);
63 ps
->prev_gr_complex
= ps
->cur_gr_complex
;
64 d
->prev_fpop
= d
->cur_fpop
;
65 d
->prev_media
= d
->cur_media
;
66 d
->prev_cc_complex
= d
->cur_cc_complex
;
71 set_use_is_fpop (SIM_CPU
*cpu
, INT fr
)
73 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
74 fr500_reset_fr_flags (cpu
, (fr
));
75 d
->cur_fpop
|= (((DI
)1) << (fr
));
79 set_use_not_fpop (SIM_CPU
*cpu
, INT fr
)
81 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
82 d
->cur_fpop
&= ~(((DI
)1) << (fr
));
86 use_is_fpop (SIM_CPU
*cpu
, INT fr
)
88 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
89 return d
->prev_fpop
& (((DI
)1) << (fr
));
93 set_use_is_media ( SIM_CPU
*cpu
, INT fr
)
95 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
96 fr500_reset_fr_flags (cpu
, (fr
));
97 d
->cur_media
|= (((DI
)1) << (fr
));
101 set_use_not_media (SIM_CPU
*cpu
, INT fr
)
103 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
104 d
->cur_media
&= ~(((DI
)1) << (fr
));
108 use_is_media (SIM_CPU
*cpu
, INT fr
)
110 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
111 return d
->prev_media
& (((DI
)1) << (fr
));
115 set_use_is_cc_complex (SIM_CPU
*cpu
, INT cc
)
117 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
118 fr500_reset_cc_flags (cpu
, cc
);
119 d
->cur_cc_complex
|= (((DI
)1) << (cc
));
123 set_use_not_cc_complex (SIM_CPU
*cpu
, INT cc
)
125 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
126 d
->cur_cc_complex
&= ~(((DI
)1) << (cc
));
130 use_is_cc_complex (SIM_CPU
*cpu
, INT cc
)
132 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
133 return d
->prev_cc_complex
& (((DI
)1) << (cc
));
137 fr500_reset_fr_flags (SIM_CPU
*cpu
, INT fr
)
139 set_use_not_fpop (cpu
, fr
);
140 set_use_not_media (cpu
, fr
);
144 fr500_reset_cc_flags (SIM_CPU
*cpu
, INT cc
)
146 set_use_not_cc_complex (cpu
, cc
);
149 /* Latency of floating point registers may be less than recorded when followed
150 by another floating point insn. */
152 adjust_float_register_busy (SIM_CPU
*cpu
, INT in_FRi
, INT in_FRj
, INT out_FRk
,
155 /* If the registers were previously used in a floating point op,
156 then their latency will be less than previously recorded.
157 See Table 13-13 in the LSI. */
159 if (use_is_fpop (cpu
, in_FRi
))
160 decrease_FR_busy (cpu
, in_FRi
, cycles
);
162 enforce_full_fr_latency (cpu
, in_FRi
);
164 if (in_FRj
>= 0 && in_FRj
!= in_FRi
)
165 if (use_is_fpop (cpu
, in_FRj
))
166 decrease_FR_busy (cpu
, in_FRj
, cycles
);
168 enforce_full_fr_latency (cpu
, in_FRj
);
170 if (out_FRk
>= 0 && out_FRk
!= in_FRi
&& out_FRk
!= in_FRj
)
171 if (use_is_fpop (cpu
, out_FRk
))
172 decrease_FR_busy (cpu
, out_FRk
, cycles
);
174 enforce_full_fr_latency (cpu
, out_FRk
);
177 /* Latency of floating point registers may be less than recorded when followed
178 by another floating point insn. */
180 adjust_double_register_busy (SIM_CPU
*cpu
, INT in_FRi
, INT in_FRj
, INT out_FRk
,
183 /* If the registers were previously used in a floating point op,
184 then their latency will be less than previously recorded.
185 See Table 13-13 in the LSI. */
186 adjust_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, cycles
);
187 if (in_FRi
>= 0) ++in_FRi
;
188 if (in_FRj
>= 0) ++in_FRj
;
189 if (out_FRk
>= 0) ++out_FRk
;
190 adjust_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, cycles
);
193 /* Latency of floating point registers is less than recorded when followed
194 by another floating point insn. */
196 restore_float_register_busy (SIM_CPU
*cpu
, INT in_FRi
, INT in_FRj
, INT out_FRk
,
199 /* If the registers were previously used in a floating point op,
200 then their latency will be less than previously recorded.
201 See Table 13-13 in the LSI. */
202 if (in_FRi
>= 0 && use_is_fpop (cpu
, in_FRi
))
203 increase_FR_busy (cpu
, in_FRi
, cycles
);
204 if (in_FRj
!= in_FRi
&& use_is_fpop (cpu
, in_FRj
))
205 increase_FR_busy (cpu
, in_FRj
, cycles
);
206 if (out_FRk
!= in_FRi
&& out_FRk
!= in_FRj
&& use_is_fpop (cpu
, out_FRk
))
207 increase_FR_busy (cpu
, out_FRk
, cycles
);
210 /* Latency of floating point registers is less than recorded when followed
211 by another floating point insn. */
213 restore_double_register_busy (SIM_CPU
*cpu
, INT in_FRi
, INT in_FRj
, INT out_FRk
,
216 /* If the registers were previously used in a floating point op,
217 then their latency will be less than previously recorded.
218 See Table 13-13 in the LSI. */
219 restore_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, cycles
);
220 if (in_FRi
>= 0) ++in_FRi
;
221 if (in_FRj
>= 0) ++in_FRj
;
222 if (out_FRk
>= 0) ++out_FRk
;
223 restore_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, cycles
);
227 frvbf_model_fr500_u_exec (SIM_CPU
*cpu
, const IDESC
*idesc
,
228 int unit_num
, int referenced
)
230 return idesc
->timing
->units
[unit_num
].done
;
234 frvbf_model_fr500_u_integer (SIM_CPU
*cpu
, const IDESC
*idesc
,
235 int unit_num
, int referenced
,
236 INT in_GRi
, INT in_GRj
, INT out_GRk
,
241 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
243 /* icc0-icc4 are the upper 4 fields of the CCR. */
247 /* The entire VLIW insn must wait if there is a dependency on a register
248 which is not ready yet.
249 The latency of the registers may be less than previously recorded,
250 depending on how they were used previously.
251 See Table 13-8 in the LSI. */
252 if (in_GRi
!= out_GRk
&& in_GRi
>= 0)
254 if (use_is_gr_complex (cpu
, in_GRi
))
255 decrease_GR_busy (cpu
, in_GRi
, 1);
257 if (in_GRj
!= out_GRk
&& in_GRj
!= in_GRi
&& in_GRj
>= 0)
259 if (use_is_gr_complex (cpu
, in_GRj
))
260 decrease_GR_busy (cpu
, in_GRj
, 1);
262 vliw_wait_for_GR (cpu
, in_GRi
);
263 vliw_wait_for_GR (cpu
, in_GRj
);
264 vliw_wait_for_GR (cpu
, out_GRk
);
265 vliw_wait_for_CCR (cpu
, out_ICCi_1
);
266 handle_resource_wait (cpu
);
267 load_wait_for_GR (cpu
, in_GRi
);
268 load_wait_for_GR (cpu
, in_GRj
);
269 load_wait_for_GR (cpu
, out_GRk
);
270 trace_vliw_wait_cycles (cpu
);
274 /* GRk is available immediately to the next VLIW insn as is ICCi_1. */
275 cycles
= idesc
->timing
->units
[unit_num
].done
;
280 frvbf_model_fr500_u_imul (SIM_CPU
*cpu
, const IDESC
*idesc
,
281 int unit_num
, int referenced
,
282 INT in_GRi
, INT in_GRj
, INT out_GRk
, INT out_ICCi_1
)
285 /* icc0-icc4 are the upper 4 fields of the CCR. */
289 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
291 /* The entire VLIW insn must wait if there is a dependency on a register
292 which is not ready yet.
293 The latency of the registers may be less than previously recorded,
294 depending on how they were used previously.
295 See Table 13-8 in the LSI. */
296 if (in_GRi
!= out_GRk
&& in_GRi
>= 0)
298 if (use_is_gr_complex (cpu
, in_GRi
))
299 decrease_GR_busy (cpu
, in_GRi
, 1);
301 if (in_GRj
!= out_GRk
&& in_GRj
!= in_GRi
&& in_GRj
>= 0)
303 if (use_is_gr_complex (cpu
, in_GRj
))
304 decrease_GR_busy (cpu
, in_GRj
, 1);
306 vliw_wait_for_GR (cpu
, in_GRi
);
307 vliw_wait_for_GR (cpu
, in_GRj
);
308 vliw_wait_for_GRdouble (cpu
, out_GRk
);
309 vliw_wait_for_CCR (cpu
, out_ICCi_1
);
310 handle_resource_wait (cpu
);
311 load_wait_for_GR (cpu
, in_GRi
);
312 load_wait_for_GR (cpu
, in_GRj
);
313 load_wait_for_GRdouble (cpu
, out_GRk
);
314 trace_vliw_wait_cycles (cpu
);
318 /* GRk has a latency of 2 cycles. */
319 cycles
= idesc
->timing
->units
[unit_num
].done
;
320 update_GRdouble_latency (cpu
, out_GRk
, cycles
+ 2);
321 set_use_is_gr_complex (cpu
, out_GRk
);
322 set_use_is_gr_complex (cpu
, out_GRk
+ 1);
324 /* ICCi_1 has a latency of 1 cycle. */
325 update_CCR_latency (cpu
, out_ICCi_1
, cycles
+ 1);
331 frvbf_model_fr500_u_idiv (SIM_CPU
*cpu
, const IDESC
*idesc
,
332 int unit_num
, int referenced
,
333 INT in_GRi
, INT in_GRj
, INT out_GRk
, INT out_ICCi_1
)
339 /* icc0-icc4 are the upper 4 fields of the CCR. */
343 vliw
= CPU_VLIW (cpu
);
344 slot
= vliw
->next_slot
- 1;
345 slot
= (*vliw
->current_vliw
)[slot
] - UNIT_I0
;
347 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
349 /* The entire VLIW insn must wait if there is a dependency on a register
350 which is not ready yet.
351 The latency of the registers may be less than previously recorded,
352 depending on how they were used previously.
353 See Table 13-8 in the LSI. */
354 if (in_GRi
!= out_GRk
&& in_GRi
>= 0)
356 if (use_is_gr_complex (cpu
, in_GRi
))
357 decrease_GR_busy (cpu
, in_GRi
, 1);
359 if (in_GRj
!= out_GRk
&& in_GRj
!= in_GRi
&& in_GRj
>= 0)
361 if (use_is_gr_complex (cpu
, in_GRj
))
362 decrease_GR_busy (cpu
, in_GRj
, 1);
364 vliw_wait_for_GR (cpu
, in_GRi
);
365 vliw_wait_for_GR (cpu
, in_GRj
);
366 vliw_wait_for_GR (cpu
, out_GRk
);
367 vliw_wait_for_CCR (cpu
, out_ICCi_1
);
368 vliw_wait_for_idiv_resource (cpu
, slot
);
369 handle_resource_wait (cpu
);
370 load_wait_for_GR (cpu
, in_GRi
);
371 load_wait_for_GR (cpu
, in_GRj
);
372 load_wait_for_GR (cpu
, out_GRk
);
373 trace_vliw_wait_cycles (cpu
);
377 /* GRk has a latency of 19 cycles! */
378 cycles
= idesc
->timing
->units
[unit_num
].done
;
379 update_GR_latency (cpu
, out_GRk
, cycles
+ 19);
380 set_use_is_gr_complex (cpu
, out_GRk
);
382 /* ICCi_1 has a latency of 19 cycles. */
383 update_CCR_latency (cpu
, out_ICCi_1
, cycles
+ 19);
384 set_use_is_cc_complex (cpu
, out_ICCi_1
);
386 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
388 /* GNER has a latency of 18 cycles. */
389 update_SPR_latency (cpu
, GNER_FOR_GR (out_GRk
), cycles
+ 18);
392 /* the idiv resource has a latency of 18 cycles! */
393 update_idiv_resource_latency (cpu
, slot
, cycles
+ 18);
399 frvbf_model_fr500_u_branch (SIM_CPU
*cpu
, const IDESC
*idesc
,
400 int unit_num
, int referenced
,
401 INT in_GRi
, INT in_GRj
,
402 INT in_ICCi_2
, INT in_FCCi_2
)
405 FRV_PROFILE_STATE
*ps
;
407 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
409 /* icc0-icc4 are the upper 4 fields of the CCR. */
413 /* The entire VLIW insn must wait if there is a dependency on a register
414 which is not ready yet.
415 The latency of the registers may be less than previously recorded,
416 depending on how they were used previously.
417 See Table 13-8 in the LSI. */
420 if (use_is_gr_complex (cpu
, in_GRi
))
421 decrease_GR_busy (cpu
, in_GRi
, 1);
423 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
425 if (use_is_gr_complex (cpu
, in_GRj
))
426 decrease_GR_busy (cpu
, in_GRj
, 1);
428 vliw_wait_for_GR (cpu
, in_GRi
);
429 vliw_wait_for_GR (cpu
, in_GRj
);
430 vliw_wait_for_CCR (cpu
, in_ICCi_2
);
431 vliw_wait_for_CCR (cpu
, in_FCCi_2
);
432 handle_resource_wait (cpu
);
433 load_wait_for_GR (cpu
, in_GRi
);
434 load_wait_for_GR (cpu
, in_GRj
);
435 trace_vliw_wait_cycles (cpu
);
439 /* When counting branches taken or not taken, don't consider branches after
440 the first taken branch in a vliw insn. */
441 ps
= CPU_PROFILE_STATE (cpu
);
442 if (! ps
->vliw_branch_taken
)
444 /* (1 << 4): The pc is the 5th element in inputs, outputs.
445 ??? can be cleaned up */
446 PROFILE_DATA
*p
= CPU_PROFILE_DATA (cpu
);
447 int taken
= (referenced
& (1 << 4)) != 0;
450 ++PROFILE_MODEL_TAKEN_COUNT (p
);
451 ps
->vliw_branch_taken
= 1;
454 ++PROFILE_MODEL_UNTAKEN_COUNT (p
);
457 cycles
= idesc
->timing
->units
[unit_num
].done
;
462 frvbf_model_fr500_u_trap (SIM_CPU
*cpu
, const IDESC
*idesc
,
463 int unit_num
, int referenced
,
464 INT in_GRi
, INT in_GRj
,
465 INT in_ICCi_2
, INT in_FCCi_2
)
469 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
471 /* icc0-icc4 are the upper 4 fields of the CCR. */
475 /* The entire VLIW insn must wait if there is a dependency on a register
476 which is not ready yet.
477 The latency of the registers may be less than previously recorded,
478 depending on how they were used previously.
479 See Table 13-8 in the LSI. */
482 if (use_is_gr_complex (cpu
, in_GRi
))
483 decrease_GR_busy (cpu
, in_GRi
, 1);
485 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
487 if (use_is_gr_complex (cpu
, in_GRj
))
488 decrease_GR_busy (cpu
, in_GRj
, 1);
490 vliw_wait_for_GR (cpu
, in_GRi
);
491 vliw_wait_for_GR (cpu
, in_GRj
);
492 vliw_wait_for_CCR (cpu
, in_ICCi_2
);
493 vliw_wait_for_CCR (cpu
, in_FCCi_2
);
494 handle_resource_wait (cpu
);
495 load_wait_for_GR (cpu
, in_GRi
);
496 load_wait_for_GR (cpu
, in_GRj
);
497 trace_vliw_wait_cycles (cpu
);
501 cycles
= idesc
->timing
->units
[unit_num
].done
;
506 frvbf_model_fr500_u_check (SIM_CPU
*cpu
, const IDESC
*idesc
,
507 int unit_num
, int referenced
,
508 INT in_ICCi_3
, INT in_FCCi_3
)
512 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
514 /* icc0-icc4 are the upper 4 fields of the CCR. */
518 /* The entire VLIW insn must wait if there is a dependency on a register
519 which is not ready yet. */
520 vliw_wait_for_CCR (cpu
, in_ICCi_3
);
521 vliw_wait_for_CCR (cpu
, in_FCCi_3
);
522 handle_resource_wait (cpu
);
523 trace_vliw_wait_cycles (cpu
);
527 cycles
= idesc
->timing
->units
[unit_num
].done
;
532 frvbf_model_fr500_u_clrgr (SIM_CPU
*cpu
, const IDESC
*idesc
,
533 int unit_num
, int referenced
,
538 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
540 /* Wait for both GNER registers or just the one specified. */
543 vliw_wait_for_SPR (cpu
, H_SPR_GNER0
);
544 vliw_wait_for_SPR (cpu
, H_SPR_GNER1
);
547 vliw_wait_for_SPR (cpu
, GNER_FOR_GR (in_GRk
));
548 handle_resource_wait (cpu
);
549 trace_vliw_wait_cycles (cpu
);
553 cycles
= idesc
->timing
->units
[unit_num
].done
;
558 frvbf_model_fr500_u_clrfr (SIM_CPU
*cpu
, const IDESC
*idesc
,
559 int unit_num
, int referenced
,
564 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
566 /* Wait for both GNER registers or just the one specified. */
569 vliw_wait_for_SPR (cpu
, H_SPR_FNER0
);
570 vliw_wait_for_SPR (cpu
, H_SPR_FNER1
);
573 vliw_wait_for_SPR (cpu
, FNER_FOR_FR (in_FRk
));
574 handle_resource_wait (cpu
);
575 trace_vliw_wait_cycles (cpu
);
579 cycles
= idesc
->timing
->units
[unit_num
].done
;
584 frvbf_model_fr500_u_commit (SIM_CPU
*cpu
, const IDESC
*idesc
,
585 int unit_num
, int referenced
,
586 INT in_GRk
, INT in_FRk
)
590 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
592 /* If GR is specified, then FR is not and vice-versa. If neither is
593 then it's a commitga or commitfa. Check the insn attribute to
596 vliw_wait_for_SPR (cpu
, GNER_FOR_GR (in_GRk
));
597 else if (in_FRk
!= -1)
598 vliw_wait_for_SPR (cpu
, FNER_FOR_FR (in_FRk
));
599 else if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_FR_ACCESS
))
601 vliw_wait_for_SPR (cpu
, H_SPR_FNER0
);
602 vliw_wait_for_SPR (cpu
, H_SPR_FNER1
);
606 vliw_wait_for_SPR (cpu
, H_SPR_GNER0
);
607 vliw_wait_for_SPR (cpu
, H_SPR_GNER1
);
609 handle_resource_wait (cpu
);
610 trace_vliw_wait_cycles (cpu
);
614 cycles
= idesc
->timing
->units
[unit_num
].done
;
619 frvbf_model_fr500_u_set_hilo (SIM_CPU
*cpu
, const IDESC
*idesc
,
620 int unit_num
, int referenced
,
621 INT out_GRkhi
, INT out_GRklo
)
625 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
627 /* The entire VLIW insn must wait if there is a dependency on a GR
628 which is not ready yet. */
629 vliw_wait_for_GR (cpu
, out_GRkhi
);
630 vliw_wait_for_GR (cpu
, out_GRklo
);
631 handle_resource_wait (cpu
);
632 load_wait_for_GR (cpu
, out_GRkhi
);
633 load_wait_for_GR (cpu
, out_GRklo
);
634 trace_vliw_wait_cycles (cpu
);
638 /* GRk is available immediately to the next VLIW insn. */
639 cycles
= idesc
->timing
->units
[unit_num
].done
;
641 set_use_not_gr_complex (cpu
, out_GRkhi
);
642 set_use_not_gr_complex (cpu
, out_GRklo
);
648 frvbf_model_fr500_u_gr_load (SIM_CPU
*cpu
, const IDESC
*idesc
,
649 int unit_num
, int referenced
,
650 INT in_GRi
, INT in_GRj
,
651 INT out_GRk
, INT out_GRdoublek
)
655 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
657 /* The entire VLIW insn must wait if there is a dependency on a register
658 which is not ready yet.
659 The latency of the registers may be less than previously recorded,
660 depending on how they were used previously.
661 See Table 13-8 in the LSI. */
662 if (in_GRi
!= out_GRk
&& in_GRi
!= out_GRdoublek
663 && in_GRi
!= out_GRdoublek
+ 1 && in_GRi
>= 0)
665 if (use_is_gr_complex (cpu
, in_GRi
))
666 decrease_GR_busy (cpu
, in_GRi
, 1);
668 if (in_GRj
!= in_GRi
&& in_GRj
!= out_GRk
&& in_GRj
!= out_GRdoublek
669 && in_GRj
!= out_GRdoublek
+ 1 && in_GRj
>= 0)
672 if (use_is_gr_complex (cpu
, in_GRj
))
673 decrease_GR_busy (cpu
, in_GRj
, 1);
675 vliw_wait_for_GR (cpu
, in_GRi
);
676 vliw_wait_for_GR (cpu
, in_GRj
);
677 vliw_wait_for_GR (cpu
, out_GRk
);
678 vliw_wait_for_GRdouble (cpu
, out_GRdoublek
);
679 handle_resource_wait (cpu
);
680 load_wait_for_GR (cpu
, in_GRi
);
681 load_wait_for_GR (cpu
, in_GRj
);
682 load_wait_for_GR (cpu
, out_GRk
);
683 load_wait_for_GRdouble (cpu
, out_GRdoublek
);
684 trace_vliw_wait_cycles (cpu
);
688 cycles
= idesc
->timing
->units
[unit_num
].done
;
690 /* The latency of GRk for a load will depend on how long it takes to retrieve
691 the the data from the cache or memory. */
692 update_GR_latency_for_load (cpu
, out_GRk
, cycles
);
693 update_GRdouble_latency_for_load (cpu
, out_GRdoublek
, cycles
);
695 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
697 /* GNER has a latency of 2 cycles. */
698 update_SPR_latency (cpu
, GNER_FOR_GR (out_GRk
), cycles
+ 2);
699 update_SPR_latency (cpu
, GNER_FOR_GR (out_GRdoublek
), cycles
+ 2);
703 set_use_is_gr_complex (cpu
, out_GRk
);
704 if (out_GRdoublek
!= -1)
706 set_use_is_gr_complex (cpu
, out_GRdoublek
);
707 set_use_is_gr_complex (cpu
, out_GRdoublek
+ 1);
714 frvbf_model_fr500_u_gr_store (SIM_CPU
*cpu
, const IDESC
*idesc
,
715 int unit_num
, int referenced
,
716 INT in_GRi
, INT in_GRj
,
717 INT in_GRk
, INT in_GRdoublek
)
721 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
723 /* The entire VLIW insn must wait if there is a dependency on a register
724 which is not ready yet.
725 The latency of the registers may be less than previously recorded,
726 depending on how they were used previously.
727 See Table 13-8 in the LSI. */
730 if (use_is_gr_complex (cpu
, in_GRi
))
731 decrease_GR_busy (cpu
, in_GRi
, 1);
733 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
735 if (use_is_gr_complex (cpu
, in_GRj
))
736 decrease_GR_busy (cpu
, in_GRj
, 1);
738 if (in_GRk
!= in_GRi
&& in_GRk
!= in_GRj
&& in_GRk
>= 0)
740 if (use_is_gr_complex (cpu
, in_GRk
))
741 decrease_GR_busy (cpu
, in_GRk
, 1);
743 if (in_GRdoublek
!= in_GRi
&& in_GRdoublek
!= in_GRj
744 && in_GRdoublek
+ 1 != in_GRi
&& in_GRdoublek
+ 1 != in_GRj
745 && in_GRdoublek
>= 0)
747 if (use_is_gr_complex (cpu
, in_GRdoublek
))
748 decrease_GR_busy (cpu
, in_GRdoublek
, 1);
749 if (use_is_gr_complex (cpu
, in_GRdoublek
+ 1))
750 decrease_GR_busy (cpu
, in_GRdoublek
+ 1, 1);
752 vliw_wait_for_GR (cpu
, in_GRi
);
753 vliw_wait_for_GR (cpu
, in_GRj
);
754 vliw_wait_for_GR (cpu
, in_GRk
);
755 vliw_wait_for_GRdouble (cpu
, in_GRdoublek
);
756 handle_resource_wait (cpu
);
757 load_wait_for_GR (cpu
, in_GRi
);
758 load_wait_for_GR (cpu
, in_GRj
);
759 load_wait_for_GR (cpu
, in_GRk
);
760 load_wait_for_GRdouble (cpu
, in_GRdoublek
);
761 trace_vliw_wait_cycles (cpu
);
765 cycles
= idesc
->timing
->units
[unit_num
].done
;
771 frvbf_model_fr500_u_gr_r_store (SIM_CPU
*cpu
, const IDESC
*idesc
,
772 int unit_num
, int referenced
,
773 INT in_GRi
, INT in_GRj
,
774 INT in_GRk
, INT in_GRdoublek
)
776 int cycles
= frvbf_model_fr500_u_gr_store (cpu
, idesc
, unit_num
, referenced
,
777 in_GRi
, in_GRj
, in_GRk
,
780 if (model_insn
== FRV_INSN_MODEL_PASS_2
)
782 if (CPU_RSTR_INVALIDATE(cpu
))
783 request_cache_invalidate (cpu
, CPU_DATA_CACHE (cpu
), cycles
);
790 frvbf_model_fr500_u_fr_load (SIM_CPU
*cpu
, const IDESC
*idesc
,
791 int unit_num
, int referenced
,
792 INT in_GRi
, INT in_GRj
,
793 INT out_FRk
, INT out_FRdoublek
)
797 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
799 /* The entire VLIW insn must wait if there is a dependency on a register
800 which is not ready yet.
801 The latency of the registers may be less than previously recorded,
802 depending on how they were used previously.
803 See Table 13-8 in the LSI. */
806 if (use_is_gr_complex (cpu
, in_GRi
))
807 decrease_GR_busy (cpu
, in_GRi
, 1);
809 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
811 if (use_is_gr_complex (cpu
, in_GRj
))
812 decrease_GR_busy (cpu
, in_GRj
, 1);
816 if (use_is_media (cpu
, out_FRk
))
817 decrease_FR_busy (cpu
, out_FRk
, 1);
819 adjust_float_register_busy (cpu
, -1, -1, out_FRk
, 1);
821 if (out_FRdoublek
>= 0)
823 if (use_is_media (cpu
, out_FRdoublek
))
824 decrease_FR_busy (cpu
, out_FRdoublek
, 1);
826 adjust_float_register_busy (cpu
, -1, -1, out_FRdoublek
, 1);
827 if (use_is_media (cpu
, out_FRdoublek
+ 1))
828 decrease_FR_busy (cpu
, out_FRdoublek
+ 1, 1);
830 adjust_float_register_busy (cpu
, -1, -1, out_FRdoublek
+ 1, 1);
832 vliw_wait_for_GR (cpu
, in_GRi
);
833 vliw_wait_for_GR (cpu
, in_GRj
);
834 vliw_wait_for_FR (cpu
, out_FRk
);
835 vliw_wait_for_FRdouble (cpu
, out_FRdoublek
);
836 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
838 vliw_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRk
));
839 vliw_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRdoublek
));
841 handle_resource_wait (cpu
);
842 load_wait_for_GR (cpu
, in_GRi
);
843 load_wait_for_GR (cpu
, in_GRj
);
844 load_wait_for_FR (cpu
, out_FRk
);
845 load_wait_for_FRdouble (cpu
, out_FRdoublek
);
846 trace_vliw_wait_cycles (cpu
);
850 cycles
= idesc
->timing
->units
[unit_num
].done
;
852 /* The latency of FRk for a load will depend on how long it takes to retrieve
853 the the data from the cache or memory. */
854 update_FR_latency_for_load (cpu
, out_FRk
, cycles
);
855 update_FRdouble_latency_for_load (cpu
, out_FRdoublek
, cycles
);
857 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
859 /* FNER has a latency of 3 cycles. */
860 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRk
), cycles
+ 3);
861 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRdoublek
), cycles
+ 3);
864 fr500_reset_fr_flags (cpu
, out_FRk
);
870 frvbf_model_fr500_u_fr_store (SIM_CPU
*cpu
, const IDESC
*idesc
,
871 int unit_num
, int referenced
,
872 INT in_GRi
, INT in_GRj
,
873 INT in_FRk
, INT in_FRdoublek
)
877 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
879 /* The entire VLIW insn must wait if there is a dependency on a register
880 which is not ready yet.
881 The latency of the registers may be less than previously recorded,
882 depending on how they were used previously.
883 See Table 13-8 in the LSI. */
886 if (use_is_gr_complex (cpu
, in_GRi
))
887 decrease_GR_busy (cpu
, in_GRi
, 1);
889 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
891 if (use_is_gr_complex (cpu
, in_GRj
))
892 decrease_GR_busy (cpu
, in_GRj
, 1);
896 if (use_is_media (cpu
, in_FRk
))
897 decrease_FR_busy (cpu
, in_FRk
, 1);
899 adjust_float_register_busy (cpu
, -1, -1, in_FRk
, 1);
901 if (in_FRdoublek
>= 0)
903 if (use_is_media (cpu
, in_FRdoublek
))
904 decrease_FR_busy (cpu
, in_FRdoublek
, 1);
906 adjust_float_register_busy (cpu
, -1, -1, in_FRdoublek
, 1);
907 if (use_is_media (cpu
, in_FRdoublek
+ 1))
908 decrease_FR_busy (cpu
, in_FRdoublek
+ 1, 1);
910 adjust_float_register_busy (cpu
, -1, -1, in_FRdoublek
+ 1, 1);
912 vliw_wait_for_GR (cpu
, in_GRi
);
913 vliw_wait_for_GR (cpu
, in_GRj
);
914 vliw_wait_for_FR (cpu
, in_FRk
);
915 vliw_wait_for_FRdouble (cpu
, in_FRdoublek
);
916 handle_resource_wait (cpu
);
917 load_wait_for_GR (cpu
, in_GRi
);
918 load_wait_for_GR (cpu
, in_GRj
);
919 load_wait_for_FR (cpu
, in_FRk
);
920 load_wait_for_FRdouble (cpu
, in_FRdoublek
);
921 trace_vliw_wait_cycles (cpu
);
925 cycles
= idesc
->timing
->units
[unit_num
].done
;
931 frvbf_model_fr500_u_fr_r_store (SIM_CPU
*cpu
, const IDESC
*idesc
,
932 int unit_num
, int referenced
,
933 INT in_GRi
, INT in_GRj
,
934 INT in_FRk
, INT in_FRdoublek
)
936 int cycles
= frvbf_model_fr500_u_fr_store (cpu
, idesc
, unit_num
, referenced
,
937 in_GRi
, in_GRj
, in_FRk
,
940 if (model_insn
== FRV_INSN_MODEL_PASS_2
)
942 if (CPU_RSTR_INVALIDATE(cpu
))
943 request_cache_invalidate (cpu
, CPU_DATA_CACHE (cpu
), cycles
);
950 frvbf_model_fr500_u_swap (SIM_CPU
*cpu
, const IDESC
*idesc
,
951 int unit_num
, int referenced
,
952 INT in_GRi
, INT in_GRj
, INT out_GRk
)
956 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
958 /* The entire VLIW insn must wait if there is a dependency on a register
959 which is not ready yet.
960 The latency of the registers may be less than previously recorded,
961 depending on how they were used previously.
962 See Table 13-8 in the LSI. */
963 if (in_GRi
!= out_GRk
&& in_GRi
>= 0)
965 if (use_is_gr_complex (cpu
, in_GRi
))
966 decrease_GR_busy (cpu
, in_GRi
, 1);
968 if (in_GRj
!= out_GRk
&& in_GRj
!= in_GRi
&& in_GRj
>= 0)
970 if (use_is_gr_complex (cpu
, in_GRj
))
971 decrease_GR_busy (cpu
, in_GRj
, 1);
973 vliw_wait_for_GR (cpu
, in_GRi
);
974 vliw_wait_for_GR (cpu
, in_GRj
);
975 vliw_wait_for_GR (cpu
, out_GRk
);
976 handle_resource_wait (cpu
);
977 load_wait_for_GR (cpu
, in_GRi
);
978 load_wait_for_GR (cpu
, in_GRj
);
979 load_wait_for_GR (cpu
, out_GRk
);
980 trace_vliw_wait_cycles (cpu
);
984 cycles
= idesc
->timing
->units
[unit_num
].done
;
986 /* The latency of GRk will depend on how long it takes to swap
987 the the data from the cache or memory. */
988 update_GR_latency_for_swap (cpu
, out_GRk
, cycles
);
989 set_use_is_gr_complex (cpu
, out_GRk
);
995 frvbf_model_fr500_u_fr2fr (SIM_CPU
*cpu
, const IDESC
*idesc
,
996 int unit_num
, int referenced
,
997 INT in_FRj
, INT out_FRk
)
1001 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1003 /* The entire VLIW insn must wait if there is a dependency on a register
1004 which is not ready yet. */
1007 if (use_is_media (cpu
, in_FRj
))
1008 decrease_FR_busy (cpu
, in_FRj
, 1);
1010 adjust_float_register_busy (cpu
, -1, in_FRj
, -1, 1);
1012 if (out_FRk
>= 0 && out_FRk
!= in_FRj
)
1014 if (use_is_media (cpu
, out_FRk
))
1015 decrease_FR_busy (cpu
, out_FRk
, 1);
1017 adjust_float_register_busy (cpu
, -1, -1, out_FRk
, 1);
1019 vliw_wait_for_FR (cpu
, in_FRj
);
1020 vliw_wait_for_FR (cpu
, out_FRk
);
1021 handle_resource_wait (cpu
);
1022 load_wait_for_FR (cpu
, in_FRj
);
1023 load_wait_for_FR (cpu
, out_FRk
);
1024 trace_vliw_wait_cycles (cpu
);
1028 /* The latency of FRj is 3 cycles. */
1029 cycles
= idesc
->timing
->units
[unit_num
].done
;
1030 update_FR_latency (cpu
, out_FRk
, cycles
+ 3);
1036 frvbf_model_fr500_u_fr2gr (SIM_CPU
*cpu
, const IDESC
*idesc
,
1037 int unit_num
, int referenced
,
1038 INT in_FRk
, INT out_GRj
)
1042 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1044 /* The entire VLIW insn must wait if there is a dependency on a register
1045 which is not ready yet. */
1048 if (use_is_media (cpu
, in_FRk
))
1049 decrease_FR_busy (cpu
, in_FRk
, 1);
1051 adjust_float_register_busy (cpu
, -1, in_FRk
, -1, 1);
1053 vliw_wait_for_FR (cpu
, in_FRk
);
1054 vliw_wait_for_GR (cpu
, out_GRj
);
1055 handle_resource_wait (cpu
);
1056 load_wait_for_FR (cpu
, in_FRk
);
1057 load_wait_for_GR (cpu
, out_GRj
);
1058 trace_vliw_wait_cycles (cpu
);
1062 /* The latency of GRj is 2 cycles. */
1063 cycles
= idesc
->timing
->units
[unit_num
].done
;
1064 update_GR_latency (cpu
, out_GRj
, cycles
+ 2);
1065 set_use_is_gr_complex (cpu
, out_GRj
);
1071 frvbf_model_fr500_u_spr2gr (SIM_CPU
*cpu
, const IDESC
*idesc
,
1072 int unit_num
, int referenced
,
1073 INT in_spr
, INT out_GRj
)
1077 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1079 /* The entire VLIW insn must wait if there is a dependency on a register
1080 which is not ready yet. */
1081 vliw_wait_for_SPR (cpu
, in_spr
);
1082 vliw_wait_for_GR (cpu
, out_GRj
);
1083 handle_resource_wait (cpu
);
1084 load_wait_for_GR (cpu
, out_GRj
);
1085 trace_vliw_wait_cycles (cpu
);
1089 cycles
= idesc
->timing
->units
[unit_num
].done
;
1091 #if 0 /* no latency? */
1092 /* The latency of GRj is 2 cycles. */
1093 update_GR_latency (cpu
, out_GRj
, cycles
+ 2);
1100 frvbf_model_fr500_u_gr2fr (SIM_CPU
*cpu
, const IDESC
*idesc
,
1101 int unit_num
, int referenced
,
1102 INT in_GRj
, INT out_FRk
)
1106 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1108 /* The entire VLIW insn must wait if there is a dependency on a register
1109 which is not ready yet.
1110 The latency of the registers may be less than previously recorded,
1111 depending on how they were used previously.
1112 See Table 13-8 in the LSI. */
1115 if (use_is_gr_complex (cpu
, in_GRj
))
1116 decrease_GR_busy (cpu
, in_GRj
, 1);
1120 if (use_is_media (cpu
, out_FRk
))
1121 decrease_FR_busy (cpu
, out_FRk
, 1);
1123 adjust_float_register_busy (cpu
, -1, -1, out_FRk
, 1);
1125 vliw_wait_for_GR (cpu
, in_GRj
);
1126 vliw_wait_for_FR (cpu
, out_FRk
);
1127 handle_resource_wait (cpu
);
1128 load_wait_for_GR (cpu
, in_GRj
);
1129 load_wait_for_FR (cpu
, out_FRk
);
1130 trace_vliw_wait_cycles (cpu
);
1134 /* The latency of FRk is 2 cycles. */
1135 cycles
= idesc
->timing
->units
[unit_num
].done
;
1136 update_FR_latency (cpu
, out_FRk
, cycles
+ 2);
1138 /* Mark this use of the register as NOT a floating point op. */
1139 fr500_reset_fr_flags (cpu
, out_FRk
);
1145 frvbf_model_fr500_u_gr2spr (SIM_CPU
*cpu
, const IDESC
*idesc
,
1146 int unit_num
, int referenced
,
1147 INT in_GRj
, INT out_spr
)
1151 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1153 /* The entire VLIW insn must wait if there is a dependency on a register
1154 which is not ready yet.
1155 The latency of the registers may be less than previously recorded,
1156 depending on how they were used previously.
1157 See Table 13-8 in the LSI. */
1160 if (use_is_gr_complex (cpu
, in_GRj
))
1161 decrease_GR_busy (cpu
, in_GRj
, 1);
1163 vliw_wait_for_GR (cpu
, in_GRj
);
1164 vliw_wait_for_SPR (cpu
, out_spr
);
1165 handle_resource_wait (cpu
);
1166 load_wait_for_GR (cpu
, in_GRj
);
1167 trace_vliw_wait_cycles (cpu
);
1171 cycles
= idesc
->timing
->units
[unit_num
].done
;
1174 /* The latency of spr is ? cycles. */
1175 update_SPR_latency (cpu
, out_spr
, cycles
+ ?);
1182 frvbf_model_fr500_u_ici (SIM_CPU
*cpu
, const IDESC
*idesc
,
1183 int unit_num
, int referenced
,
1184 INT in_GRi
, INT in_GRj
)
1188 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1190 /* The entire VLIW insn must wait if there is a dependency on a register
1191 which is not ready yet.
1192 The latency of the registers may be less than previously recorded,
1193 depending on how they were used previously.
1194 See Table 13-8 in the LSI. */
1197 if (use_is_gr_complex (cpu
, in_GRi
))
1198 decrease_GR_busy (cpu
, in_GRi
, 1);
1200 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
1202 if (use_is_gr_complex (cpu
, in_GRj
))
1203 decrease_GR_busy (cpu
, in_GRj
, 1);
1205 vliw_wait_for_GR (cpu
, in_GRi
);
1206 vliw_wait_for_GR (cpu
, in_GRj
);
1207 handle_resource_wait (cpu
);
1208 load_wait_for_GR (cpu
, in_GRi
);
1209 load_wait_for_GR (cpu
, in_GRj
);
1210 trace_vliw_wait_cycles (cpu
);
1214 cycles
= idesc
->timing
->units
[unit_num
].done
;
1215 request_cache_invalidate (cpu
, CPU_INSN_CACHE (cpu
), cycles
);
1220 frvbf_model_fr500_u_dci (SIM_CPU
*cpu
, const IDESC
*idesc
,
1221 int unit_num
, int referenced
,
1222 INT in_GRi
, INT in_GRj
)
1226 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1228 /* The entire VLIW insn must wait if there is a dependency on a register
1229 which is not ready yet.
1230 The latency of the registers may be less than previously recorded,
1231 depending on how they were used previously.
1232 See Table 13-8 in the LSI. */
1235 if (use_is_gr_complex (cpu
, in_GRi
))
1236 decrease_GR_busy (cpu
, in_GRi
, 1);
1238 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
1240 if (use_is_gr_complex (cpu
, in_GRj
))
1241 decrease_GR_busy (cpu
, in_GRj
, 1);
1243 vliw_wait_for_GR (cpu
, in_GRi
);
1244 vliw_wait_for_GR (cpu
, in_GRj
);
1245 handle_resource_wait (cpu
);
1246 load_wait_for_GR (cpu
, in_GRi
);
1247 load_wait_for_GR (cpu
, in_GRj
);
1248 trace_vliw_wait_cycles (cpu
);
1252 cycles
= idesc
->timing
->units
[unit_num
].done
;
1253 request_cache_invalidate (cpu
, CPU_DATA_CACHE (cpu
), cycles
);
1258 frvbf_model_fr500_u_dcf (SIM_CPU
*cpu
, const IDESC
*idesc
,
1259 int unit_num
, int referenced
,
1260 INT in_GRi
, INT in_GRj
)
1264 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1266 /* The entire VLIW insn must wait if there is a dependency on a register
1267 which is not ready yet.
1268 The latency of the registers may be less than previously recorded,
1269 depending on how they were used previously.
1270 See Table 13-8 in the LSI. */
1273 if (use_is_gr_complex (cpu
, in_GRi
))
1274 decrease_GR_busy (cpu
, in_GRi
, 1);
1276 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
1278 if (use_is_gr_complex (cpu
, in_GRj
))
1279 decrease_GR_busy (cpu
, in_GRj
, 1);
1281 vliw_wait_for_GR (cpu
, in_GRi
);
1282 vliw_wait_for_GR (cpu
, in_GRj
);
1283 handle_resource_wait (cpu
);
1284 load_wait_for_GR (cpu
, in_GRi
);
1285 load_wait_for_GR (cpu
, in_GRj
);
1286 trace_vliw_wait_cycles (cpu
);
1290 cycles
= idesc
->timing
->units
[unit_num
].done
;
1291 request_cache_flush (cpu
, CPU_DATA_CACHE (cpu
), cycles
);
1296 frvbf_model_fr500_u_icpl (SIM_CPU
*cpu
, const IDESC
*idesc
,
1297 int unit_num
, int referenced
,
1298 INT in_GRi
, INT in_GRj
)
1302 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1304 /* The entire VLIW insn must wait if there is a dependency on a register
1305 which is not ready yet.
1306 The latency of the registers may be less than previously recorded,
1307 depending on how they were used previously.
1308 See Table 13-8 in the LSI. */
1311 if (use_is_gr_complex (cpu
, in_GRi
))
1312 decrease_GR_busy (cpu
, in_GRi
, 1);
1314 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
1316 if (use_is_gr_complex (cpu
, in_GRj
))
1317 decrease_GR_busy (cpu
, in_GRj
, 1);
1319 vliw_wait_for_GR (cpu
, in_GRi
);
1320 vliw_wait_for_GR (cpu
, in_GRj
);
1321 handle_resource_wait (cpu
);
1322 load_wait_for_GR (cpu
, in_GRi
);
1323 load_wait_for_GR (cpu
, in_GRj
);
1324 trace_vliw_wait_cycles (cpu
);
1328 cycles
= idesc
->timing
->units
[unit_num
].done
;
1329 request_cache_preload (cpu
, CPU_INSN_CACHE (cpu
), cycles
);
1334 frvbf_model_fr500_u_dcpl (SIM_CPU
*cpu
, const IDESC
*idesc
,
1335 int unit_num
, int referenced
,
1336 INT in_GRi
, INT in_GRj
)
1340 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1342 /* The entire VLIW insn must wait if there is a dependency on a register
1343 which is not ready yet.
1344 The latency of the registers may be less than previously recorded,
1345 depending on how they were used previously.
1346 See Table 13-8 in the LSI. */
1349 if (use_is_gr_complex (cpu
, in_GRi
))
1350 decrease_GR_busy (cpu
, in_GRi
, 1);
1352 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
1354 if (use_is_gr_complex (cpu
, in_GRj
))
1355 decrease_GR_busy (cpu
, in_GRj
, 1);
1357 vliw_wait_for_GR (cpu
, in_GRi
);
1358 vliw_wait_for_GR (cpu
, in_GRj
);
1359 handle_resource_wait (cpu
);
1360 load_wait_for_GR (cpu
, in_GRi
);
1361 load_wait_for_GR (cpu
, in_GRj
);
1362 trace_vliw_wait_cycles (cpu
);
1366 cycles
= idesc
->timing
->units
[unit_num
].done
;
1367 request_cache_preload (cpu
, CPU_DATA_CACHE (cpu
), cycles
);
1372 frvbf_model_fr500_u_icul (SIM_CPU
*cpu
, const IDESC
*idesc
,
1373 int unit_num
, int referenced
,
1374 INT in_GRi
, INT in_GRj
)
1378 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1380 /* The entire VLIW insn must wait if there is a dependency on a register
1381 which is not ready yet.
1382 The latency of the registers may be less than previously recorded,
1383 depending on how they were used previously.
1384 See Table 13-8 in the LSI. */
1387 if (use_is_gr_complex (cpu
, in_GRi
))
1388 decrease_GR_busy (cpu
, in_GRi
, 1);
1390 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
1392 if (use_is_gr_complex (cpu
, in_GRj
))
1393 decrease_GR_busy (cpu
, in_GRj
, 1);
1395 vliw_wait_for_GR (cpu
, in_GRi
);
1396 vliw_wait_for_GR (cpu
, in_GRj
);
1397 handle_resource_wait (cpu
);
1398 load_wait_for_GR (cpu
, in_GRi
);
1399 load_wait_for_GR (cpu
, in_GRj
);
1400 trace_vliw_wait_cycles (cpu
);
1404 cycles
= idesc
->timing
->units
[unit_num
].done
;
1405 request_cache_unlock (cpu
, CPU_INSN_CACHE (cpu
), cycles
);
1410 frvbf_model_fr500_u_dcul (SIM_CPU
*cpu
, const IDESC
*idesc
,
1411 int unit_num
, int referenced
,
1412 INT in_GRi
, INT in_GRj
)
1416 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1418 /* The entire VLIW insn must wait if there is a dependency on a register
1419 which is not ready yet.
1420 The latency of the registers may be less than previously recorded,
1421 depending on how they were used previously.
1422 See Table 13-8 in the LSI. */
1425 if (use_is_gr_complex (cpu
, in_GRi
))
1426 decrease_GR_busy (cpu
, in_GRi
, 1);
1428 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
1430 if (use_is_gr_complex (cpu
, in_GRj
))
1431 decrease_GR_busy (cpu
, in_GRj
, 1);
1433 vliw_wait_for_GR (cpu
, in_GRi
);
1434 vliw_wait_for_GR (cpu
, in_GRj
);
1435 handle_resource_wait (cpu
);
1436 load_wait_for_GR (cpu
, in_GRi
);
1437 load_wait_for_GR (cpu
, in_GRj
);
1438 trace_vliw_wait_cycles (cpu
);
1442 cycles
= idesc
->timing
->units
[unit_num
].done
;
1443 request_cache_unlock (cpu
, CPU_DATA_CACHE (cpu
), cycles
);
1448 frvbf_model_fr500_u_float_arith (SIM_CPU
*cpu
, const IDESC
*idesc
,
1449 int unit_num
, int referenced
,
1450 INT in_FRi
, INT in_FRj
,
1451 INT in_FRdoublei
, INT in_FRdoublej
,
1452 INT out_FRk
, INT out_FRdoublek
)
1455 FRV_PROFILE_STATE
*ps
;
1457 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1460 /* The preprocessing can execute right away. */
1461 cycles
= idesc
->timing
->units
[unit_num
].done
;
1463 /* The post processing must wait if there is a dependency on a FR
1464 which is not ready yet. */
1465 adjust_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, 1);
1466 adjust_double_register_busy (cpu
, in_FRdoublei
, in_FRdoublej
, out_FRdoublek
,
1468 ps
= CPU_PROFILE_STATE (cpu
);
1469 ps
->post_wait
= cycles
;
1470 post_wait_for_FR (cpu
, in_FRi
);
1471 post_wait_for_FR (cpu
, in_FRj
);
1472 post_wait_for_FR (cpu
, out_FRk
);
1473 post_wait_for_FRdouble (cpu
, in_FRdoublei
);
1474 post_wait_for_FRdouble (cpu
, in_FRdoublej
);
1475 post_wait_for_FRdouble (cpu
, out_FRdoublek
);
1476 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1478 post_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRk
));
1479 post_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRdoublek
));
1481 restore_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, 1);
1482 restore_double_register_busy (cpu
, in_FRdoublei
, in_FRdoublej
, out_FRdoublek
,
1485 /* The latency of FRk will be at least the latency of the other inputs. */
1486 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1487 update_FRdouble_latency (cpu
, out_FRdoublek
, ps
->post_wait
);
1489 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1491 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRk
), ps
->post_wait
);
1492 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRdoublek
), ps
->post_wait
);
1495 /* Once initiated, post-processing will take 3 cycles. */
1496 update_FR_ptime (cpu
, out_FRk
, 3);
1497 update_FRdouble_ptime (cpu
, out_FRdoublek
, 3);
1499 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1501 update_SPR_ptime (cpu
, FNER_FOR_FR (out_FRk
), 3);
1502 update_SPR_ptime (cpu
, FNER_FOR_FR (out_FRdoublek
), 3);
1505 /* Mark this use of the register as a floating point op. */
1507 set_use_is_fpop (cpu
, out_FRk
);
1508 if (out_FRdoublek
>= 0)
1510 set_use_is_fpop (cpu
, out_FRdoublek
);
1511 if (out_FRdoublek
< 63)
1512 set_use_is_fpop (cpu
, out_FRdoublek
+ 1);
1519 frvbf_model_fr500_u_float_dual_arith (SIM_CPU
*cpu
, const IDESC
*idesc
,
1520 int unit_num
, int referenced
,
1521 INT in_FRi
, INT in_FRj
,
1522 INT in_FRdoublei
, INT in_FRdoublej
,
1523 INT out_FRk
, INT out_FRdoublek
)
1532 FRV_PROFILE_STATE
*ps
;
1534 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1537 /* The preprocessing can execute right away. */
1538 cycles
= idesc
->timing
->units
[unit_num
].done
;
1540 /* The post processing must wait if there is a dependency on a FR
1541 which is not ready yet. */
1542 dual_FRi
= DUAL_REG (in_FRi
);
1543 dual_FRj
= DUAL_REG (in_FRj
);
1544 dual_FRk
= DUAL_REG (out_FRk
);
1545 dual_FRdoublei
= DUAL_DOUBLE (in_FRdoublei
);
1546 dual_FRdoublej
= DUAL_DOUBLE (in_FRdoublej
);
1547 dual_FRdoublek
= DUAL_DOUBLE (out_FRdoublek
);
1549 adjust_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, 1);
1550 adjust_float_register_busy (cpu
, dual_FRi
, dual_FRj
, dual_FRk
, 1);
1551 adjust_double_register_busy (cpu
, in_FRdoublei
, in_FRdoublej
, out_FRdoublek
,
1553 adjust_double_register_busy (cpu
, dual_FRdoublei
, dual_FRdoublej
,
1555 ps
= CPU_PROFILE_STATE (cpu
);
1556 ps
->post_wait
= cycles
;
1557 post_wait_for_FR (cpu
, in_FRi
);
1558 post_wait_for_FR (cpu
, in_FRj
);
1559 post_wait_for_FR (cpu
, out_FRk
);
1560 post_wait_for_FR (cpu
, dual_FRi
);
1561 post_wait_for_FR (cpu
, dual_FRj
);
1562 post_wait_for_FR (cpu
, dual_FRk
);
1563 post_wait_for_FRdouble (cpu
, in_FRdoublei
);
1564 post_wait_for_FRdouble (cpu
, in_FRdoublej
);
1565 post_wait_for_FRdouble (cpu
, out_FRdoublek
);
1566 post_wait_for_FRdouble (cpu
, dual_FRdoublei
);
1567 post_wait_for_FRdouble (cpu
, dual_FRdoublej
);
1568 post_wait_for_FRdouble (cpu
, dual_FRdoublek
);
1569 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1571 post_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRk
));
1572 post_wait_for_SPR (cpu
, FNER_FOR_FR (dual_FRk
));
1573 post_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRdoublek
));
1574 post_wait_for_SPR (cpu
, FNER_FOR_FR (dual_FRdoublek
));
1576 restore_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, 1);
1577 restore_float_register_busy (cpu
, dual_FRi
, dual_FRj
, dual_FRk
, 1);
1578 restore_double_register_busy (cpu
, in_FRdoublei
, in_FRdoublej
, out_FRdoublek
,
1580 restore_double_register_busy (cpu
, dual_FRdoublei
, dual_FRdoublej
,
1583 /* The latency of FRk will be at least the latency of the other inputs. */
1584 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1585 update_FR_latency (cpu
, dual_FRk
, ps
->post_wait
);
1586 update_FRdouble_latency (cpu
, out_FRdoublek
, ps
->post_wait
);
1587 update_FRdouble_latency (cpu
, dual_FRdoublek
, ps
->post_wait
);
1589 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1591 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRk
), ps
->post_wait
);
1592 update_SPR_latency (cpu
, FNER_FOR_FR (dual_FRk
), ps
->post_wait
);
1593 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRdoublek
), ps
->post_wait
);
1594 update_SPR_latency (cpu
, FNER_FOR_FR (dual_FRdoublek
), ps
->post_wait
);
1597 /* Once initiated, post-processing will take 3 cycles. */
1598 update_FR_ptime (cpu
, out_FRk
, 3);
1599 update_FR_ptime (cpu
, dual_FRk
, 3);
1600 update_FRdouble_ptime (cpu
, out_FRdoublek
, 3);
1601 update_FRdouble_ptime (cpu
, dual_FRdoublek
, 3);
1603 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1605 update_SPR_ptime (cpu
, FNER_FOR_FR (out_FRk
), 3);
1606 update_SPR_ptime (cpu
, FNER_FOR_FR (dual_FRk
), 3);
1607 update_SPR_ptime (cpu
, FNER_FOR_FR (out_FRdoublek
), 3);
1608 update_SPR_ptime (cpu
, FNER_FOR_FR (dual_FRdoublek
), 3);
1611 /* Mark this use of the register as a floating point op. */
1613 set_use_is_fpop (cpu
, out_FRk
);
1615 set_use_is_fpop (cpu
, dual_FRk
);
1616 if (out_FRdoublek
>= 0)
1618 set_use_is_fpop (cpu
, out_FRdoublek
);
1619 if (out_FRdoublek
< 63)
1620 set_use_is_fpop (cpu
, out_FRdoublek
+ 1);
1622 if (dual_FRdoublek
>= 0)
1624 set_use_is_fpop (cpu
, dual_FRdoublek
);
1625 if (dual_FRdoublek
< 63)
1626 set_use_is_fpop (cpu
, dual_FRdoublek
+ 1);
1633 frvbf_model_fr500_u_float_div (SIM_CPU
*cpu
, const IDESC
*idesc
,
1634 int unit_num
, int referenced
,
1635 INT in_FRi
, INT in_FRj
, INT out_FRk
)
1640 FRV_PROFILE_STATE
*ps
;
1642 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1645 cycles
= idesc
->timing
->units
[unit_num
].done
;
1647 /* The post processing must wait if there is a dependency on a FR
1648 which is not ready yet. */
1649 adjust_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, 1);
1650 ps
= CPU_PROFILE_STATE (cpu
);
1651 ps
->post_wait
= cycles
;
1652 post_wait_for_FR (cpu
, in_FRi
);
1653 post_wait_for_FR (cpu
, in_FRj
);
1654 post_wait_for_FR (cpu
, out_FRk
);
1655 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1656 post_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRk
));
1657 vliw
= CPU_VLIW (cpu
);
1658 slot
= vliw
->next_slot
- 1;
1659 slot
= (*vliw
->current_vliw
)[slot
] - UNIT_FM0
;
1660 post_wait_for_fdiv (cpu
, slot
);
1661 restore_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, 1);
1663 /* The latency of FRk will be at least the latency of the other inputs. */
1664 /* Once initiated, post-processing will take 10 cycles. */
1665 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1666 update_FR_ptime (cpu
, out_FRk
, 10);
1668 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1670 /* FNER has a latency of 10 cycles. */
1671 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRk
), ps
->post_wait
);
1672 update_SPR_ptime (cpu
, FNER_FOR_FR (out_FRk
), 10);
1675 /* The latency of the fdiv unit will be at least the latency of the other
1676 inputs. Once initiated, post-processing will take 9 cycles. */
1677 update_fdiv_resource_latency (cpu
, slot
, ps
->post_wait
+ 9);
1679 /* Mark this use of the register as a floating point op. */
1680 set_use_is_fpop (cpu
, out_FRk
);
1686 frvbf_model_fr500_u_float_sqrt (SIM_CPU
*cpu
, const IDESC
*idesc
,
1687 int unit_num
, int referenced
,
1688 INT in_FRj
, INT in_FRdoublej
,
1689 INT out_FRk
, INT out_FRdoublek
)
1694 FRV_PROFILE_STATE
*ps
;
1696 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1699 cycles
= idesc
->timing
->units
[unit_num
].done
;
1701 /* The post processing must wait if there is a dependency on a FR
1702 which is not ready yet. */
1703 adjust_float_register_busy (cpu
, -1, in_FRj
, out_FRk
, 1);
1704 adjust_double_register_busy (cpu
, -1, in_FRdoublej
, out_FRdoublek
, 1);
1705 ps
= CPU_PROFILE_STATE (cpu
);
1706 ps
->post_wait
= cycles
;
1707 post_wait_for_FR (cpu
, in_FRj
);
1708 post_wait_for_FR (cpu
, out_FRk
);
1709 post_wait_for_FRdouble (cpu
, in_FRdoublej
);
1710 post_wait_for_FRdouble (cpu
, out_FRdoublek
);
1711 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1712 post_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRk
));
1713 vliw
= CPU_VLIW (cpu
);
1714 slot
= vliw
->next_slot
- 1;
1715 slot
= (*vliw
->current_vliw
)[slot
] - UNIT_FM0
;
1716 post_wait_for_fsqrt (cpu
, slot
);
1717 restore_float_register_busy (cpu
, -1, in_FRj
, out_FRk
, 1);
1718 restore_double_register_busy (cpu
, -1, in_FRdoublej
, out_FRdoublek
, 1);
1720 /* The latency of FRk will be at least the latency of the other inputs. */
1721 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1722 update_FRdouble_latency (cpu
, out_FRdoublek
, ps
->post_wait
);
1723 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1724 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRk
), ps
->post_wait
);
1726 /* Once initiated, post-processing will take 15 cycles. */
1727 update_FR_ptime (cpu
, out_FRk
, 15);
1728 update_FRdouble_ptime (cpu
, out_FRdoublek
, 15);
1730 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1731 update_SPR_ptime (cpu
, FNER_FOR_FR (out_FRk
), 15);
1733 /* The latency of the sqrt unit will be the latency of the other
1734 inputs plus 14 cycles. */
1735 update_fsqrt_resource_latency (cpu
, slot
, ps
->post_wait
+ 14);
1737 /* Mark this use of the register as a floating point op. */
1739 set_use_is_fpop (cpu
, out_FRk
);
1740 if (out_FRdoublek
>= 0)
1742 set_use_is_fpop (cpu
, out_FRdoublek
);
1743 if (out_FRdoublek
< 63)
1744 set_use_is_fpop (cpu
, out_FRdoublek
+ 1);
1751 frvbf_model_fr500_u_float_dual_sqrt (SIM_CPU
*cpu
, const IDESC
*idesc
,
1752 int unit_num
, int referenced
,
1753 INT in_FRj
, INT out_FRk
)
1760 FRV_PROFILE_STATE
*ps
;
1762 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1765 cycles
= idesc
->timing
->units
[unit_num
].done
;
1767 /* The post processing must wait if there is a dependency on a FR
1768 which is not ready yet. */
1769 dual_FRj
= DUAL_REG (in_FRj
);
1770 dual_FRk
= DUAL_REG (out_FRk
);
1771 adjust_float_register_busy (cpu
, -1, in_FRj
, out_FRk
, 1);
1772 adjust_float_register_busy (cpu
, -1, dual_FRj
, dual_FRk
, 1);
1773 ps
= CPU_PROFILE_STATE (cpu
);
1774 ps
->post_wait
= cycles
;
1775 post_wait_for_FR (cpu
, in_FRj
);
1776 post_wait_for_FR (cpu
, out_FRk
);
1777 post_wait_for_FR (cpu
, dual_FRj
);
1778 post_wait_for_FR (cpu
, dual_FRk
);
1780 vliw
= CPU_VLIW (cpu
);
1781 slot
= vliw
->next_slot
- 1;
1782 slot
= (*vliw
->current_vliw
)[slot
] - UNIT_FM0
;
1783 post_wait_for_fsqrt (cpu
, slot
);
1784 restore_float_register_busy (cpu
, -1, in_FRj
, out_FRk
, 1);
1785 restore_float_register_busy (cpu
, -1, dual_FRj
, dual_FRk
, 1);
1787 /* The latency of FRk will be at least the latency of the other inputs. */
1788 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1789 update_FR_latency (cpu
, dual_FRk
, ps
->post_wait
);
1791 /* Once initiated, post-processing will take 15 cycles. */
1792 update_FR_ptime (cpu
, out_FRk
, 15);
1793 update_FR_ptime (cpu
, dual_FRk
, 15);
1795 /* The latency of the sqrt unit will be at least the latency of the other
1797 update_fsqrt_resource_latency (cpu
, slot
, ps
->post_wait
+ 14);
1799 /* Mark this use of the register as a floating point op. */
1801 set_use_is_fpop (cpu
, out_FRk
);
1803 set_use_is_fpop (cpu
, dual_FRk
);
1809 frvbf_model_fr500_u_float_compare (SIM_CPU
*cpu
, const IDESC
*idesc
,
1810 int unit_num
, int referenced
,
1811 INT in_FRi
, INT in_FRj
,
1812 INT in_FRdoublei
, INT in_FRdoublej
,
1816 FRV_PROFILE_STATE
*ps
;
1818 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1821 /* The preprocessing can execute right away. */
1822 cycles
= idesc
->timing
->units
[unit_num
].done
;
1824 /* The post processing must wait if there is a dependency on a FR
1825 which is not ready yet. */
1826 adjust_double_register_busy (cpu
, in_FRdoublei
, in_FRdoublej
, -1, 1);
1827 ps
= CPU_PROFILE_STATE (cpu
);
1828 ps
->post_wait
= cycles
;
1829 post_wait_for_FR (cpu
, in_FRi
);
1830 post_wait_for_FR (cpu
, in_FRj
);
1831 post_wait_for_FRdouble (cpu
, in_FRdoublei
);
1832 post_wait_for_FRdouble (cpu
, in_FRdoublej
);
1833 post_wait_for_CCR (cpu
, out_FCCi_2
);
1834 restore_double_register_busy (cpu
, in_FRdoublei
, in_FRdoublej
, -1, 1);
1836 /* The latency of FCCi_2 will be the latency of the other inputs plus 3
1838 update_CCR_latency (cpu
, out_FCCi_2
, ps
->post_wait
+ 3);
1844 frvbf_model_fr500_u_float_dual_compare (SIM_CPU
*cpu
, const IDESC
*idesc
,
1845 int unit_num
, int referenced
,
1846 INT in_FRi
, INT in_FRj
,
1853 FRV_PROFILE_STATE
*ps
;
1855 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1858 /* The preprocessing can execute right away. */
1859 cycles
= idesc
->timing
->units
[unit_num
].done
;
1861 /* The post processing must wait if there is a dependency on a FR
1862 which is not ready yet. */
1863 ps
= CPU_PROFILE_STATE (cpu
);
1864 ps
->post_wait
= cycles
;
1865 dual_FRi
= DUAL_REG (in_FRi
);
1866 dual_FRj
= DUAL_REG (in_FRj
);
1867 dual_FCCi_2
= out_FCCi_2
+ 1;
1868 adjust_float_register_busy (cpu
, in_FRi
, in_FRj
, -1, 1);
1869 adjust_float_register_busy (cpu
, dual_FRi
, dual_FRj
, -1, 1);
1870 post_wait_for_FR (cpu
, in_FRi
);
1871 post_wait_for_FR (cpu
, in_FRj
);
1872 post_wait_for_FR (cpu
, dual_FRi
);
1873 post_wait_for_FR (cpu
, dual_FRj
);
1874 post_wait_for_CCR (cpu
, out_FCCi_2
);
1875 post_wait_for_CCR (cpu
, dual_FCCi_2
);
1876 restore_float_register_busy (cpu
, in_FRi
, in_FRj
, -1, 1);
1877 restore_float_register_busy (cpu
, dual_FRi
, dual_FRj
, -1, 1);
1879 /* The latency of FCCi_2 will be the latency of the other inputs plus 3
1881 update_CCR_latency (cpu
, out_FCCi_2
, ps
->post_wait
+ 3);
1882 update_CCR_latency (cpu
, dual_FCCi_2
, ps
->post_wait
+ 3);
1888 frvbf_model_fr500_u_float_convert (SIM_CPU
*cpu
, const IDESC
*idesc
,
1889 int unit_num
, int referenced
,
1890 INT in_FRj
, INT in_FRintj
, INT in_FRdoublej
,
1891 INT out_FRk
, INT out_FRintk
,
1895 FRV_PROFILE_STATE
*ps
;
1897 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1900 /* The preprocessing can execute right away. */
1901 cycles
= idesc
->timing
->units
[unit_num
].done
;
1903 /* The post processing must wait if there is a dependency on a FR
1904 which is not ready yet. */
1905 ps
= CPU_PROFILE_STATE (cpu
);
1906 ps
->post_wait
= cycles
;
1907 adjust_float_register_busy (cpu
, -1, in_FRj
, out_FRk
, 1);
1908 adjust_float_register_busy (cpu
, -1, in_FRintj
, out_FRintk
, 1);
1909 adjust_double_register_busy (cpu
, -1, in_FRdoublej
, out_FRdoublek
, 1);
1910 post_wait_for_FR (cpu
, in_FRj
);
1911 post_wait_for_FR (cpu
, in_FRintj
);
1912 post_wait_for_FRdouble (cpu
, in_FRdoublej
);
1913 post_wait_for_FR (cpu
, out_FRk
);
1914 post_wait_for_FR (cpu
, out_FRintk
);
1915 post_wait_for_FRdouble (cpu
, out_FRdoublek
);
1916 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1918 post_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRk
));
1919 post_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRintk
));
1920 post_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRdoublek
));
1922 restore_float_register_busy (cpu
, -1, in_FRj
, out_FRk
, 1);
1923 restore_float_register_busy (cpu
, -1, in_FRintj
, out_FRintk
, 1);
1924 restore_double_register_busy (cpu
, -1, in_FRdoublej
, out_FRdoublek
, 1);
1926 /* The latency of FRk will be at least the latency of the other inputs. */
1927 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1928 update_FR_latency (cpu
, out_FRintk
, ps
->post_wait
);
1929 update_FRdouble_latency (cpu
, out_FRdoublek
, ps
->post_wait
);
1931 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1933 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRk
), ps
->post_wait
);
1934 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRintk
), ps
->post_wait
);
1935 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRdoublek
), ps
->post_wait
);
1938 /* Once initiated, post-processing will take 3 cycles. */
1939 update_FR_ptime (cpu
, out_FRk
, 3);
1940 update_FR_ptime (cpu
, out_FRintk
, 3);
1941 update_FRdouble_ptime (cpu
, out_FRdoublek
, 3);
1943 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1945 update_SPR_ptime (cpu
, FNER_FOR_FR (out_FRk
), 3);
1946 update_SPR_ptime (cpu
, FNER_FOR_FR (out_FRintk
), 3);
1947 update_SPR_ptime (cpu
, FNER_FOR_FR (out_FRdoublek
), 3);
1950 /* Mark this use of the register as a floating point op. */
1952 set_use_is_fpop (cpu
, out_FRk
);
1953 if (out_FRintk
>= 0)
1954 set_use_is_fpop (cpu
, out_FRintk
);
1955 if (out_FRdoublek
>= 0)
1957 set_use_is_fpop (cpu
, out_FRdoublek
);
1958 set_use_is_fpop (cpu
, out_FRdoublek
+ 1);
1965 frvbf_model_fr500_u_float_dual_convert (SIM_CPU
*cpu
, const IDESC
*idesc
,
1966 int unit_num
, int referenced
,
1967 INT in_FRj
, INT in_FRintj
,
1968 INT out_FRk
, INT out_FRintk
)
1975 FRV_PROFILE_STATE
*ps
;
1977 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1980 /* The preprocessing can execute right away. */
1981 cycles
= idesc
->timing
->units
[unit_num
].done
;
1983 /* The post processing must wait if there is a dependency on a FR
1984 which is not ready yet. */
1985 ps
= CPU_PROFILE_STATE (cpu
);
1986 ps
->post_wait
= cycles
;
1987 dual_FRj
= DUAL_REG (in_FRj
);
1988 dual_FRintj
= DUAL_REG (in_FRintj
);
1989 dual_FRk
= DUAL_REG (out_FRk
);
1990 dual_FRintk
= DUAL_REG (out_FRintk
);
1991 adjust_float_register_busy (cpu
, -1, in_FRj
, out_FRk
, 1);
1992 adjust_float_register_busy (cpu
, -1, dual_FRj
, dual_FRk
, 1);
1993 adjust_float_register_busy (cpu
, -1, in_FRintj
, out_FRintk
, 1);
1994 adjust_float_register_busy (cpu
, -1, dual_FRintj
, dual_FRintk
, 1);
1995 post_wait_for_FR (cpu
, in_FRj
);
1996 post_wait_for_FR (cpu
, in_FRintj
);
1997 post_wait_for_FR (cpu
, out_FRk
);
1998 post_wait_for_FR (cpu
, out_FRintk
);
1999 post_wait_for_FR (cpu
, dual_FRj
);
2000 post_wait_for_FR (cpu
, dual_FRintj
);
2001 post_wait_for_FR (cpu
, dual_FRk
);
2002 post_wait_for_FR (cpu
, dual_FRintk
);
2003 restore_float_register_busy (cpu
, -1, in_FRj
, out_FRk
, 1);
2004 restore_float_register_busy (cpu
, -1, dual_FRj
, dual_FRk
, 1);
2005 restore_float_register_busy (cpu
, -1, in_FRintj
, out_FRintk
, 1);
2006 restore_float_register_busy (cpu
, -1, dual_FRintj
, dual_FRintk
, 1);
2008 /* The latency of FRk will be at least the latency of the other inputs. */
2009 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
2010 update_FR_latency (cpu
, out_FRintk
, ps
->post_wait
);
2011 update_FR_latency (cpu
, dual_FRk
, ps
->post_wait
);
2012 update_FR_latency (cpu
, dual_FRintk
, ps
->post_wait
);
2014 /* Once initiated, post-processing will take 3 cycles. */
2015 update_FR_ptime (cpu
, out_FRk
, 3);
2016 update_FR_ptime (cpu
, out_FRintk
, 3);
2017 update_FR_ptime (cpu
, dual_FRk
, 3);
2018 update_FR_ptime (cpu
, dual_FRintk
, 3);
2020 /* Mark this use of the register as a floating point op. */
2022 set_use_is_fpop (cpu
, out_FRk
);
2023 if (out_FRintk
>= 0)
2024 set_use_is_fpop (cpu
, out_FRintk
);
2030 frvbf_model_fr500_u_media (SIM_CPU
*cpu
, const IDESC
*idesc
,
2031 int unit_num
, int referenced
,
2032 INT in_FRi
, INT in_FRj
, INT in_ACC40Si
, INT in_ACCGi
,
2034 INT out_ACC40Sk
, INT out_ACC40Uk
, INT out_ACCGk
)
2037 FRV_PROFILE_STATE
*ps
;
2038 const CGEN_INSN
*insn
;
2041 int busy_adjustment
[] = {0, 0, 0};
2045 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2048 /* The preprocessing can execute right away. */
2049 cycles
= idesc
->timing
->units
[unit_num
].done
;
2051 ps
= CPU_PROFILE_STATE (cpu
);
2052 insn
= idesc
->idata
;
2054 /* If the previous use of the registers was a media op,
2055 then their latency will be less than previously recorded.
2056 See Table 13-13 in the LSI. */
2059 if (use_is_media (cpu
, in_FRi
))
2061 busy_adjustment
[0] = 2;
2062 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
2065 enforce_full_fr_latency (cpu
, in_FRi
);
2067 if (in_FRj
>= 0 && in_FRj
!= in_FRi
)
2069 if (use_is_media (cpu
, in_FRj
))
2071 busy_adjustment
[1] = 2;
2072 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[1]);
2075 enforce_full_fr_latency (cpu
, in_FRj
);
2077 if (out_FRk
>= 0 && out_FRk
!= in_FRi
&& out_FRk
!= in_FRj
)
2079 if (use_is_media (cpu
, out_FRk
))
2081 busy_adjustment
[2] = 2;
2082 decrease_FR_busy (cpu
, out_FRk
, busy_adjustment
[2]);
2085 enforce_full_fr_latency (cpu
, out_FRk
);
2088 /* The post processing must wait if there is a dependency on a FR
2089 which is not ready yet. */
2090 ps
->post_wait
= cycles
;
2091 post_wait_for_FR (cpu
, in_FRi
);
2092 post_wait_for_FR (cpu
, in_FRj
);
2093 post_wait_for_FR (cpu
, out_FRk
);
2094 post_wait_for_ACC (cpu
, in_ACC40Si
);
2095 post_wait_for_ACC (cpu
, in_ACCGi
);
2096 post_wait_for_ACC (cpu
, out_ACC40Sk
);
2097 post_wait_for_ACC (cpu
, out_ACC40Uk
);
2098 post_wait_for_ACC (cpu
, out_ACCGk
);
2100 /* Restore the busy cycles of the registers we used. */
2103 fr
[in_FRi
] += busy_adjustment
[0];
2105 fr
[in_FRj
] += busy_adjustment
[1];
2107 fr
[out_FRk
] += busy_adjustment
[2];
2109 /* The latency of tht output register will be at least the latency of the
2110 other inputs. Once initiated, post-processing will take 3 cycles. */
2113 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
2114 update_FR_ptime (cpu
, out_FRk
, 3);
2115 /* Mark this use of the register as a media op. */
2116 set_use_is_media (cpu
, out_FRk
);
2118 /* The latency of tht output accumulator will be at least the latency of the
2119 other inputs. Once initiated, post-processing will take 1 cycle. */
2120 if (out_ACC40Sk
>= 0)
2121 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
2122 if (out_ACC40Uk
>= 0)
2123 update_ACC_latency (cpu
, out_ACC40Uk
, ps
->post_wait
+ 1);
2125 update_ACC_latency (cpu
, out_ACCGk
, ps
->post_wait
+ 1);
2131 frvbf_model_fr500_u_media_quad_arith (SIM_CPU
*cpu
, const IDESC
*idesc
,
2132 int unit_num
, int referenced
,
2133 INT in_FRi
, INT in_FRj
,
2140 FRV_PROFILE_STATE
*ps
;
2141 int busy_adjustment
[] = {0, 0, 0, 0, 0, 0};
2144 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2147 /* The preprocessing can execute right away. */
2148 cycles
= idesc
->timing
->units
[unit_num
].done
;
2150 ps
= CPU_PROFILE_STATE (cpu
);
2151 dual_FRi
= DUAL_REG (in_FRi
);
2152 dual_FRj
= DUAL_REG (in_FRj
);
2153 dual_FRk
= DUAL_REG (out_FRk
);
2155 /* If the previous use of the registers was a media op,
2156 then their latency will be less than previously recorded.
2157 See Table 13-13 in the LSI. */
2158 if (use_is_media (cpu
, in_FRi
))
2160 busy_adjustment
[0] = 2;
2161 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
2164 enforce_full_fr_latency (cpu
, in_FRi
);
2165 if (dual_FRi
>= 0 && use_is_media (cpu
, dual_FRi
))
2167 busy_adjustment
[1] = 2;
2168 decrease_FR_busy (cpu
, dual_FRi
, busy_adjustment
[1]);
2171 enforce_full_fr_latency (cpu
, dual_FRi
);
2172 if (in_FRj
!= in_FRi
)
2174 if (use_is_media (cpu
, in_FRj
))
2176 busy_adjustment
[2] = 2;
2177 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[2]);
2180 enforce_full_fr_latency (cpu
, in_FRj
);
2181 if (dual_FRj
>= 0 && use_is_media (cpu
, dual_FRj
))
2183 busy_adjustment
[3] = 2;
2184 decrease_FR_busy (cpu
, dual_FRj
, busy_adjustment
[3]);
2187 enforce_full_fr_latency (cpu
, dual_FRj
+ 1);
2189 if (out_FRk
!= in_FRi
&& out_FRk
!= in_FRj
)
2191 if (use_is_media (cpu
, out_FRk
))
2193 busy_adjustment
[4] = 2;
2194 decrease_FR_busy (cpu
, out_FRk
, busy_adjustment
[4]);
2197 enforce_full_fr_latency (cpu
, out_FRk
);
2198 if (dual_FRk
>= 0 && use_is_media (cpu
, dual_FRk
))
2200 busy_adjustment
[5] = 2;
2201 decrease_FR_busy (cpu
, dual_FRk
, busy_adjustment
[5]);
2204 enforce_full_fr_latency (cpu
, dual_FRk
);
2207 /* The post processing must wait if there is a dependency on a FR
2208 which is not ready yet. */
2209 ps
->post_wait
= cycles
;
2210 post_wait_for_FR (cpu
, in_FRi
);
2211 post_wait_for_FR (cpu
, dual_FRi
);
2212 post_wait_for_FR (cpu
, in_FRj
);
2213 post_wait_for_FR (cpu
, dual_FRj
);
2214 post_wait_for_FR (cpu
, out_FRk
);
2215 post_wait_for_FR (cpu
, dual_FRk
);
2217 /* Restore the busy cycles of the registers we used. */
2219 fr
[in_FRi
] += busy_adjustment
[0];
2221 fr
[dual_FRi
] += busy_adjustment
[1];
2222 fr
[in_FRj
] += busy_adjustment
[2];
2224 fr
[dual_FRj
] += busy_adjustment
[3];
2225 fr
[out_FRk
] += busy_adjustment
[4];
2227 fr
[dual_FRk
] += busy_adjustment
[5];
2229 /* The latency of tht output register will be at least the latency of the
2231 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
2233 /* Once initiated, post-processing will take 3 cycles. */
2234 update_FR_ptime (cpu
, out_FRk
, 3);
2236 /* Mark this use of the register as a media op. */
2237 set_use_is_media (cpu
, out_FRk
);
2240 update_FR_latency (cpu
, dual_FRk
, ps
->post_wait
);
2241 update_FR_ptime (cpu
, dual_FRk
, 3);
2242 /* Mark this use of the register as a media op. */
2243 set_use_is_media (cpu
, dual_FRk
);
2250 frvbf_model_fr500_u_media_dual_mul (SIM_CPU
*cpu
, const IDESC
*idesc
,
2251 int unit_num
, int referenced
,
2252 INT in_FRi
, INT in_FRj
,
2253 INT out_ACC40Sk
, INT out_ACC40Uk
)
2258 FRV_PROFILE_STATE
*ps
;
2259 int busy_adjustment
[] = {0, 0, 0, 0, 0, 0};
2263 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2266 /* The preprocessing can execute right away. */
2267 cycles
= idesc
->timing
->units
[unit_num
].done
;
2269 ps
= CPU_PROFILE_STATE (cpu
);
2270 dual_ACC40Sk
= DUAL_REG (out_ACC40Sk
);
2271 dual_ACC40Uk
= DUAL_REG (out_ACC40Uk
);
2273 /* If the previous use of the registers was a media op,
2274 then their latency will be less than previously recorded.
2275 See Table 13-13 in the LSI. */
2276 if (use_is_media (cpu
, in_FRi
))
2278 busy_adjustment
[0] = 2;
2279 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
2282 enforce_full_fr_latency (cpu
, in_FRi
);
2283 if (in_FRj
!= in_FRi
)
2285 if (use_is_media (cpu
, in_FRj
))
2287 busy_adjustment
[1] = 2;
2288 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[1]);
2291 enforce_full_fr_latency (cpu
, in_FRj
);
2293 if (out_ACC40Sk
>= 0)
2295 busy_adjustment
[2] = 1;
2296 decrease_ACC_busy (cpu
, out_ACC40Sk
, busy_adjustment
[2]);
2298 if (dual_ACC40Sk
>= 0)
2300 busy_adjustment
[3] = 1;
2301 decrease_ACC_busy (cpu
, dual_ACC40Sk
, busy_adjustment
[3]);
2303 if (out_ACC40Uk
>= 0)
2305 busy_adjustment
[4] = 1;
2306 decrease_ACC_busy (cpu
, out_ACC40Uk
, busy_adjustment
[4]);
2308 if (dual_ACC40Uk
>= 0)
2310 busy_adjustment
[5] = 1;
2311 decrease_ACC_busy (cpu
, dual_ACC40Uk
, busy_adjustment
[5]);
2314 /* The post processing must wait if there is a dependency on a FR
2315 which is not ready yet. */
2316 ps
->post_wait
= cycles
;
2317 post_wait_for_FR (cpu
, in_FRi
);
2318 post_wait_for_FR (cpu
, in_FRj
);
2319 post_wait_for_ACC (cpu
, out_ACC40Sk
);
2320 post_wait_for_ACC (cpu
, dual_ACC40Sk
);
2321 post_wait_for_ACC (cpu
, out_ACC40Uk
);
2322 post_wait_for_ACC (cpu
, dual_ACC40Uk
);
2324 /* Restore the busy cycles of the registers we used. */
2327 fr
[in_FRi
] += busy_adjustment
[0];
2328 fr
[in_FRj
] += busy_adjustment
[1];
2329 if (out_ACC40Sk
>= 0)
2330 acc
[out_ACC40Sk
] += busy_adjustment
[2];
2331 if (dual_ACC40Sk
>= 0)
2332 acc
[dual_ACC40Sk
] += busy_adjustment
[3];
2333 if (out_ACC40Uk
>= 0)
2334 acc
[out_ACC40Uk
] += busy_adjustment
[4];
2335 if (dual_ACC40Uk
>= 0)
2336 acc
[dual_ACC40Uk
] += busy_adjustment
[5];
2338 /* The latency of tht output register will be at least the latency of the
2339 other inputs. Once initiated, post-processing will take 1 cycle. */
2340 if (out_ACC40Sk
>= 0)
2341 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
2342 if (dual_ACC40Sk
>= 0)
2343 update_ACC_latency (cpu
, dual_ACC40Sk
, ps
->post_wait
+ 1);
2344 if (out_ACC40Uk
>= 0)
2345 update_ACC_latency (cpu
, out_ACC40Uk
, ps
->post_wait
+ 1);
2346 if (dual_ACC40Uk
>= 0)
2347 update_ACC_latency (cpu
, dual_ACC40Uk
, ps
->post_wait
+ 1);
2353 frvbf_model_fr500_u_media_quad_mul (SIM_CPU
*cpu
, const IDESC
*idesc
,
2354 int unit_num
, int referenced
,
2355 INT in_FRi
, INT in_FRj
,
2356 INT out_ACC40Sk
, INT out_ACC40Uk
)
2367 FRV_PROFILE_STATE
*ps
;
2368 int busy_adjustment
[] = {0, 0, 0, 0, 0, 0, 0 ,0};
2372 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2375 /* The preprocessing can execute right away. */
2376 cycles
= idesc
->timing
->units
[unit_num
].done
;
2378 FRi_1
= DUAL_REG (in_FRi
);
2379 FRj_1
= DUAL_REG (in_FRj
);
2380 ACC40Sk_1
= DUAL_REG (out_ACC40Sk
);
2381 ACC40Sk_2
= DUAL_REG (ACC40Sk_1
);
2382 ACC40Sk_3
= DUAL_REG (ACC40Sk_2
);
2383 ACC40Uk_1
= DUAL_REG (out_ACC40Uk
);
2384 ACC40Uk_2
= DUAL_REG (ACC40Uk_1
);
2385 ACC40Uk_3
= DUAL_REG (ACC40Uk_2
);
2387 /* If the previous use of the registers was a media op,
2388 then their latency will be less than previously recorded.
2389 See Table 13-13 in the LSI. */
2390 ps
= CPU_PROFILE_STATE (cpu
);
2391 if (use_is_media (cpu
, in_FRi
))
2393 busy_adjustment
[0] = 2;
2394 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
2397 enforce_full_fr_latency (cpu
, in_FRi
);
2400 if (use_is_media (cpu
, FRi_1
))
2402 busy_adjustment
[1] = 2;
2403 decrease_FR_busy (cpu
, FRi_1
, busy_adjustment
[1]);
2406 enforce_full_fr_latency (cpu
, FRi_1
);
2408 if (in_FRj
!= in_FRi
)
2410 if (use_is_media (cpu
, in_FRj
))
2412 busy_adjustment
[2] = 2;
2413 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[2]);
2416 enforce_full_fr_latency (cpu
, in_FRj
);
2419 if (use_is_media (cpu
, FRj_1
))
2421 busy_adjustment
[3] = 2;
2422 decrease_FR_busy (cpu
, FRj_1
, busy_adjustment
[3]);
2425 enforce_full_fr_latency (cpu
, FRj_1
);
2428 if (out_ACC40Sk
>= 0)
2430 busy_adjustment
[4] = 1;
2431 decrease_ACC_busy (cpu
, out_ACC40Sk
, busy_adjustment
[4]);
2435 busy_adjustment
[5] = 1;
2436 decrease_ACC_busy (cpu
, ACC40Sk_1
, busy_adjustment
[5]);
2440 busy_adjustment
[6] = 1;
2441 decrease_ACC_busy (cpu
, ACC40Sk_2
, busy_adjustment
[6]);
2445 busy_adjustment
[7] = 1;
2446 decrease_ACC_busy (cpu
, ACC40Sk_3
, busy_adjustment
[7]);
2449 else if (out_ACC40Uk
>= 0)
2451 busy_adjustment
[4] = 1;
2452 decrease_ACC_busy (cpu
, out_ACC40Uk
, busy_adjustment
[4]);
2456 busy_adjustment
[5] = 1;
2457 decrease_ACC_busy (cpu
, ACC40Uk_1
, busy_adjustment
[5]);
2461 busy_adjustment
[6] = 1;
2462 decrease_ACC_busy (cpu
, ACC40Uk_2
, busy_adjustment
[6]);
2466 busy_adjustment
[7] = 1;
2467 decrease_ACC_busy (cpu
, ACC40Uk_3
, busy_adjustment
[7]);
2471 /* The post processing must wait if there is a dependency on a FR
2472 which is not ready yet. */
2473 ps
->post_wait
= cycles
;
2474 post_wait_for_FR (cpu
, in_FRi
);
2475 post_wait_for_FR (cpu
, FRi_1
);
2476 post_wait_for_FR (cpu
, in_FRj
);
2477 post_wait_for_FR (cpu
, FRj_1
);
2478 post_wait_for_ACC (cpu
, out_ACC40Sk
);
2479 post_wait_for_ACC (cpu
, ACC40Sk_1
);
2480 post_wait_for_ACC (cpu
, ACC40Sk_2
);
2481 post_wait_for_ACC (cpu
, ACC40Sk_3
);
2482 post_wait_for_ACC (cpu
, out_ACC40Uk
);
2483 post_wait_for_ACC (cpu
, ACC40Uk_1
);
2484 post_wait_for_ACC (cpu
, ACC40Uk_2
);
2485 post_wait_for_ACC (cpu
, ACC40Uk_3
);
2487 /* Restore the busy cycles of the registers we used. */
2490 fr
[in_FRi
] += busy_adjustment
[0];
2492 fr
[FRi_1
] += busy_adjustment
[1];
2493 fr
[in_FRj
] += busy_adjustment
[2];
2495 fr
[FRj_1
] += busy_adjustment
[3];
2496 if (out_ACC40Sk
>= 0)
2498 acc
[out_ACC40Sk
] += busy_adjustment
[4];
2500 acc
[ACC40Sk_1
] += busy_adjustment
[5];
2502 acc
[ACC40Sk_2
] += busy_adjustment
[6];
2504 acc
[ACC40Sk_3
] += busy_adjustment
[7];
2506 else if (out_ACC40Uk
>= 0)
2508 acc
[out_ACC40Uk
] += busy_adjustment
[4];
2510 acc
[ACC40Uk_1
] += busy_adjustment
[5];
2512 acc
[ACC40Uk_2
] += busy_adjustment
[6];
2514 acc
[ACC40Uk_3
] += busy_adjustment
[7];
2517 /* The latency of tht output register will be at least the latency of the
2518 other inputs. Once initiated, post-processing will take 1 cycle. */
2519 if (out_ACC40Sk
>= 0)
2521 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
2523 update_ACC_latency (cpu
, ACC40Sk_1
, ps
->post_wait
+ 1);
2525 update_ACC_latency (cpu
, ACC40Sk_2
, ps
->post_wait
+ 1);
2527 update_ACC_latency (cpu
, ACC40Sk_3
, ps
->post_wait
+ 1);
2529 else if (out_ACC40Uk
>= 0)
2531 update_ACC_latency (cpu
, out_ACC40Uk
, ps
->post_wait
+ 1);
2533 update_ACC_latency (cpu
, ACC40Uk_1
, ps
->post_wait
+ 1);
2535 update_ACC_latency (cpu
, ACC40Uk_2
, ps
->post_wait
+ 1);
2537 update_ACC_latency (cpu
, ACC40Uk_3
, ps
->post_wait
+ 1);
2544 frvbf_model_fr500_u_media_quad_complex (SIM_CPU
*cpu
, const IDESC
*idesc
,
2545 int unit_num
, int referenced
,
2546 INT in_FRi
, INT in_FRj
,
2553 FRV_PROFILE_STATE
*ps
;
2554 int busy_adjustment
[] = {0, 0, 0, 0, 0, 0};
2558 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2561 /* The preprocessing can execute right away. */
2562 cycles
= idesc
->timing
->units
[unit_num
].done
;
2564 FRi_1
= DUAL_REG (in_FRi
);
2565 FRj_1
= DUAL_REG (in_FRj
);
2566 ACC40Sk_1
= DUAL_REG (out_ACC40Sk
);
2568 /* If the previous use of the registers was a media op,
2569 then their latency will be less than previously recorded.
2570 See Table 13-13 in the LSI. */
2571 ps
= CPU_PROFILE_STATE (cpu
);
2572 if (use_is_media (cpu
, in_FRi
))
2574 busy_adjustment
[0] = 2;
2575 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
2578 enforce_full_fr_latency (cpu
, in_FRi
);
2581 if (use_is_media (cpu
, FRi_1
))
2583 busy_adjustment
[1] = 2;
2584 decrease_FR_busy (cpu
, FRi_1
, busy_adjustment
[1]);
2587 enforce_full_fr_latency (cpu
, FRi_1
);
2589 if (in_FRj
!= in_FRi
)
2591 if (use_is_media (cpu
, in_FRj
))
2593 busy_adjustment
[2] = 2;
2594 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[2]);
2597 enforce_full_fr_latency (cpu
, in_FRj
);
2600 if (use_is_media (cpu
, FRj_1
))
2602 busy_adjustment
[3] = 2;
2603 decrease_FR_busy (cpu
, FRj_1
, busy_adjustment
[3]);
2606 enforce_full_fr_latency (cpu
, FRj_1
);
2609 if (out_ACC40Sk
>= 0)
2611 busy_adjustment
[4] = 1;
2612 decrease_ACC_busy (cpu
, out_ACC40Sk
, busy_adjustment
[4]);
2616 busy_adjustment
[5] = 1;
2617 decrease_ACC_busy (cpu
, ACC40Sk_1
, busy_adjustment
[5]);
2621 /* The post processing must wait if there is a dependency on a FR
2622 which is not ready yet. */
2623 ps
->post_wait
= cycles
;
2624 post_wait_for_FR (cpu
, in_FRi
);
2625 post_wait_for_FR (cpu
, FRi_1
);
2626 post_wait_for_FR (cpu
, in_FRj
);
2627 post_wait_for_FR (cpu
, FRj_1
);
2628 post_wait_for_ACC (cpu
, out_ACC40Sk
);
2629 post_wait_for_ACC (cpu
, ACC40Sk_1
);
2631 /* Restore the busy cycles of the registers we used. */
2634 fr
[in_FRi
] += busy_adjustment
[0];
2636 fr
[FRi_1
] += busy_adjustment
[1];
2637 fr
[in_FRj
] += busy_adjustment
[2];
2639 fr
[FRj_1
] += busy_adjustment
[3];
2640 if (out_ACC40Sk
>= 0)
2642 acc
[out_ACC40Sk
] += busy_adjustment
[4];
2644 acc
[ACC40Sk_1
] += busy_adjustment
[5];
2647 /* The latency of tht output register will be at least the latency of the
2648 other inputs. Once initiated, post-processing will take 1 cycle. */
2649 if (out_ACC40Sk
>= 0)
2651 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
2653 update_ACC_latency (cpu
, ACC40Sk_1
, ps
->post_wait
+ 1);
2660 frvbf_model_fr500_u_media_dual_expand (SIM_CPU
*cpu
, const IDESC
*idesc
,
2661 int unit_num
, int referenced
,
2667 FRV_PROFILE_STATE
*ps
;
2668 int busy_adjustment
[] = {0, 0, 0};
2671 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2674 /* The preprocessing can execute right away. */
2675 cycles
= idesc
->timing
->units
[unit_num
].done
;
2677 /* If the previous use of the registers was a media op,
2678 then their latency will be less than previously recorded.
2679 See Table 13-13 in the LSI. */
2680 dual_FRk
= DUAL_REG (out_FRk
);
2681 ps
= CPU_PROFILE_STATE (cpu
);
2682 if (use_is_media (cpu
, in_FRi
))
2684 busy_adjustment
[0] = 2;
2685 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
2688 enforce_full_fr_latency (cpu
, in_FRi
);
2689 if (out_FRk
!= in_FRi
)
2691 if (use_is_media (cpu
, out_FRk
))
2693 busy_adjustment
[1] = 2;
2694 decrease_FR_busy (cpu
, out_FRk
, busy_adjustment
[1]);
2697 enforce_full_fr_latency (cpu
, out_FRk
);
2699 if (dual_FRk
>= 0 && dual_FRk
!= in_FRi
)
2701 if (use_is_media (cpu
, dual_FRk
))
2703 busy_adjustment
[2] = 2;
2704 decrease_FR_busy (cpu
, dual_FRk
, busy_adjustment
[2]);
2707 enforce_full_fr_latency (cpu
, dual_FRk
);
2710 /* The post processing must wait if there is a dependency on a FR
2711 which is not ready yet. */
2712 ps
->post_wait
= cycles
;
2713 post_wait_for_FR (cpu
, in_FRi
);
2714 post_wait_for_FR (cpu
, out_FRk
);
2715 post_wait_for_FR (cpu
, dual_FRk
);
2717 /* Restore the busy cycles of the registers we used. */
2719 fr
[in_FRi
] += busy_adjustment
[0];
2720 fr
[out_FRk
] += busy_adjustment
[1];
2722 fr
[dual_FRk
] += busy_adjustment
[2];
2724 /* The latency of the output register will be at least the latency of the
2725 other inputs. Once initiated, post-processing will take 3 cycles. */
2726 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
2727 update_FR_ptime (cpu
, out_FRk
, 3);
2729 /* Mark this use of the register as a media op. */
2730 set_use_is_media (cpu
, out_FRk
);
2733 update_FR_latency (cpu
, dual_FRk
, ps
->post_wait
);
2734 update_FR_ptime (cpu
, dual_FRk
, 3);
2736 /* Mark this use of the register as a media op. */
2737 set_use_is_media (cpu
, dual_FRk
);
2744 frvbf_model_fr500_u_media_dual_unpack (SIM_CPU
*cpu
, const IDESC
*idesc
,
2745 int unit_num
, int referenced
,
2754 FRV_PROFILE_STATE
*ps
;
2755 int busy_adjustment
[] = {0, 0, 0, 0, 0, 0};
2758 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2761 /* The preprocessing can execute right away. */
2762 cycles
= idesc
->timing
->units
[unit_num
].done
;
2764 FRi_1
= DUAL_REG (in_FRi
);
2765 FRk_1
= DUAL_REG (out_FRk
);
2766 FRk_2
= DUAL_REG (FRk_1
);
2767 FRk_3
= DUAL_REG (FRk_2
);
2769 /* If the previous use of the registers was a media op,
2770 then their latency will be less than previously recorded.
2771 See Table 13-13 in the LSI. */
2772 ps
= CPU_PROFILE_STATE (cpu
);
2773 if (use_is_media (cpu
, in_FRi
))
2775 busy_adjustment
[0] = 2;
2776 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
2779 enforce_full_fr_latency (cpu
, in_FRi
);
2780 if (FRi_1
>= 0 && use_is_media (cpu
, FRi_1
))
2782 busy_adjustment
[1] = 2;
2783 decrease_FR_busy (cpu
, FRi_1
, busy_adjustment
[1]);
2786 enforce_full_fr_latency (cpu
, FRi_1
);
2787 if (out_FRk
!= in_FRi
)
2789 if (use_is_media (cpu
, out_FRk
))
2791 busy_adjustment
[2] = 2;
2792 decrease_FR_busy (cpu
, out_FRk
, busy_adjustment
[2]);
2795 enforce_full_fr_latency (cpu
, out_FRk
);
2796 if (FRk_1
>= 0 && FRk_1
!= in_FRi
)
2798 if (use_is_media (cpu
, FRk_1
))
2800 busy_adjustment
[3] = 2;
2801 decrease_FR_busy (cpu
, FRk_1
, busy_adjustment
[3]);
2804 enforce_full_fr_latency (cpu
, FRk_1
);
2806 if (FRk_2
>= 0 && FRk_2
!= in_FRi
)
2808 if (use_is_media (cpu
, FRk_2
))
2810 busy_adjustment
[4] = 2;
2811 decrease_FR_busy (cpu
, FRk_2
, busy_adjustment
[4]);
2814 enforce_full_fr_latency (cpu
, FRk_2
);
2816 if (FRk_3
>= 0 && FRk_3
!= in_FRi
)
2818 if (use_is_media (cpu
, FRk_3
))
2820 busy_adjustment
[5] = 2;
2821 decrease_FR_busy (cpu
, FRk_3
, busy_adjustment
[5]);
2824 enforce_full_fr_latency (cpu
, FRk_3
);
2828 /* The post processing must wait if there is a dependency on a FR
2829 which is not ready yet. */
2830 ps
->post_wait
= cycles
;
2831 post_wait_for_FR (cpu
, in_FRi
);
2832 post_wait_for_FR (cpu
, FRi_1
);
2833 post_wait_for_FR (cpu
, out_FRk
);
2834 post_wait_for_FR (cpu
, FRk_1
);
2835 post_wait_for_FR (cpu
, FRk_2
);
2836 post_wait_for_FR (cpu
, FRk_3
);
2838 /* Restore the busy cycles of the registers we used. */
2840 fr
[in_FRi
] += busy_adjustment
[0];
2842 fr
[FRi_1
] += busy_adjustment
[1];
2843 fr
[out_FRk
] += busy_adjustment
[2];
2845 fr
[FRk_1
] += busy_adjustment
[3];
2847 fr
[FRk_2
] += busy_adjustment
[4];
2849 fr
[FRk_3
] += busy_adjustment
[5];
2851 /* The latency of tht output register will be at least the latency of the
2852 other inputs. Once initiated, post-processing will take 3 cycles. */
2853 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
2854 update_FR_ptime (cpu
, out_FRk
, 3);
2856 /* Mark this use of the register as a media op. */
2857 set_use_is_media (cpu
, out_FRk
);
2860 update_FR_latency (cpu
, FRk_1
, ps
->post_wait
);
2861 update_FR_ptime (cpu
, FRk_1
, 3);
2863 /* Mark this use of the register as a media op. */
2864 set_use_is_media (cpu
, FRk_1
);
2868 update_FR_latency (cpu
, FRk_2
, ps
->post_wait
);
2869 update_FR_ptime (cpu
, FRk_2
, 3);
2871 /* Mark this use of the register as a media op. */
2872 set_use_is_media (cpu
, FRk_2
);
2876 update_FR_latency (cpu
, FRk_3
, ps
->post_wait
);
2877 update_FR_ptime (cpu
, FRk_3
, 3);
2879 /* Mark this use of the register as a media op. */
2880 set_use_is_media (cpu
, FRk_3
);
2887 frvbf_model_fr500_u_media_dual_btoh (SIM_CPU
*cpu
, const IDESC
*idesc
,
2888 int unit_num
, int referenced
,
2892 return frvbf_model_fr500_u_media_dual_expand (cpu
, idesc
, unit_num
,
2893 referenced
, in_FRj
, out_FRk
);
2897 frvbf_model_fr500_u_media_dual_htob (SIM_CPU
*cpu
, const IDESC
*idesc
,
2898 int unit_num
, int referenced
,
2904 FRV_PROFILE_STATE
*ps
;
2905 int busy_adjustment
[] = {0, 0, 0};
2908 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2911 /* The preprocessing can execute right away. */
2912 cycles
= idesc
->timing
->units
[unit_num
].done
;
2914 /* If the previous use of the registers was a media op,
2915 then their latency will be less than previously recorded.
2916 See Table 13-13 in the LSI. */
2917 dual_FRj
= DUAL_REG (in_FRj
);
2918 ps
= CPU_PROFILE_STATE (cpu
);
2919 if (use_is_media (cpu
, in_FRj
))
2921 busy_adjustment
[0] = 2;
2922 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[0]);
2925 enforce_full_fr_latency (cpu
, in_FRj
);
2928 if (use_is_media (cpu
, dual_FRj
))
2930 busy_adjustment
[1] = 2;
2931 decrease_FR_busy (cpu
, dual_FRj
, busy_adjustment
[1]);
2934 enforce_full_fr_latency (cpu
, dual_FRj
);
2936 if (out_FRk
!= in_FRj
)
2938 if (use_is_media (cpu
, out_FRk
))
2940 busy_adjustment
[2] = 2;
2941 decrease_FR_busy (cpu
, out_FRk
, busy_adjustment
[2]);
2944 enforce_full_fr_latency (cpu
, out_FRk
);
2947 /* The post processing must wait if there is a dependency on a FR
2948 which is not ready yet. */
2949 ps
->post_wait
= cycles
;
2950 post_wait_for_FR (cpu
, in_FRj
);
2951 post_wait_for_FR (cpu
, dual_FRj
);
2952 post_wait_for_FR (cpu
, out_FRk
);
2954 /* Restore the busy cycles of the registers we used. */
2956 fr
[in_FRj
] += busy_adjustment
[0];
2958 fr
[dual_FRj
] += busy_adjustment
[1];
2959 fr
[out_FRk
] += busy_adjustment
[2];
2961 /* The latency of tht output register will be at least the latency of the
2963 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
2965 /* Once initiated, post-processing will take 3 cycles. */
2966 update_FR_ptime (cpu
, out_FRk
, 3);
2968 /* Mark this use of the register as a media op. */
2969 set_use_is_media (cpu
, out_FRk
);
2975 frvbf_model_fr500_u_media_dual_btohe (SIM_CPU
*cpu
, const IDESC
*idesc
,
2976 int unit_num
, int referenced
,
2984 FRV_PROFILE_STATE
*ps
;
2985 int busy_adjustment
[] = {0, 0, 0, 0, 0};
2988 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2991 /* The preprocessing can execute right away. */
2992 cycles
= idesc
->timing
->units
[unit_num
].done
;
2994 FRk_1
= DUAL_REG (out_FRk
);
2995 FRk_2
= DUAL_REG (FRk_1
);
2996 FRk_3
= DUAL_REG (FRk_2
);
2998 /* If the previous use of the registers was a media op,
2999 then their latency will be less than previously recorded.
3000 See Table 13-13 in the LSI. */
3001 ps
= CPU_PROFILE_STATE (cpu
);
3002 if (use_is_media (cpu
, in_FRj
))
3004 busy_adjustment
[0] = 2;
3005 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[0]);
3008 enforce_full_fr_latency (cpu
, in_FRj
);
3009 if (out_FRk
!= in_FRj
)
3011 if (use_is_media (cpu
, out_FRk
))
3013 busy_adjustment
[1] = 2;
3014 decrease_FR_busy (cpu
, out_FRk
, busy_adjustment
[1]);
3017 enforce_full_fr_latency (cpu
, out_FRk
);
3018 if (FRk_1
>= 0 && FRk_1
!= in_FRj
)
3020 if (use_is_media (cpu
, FRk_1
))
3022 busy_adjustment
[2] = 2;
3023 decrease_FR_busy (cpu
, FRk_1
, busy_adjustment
[2]);
3026 enforce_full_fr_latency (cpu
, FRk_1
);
3028 if (FRk_2
>= 0 && FRk_2
!= in_FRj
)
3030 if (use_is_media (cpu
, FRk_2
))
3032 busy_adjustment
[3] = 2;
3033 decrease_FR_busy (cpu
, FRk_2
, busy_adjustment
[3]);
3036 enforce_full_fr_latency (cpu
, FRk_2
);
3038 if (FRk_3
>= 0 && FRk_3
!= in_FRj
)
3040 if (use_is_media (cpu
, FRk_3
))
3042 busy_adjustment
[4] = 2;
3043 decrease_FR_busy (cpu
, FRk_3
, busy_adjustment
[4]);
3046 enforce_full_fr_latency (cpu
, FRk_3
);
3050 /* The post processing must wait if there is a dependency on a FR
3051 which is not ready yet. */
3052 ps
->post_wait
= cycles
;
3053 post_wait_for_FR (cpu
, in_FRj
);
3054 post_wait_for_FR (cpu
, out_FRk
);
3055 post_wait_for_FR (cpu
, FRk_1
);
3056 post_wait_for_FR (cpu
, FRk_2
);
3057 post_wait_for_FR (cpu
, FRk_3
);
3059 /* Restore the busy cycles of the registers we used. */
3061 fr
[in_FRj
] += busy_adjustment
[0];
3062 fr
[out_FRk
] += busy_adjustment
[1];
3064 fr
[FRk_1
] += busy_adjustment
[2];
3066 fr
[FRk_2
] += busy_adjustment
[3];
3068 fr
[FRk_3
] += busy_adjustment
[4];
3070 /* The latency of tht output register will be at least the latency of the
3071 other inputs. Once initiated, post-processing will take 3 cycles. */
3072 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
3073 update_FR_ptime (cpu
, out_FRk
, 3);
3075 /* Mark this use of the register as a media op. */
3076 set_use_is_media (cpu
, out_FRk
);
3079 update_FR_latency (cpu
, FRk_1
, ps
->post_wait
);
3080 update_FR_ptime (cpu
, FRk_1
, 3);
3082 /* Mark this use of the register as a media op. */
3083 set_use_is_media (cpu
, FRk_1
);
3087 update_FR_latency (cpu
, FRk_2
, ps
->post_wait
);
3088 update_FR_ptime (cpu
, FRk_2
, 3);
3090 /* Mark this use of the register as a media op. */
3091 set_use_is_media (cpu
, FRk_2
);
3095 update_FR_latency (cpu
, FRk_3
, ps
->post_wait
);
3096 update_FR_ptime (cpu
, FRk_3
, 3);
3098 /* Mark this use of the register as a media op. */
3099 set_use_is_media (cpu
, FRk_3
);
3106 frvbf_model_fr500_u_barrier (SIM_CPU
*cpu
, const IDESC
*idesc
,
3107 int unit_num
, int referenced
)
3110 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
3113 /* Wait for ALL resources. */
3114 for (i
= 0; i
< 64; ++i
)
3116 enforce_full_fr_latency (cpu
, i
);
3117 vliw_wait_for_GR (cpu
, i
);
3118 vliw_wait_for_FR (cpu
, i
);
3119 vliw_wait_for_ACC (cpu
, i
);
3121 for (i
= 0; i
< 8; ++i
)
3122 vliw_wait_for_CCR (cpu
, i
);
3123 for (i
= 0; i
< 2; ++i
)
3125 vliw_wait_for_idiv_resource (cpu
, i
);
3126 vliw_wait_for_fdiv_resource (cpu
, i
);
3127 vliw_wait_for_fsqrt_resource (cpu
, i
);
3129 handle_resource_wait (cpu
);
3130 for (i
= 0; i
< 64; ++i
)
3132 load_wait_for_GR (cpu
, i
);
3133 load_wait_for_FR (cpu
, i
);
3135 trace_vliw_wait_cycles (cpu
);
3139 cycles
= idesc
->timing
->units
[unit_num
].done
;
3144 frvbf_model_fr500_u_membar (SIM_CPU
*cpu
, const IDESC
*idesc
,
3145 int unit_num
, int referenced
)
3148 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
3151 /* Wait for ALL resources, except GR and ICC. */
3152 for (i
= 0; i
< 64; ++i
)
3154 enforce_full_fr_latency (cpu
, i
);
3155 vliw_wait_for_FR (cpu
, i
);
3156 vliw_wait_for_ACC (cpu
, i
);
3158 for (i
= 0; i
< 4; ++i
)
3159 vliw_wait_for_CCR (cpu
, i
);
3160 for (i
= 0; i
< 2; ++i
)
3162 vliw_wait_for_idiv_resource (cpu
, i
);
3163 vliw_wait_for_fdiv_resource (cpu
, i
);
3164 vliw_wait_for_fsqrt_resource (cpu
, i
);
3166 handle_resource_wait (cpu
);
3167 for (i
= 0; i
< 64; ++i
)
3169 load_wait_for_FR (cpu
, i
);
3171 trace_vliw_wait_cycles (cpu
);
3175 cycles
= idesc
->timing
->units
[unit_num
].done
;
3179 /* The frv machine is a fictional implementation of the fr500 which implements
3180 all frv architectural features. */
3182 frvbf_model_frv_u_exec (SIM_CPU
*cpu
, const IDESC
*idesc
,
3183 int unit_num
, int referenced
)
3185 return idesc
->timing
->units
[unit_num
].done
;
3188 /* The simple machine is a fictional implementation of the fr500 which
3189 implements limited frv architectural features. */
3191 frvbf_model_simple_u_exec (SIM_CPU
*cpu
, const IDESC
*idesc
,
3192 int unit_num
, int referenced
)
3194 return idesc
->timing
->units
[unit_num
].done
;
3197 /* The tomcat machine is models a prototype fr500 machine which had a few
3198 bugs and restrictions to work around. */
3200 frvbf_model_tomcat_u_exec (SIM_CPU
*cpu
, const IDESC
*idesc
,
3201 int unit_num
, int referenced
)
3203 return idesc
->timing
->units
[unit_num
].done
;
3206 #endif /* WITH_PROFILE_MODEL_P */