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2000-06-13 Kazu Hirata <kazu@hxi.com>
[thirdparty/binutils-gdb.git] / sim / h8300 / compile.c
1 /*
2 * Simulator for the Hitachi H8/300 architecture.
3 *
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
5 *
6 * This file is part of H8/300 sim
7 *
8 *
9 * THIS SOFTWARE IS NOT COPYRIGHTED
10 *
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
14 *
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
18 */
19
20 #include "config.h"
21
22 #include <stdio.h>
23 #include <signal.h>
24 #ifdef HAVE_TIME_H
25 #include <time.h>
26 #endif
27 #ifdef HAVE_STDLIB_H
28 #include <stdlib.h>
29 #endif
30 #ifdef HAVE_SYS_PARAM_H
31 #include <sys/param.h>
32 #endif
33 #include "wait.h"
34 #include "ansidecl.h"
35 #include "bfd.h"
36 #include "callback.h"
37 #include "remote-sim.h"
38
39 #ifndef SIGTRAP
40 # define SIGTRAP 5
41 #endif
42
43 int debug;
44
45 host_callback *sim_callback;
46
47 static SIM_OPEN_KIND sim_kind;
48 static char *myname;
49
50 /* FIXME: Needs to live in header file.
51 This header should also include the things in remote-sim.h.
52 One could move this to remote-sim.h but this function isn't needed
53 by gdb. */
54 void sim_set_simcache_size PARAMS ((int));
55
56 #define X(op, size) op*4+size
57
58 #define SP (h8300hmode ? SL:SW)
59 #define SB 0
60 #define SW 1
61 #define SL 2
62 #define OP_REG 1
63 #define OP_DEC 2
64 #define OP_DISP 3
65 #define OP_INC 4
66 #define OP_PCREL 5
67 #define OP_MEM 6
68 #define OP_CCR 7
69 #define OP_IMM 8
70 #define OP_ABS 10
71 #define h8_opcodes ops
72 #define DEFINE_TABLE
73 #include "opcode/h8300.h"
74
75 #include "inst.h"
76
77 /* The rate at which to call the host's poll_quit callback. */
78
79 #define POLL_QUIT_INTERVAL 0x80000
80
81 #define LOW_BYTE(x) ((x) & 0xff)
82 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
83 #define P(X,Y) ((X<<8) | Y)
84
85 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
86
87 #define GETSR() \
88 c = (cpu.ccr >> 0) & 1;\
89 v = (cpu.ccr >> 1) & 1;\
90 nz = !((cpu.ccr >> 2) & 1);\
91 n = (cpu.ccr >> 3) & 1;
92
93 #ifdef __CHAR_IS_SIGNED__
94 #define SEXTCHAR(x) ((char)(x))
95 #endif
96
97 #ifndef SEXTCHAR
98 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
99 #endif
100
101 #define UEXTCHAR(x) ((x) & 0xff)
102 #define UEXTSHORT(x) ((x) & 0xffff)
103 #define SEXTSHORT(x) ((short)(x))
104
105 static cpu_state_type cpu;
106
107 int h8300hmode = 0;
108 int h8300smode = 0;
109
110 static int memory_size;
111
112 static int
113 get_now ()
114 {
115 #ifndef WIN32
116 return time (0);
117 #endif
118 return 0;
119 }
120
121 static int
122 now_persec ()
123 {
124 return 1;
125 }
126
127 static int
128 bitfrom (x)
129 {
130 switch (x & SIZE)
131 {
132 case L_8:
133 return SB;
134 case L_16:
135 return SW;
136 case L_32:
137 return SL;
138 case L_P:
139 return h8300hmode ? SL : SW;
140 }
141 }
142
143 static unsigned int
144 lvalue (x, rn)
145 {
146 switch (x / 4)
147 {
148 case OP_DISP:
149 if (rn == 8)
150 {
151 return X (OP_IMM, SP);
152 }
153 return X (OP_REG, SP);
154
155 case OP_MEM:
156 return X (OP_MEM, SP);
157
158 default:
159 abort ();
160 }
161 }
162
163 static unsigned int
164 decode (addr, data, dst)
165 int addr;
166 unsigned char *data;
167 decoded_inst *dst;
168
169 {
170 int rs = 0;
171 int rd = 0;
172 int rdisp = 0;
173 int abs = 0;
174 int bit = 0;
175 int plen = 0;
176 struct h8_opcode *q = h8_opcodes;
177 int size = 0;
178
179 dst->dst.type = -1;
180 dst->src.type = -1;
181
182 /* Find the exact opcode/arg combo. */
183 while (q->name)
184 {
185 op_type *nib;
186 unsigned int len = 0;
187
188 nib = q->data.nib;
189
190 while (1)
191 {
192 op_type looking_for = *nib;
193 int thisnib = data[len >> 1];
194
195 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
196
197 if (looking_for < 16 && looking_for >= 0)
198 {
199 if (looking_for != thisnib)
200 goto fail;
201 }
202 else
203 {
204 if ((int) looking_for & (int) B31)
205 {
206 if (!(((int) thisnib & 0x8) != 0))
207 goto fail;
208
209 looking_for = (op_type) ((int) looking_for & ~(int) B31);
210 thisnib &= 0x7;
211 }
212
213 if ((int) looking_for & (int) B30)
214 {
215 if (!(((int) thisnib & 0x8) == 0))
216 goto fail;
217
218 looking_for = (op_type) ((int) looking_for & ~(int) B30);
219 }
220
221 if (looking_for & DBIT)
222 {
223 if ((looking_for & 5) != (thisnib & 5))
224 goto fail;
225
226 abs = (thisnib & 0x8) ? 2 : 1;
227 }
228 else if (looking_for & (REG | IND | INC | DEC))
229 {
230 if (looking_for & REG)
231 {
232 /* Can work out size from the register. */
233 size = bitfrom (looking_for);
234 }
235 if (looking_for & SRC)
236 rs = thisnib;
237 else
238 rd = thisnib;
239 }
240 else if (looking_for & L_16)
241 {
242 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
243 plen = 16;
244 if (looking_for & (PCREL | DISP))
245 {
246 abs = (short) (abs);
247 }
248 }
249 else if (looking_for & ABSJMP)
250 {
251 abs = (data[1] << 16) | (data[2] << 8) | (data[3]);
252 }
253 else if (looking_for & MEMIND)
254 {
255 abs = data[1];
256 }
257 else if (looking_for & L_32)
258 {
259 int i = len >> 1;
260
261 abs = (data[i] << 24)
262 | (data[i + 1] << 16)
263 | (data[i + 2] << 8)
264 | (data[i + 3]);
265
266 plen = 32;
267 }
268 else if (looking_for & L_24)
269 {
270 int i = len >> 1;
271
272 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
273 plen = 24;
274 }
275 else if (looking_for & IGNORE)
276 {
277 ;
278 }
279 else if (looking_for & DISPREG)
280 {
281 rdisp = thisnib & 0x7;
282 }
283 else if (looking_for & KBIT)
284 {
285 switch (thisnib)
286 {
287 case 9:
288 abs = 4;
289 break;
290 case 8:
291 abs = 2;
292 break;
293 case 0:
294 abs = 1;
295 break;
296 }
297 }
298 else if (looking_for & L_8)
299 {
300 plen = 8;
301
302 if (looking_for & PCREL)
303 {
304 abs = SEXTCHAR (data[len >> 1]);
305 }
306 else if (looking_for & ABS8MEM)
307 {
308 plen = 8;
309 abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff;
310 abs |= data[len >> 1] & 0xff;
311 }
312 else
313 {
314 abs = data[len >> 1] & 0xff;
315 }
316 }
317 else if (looking_for & L_3)
318 {
319 plen = 3;
320
321 bit = thisnib;
322 }
323 else if (looking_for == E)
324 {
325 dst->op = q;
326
327 /* Fill in the args. */
328 {
329 op_type *args = q->args.nib;
330 int hadone = 0;
331
332 while (*args != E)
333 {
334 int x = *args;
335 int rn = (x & DST) ? rd : rs;
336 ea_type *p;
337
338 if (x & DST)
339 p = &(dst->dst);
340 else
341 p = &(dst->src);
342
343 if (x & L_3)
344 {
345 p->type = X (OP_IMM, size);
346 p->literal = bit;
347 }
348 else if (x & (IMM | KBIT | DBIT))
349 {
350 p->type = X (OP_IMM, size);
351 p->literal = abs;
352 }
353 else if (x & REG)
354 {
355 /* Reset the size, some
356 ops (like mul) have two sizes */
357
358 size = bitfrom (x);
359 p->type = X (OP_REG, size);
360 p->reg = rn;
361 }
362 else if (x & INC)
363 {
364 p->type = X (OP_INC, size);
365 p->reg = rn & 0x7;
366 }
367 else if (x & DEC)
368 {
369 p->type = X (OP_DEC, size);
370 p->reg = rn & 0x7;
371 }
372 else if (x & IND)
373 {
374 p->type = X (OP_DISP, size);
375 p->reg = rn & 0x7;
376 p->literal = 0;
377 }
378 else if (x & (ABS | ABSJMP | ABS8MEM))
379 {
380 p->type = X (OP_DISP, size);
381 p->literal = abs;
382 p->reg = 8;
383 }
384 else if (x & MEMIND)
385 {
386 p->type = X (OP_MEM, size);
387 p->literal = abs;
388 }
389 else if (x & PCREL)
390 {
391 p->type = X (OP_PCREL, size);
392 p->literal = abs + addr + 2;
393 if (x & L_16)
394 p->literal += 2;
395 }
396 else if (x & ABSJMP)
397 {
398 p->type = X (OP_IMM, SP);
399 p->literal = abs;
400 }
401 else if (x & DISP)
402 {
403 p->type = X (OP_DISP, size);
404 p->literal = abs;
405 p->reg = rdisp & 0x7;
406 }
407 else if (x & CCR)
408 {
409 p->type = OP_CCR;
410 }
411 else
412 printf ("Hmmmm %x", x);
413
414 args++;
415 }
416 }
417
418 /* But a jmp or a jsr gets automagically lvalued,
419 since we branch to their address not their
420 contents. */
421 if (q->how == O (O_JSR, SB)
422 || q->how == O (O_JMP, SB))
423 {
424 dst->src.type = lvalue (dst->src.type, dst->src.reg);
425 }
426
427 if (dst->dst.type == -1)
428 dst->dst = dst->src;
429
430 dst->opcode = q->how;
431 dst->cycles = q->time;
432
433 /* And a jsr to 0xc4 is turned into a magic trap. */
434
435 if (dst->opcode == O (O_JSR, SB))
436 {
437 if (dst->src.literal == 0xc4)
438 {
439 dst->opcode = O (O_SYSCALL, SB);
440 }
441 }
442
443 dst->next_pc = addr + len / 2;
444 return;
445 }
446 else
447 printf ("Dont understand %x \n", looking_for);
448 }
449
450 len++;
451 nib++;
452 }
453
454 fail:
455 q++;
456 }
457
458 /* Fell off the end. */
459 dst->opcode = O (O_ILL, SB);
460 }
461
462 static void
463 compile (pc)
464 {
465 int idx;
466
467 /* find the next cache entry to use */
468
469 idx = cpu.cache_top + 1;
470 cpu.compiles++;
471 if (idx >= cpu.csize)
472 {
473 idx = 1;
474 }
475 cpu.cache_top = idx;
476
477 /* Throw away its old meaning */
478 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
479
480 /* set to new address */
481 cpu.cache[idx].oldpc = pc;
482
483 /* fill in instruction info */
484 decode (pc, cpu.memory + pc, cpu.cache + idx);
485
486 /* point to new cache entry */
487 cpu.cache_idx[pc] = idx;
488 }
489
490
491 static unsigned char *breg[18];
492 static unsigned short *wreg[18];
493 static unsigned int *lreg[18];
494
495 #define GET_B_REG(x) *(breg[x])
496 #define SET_B_REG(x,y) (*(breg[x])) = (y)
497 #define GET_W_REG(x) *(wreg[x])
498 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
499
500 #define GET_L_REG(x) *(lreg[x])
501 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
502
503 #define GET_MEMORY_L(x) \
504 (x < memory_size \
505 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
506 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
507 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
508 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
509
510 #define GET_MEMORY_W(x) \
511 (x < memory_size \
512 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
513 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
514
515
516 #define GET_MEMORY_B(x) \
517 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
518
519 #define SET_MEMORY_L(x,y) \
520 { register unsigned char *_p; register int __y = y; \
521 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
522 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
523 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
524
525 #define SET_MEMORY_W(x,y) \
526 { register unsigned char *_p; register int __y = y; \
527 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
528 _p[0] = (__y)>>8; _p[1] =(__y);}
529
530 #define SET_MEMORY_B(x,y) \
531 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
532
533 int
534 fetch (arg, n)
535 ea_type *arg;
536 {
537 int rn = arg->reg;
538 int abs = arg->literal;
539 int r;
540 int t;
541
542 switch (arg->type)
543 {
544 case X (OP_REG, SB):
545 return GET_B_REG (rn);
546 case X (OP_REG, SW):
547 return GET_W_REG (rn);
548 case X (OP_REG, SL):
549 return GET_L_REG (rn);
550 case X (OP_IMM, SB):
551 case X (OP_IMM, SW):
552 case X (OP_IMM, SL):
553 return abs;
554 case X (OP_DEC, SB):
555 abort ();
556
557 case X (OP_INC, SB):
558 t = GET_L_REG (rn);
559 t &= cpu.mask;
560 r = GET_MEMORY_B (t);
561 t++;
562 t = t & cpu.mask;
563 SET_L_REG (rn, t);
564 return r;
565 break;
566 case X (OP_INC, SW):
567 t = GET_L_REG (rn);
568 t &= cpu.mask;
569 r = GET_MEMORY_W (t);
570 t += 2;
571 t = t & cpu.mask;
572 SET_L_REG (rn, t);
573 return r;
574 case X (OP_INC, SL):
575 t = GET_L_REG (rn);
576 t &= cpu.mask;
577 r = GET_MEMORY_L (t);
578
579 t += 4;
580 t = t & cpu.mask;
581 SET_L_REG (rn, t);
582 return r;
583
584 case X (OP_DISP, SB):
585 t = GET_L_REG (rn) + abs;
586 t &= cpu.mask;
587 return GET_MEMORY_B (t);
588
589 case X (OP_DISP, SW):
590 t = GET_L_REG (rn) + abs;
591 t &= cpu.mask;
592 return GET_MEMORY_W (t);
593
594 case X (OP_DISP, SL):
595 t = GET_L_REG (rn) + abs;
596 t &= cpu.mask;
597 return GET_MEMORY_L (t);
598
599 case X (OP_MEM, SL):
600 t = GET_MEMORY_L (abs);
601 t &= cpu.mask;
602 return t;
603
604 case X (OP_MEM, SW):
605 t = GET_MEMORY_W (abs);
606 t &= cpu.mask;
607 return t;
608
609 default:
610 abort ();
611
612 }
613 }
614
615
616 static
617 void
618 store (arg, n)
619 ea_type *arg;
620 int n;
621 {
622 int rn = arg->reg;
623 int abs = arg->literal;
624 int t;
625
626 switch (arg->type)
627 {
628 case X (OP_REG, SB):
629 SET_B_REG (rn, n);
630 break;
631 case X (OP_REG, SW):
632 SET_W_REG (rn, n);
633 break;
634 case X (OP_REG, SL):
635 SET_L_REG (rn, n);
636 break;
637
638 case X (OP_DEC, SB):
639 t = GET_L_REG (rn) - 1;
640 t &= cpu.mask;
641 SET_L_REG (rn, t);
642 SET_MEMORY_B (t, n);
643
644 break;
645 case X (OP_DEC, SW):
646 t = (GET_L_REG (rn) - 2) & cpu.mask;
647 SET_L_REG (rn, t);
648 SET_MEMORY_W (t, n);
649 break;
650
651 case X (OP_DEC, SL):
652 t = (GET_L_REG (rn) - 4) & cpu.mask;
653 SET_L_REG (rn, t);
654 SET_MEMORY_L (t, n);
655 break;
656
657 case X (OP_DISP, SB):
658 t = GET_L_REG (rn) + abs;
659 t &= cpu.mask;
660 SET_MEMORY_B (t, n);
661 break;
662
663 case X (OP_DISP, SW):
664 t = GET_L_REG (rn) + abs;
665 t &= cpu.mask;
666 SET_MEMORY_W (t, n);
667 break;
668
669 case X (OP_DISP, SL):
670 t = GET_L_REG (rn) + abs;
671 t &= cpu.mask;
672 SET_MEMORY_L (t, n);
673 break;
674 default:
675 abort ();
676 }
677 }
678
679
680 static union
681 {
682 short int i;
683 struct
684 {
685 char low;
686 char high;
687 }
688 u;
689 }
690
691 littleendian;
692
693 static
694 void
695 init_pointers ()
696 {
697 static int init;
698
699 if (!init)
700 {
701 int i;
702
703 init = 1;
704 littleendian.i = 1;
705
706 if (h8300hmode)
707 memory_size = H8300H_MSIZE;
708 else
709 memory_size = H8300_MSIZE;
710 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
711 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
712 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
713
714 /* `msize' must be a power of two */
715 if ((memory_size & (memory_size - 1)) != 0)
716 abort ();
717 cpu.mask = memory_size - 1;
718
719 for (i = 0; i < 9; i++)
720 {
721 cpu.regs[i] = 0;
722 }
723
724 for (i = 0; i < 8; i++)
725 {
726 unsigned char *p = (unsigned char *) (cpu.regs + i);
727 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
728 unsigned short *q = (unsigned short *) (cpu.regs + i);
729 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
730 cpu.regs[i] = 0x00112233;
731 while (p < e)
732 {
733 if (*p == 0x22)
734 {
735 breg[i] = p;
736 }
737 if (*p == 0x33)
738 {
739 breg[i + 8] = p;
740 }
741 p++;
742 }
743 while (q < u)
744 {
745 if (*q == 0x2233)
746 {
747 wreg[i] = q;
748 }
749 if (*q == 0x0011)
750 {
751 wreg[i + 8] = q;
752 }
753 q++;
754 }
755 cpu.regs[i] = 0;
756 lreg[i] = &cpu.regs[i];
757 }
758
759 lreg[8] = &cpu.regs[8];
760
761 /* initialize the seg registers */
762 if (!cpu.cache)
763 sim_set_simcache_size (CSIZE);
764 }
765 }
766
767 static void
768 control_c (sig, code, scp, addr)
769 int sig;
770 int code;
771 char *scp;
772 char *addr;
773 {
774 cpu.state = SIM_STATE_STOPPED;
775 cpu.exception = SIGINT;
776 }
777
778 #define C (c != 0)
779 #define Z (nz == 0)
780 #define V (v != 0)
781 #define N (n != 0)
782
783 static int
784 mop (code, bsize, sign)
785 decoded_inst *code;
786 int bsize;
787 int sign;
788 {
789 int multiplier;
790 int multiplicand;
791 int result;
792 int n, nz;
793
794 if (sign)
795 {
796 multiplicand =
797 bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
798 SEXTSHORT (GET_W_REG (code->dst.reg));
799 multiplier =
800 bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
801 SEXTSHORT (GET_W_REG (code->src.reg));
802 }
803 else
804 {
805 multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
806 UEXTSHORT (GET_W_REG (code->dst.reg));
807 multiplier =
808 bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
809 UEXTSHORT (GET_W_REG (code->src.reg));
810
811 }
812 result = multiplier * multiplicand;
813
814 if (sign)
815 {
816 n = result & (bsize ? 0x8000 : 0x80000000);
817 nz = result & (bsize ? 0xffff : 0xffffffff);
818 }
819 if (bsize)
820 {
821 SET_W_REG (code->dst.reg, result);
822 }
823 else
824 {
825 SET_L_REG (code->dst.reg, result);
826 }
827 /* return ((n==1) << 1) | (nz==1); */
828
829 }
830
831 #define ONOT(name, how) \
832 case O(name, SB): \
833 { \
834 int t; \
835 int hm = 0x80; \
836 rd = GET_B_REG (code->src.reg); \
837 how; \
838 goto shift8; \
839 } \
840 case O(name, SW): \
841 { \
842 int t; \
843 int hm = 0x8000; \
844 rd = GET_W_REG (code->src.reg); \
845 how; \
846 goto shift16; \
847 } \
848 case O(name, SL): \
849 { \
850 int t; \
851 int hm = 0x80000000; \
852 rd = GET_L_REG (code->src.reg); \
853 how; \
854 goto shift32; \
855 }
856
857 #define OSHIFTS(name, how1, how2) \
858 case O(name, SB): \
859 { \
860 int t; \
861 int hm = 0x80; \
862 rd = GET_B_REG (code->src.reg); \
863 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
864 { \
865 how1; \
866 } \
867 else \
868 { \
869 how2; \
870 } \
871 goto shift8; \
872 } \
873 case O(name, SW): \
874 { \
875 int t; \
876 int hm = 0x8000; \
877 rd = GET_W_REG (code->src.reg); \
878 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
879 { \
880 how1; \
881 } \
882 else \
883 { \
884 how2; \
885 } \
886 goto shift16; \
887 } \
888 case O(name, SL): \
889 { \
890 int t; \
891 int hm = 0x80000000; \
892 rd = GET_L_REG (code->src.reg); \
893 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
894 { \
895 how1; \
896 } \
897 else \
898 { \
899 how2; \
900 } \
901 goto shift32; \
902 }
903
904 #define OBITOP(name,f, s, op) \
905 case O(name, SB): \
906 { \
907 int m; \
908 int b; \
909 if (f) ea = fetch (&code->dst); \
910 m=1<< fetch(&code->src); \
911 op; \
912 if(s) store (&code->dst,ea); goto next; \
913 }
914
915 int
916 sim_stop (sd)
917 SIM_DESC sd;
918 {
919 cpu.state = SIM_STATE_STOPPED;
920 cpu.exception = SIGINT;
921 return 1;
922 }
923
924 void
925 sim_resume (sd, step, siggnal)
926 SIM_DESC sd;
927 {
928 static int init1;
929 int cycles = 0;
930 int insts = 0;
931 int tick_start = get_now ();
932 void (*prev) ();
933 int poll_count = 0;
934 int res;
935 int tmp;
936 int rd;
937 int ea;
938 int bit;
939 int pc;
940 int c, nz, v, n;
941 int oldmask;
942 init_pointers ();
943
944 prev = signal (SIGINT, control_c);
945
946 if (step)
947 {
948 cpu.state = SIM_STATE_STOPPED;
949 cpu.exception = SIGTRAP;
950 }
951 else
952 {
953 cpu.state = SIM_STATE_RUNNING;
954 cpu.exception = 0;
955 }
956
957 pc = cpu.pc;
958
959 /* The PC should never be odd. */
960 if (pc & 0x1)
961 abort ();
962
963 GETSR ();
964 oldmask = cpu.mask;
965 if (!h8300hmode)
966 cpu.mask = 0xffff;
967 do
968 {
969 int cidx;
970 decoded_inst *code;
971
972 top:
973 cidx = cpu.cache_idx[pc];
974 code = cpu.cache + cidx;
975
976
977 #define ALUOP(STORE, NAME, HOW) \
978 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
979 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
980 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
981
982
983 #define LOGOP(NAME, HOW) \
984 case O(NAME,SB): HOW; goto log8;\
985 case O(NAME, SW): HOW; goto log16;\
986 case O(NAME,SL): HOW; goto log32;
987
988
989
990 #if ADEBUG
991 if (debug)
992 {
993 printf ("%x %d %s\n", pc, code->opcode,
994 code->op ? code->op->name : "**");
995 }
996 cpu.stats[code->opcode]++;
997
998 #endif
999
1000 cycles += code->cycles;
1001 insts++;
1002 switch (code->opcode)
1003 {
1004 case 0:
1005 /*
1006 * This opcode is a fake for when we get to an
1007 * instruction which hasnt been compiled
1008 */
1009 compile (pc);
1010 goto top;
1011 break;
1012
1013
1014 case O (O_SUBX, SB):
1015 rd = fetch (&code->dst);
1016 ea = fetch (&code->src);
1017 ea = -(ea + C);
1018 res = rd + ea;
1019 goto alu8;
1020
1021 case O (O_ADDX, SB):
1022 rd = fetch (&code->dst);
1023 ea = fetch (&code->src);
1024 ea = C + ea;
1025 res = rd + ea;
1026 goto alu8;
1027
1028 #define EA ea = fetch(&code->src);
1029 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
1030
1031 ALUOP (1, O_SUB, RD_EA;
1032 ea = -ea;
1033 res = rd + ea);
1034 ALUOP (1, O_NEG, EA;
1035 ea = -ea;
1036 rd = 0;
1037 res = rd + ea);
1038
1039 case O (O_ADD, SB):
1040 rd = GET_B_REG (code->dst.reg);
1041 ea = fetch (&code->src);
1042 res = rd + ea;
1043 goto alu8;
1044 case O (O_ADD, SW):
1045 rd = GET_W_REG (code->dst.reg);
1046 ea = fetch (&code->src);
1047 res = rd + ea;
1048 goto alu16;
1049 case O (O_ADD, SL):
1050 rd = GET_L_REG (code->dst.reg);
1051 ea = fetch (&code->src);
1052 res = rd + ea;
1053 goto alu32;
1054
1055
1056 LOGOP (O_AND, RD_EA;
1057 res = rd & ea);
1058
1059 LOGOP (O_OR, RD_EA;
1060 res = rd | ea);
1061
1062 LOGOP (O_XOR, RD_EA;
1063 res = rd ^ ea);
1064
1065
1066 case O (O_MOV_TO_MEM, SB):
1067 res = GET_B_REG (code->src.reg);
1068 goto log8;
1069 case O (O_MOV_TO_MEM, SW):
1070 res = GET_W_REG (code->src.reg);
1071 goto log16;
1072 case O (O_MOV_TO_MEM, SL):
1073 res = GET_L_REG (code->src.reg);
1074 goto log32;
1075
1076
1077 case O (O_MOV_TO_REG, SB):
1078 res = fetch (&code->src);
1079 SET_B_REG (code->dst.reg, res);
1080 goto just_flags_log8;
1081 case O (O_MOV_TO_REG, SW):
1082 res = fetch (&code->src);
1083 SET_W_REG (code->dst.reg, res);
1084 goto just_flags_log16;
1085 case O (O_MOV_TO_REG, SL):
1086 res = fetch (&code->src);
1087 SET_L_REG (code->dst.reg, res);
1088 goto just_flags_log32;
1089
1090
1091 case O (O_ADDS, SL):
1092 SET_L_REG (code->dst.reg,
1093 GET_L_REG (code->dst.reg)
1094 + code->src.literal);
1095
1096 goto next;
1097
1098 case O (O_SUBS, SL):
1099 SET_L_REG (code->dst.reg,
1100 GET_L_REG (code->dst.reg)
1101 - code->src.literal);
1102 goto next;
1103
1104 case O (O_CMP, SB):
1105 rd = fetch (&code->dst);
1106 ea = fetch (&code->src);
1107 ea = -ea;
1108 res = rd + ea;
1109 goto just_flags_alu8;
1110
1111 case O (O_CMP, SW):
1112 rd = fetch (&code->dst);
1113 ea = fetch (&code->src);
1114 ea = -ea;
1115 res = rd + ea;
1116 goto just_flags_alu16;
1117
1118 case O (O_CMP, SL):
1119 rd = fetch (&code->dst);
1120 ea = fetch (&code->src);
1121 ea = -ea;
1122 res = rd + ea;
1123 goto just_flags_alu32;
1124
1125
1126 case O (O_DEC, SB):
1127 rd = GET_B_REG (code->src.reg);
1128 ea = -1;
1129 res = rd + ea;
1130 SET_B_REG (code->src.reg, res);
1131 goto just_flags_inc8;
1132
1133 case O (O_DEC, SW):
1134 rd = GET_W_REG (code->dst.reg);
1135 ea = -code->src.literal;
1136 res = rd + ea;
1137 SET_W_REG (code->dst.reg, res);
1138 goto just_flags_inc16;
1139
1140 case O (O_DEC, SL):
1141 rd = GET_L_REG (code->dst.reg);
1142 ea = -code->src.literal;
1143 res = rd + ea;
1144 SET_L_REG (code->dst.reg, res);
1145 goto just_flags_inc32;
1146
1147
1148 case O (O_INC, SB):
1149 rd = GET_B_REG (code->src.reg);
1150 ea = 1;
1151 res = rd + ea;
1152 SET_B_REG (code->src.reg, res);
1153 goto just_flags_inc8;
1154
1155 case O (O_INC, SW):
1156 rd = GET_W_REG (code->dst.reg);
1157 ea = code->src.literal;
1158 res = rd + ea;
1159 SET_W_REG (code->dst.reg, res);
1160 goto just_flags_inc16;
1161
1162 case O (O_INC, SL):
1163 rd = GET_L_REG (code->dst.reg);
1164 ea = code->src.literal;
1165 res = rd + ea;
1166 SET_L_REG (code->dst.reg, res);
1167 goto just_flags_inc32;
1168
1169
1170 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1171
1172 case O (O_ANDC, SB):
1173 GET_CCR (rd);
1174 ea = code->src.literal;
1175 res = rd & ea;
1176 goto setc;
1177
1178 case O (O_ORC, SB):
1179 GET_CCR (rd);
1180 ea = code->src.literal;
1181 res = rd | ea;
1182 goto setc;
1183
1184 case O (O_XORC, SB):
1185 GET_CCR (rd);
1186 ea = code->src.literal;
1187 res = rd ^ ea;
1188 goto setc;
1189
1190
1191 case O (O_BRA, SB):
1192 if (1)
1193 goto condtrue;
1194 goto next;
1195
1196 case O (O_BRN, SB):
1197 if (0)
1198 goto condtrue;
1199 goto next;
1200
1201 case O (O_BHI, SB):
1202 if ((C || Z) == 0)
1203 goto condtrue;
1204 goto next;
1205
1206
1207 case O (O_BLS, SB):
1208 if ((C || Z))
1209 goto condtrue;
1210 goto next;
1211
1212 case O (O_BCS, SB):
1213 if ((C == 1))
1214 goto condtrue;
1215 goto next;
1216
1217 case O (O_BCC, SB):
1218 if ((C == 0))
1219 goto condtrue;
1220 goto next;
1221
1222 case O (O_BEQ, SB):
1223 if (Z)
1224 goto condtrue;
1225 goto next;
1226 case O (O_BGT, SB):
1227 if (((Z || (N ^ V)) == 0))
1228 goto condtrue;
1229 goto next;
1230
1231
1232 case O (O_BLE, SB):
1233 if (((Z || (N ^ V)) == 1))
1234 goto condtrue;
1235 goto next;
1236
1237 case O (O_BGE, SB):
1238 if ((N ^ V) == 0)
1239 goto condtrue;
1240 goto next;
1241 case O (O_BLT, SB):
1242 if ((N ^ V))
1243 goto condtrue;
1244 goto next;
1245 case O (O_BMI, SB):
1246 if ((N))
1247 goto condtrue;
1248 goto next;
1249 case O (O_BNE, SB):
1250 if ((Z == 0))
1251 goto condtrue;
1252 goto next;
1253
1254 case O (O_BPL, SB):
1255 if (N == 0)
1256 goto condtrue;
1257 goto next;
1258 case O (O_BVC, SB):
1259 if ((V == 0))
1260 goto condtrue;
1261 goto next;
1262 case O (O_BVS, SB):
1263 if ((V == 1))
1264 goto condtrue;
1265 goto next;
1266
1267 case O (O_SYSCALL, SB):
1268 {
1269 char c = cpu.regs[2];
1270 sim_callback->write_stdout (sim_callback, &c, 1);
1271 }
1272 goto next;
1273
1274 ONOT (O_NOT, rd = ~rd; v = 0;);
1275 OSHIFTS (O_SHLL,
1276 c = rd & hm; v = 0; rd <<= 1,
1277 c = rd & (hm >> 1); v = 0; rd <<= 2);
1278 OSHIFTS (O_SHLR,
1279 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1,
1280 c = rd & 2; v = 0; rd = (unsigned int) rd >> 2);
1281 OSHIFTS (O_SHAL,
1282 c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1,
1283 c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2);
1284 OSHIFTS (O_SHAR,
1285 t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t,
1286 t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 );
1287 OSHIFTS (O_ROTL,
1288 c = rd & hm; v = 0; rd <<= 1; rd |= C,
1289 c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C);
1290 OSHIFTS (O_ROTR,
1291 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm,
1292 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm);
1293 OSHIFTS (O_ROTXL,
1294 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0,
1295 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t);
1296 OSHIFTS (O_ROTXR,
1297 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0,
1298 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t);
1299
1300 case O (O_JMP, SB):
1301 {
1302 pc = fetch (&code->src);
1303 goto end;
1304
1305 }
1306
1307 case O (O_JSR, SB):
1308 {
1309 int tmp;
1310 pc = fetch (&code->src);
1311 call:
1312 tmp = cpu.regs[7];
1313
1314 if (h8300hmode)
1315 {
1316 tmp -= 4;
1317 SET_MEMORY_L (tmp, code->next_pc);
1318 }
1319 else
1320 {
1321 tmp -= 2;
1322 SET_MEMORY_W (tmp, code->next_pc);
1323 }
1324 cpu.regs[7] = tmp;
1325
1326 goto end;
1327 }
1328 case O (O_BSR, SB):
1329 pc = code->src.literal;
1330 goto call;
1331
1332 case O (O_RTS, SN):
1333 {
1334 int tmp;
1335
1336 tmp = cpu.regs[7];
1337
1338 if (h8300hmode)
1339 {
1340 pc = GET_MEMORY_L (tmp);
1341 tmp += 4;
1342 }
1343 else
1344 {
1345 pc = GET_MEMORY_W (tmp);
1346 tmp += 2;
1347 }
1348
1349 cpu.regs[7] = tmp;
1350 goto end;
1351 }
1352
1353 case O (O_ILL, SB):
1354 cpu.state = SIM_STATE_STOPPED;
1355 cpu.exception = SIGILL;
1356 goto end;
1357 case O (O_SLEEP, SN):
1358 /* The format of r0 is defined by devo/include/wait.h. */
1359 #if 0 /* FIXME: Ugh. A breakpoint is the sleep insn. */
1360 if (WIFEXITED (cpu.regs[0]))
1361 {
1362 cpu.state = SIM_STATE_EXITED;
1363 cpu.exception = WEXITSTATUS (cpu.regs[0]);
1364 }
1365 else if (WIFSTOPPED (cpu.regs[0]))
1366 {
1367 cpu.state = SIM_STATE_STOPPED;
1368 cpu.exception = WSTOPSIG (cpu.regs[0]);
1369 }
1370 else
1371 {
1372 cpu.state = SIM_STATE_SIGNALLED;
1373 cpu.exception = WTERMSIG (cpu.regs[0]);
1374 }
1375 #else
1376 /* FIXME: Doesn't this break for breakpoints when r0
1377 contains just the right (er, wrong) value? */
1378 cpu.state = SIM_STATE_STOPPED;
1379 if (! WIFEXITED (cpu.regs[0]) && WIFSIGNALED (cpu.regs[0]))
1380 cpu.exception = SIGILL;
1381 else
1382 cpu.exception = SIGTRAP;
1383 #endif
1384 goto end;
1385 case O (O_BPT, SN):
1386 cpu.state = SIM_STATE_STOPPED;
1387 cpu.exception = SIGTRAP;
1388 goto end;
1389
1390 OBITOP (O_BNOT, 1, 1, ea ^= m);
1391 OBITOP (O_BTST, 1, 0, nz = ea & m);
1392 OBITOP (O_BCLR, 1, 1, ea &= ~m);
1393 OBITOP (O_BSET, 1, 1, ea |= m);
1394 OBITOP (O_BLD, 1, 0, c = ea & m);
1395 OBITOP (O_BILD, 1, 0, c = !(ea & m));
1396 OBITOP (O_BST, 1, 1, ea &= ~m;
1397 if (C) ea |= m);
1398 OBITOP (O_BIST, 1, 1, ea &= ~m;
1399 if (!C) ea |= m);
1400 OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1401 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1402 OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1403 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1404 OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1405 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1406
1407
1408 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1409
1410 case O (O_MULS, SB):
1411 MOP (1, 1);
1412 break;
1413 case O (O_MULS, SW):
1414 MOP (0, 1);
1415 break;
1416 case O (O_MULU, SB):
1417 MOP (1, 0);
1418 break;
1419 case O (O_MULU, SW):
1420 MOP (0, 0);
1421 break;
1422
1423
1424 case O (O_DIVU, SB):
1425 {
1426 rd = GET_W_REG (code->dst.reg);
1427 ea = GET_B_REG (code->src.reg);
1428 if (ea)
1429 {
1430 tmp = (unsigned)rd % ea;
1431 rd = (unsigned)rd / ea;
1432 }
1433 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1434 n = ea & 0x80;
1435 nz = ea & 0xff;
1436
1437 goto next;
1438 }
1439 case O (O_DIVU, SW):
1440 {
1441 rd = GET_L_REG (code->dst.reg);
1442 ea = GET_W_REG (code->src.reg);
1443 n = ea & 0x8000;
1444 nz = ea & 0xffff;
1445 if (ea)
1446 {
1447 tmp = (unsigned)rd % ea;
1448 rd = (unsigned)rd / ea;
1449 }
1450 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1451 goto next;
1452 }
1453
1454 case O (O_DIVS, SB):
1455 {
1456
1457 rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1458 ea = SEXTCHAR (GET_B_REG (code->src.reg));
1459 if (ea)
1460 {
1461 tmp = (int) rd % (int) ea;
1462 rd = (int) rd / (int) ea;
1463 n = rd & 0x8000;
1464 nz = 1;
1465 }
1466 else
1467 nz = 0;
1468 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1469 goto next;
1470 }
1471 case O (O_DIVS, SW):
1472 {
1473 rd = GET_L_REG (code->dst.reg);
1474 ea = SEXTSHORT (GET_W_REG (code->src.reg));
1475 if (ea)
1476 {
1477 tmp = (int) rd % (int) ea;
1478 rd = (int) rd / (int) ea;
1479 n = rd & 0x80000000;
1480 nz = 1;
1481 }
1482 else
1483 nz = 0;
1484 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1485 goto next;
1486 }
1487 case O (O_EXTS, SW):
1488 rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
1489 ea = rd & 0x80 ? -256 : 0;
1490 res = rd + ea;
1491 goto log16;
1492 case O (O_EXTS, SL):
1493 rd = GET_W_REG (code->src.reg) & 0xffff;
1494 ea = rd & 0x8000 ? -65536 : 0;
1495 res = rd + ea;
1496 goto log32;
1497 case O (O_EXTU, SW):
1498 rd = GET_B_REG (code->src.reg + 8) & 0xff;
1499 ea = 0;
1500 res = rd + ea;
1501 goto log16;
1502 case O (O_EXTU, SL):
1503 rd = GET_W_REG (code->src.reg) & 0xffff;
1504 ea = 0;
1505 res = rd + ea;
1506 goto log32;
1507
1508 case O (O_NOP, SN):
1509 goto next;
1510
1511 case O (O_STM, SL):
1512 {
1513 int nregs, firstreg, i;
1514
1515 nregs = GET_MEMORY_B (pc + 1);
1516 nregs >>= 4;
1517 nregs &= 0xf;
1518 firstreg = GET_MEMORY_B (pc + 3);
1519 firstreg &= 0xf;
1520 for (i = firstreg; i <= firstreg + nregs; i++)
1521 {
1522 cpu.regs[7] -= 4;
1523 SET_MEMORY_L (cpu.regs[7], cpu.regs[i]);
1524 }
1525 }
1526 goto next;
1527
1528 case O (O_LDM, SL):
1529 {
1530 int nregs, firstreg, i;
1531
1532 nregs = GET_MEMORY_B (pc + 1);
1533 nregs >>= 4;
1534 nregs &= 0xf;
1535 firstreg = GET_MEMORY_B (pc + 3);
1536 firstreg &= 0xf;
1537 for (i = firstreg; i >= firstreg - nregs; i--)
1538 {
1539 cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]);
1540 cpu.regs[7] += 4;
1541 }
1542 }
1543 goto next;
1544
1545 default:
1546 cpu.state = SIM_STATE_STOPPED;
1547 cpu.exception = SIGILL;
1548 goto end;
1549
1550 }
1551 abort ();
1552
1553 setc:
1554 cpu.ccr = res;
1555 GETSR ();
1556 goto next;
1557
1558 condtrue:
1559 /* When a branch works */
1560 pc = code->src.literal;
1561 goto end;
1562
1563 /* Set the cond codes from res */
1564 bitop:
1565
1566 /* Set the flags after an 8 bit inc/dec operation */
1567 just_flags_inc8:
1568 n = res & 0x80;
1569 nz = res & 0xff;
1570 v = (rd & 0x7f) == 0x7f;
1571 goto next;
1572
1573
1574 /* Set the flags after an 16 bit inc/dec operation */
1575 just_flags_inc16:
1576 n = res & 0x8000;
1577 nz = res & 0xffff;
1578 v = (rd & 0x7fff) == 0x7fff;
1579 goto next;
1580
1581
1582 /* Set the flags after an 32 bit inc/dec operation */
1583 just_flags_inc32:
1584 n = res & 0x80000000;
1585 nz = res & 0xffffffff;
1586 v = (rd & 0x7fffffff) == 0x7fffffff;
1587 goto next;
1588
1589
1590 shift8:
1591 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1592 n = (rd & 0x80);
1593 nz = rd & 0xff;
1594 SET_B_REG (code->src.reg, rd);
1595 goto next;
1596
1597 shift16:
1598 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1599 n = (rd & 0x8000);
1600 nz = rd & 0xffff;
1601 SET_W_REG (code->src.reg, rd);
1602 goto next;
1603
1604 shift32:
1605 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1606 n = (rd & 0x80000000);
1607 nz = rd & 0xffffffff;
1608 SET_L_REG (code->src.reg, rd);
1609 goto next;
1610
1611 log32:
1612 store (&code->dst, res);
1613 just_flags_log32:
1614 /* flags after a 32bit logical operation */
1615 n = res & 0x80000000;
1616 nz = res & 0xffffffff;
1617 v = 0;
1618 goto next;
1619
1620 log16:
1621 store (&code->dst, res);
1622 just_flags_log16:
1623 /* flags after a 16bit logical operation */
1624 n = res & 0x8000;
1625 nz = res & 0xffff;
1626 v = 0;
1627 goto next;
1628
1629
1630 log8:
1631 store (&code->dst, res);
1632 just_flags_log8:
1633 n = res & 0x80;
1634 nz = res & 0xff;
1635 v = 0;
1636 goto next;
1637
1638 alu8:
1639 SET_B_REG (code->dst.reg, res);
1640 just_flags_alu8:
1641 n = res & 0x80;
1642 nz = res & 0xff;
1643 c = (res & 0x100);
1644 switch (code->opcode / 4)
1645 {
1646 case O_ADD:
1647 v = ((rd & 0x80) == (ea & 0x80)
1648 && (rd & 0x80) != (res & 0x80));
1649 break;
1650 case O_SUB:
1651 case O_CMP:
1652 v = ((rd & 0x80) != (-ea & 0x80)
1653 && (rd & 0x80) != (res & 0x80));
1654 break;
1655 case O_NEG:
1656 v = (rd == 0x80);
1657 break;
1658 }
1659 goto next;
1660
1661 alu16:
1662 SET_W_REG (code->dst.reg, res);
1663 just_flags_alu16:
1664 n = res & 0x8000;
1665 nz = res & 0xffff;
1666 c = (res & 0x10000);
1667 switch (code->opcode / 4)
1668 {
1669 case O_ADD:
1670 v = ((rd & 0x8000) == (ea & 0x8000)
1671 && (rd & 0x8000) != (res & 0x8000));
1672 break;
1673 case O_SUB:
1674 case O_CMP:
1675 v = ((rd & 0x8000) != (-ea & 0x8000)
1676 && (rd & 0x8000) != (res & 0x8000));
1677 break;
1678 case O_NEG:
1679 v = (rd == 0x8000);
1680 break;
1681 }
1682 goto next;
1683
1684 alu32:
1685 SET_L_REG (code->dst.reg, res);
1686 just_flags_alu32:
1687 n = res & 0x80000000;
1688 nz = res & 0xffffffff;
1689 switch (code->opcode / 4)
1690 {
1691 case O_ADD:
1692 v = ((rd & 0x80000000) == (ea & 0x80000000)
1693 && (rd & 0x80000000) != (res & 0x80000000));
1694 c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1695 break;
1696 case O_SUB:
1697 case O_CMP:
1698 v = ((rd & 0x80000000) != (-ea & 0x80000000)
1699 && (rd & 0x80000000) != (res & 0x80000000));
1700 c = (unsigned) rd < (unsigned) -ea;
1701 break;
1702 case O_NEG:
1703 v = (rd == 0x80000000);
1704 c = res != 0;
1705 break;
1706 }
1707 goto next;
1708
1709 next:;
1710 pc = code->next_pc;
1711
1712 end:
1713 ;
1714 /* if (cpu.regs[8] ) abort(); */
1715
1716 if (--poll_count < 0)
1717 {
1718 poll_count = POLL_QUIT_INTERVAL;
1719 if ((*sim_callback->poll_quit) != NULL
1720 && (*sim_callback->poll_quit) (sim_callback))
1721 sim_stop (sd);
1722 }
1723
1724 }
1725 while (cpu.state == SIM_STATE_RUNNING);
1726 cpu.ticks += get_now () - tick_start;
1727 cpu.cycles += cycles;
1728 cpu.insts += insts;
1729
1730 cpu.pc = pc;
1731 BUILDSR ();
1732 cpu.mask = oldmask;
1733 signal (SIGINT, prev);
1734 }
1735
1736 int
1737 sim_trace (sd)
1738 SIM_DESC sd;
1739 {
1740 /* FIXME: unfinished */
1741 abort ();
1742 }
1743
1744 int
1745 sim_write (sd, addr, buffer, size)
1746 SIM_DESC sd;
1747 SIM_ADDR addr;
1748 unsigned char *buffer;
1749 int size;
1750 {
1751 int i;
1752
1753 init_pointers ();
1754 if (addr < 0)
1755 return 0;
1756 for (i = 0; i < size; i++)
1757 {
1758 if (addr < memory_size)
1759 {
1760 cpu.memory[addr + i] = buffer[i];
1761 cpu.cache_idx[addr + i] = 0;
1762 }
1763 else
1764 cpu.eightbit[(addr + i) & 0xff] = buffer[i];
1765 }
1766 return size;
1767 }
1768
1769 int
1770 sim_read (sd, addr, buffer, size)
1771 SIM_DESC sd;
1772 SIM_ADDR addr;
1773 unsigned char *buffer;
1774 int size;
1775 {
1776 init_pointers ();
1777 if (addr < 0)
1778 return 0;
1779 if (addr < memory_size)
1780 memcpy (buffer, cpu.memory + addr, size);
1781 else
1782 memcpy (buffer, cpu.eightbit + (addr & 0xff), size);
1783 return size;
1784 }
1785
1786
1787 #define R0_REGNUM 0
1788 #define R1_REGNUM 1
1789 #define R2_REGNUM 2
1790 #define R3_REGNUM 3
1791 #define R4_REGNUM 4
1792 #define R5_REGNUM 5
1793 #define R6_REGNUM 6
1794 #define R7_REGNUM 7
1795
1796 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1797 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1798 * stack frame */
1799
1800 #define CCR_REGNUM 8 /* Contains processor status */
1801 #define PC_REGNUM 9 /* Contains program counter */
1802
1803 #define CYCLE_REGNUM 10
1804 #define INST_REGNUM 11
1805 #define TICK_REGNUM 12
1806
1807
1808 int
1809 sim_store_register (sd, rn, value, length)
1810 SIM_DESC sd;
1811 int rn;
1812 unsigned char *value;
1813 int length;
1814 {
1815 int longval;
1816 int shortval;
1817 int intval;
1818 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1819 shortval = (value[0] << 8) | (value[1]);
1820 intval = h8300hmode ? longval : shortval;
1821
1822 init_pointers ();
1823 switch (rn)
1824 {
1825 case PC_REGNUM:
1826 cpu.pc = intval;
1827 break;
1828 default:
1829 abort ();
1830 case R0_REGNUM:
1831 case R1_REGNUM:
1832 case R2_REGNUM:
1833 case R3_REGNUM:
1834 case R4_REGNUM:
1835 case R5_REGNUM:
1836 case R6_REGNUM:
1837 case R7_REGNUM:
1838 cpu.regs[rn] = intval;
1839 break;
1840 case CCR_REGNUM:
1841 cpu.ccr = intval;
1842 break;
1843 case CYCLE_REGNUM:
1844 cpu.cycles = longval;
1845 break;
1846
1847 case INST_REGNUM:
1848 cpu.insts = longval;
1849 break;
1850
1851 case TICK_REGNUM:
1852 cpu.ticks = longval;
1853 break;
1854 }
1855 return -1;
1856 }
1857
1858 int
1859 sim_fetch_register (sd, rn, buf, length)
1860 SIM_DESC sd;
1861 int rn;
1862 unsigned char *buf;
1863 int length;
1864 {
1865 int v;
1866 int longreg = 0;
1867
1868 init_pointers ();
1869
1870 switch (rn)
1871 {
1872 default:
1873 abort ();
1874 case 8:
1875 v = cpu.ccr;
1876 break;
1877 case 9:
1878 v = cpu.pc;
1879 break;
1880 case R0_REGNUM:
1881 case R1_REGNUM:
1882 case R2_REGNUM:
1883 case R3_REGNUM:
1884 case R4_REGNUM:
1885 case R5_REGNUM:
1886 case R6_REGNUM:
1887 case R7_REGNUM:
1888 v = cpu.regs[rn];
1889 break;
1890 case 10:
1891 v = cpu.cycles;
1892 longreg = 1;
1893 break;
1894 case 11:
1895 v = cpu.ticks;
1896 longreg = 1;
1897 break;
1898 case 12:
1899 v = cpu.insts;
1900 longreg = 1;
1901 break;
1902 }
1903 if (h8300hmode || longreg)
1904 {
1905 buf[0] = v >> 24;
1906 buf[1] = v >> 16;
1907 buf[2] = v >> 8;
1908 buf[3] = v >> 0;
1909 }
1910 else
1911 {
1912 buf[0] = v >> 8;
1913 buf[1] = v;
1914 }
1915 return -1;
1916 }
1917
1918 void
1919 sim_stop_reason (sd, reason, sigrc)
1920 SIM_DESC sd;
1921 enum sim_stop *reason;
1922 int *sigrc;
1923 {
1924 #if 0 /* FIXME: This should work but we can't use it.
1925 grep for SLEEP above. */
1926 switch (cpu.state)
1927 {
1928 case SIM_STATE_EXITED : *reason = sim_exited; break;
1929 case SIM_STATE_SIGNALLED : *reason = sim_signalled; break;
1930 case SIM_STATE_STOPPED : *reason = sim_stopped; break;
1931 default : abort ();
1932 }
1933 #else
1934 *reason = sim_stopped;
1935 #endif
1936 *sigrc = cpu.exception;
1937 }
1938
1939 /* FIXME: Rename to sim_set_mem_size. */
1940
1941 void
1942 sim_size (n)
1943 int n;
1944 {
1945 /* Memory size is fixed. */
1946 }
1947
1948 void
1949 sim_set_simcache_size (n)
1950 {
1951 if (cpu.cache)
1952 free (cpu.cache);
1953 if (n < 2)
1954 n = 2;
1955 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1956 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1957 cpu.csize = n;
1958 }
1959
1960
1961 void
1962 sim_info (sd, verbose)
1963 SIM_DESC sd;
1964 int verbose;
1965 {
1966 double timetaken = (double) cpu.ticks / (double) now_persec ();
1967 double virttime = cpu.cycles / 10.0e6;
1968
1969 (*sim_callback->printf_filtered) (sim_callback,
1970 "\n\n#instructions executed %10d\n",
1971 cpu.insts);
1972 (*sim_callback->printf_filtered) (sim_callback,
1973 "#cycles (v approximate) %10d\n",
1974 cpu.cycles);
1975 (*sim_callback->printf_filtered) (sim_callback,
1976 "#real time taken %10.4f\n",
1977 timetaken);
1978 (*sim_callback->printf_filtered) (sim_callback,
1979 "#virtual time taked %10.4f\n",
1980 virttime);
1981 if (timetaken != 0.0)
1982 (*sim_callback->printf_filtered) (sim_callback,
1983 "#simulation ratio %10.4f\n",
1984 virttime / timetaken);
1985 (*sim_callback->printf_filtered) (sim_callback,
1986 "#compiles %10d\n",
1987 cpu.compiles);
1988 (*sim_callback->printf_filtered) (sim_callback,
1989 "#cache size %10d\n",
1990 cpu.csize);
1991
1992 #ifdef ADEBUG
1993 /* This to be conditional on `what' (aka `verbose'),
1994 however it was never passed as non-zero. */
1995 if (1)
1996 {
1997 int i;
1998 for (i = 0; i < O_LAST; i++)
1999 {
2000 if (cpu.stats[i])
2001 (*sim_callback->printf_filtered) (sim_callback,
2002 "%d: %d\n", i, cpu.stats[i]);
2003 }
2004 }
2005 #endif
2006 }
2007
2008 /* Indicate whether the cpu is an h8/300 or h8/300h.
2009 FLAG is non-zero for the h8/300h. */
2010
2011 void
2012 set_h8300h (flag)
2013 int flag;
2014 {
2015 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2016 This function being replaced by a sim_open:ARGV configuration
2017 option */
2018 h8300hmode = flag;
2019 }
2020
2021 SIM_DESC
2022 sim_open (kind, ptr, abfd, argv)
2023 SIM_OPEN_KIND kind;
2024 struct host_callback_struct *ptr;
2025 struct _bfd *abfd;
2026 char **argv;
2027 {
2028 /* FIXME: Much of the code in sim_load can be moved here */
2029
2030 sim_kind = kind;
2031 myname = argv[0];
2032 sim_callback = ptr;
2033 /* fudge our descriptor */
2034 return (SIM_DESC) 1;
2035 }
2036
2037 void
2038 sim_close (sd, quitting)
2039 SIM_DESC sd;
2040 int quitting;
2041 {
2042 /* nothing to do */
2043 }
2044
2045 /* Called by gdb to load a program into memory. */
2046
2047 SIM_RC
2048 sim_load (sd, prog, abfd, from_tty)
2049 SIM_DESC sd;
2050 char *prog;
2051 bfd *abfd;
2052 int from_tty;
2053 {
2054 bfd *prog_bfd;
2055
2056 /* FIXME: The code below that sets a specific variant of the h8/300
2057 being simulated should be moved to sim_open(). */
2058
2059 /* See if the file is for the h8/300 or h8/300h. */
2060 /* ??? This may not be the most efficient way. The z8k simulator
2061 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2062 if (abfd != NULL)
2063 prog_bfd = abfd;
2064 else
2065 prog_bfd = bfd_openr (prog, "coff-h8300");
2066 if (prog_bfd != NULL)
2067 {
2068 /* Set the cpu type. We ignore failure from bfd_check_format
2069 and bfd_openr as sim_load_file checks too. */
2070 if (bfd_check_format (prog_bfd, bfd_object))
2071 {
2072 unsigned long mach = bfd_get_mach (prog_bfd);
2073 set_h8300h (mach == bfd_mach_h8300h
2074 || mach == bfd_mach_h8300s);
2075 }
2076 }
2077
2078 /* If we're using gdb attached to the simulator, then we have to
2079 reallocate memory for the simulator.
2080
2081 When gdb first starts, it calls fetch_registers (among other
2082 functions), which in turn calls init_pointers, which allocates
2083 simulator memory.
2084
2085 The problem is when we do that, we don't know whether we're
2086 debugging an h8/300 or h8/300h program.
2087
2088 This is the first point at which we can make that determination,
2089 so we just reallocate memory now; this will also allow us to handle
2090 switching between h8/300 and h8/300h programs without exiting
2091 gdb. */
2092 if (h8300hmode)
2093 memory_size = H8300H_MSIZE;
2094 else
2095 memory_size = H8300_MSIZE;
2096
2097 if (cpu.memory)
2098 free (cpu.memory);
2099 if (cpu.cache_idx)
2100 free (cpu.cache_idx);
2101 if (cpu.eightbit)
2102 free (cpu.eightbit);
2103
2104 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
2105 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
2106 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
2107
2108 /* `msize' must be a power of two */
2109 if ((memory_size & (memory_size - 1)) != 0)
2110 abort ();
2111 cpu.mask = memory_size - 1;
2112
2113 if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd,
2114 sim_kind == SIM_OPEN_DEBUG,
2115 0, sim_write)
2116 == NULL)
2117 {
2118 /* Close the bfd if we opened it. */
2119 if (abfd == NULL && prog_bfd != NULL)
2120 bfd_close (prog_bfd);
2121 return SIM_RC_FAIL;
2122 }
2123
2124 /* Close the bfd if we opened it. */
2125 if (abfd == NULL && prog_bfd != NULL)
2126 bfd_close (prog_bfd);
2127 return SIM_RC_OK;
2128 }
2129
2130 SIM_RC
2131 sim_create_inferior (sd, abfd, argv, env)
2132 SIM_DESC sd;
2133 struct _bfd *abfd;
2134 char **argv;
2135 char **env;
2136 {
2137 if (abfd != NULL)
2138 cpu.pc = bfd_get_start_address (abfd);
2139 else
2140 cpu.pc = 0;
2141 return SIM_RC_OK;
2142 }
2143
2144 void
2145 sim_do_command (sd, cmd)
2146 SIM_DESC sd;
2147 char *cmd;
2148 {
2149 (*sim_callback->printf_filtered) (sim_callback,
2150 "This simulator does not accept any commands.\n");
2151 }
2152
2153 void
2154 sim_set_callbacks (ptr)
2155 struct host_callback_struct *ptr;
2156 {
2157 sim_callback = ptr;
2158 }
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