2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
28 #ifdef HAVE_SYS_PARAM_H
29 #include <sys/param.h>
34 #include "gdb/sim-h8300.h"
36 #include "sys/types.h"
37 #include "sim-options.h"
45 host_callback
*sim_callback
;
47 static SIM_OPEN_KIND sim_kind
;
50 /* FIXME: Needs to live in header file.
51 This header should also include the things in remote-sim.h.
52 One could move this to remote-sim.h but this function isn't needed
54 static void set_simcache_size (SIM_DESC
, int);
56 #define X(op, size) (op * 4 + size)
58 #define SP (h8300hmode && !h8300_normal_mode ? SL : SW)
60 #define h8_opcodes ops
62 #include "opcode/h8300.h"
64 /* CPU data object: */
67 sim_state_initialize (SIM_DESC sd
, sim_cpu
*cpu
)
69 /* FIXME: not really necessary, since sim_cpu_alloc calls zalloc. */
71 memset (&cpu
->regs
, 0, sizeof(cpu
->regs
));
72 cpu
->regs
[SBR_REGNUM
] = 0xFFFFFF00;
74 cpu
->delayed_branch
= 0;
79 /* Initialize local simulator state. */
81 sd
->sim_cache_size
= 0;
87 memset (&cpu
->stats
, 0, sizeof (cpu
->stats
));
93 h8_get_pc (SIM_DESC sd
)
95 return (STATE_CPU (sd
, 0)) -> pc
;
99 h8_set_pc (SIM_DESC sd
, unsigned int val
)
101 (STATE_CPU (sd
, 0)) -> pc
= val
;
105 h8_get_ccr (SIM_DESC sd
)
107 return (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
];
111 h8_set_ccr (SIM_DESC sd
, unsigned int val
)
113 (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
] = val
;
117 h8_get_exr (SIM_DESC sd
)
119 return (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
];
123 h8_set_exr (SIM_DESC sd
, unsigned int val
)
125 (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
] = val
;
129 h8_get_sbr (SIM_DESC sd
)
131 return (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
];
135 h8_set_sbr (SIM_DESC sd
, int val
)
137 (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
] = val
;
141 h8_get_vbr (SIM_DESC sd
)
143 return (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
];
147 h8_set_vbr (SIM_DESC sd
, int val
)
149 (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
] = val
;
153 h8_get_cache_top (SIM_DESC sd
)
155 return sd
-> cache_top
;
159 h8_set_cache_top (SIM_DESC sd
, int val
)
161 sd
-> cache_top
= val
;
165 h8_get_mask (SIM_DESC sd
)
167 return (STATE_CPU (sd
, 0)) -> mask
;
171 h8_set_mask (SIM_DESC sd
, int val
)
173 (STATE_CPU (sd
, 0)) -> mask
= val
;
177 h8_get_exception (SIM_DESC sd
)
179 return (STATE_CPU (sd
, 0)) -> exception
;
183 h8_set_exception (SIM_DESC sd
, int val
)
185 (STATE_CPU (sd
, 0)) -> exception
= val
;
188 static enum h8300_sim_state
189 h8_get_state (SIM_DESC sd
)
195 h8_set_state (SIM_DESC sd
, enum h8300_sim_state val
)
201 h8_get_cycles (SIM_DESC sd
)
203 return (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
];
207 h8_set_cycles (SIM_DESC sd
, unsigned int val
)
209 (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
] = val
;
213 h8_get_insts (SIM_DESC sd
)
215 return (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
];
219 h8_set_insts (SIM_DESC sd
, unsigned int val
)
221 (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
] = val
;
225 h8_get_ticks (SIM_DESC sd
)
227 return (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
];
231 h8_set_ticks (SIM_DESC sd
, unsigned int val
)
233 (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
] = val
;
237 h8_get_mach (SIM_DESC sd
)
239 return (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
];
243 h8_set_mach (SIM_DESC sd
, unsigned int val
)
245 (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
] = val
;
249 h8_get_macl (SIM_DESC sd
)
251 return (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
];
255 h8_set_macl (SIM_DESC sd
, unsigned int val
)
257 (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
] = val
;
261 h8_get_compiles (SIM_DESC sd
)
263 return sd
-> compiles
;
267 h8_increment_compiles (SIM_DESC sd
)
272 static unsigned int *
273 h8_get_reg_buf (SIM_DESC sd
)
275 return &(((STATE_CPU (sd
, 0)) -> regs
)[0]);
279 h8_get_reg (SIM_DESC sd
, int regnum
)
281 return (STATE_CPU (sd
, 0)) -> regs
[regnum
];
285 h8_set_reg (SIM_DESC sd
, int regnum
, int val
)
287 (STATE_CPU (sd
, 0)) -> regs
[regnum
] = val
;
292 h8_get_stats (SIM_DESC sd
, int idx
)
294 return sd
-> stats
[idx
];
298 h8_increment_stats (SIM_DESC sd
, int idx
)
304 static unsigned short *
305 h8_get_cache_idx_buf (SIM_DESC sd
)
307 return sd
-> cache_idx
;
311 h8_set_cache_idx_buf (SIM_DESC sd
, unsigned short *ptr
)
313 sd
-> cache_idx
= ptr
;
316 static unsigned short
317 h8_get_cache_idx (SIM_DESC sd
, unsigned int idx
)
319 if (idx
> sd
->memory_size
)
320 return (unsigned short) -1;
321 return sd
-> cache_idx
[idx
];
325 h8_set_cache_idx (SIM_DESC sd
, int idx
, unsigned int val
)
327 sd
-> cache_idx
[idx
] = (unsigned short) val
;
330 static unsigned char *
331 h8_get_memory_buf (SIM_DESC sd
)
333 return (STATE_CPU (sd
, 0)) -> memory
;
337 h8_set_memory_buf (SIM_DESC sd
, unsigned char *ptr
)
339 (STATE_CPU (sd
, 0)) -> memory
= ptr
;
343 h8_get_memory (SIM_DESC sd
, int idx
)
345 return (STATE_CPU (sd
, 0)) -> memory
[idx
];
349 h8_set_memory (SIM_DESC sd
, int idx
, unsigned int val
)
351 (STATE_CPU (sd
, 0)) -> memory
[idx
] = (unsigned char) val
;
354 static unsigned char *
355 h8_get_eightbit_buf (SIM_DESC sd
)
357 return (STATE_CPU (sd
, 0)) -> eightbit
;
361 h8_set_eightbit_buf (SIM_DESC sd
, unsigned char *ptr
)
363 (STATE_CPU (sd
, 0)) -> eightbit
= ptr
;
367 h8_get_eightbit (SIM_DESC sd
, int idx
)
369 return (STATE_CPU (sd
, 0)) -> eightbit
[idx
];
373 h8_set_eightbit (SIM_DESC sd
, int idx
, unsigned int val
)
375 (STATE_CPU (sd
, 0)) -> eightbit
[idx
] = (unsigned char) val
;
379 h8_get_delayed_branch (SIM_DESC sd
)
381 return (STATE_CPU (sd
, 0)) -> delayed_branch
;
385 h8_set_delayed_branch (SIM_DESC sd
, unsigned int dest
)
387 (STATE_CPU (sd
, 0)) -> delayed_branch
= dest
;
391 h8_get_command_line (SIM_DESC sd
)
393 return (STATE_CPU (sd
, 0)) -> command_line
;
397 h8_set_command_line (SIM_DESC sd
, char ** val
)
399 (STATE_CPU (sd
, 0)) -> command_line
= val
;
403 h8_get_cmdline_arg (SIM_DESC sd
, int index
)
405 return (STATE_CPU (sd
, 0)) -> command_line
[index
];
409 h8_set_cmdline_arg (SIM_DESC sd
, int index
, char * val
)
411 (STATE_CPU (sd
, 0)) -> command_line
[index
] = val
;
414 /* MAC Saturation Mode */
416 h8_get_macS (SIM_DESC sd
)
418 return (STATE_CPU (sd
, 0)) -> macS
;
422 h8_set_macS (SIM_DESC sd
, int val
)
424 (STATE_CPU (sd
, 0)) -> macS
= (val
!= 0);
429 h8_get_macZ (SIM_DESC sd
)
431 return (STATE_CPU (sd
, 0)) -> macZ
;
435 h8_set_macZ (SIM_DESC sd
, int val
)
437 (STATE_CPU (sd
, 0)) -> macZ
= (val
!= 0);
440 /* MAC Negative Flag */
442 h8_get_macN (SIM_DESC sd
)
444 return (STATE_CPU (sd
, 0)) -> macN
;
448 h8_set_macN (SIM_DESC sd
, int val
)
450 (STATE_CPU (sd
, 0)) -> macN
= (val
!= 0);
453 /* MAC Overflow Flag */
455 h8_get_macV (SIM_DESC sd
)
457 return (STATE_CPU (sd
, 0)) -> macV
;
461 h8_set_macV (SIM_DESC sd
, int val
)
463 (STATE_CPU (sd
, 0)) -> macV
= (val
!= 0);
466 /* End CPU data object. */
468 /* The rate at which to call the host's poll_quit callback. */
470 enum { POLL_QUIT_INTERVAL
= 0x80000 };
472 #define LOW_BYTE(x) ((x) & 0xff)
473 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
474 #define P(X, Y) ((X << 8) | Y)
483 #define I (intMaskBit != 0)
485 #define BUILDSR(SD) \
486 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
487 | (N << 3) | (Z << 2) | (V << 1) | C)
490 /* Get Status Register (flags). */ \
491 c = (h8_get_ccr (sd) >> 0) & 1; \
492 v = (h8_get_ccr (sd) >> 1) & 1; \
493 nz = !((h8_get_ccr (sd) >> 2) & 1); \
494 n = (h8_get_ccr (sd) >> 3) & 1; \
495 u = (h8_get_ccr (sd) >> 4) & 1; \
496 h = (h8_get_ccr (sd) >> 5) & 1; \
497 ui = ((h8_get_ccr (sd) >> 6) & 1); \
498 intMaskBit = (h8_get_ccr (sd) >> 7) & 1
501 #ifdef __CHAR_IS_SIGNED__
502 #define SEXTCHAR(x) ((char) (x))
506 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
509 #define UEXTCHAR(x) ((x) & 0xff)
510 #define UEXTSHORT(x) ((x) & 0xffff)
511 #define SEXTSHORT(x) ((short) (x))
515 int h8300_normal_mode
= 0;
518 static int memory_size
;
523 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
545 return (h8300hmode
&& !h8300_normal_mode
)? SL
: SW
;
550 /* Simulate an indirection / dereference.
551 return 0 for success, -1 for failure.
555 lvalue (SIM_DESC sd
, int x
, int rn
, unsigned int *val
)
557 if (val
== NULL
) /* Paranoia. */
563 if (rn
== ZERO_REGNUM
)
564 *val
= X (OP_IMM
, SP
);
566 *val
= X (OP_REG
, SP
);
569 *val
= X (OP_MEM
, SP
);
572 sim_engine_set_run_state (sd
, sim_stopped
, SIGSEGV
);
581 if (h8300smode
&& !h8300_normal_mode
)
583 else if (h8300hmode
&& !h8300_normal_mode
)
590 decode (SIM_DESC sd
, int addr
, unsigned char *data
, decoded_inst
*dst
)
592 int cst
[3] = {0, 0, 0};
593 int reg
[3] = {0, 0, 0};
594 int rdisp
[3] = {0, 0, 0};
596 const struct h8_opcode
*q
;
601 /* Find the exact opcode/arg combo. */
602 for (q
= h8_opcodes
; q
->name
; q
++)
604 const op_type
*nib
= q
->data
.nib
;
605 unsigned int len
= 0;
607 if ((q
->available
== AV_H8SX
&& !h8300sxmode
) ||
608 (q
->available
== AV_H8S
&& !h8300smode
) ||
609 (q
->available
== AV_H8H
&& !h8300hmode
))
612 cst
[0] = cst
[1] = cst
[2] = 0;
613 reg
[0] = reg
[1] = reg
[2] = 0;
614 rdisp
[0] = rdisp
[1] = rdisp
[2] = 0;
618 op_type looking_for
= *nib
;
619 int thisnib
= data
[len
/ 2];
621 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
622 opnum
= ((looking_for
& OP3
) ? 2 :
623 (looking_for
& DST
) ? 1 : 0);
625 if (looking_for
< 16 && looking_for
>= 0)
627 if (looking_for
!= thisnib
)
632 if (looking_for
& B31
)
634 if (!((thisnib
& 0x8) != 0))
637 looking_for
= (op_type
) (looking_for
& ~B31
);
640 else if (looking_for
& B30
)
642 if (!((thisnib
& 0x8) == 0))
645 looking_for
= (op_type
) (looking_for
& ~B30
);
648 if (looking_for
& B21
)
650 if (!((thisnib
& 0x4) != 0))
653 looking_for
= (op_type
) (looking_for
& ~B21
);
656 else if (looking_for
& B20
)
658 if (!((thisnib
& 0x4) == 0))
661 looking_for
= (op_type
) (looking_for
& ~B20
);
664 if (looking_for
& B11
)
666 if (!((thisnib
& 0x2) != 0))
669 looking_for
= (op_type
) (looking_for
& ~B11
);
672 else if (looking_for
& B10
)
674 if (!((thisnib
& 0x2) == 0))
677 looking_for
= (op_type
) (looking_for
& ~B10
);
680 if (looking_for
& B01
)
682 if (!((thisnib
& 0x1) != 0))
685 looking_for
= (op_type
) (looking_for
& ~B01
);
688 else if (looking_for
& B00
)
690 if (!((thisnib
& 0x1) == 0))
693 looking_for
= (op_type
) (looking_for
& ~B00
);
696 if (looking_for
& IGNORE
)
698 /* Hitachi has declared that IGNORE must be zero. */
702 else if ((looking_for
& MODE
) == DATA
)
704 ; /* Skip embedded data. */
706 else if ((looking_for
& MODE
) == DBIT
)
708 /* Exclude adds/subs by looking at bit 0 and 2, and
709 make sure the operand size, either w or l,
710 matches by looking at bit 1. */
711 if ((looking_for
& 7) != (thisnib
& 7))
714 cst
[opnum
] = (thisnib
& 0x8) ? 2 : 1;
716 else if ((looking_for
& MODE
) == REG
||
717 (looking_for
& MODE
) == LOWREG
||
718 (looking_for
& MODE
) == IND
||
719 (looking_for
& MODE
) == PREINC
||
720 (looking_for
& MODE
) == POSTINC
||
721 (looking_for
& MODE
) == PREDEC
||
722 (looking_for
& MODE
) == POSTDEC
)
724 reg
[opnum
] = thisnib
;
726 else if (looking_for
& CTRL
)
729 if (((looking_for
& MODE
) == CCR
&& (thisnib
!= C_CCR
)) ||
730 ((looking_for
& MODE
) == EXR
&& (thisnib
!= C_EXR
)) ||
731 ((looking_for
& MODE
) == MACH
&& (thisnib
!= C_MACH
)) ||
732 ((looking_for
& MODE
) == MACL
&& (thisnib
!= C_MACL
)) ||
733 ((looking_for
& MODE
) == VBR
&& (thisnib
!= C_VBR
)) ||
734 ((looking_for
& MODE
) == SBR
&& (thisnib
!= C_SBR
)))
736 if (((looking_for
& MODE
) == CCR_EXR
&&
737 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
)) ||
738 ((looking_for
& MODE
) == VBR_SBR
&&
739 (thisnib
!= C_VBR
&& thisnib
!= C_SBR
)) ||
740 ((looking_for
& MODE
) == MACREG
&&
741 (thisnib
!= C_MACH
&& thisnib
!= C_MACL
)))
743 if (((looking_for
& MODE
) == CC_EX_VB_SB
&&
744 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
&&
745 thisnib
!= C_VBR
&& thisnib
!= C_SBR
)))
748 reg
[opnum
] = thisnib
;
750 else if ((looking_for
& MODE
) == ABS
)
752 /* Absolute addresses are unsigned. */
753 switch (looking_for
& SIZE
)
756 cst
[opnum
] = UEXTCHAR (data
[len
/ 2]);
760 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
764 (data
[len
/ 2 + 0] << 24) +
765 (data
[len
/ 2 + 1] << 16) +
766 (data
[len
/ 2 + 2] << 8) +
770 printf ("decode: bad size ABS: %d\n",
771 (looking_for
& SIZE
));
775 else if ((looking_for
& MODE
) == DISP
||
776 (looking_for
& MODE
) == PCREL
||
777 (looking_for
& MODE
) == INDEXB
||
778 (looking_for
& MODE
) == INDEXW
||
779 (looking_for
& MODE
) == INDEXL
)
781 switch (looking_for
& SIZE
)
784 cst
[opnum
] = thisnib
& 3;
787 cst
[opnum
] = SEXTCHAR (data
[len
/ 2]);
790 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
791 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
794 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
798 (data
[len
/ 2 + 0] << 24) +
799 (data
[len
/ 2 + 1] << 16) +
800 (data
[len
/ 2 + 2] << 8) +
804 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
805 (looking_for
& SIZE
));
809 else if ((looking_for
& SIZE
) == L_16
||
810 (looking_for
& SIZE
) == L_16U
)
812 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
813 /* Immediates are always unsigned. */
814 if ((looking_for
& SIZE
) != L_16U
&&
815 (looking_for
& MODE
) != IMM
)
816 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
818 else if (looking_for
& ABSJMP
)
820 switch (looking_for
& SIZE
) {
822 cst
[opnum
] = (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
826 (data
[len
/ 2 + 0] << 24) +
827 (data
[len
/ 2 + 1] << 16) +
828 (data
[len
/ 2 + 2] << 8) +
832 printf ("decode: bad size ABSJMP: %d\n",
833 (looking_for
& SIZE
));
837 else if ((looking_for
& MODE
) == MEMIND
)
839 cst
[opnum
] = data
[1];
841 else if ((looking_for
& MODE
) == VECIND
)
843 if(h8300_normal_mode
)
844 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 2;
846 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 4;
847 cst
[opnum
] += h8_get_vbr (sd
); /* Add vector base reg. */
849 else if ((looking_for
& SIZE
) == L_32
)
854 (data
[i
+ 0] << 24) |
855 (data
[i
+ 1] << 16) |
859 else if ((looking_for
& SIZE
) == L_24
)
864 (data
[i
+ 0] << 16) |
868 else if (looking_for
& DISPREG
)
870 rdisp
[opnum
] = thisnib
& 0x7;
872 else if ((looking_for
& MODE
) == KBIT
)
889 else if ((looking_for
& SIZE
) == L_8
)
891 if ((looking_for
& MODE
) == ABS
)
893 /* Will be combined with contents of SBR_REGNUM
894 by fetch (). For all modes except h8sx, this
895 will always contain the value 0xFFFFFF00. */
896 cst
[opnum
] = data
[len
/ 2] & 0xff;
900 cst
[opnum
] = data
[len
/ 2] & 0xff;
903 else if ((looking_for
& SIZE
) == L_2
)
905 cst
[opnum
] = thisnib
& 3;
907 else if ((looking_for
& SIZE
) == L_3
||
908 (looking_for
& SIZE
) == L_3NZ
)
910 cst
[opnum
] = thisnib
& 7;
911 if (cst
[opnum
] == 0 && (looking_for
& SIZE
) == L_3NZ
)
914 else if ((looking_for
& SIZE
) == L_4
)
916 cst
[opnum
] = thisnib
& 15;
918 else if ((looking_for
& SIZE
) == L_5
)
920 cst
[opnum
] = data
[len
/ 2] & 0x1f;
922 else if (looking_for
== E
)
927 /* Fill in the args. */
929 const op_type
*args
= q
->args
.nib
;
934 nargs
< 3 && *args
!= E
;
940 opnum
= ((x
& OP3
) ? 2 :
949 if ((x
& MODE
) == IMM
||
950 (x
& MODE
) == KBIT
||
953 /* Use the instruction to determine
955 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
956 p
->literal
= cst
[opnum
];
958 else if ((x
& MODE
) == CONST_2
||
959 (x
& MODE
) == CONST_4
||
960 (x
& MODE
) == CONST_8
||
961 (x
& MODE
) == CONST_16
)
963 /* Use the instruction to determine
965 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
967 case CONST_2
: p
->literal
= 2; break;
968 case CONST_4
: p
->literal
= 4; break;
969 case CONST_8
: p
->literal
= 8; break;
970 case CONST_16
: p
->literal
= 16; break;
973 else if ((x
& MODE
) == REG
)
975 p
->type
= X (OP_REG
, bitfrom (x
));
978 else if ((x
& MODE
) == LOWREG
)
980 p
->type
= X (OP_LOWREG
, bitfrom (x
));
983 else if ((x
& MODE
) == PREINC
)
985 /* Use the instruction to determine
987 p
->type
= X (OP_PREINC
, OP_SIZE (q
->how
));
988 p
->reg
= reg
[opnum
] & 0x7;
990 else if ((x
& MODE
) == POSTINC
)
992 /* Use the instruction to determine
994 p
->type
= X (OP_POSTINC
, OP_SIZE (q
->how
));
995 p
->reg
= reg
[opnum
] & 0x7;
997 else if ((x
& MODE
) == PREDEC
)
999 /* Use the instruction to determine
1000 the operand size. */
1001 p
->type
= X (OP_PREDEC
, OP_SIZE (q
->how
));
1002 p
->reg
= reg
[opnum
] & 0x7;
1004 else if ((x
& MODE
) == POSTDEC
)
1006 /* Use the instruction to determine
1007 the operand size. */
1008 p
->type
= X (OP_POSTDEC
, OP_SIZE (q
->how
));
1009 p
->reg
= reg
[opnum
] & 0x7;
1011 else if ((x
& MODE
) == IND
)
1013 /* Note: an indirect is transformed into
1014 a displacement of zero.
1016 /* Use the instruction to determine
1017 the operand size. */
1018 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1019 p
->reg
= reg
[opnum
] & 0x7;
1021 if (OP_KIND (q
->how
) == O_JSR
||
1022 OP_KIND (q
->how
) == O_JMP
)
1023 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
1026 else if ((x
& MODE
) == ABS
)
1028 /* Note: a 16 or 32 bit ABS is transformed into a
1029 displacement from pseudo-register ZERO_REGNUM,
1030 which is always zero. An 8 bit ABS becomes
1031 a displacement from SBR_REGNUM.
1033 /* Use the instruction to determine
1034 the operand size. */
1035 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1036 p
->literal
= cst
[opnum
];
1038 /* 8-bit ABS is displacement from SBR.
1039 16 and 32-bit ABS are displacement from ZERO.
1040 (SBR will always be zero except for h8/sx)
1042 if ((x
& SIZE
) == L_8
)
1043 p
->reg
= SBR_REGNUM
;
1045 p
->reg
= ZERO_REGNUM
;;
1047 else if ((x
& MODE
) == MEMIND
||
1048 (x
& MODE
) == VECIND
)
1050 /* Size doesn't matter. */
1051 p
->type
= X (OP_MEM
, SB
);
1052 p
->literal
= cst
[opnum
];
1053 if (OP_KIND (q
->how
) == O_JSR
||
1054 OP_KIND (q
->how
) == O_JMP
)
1055 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
1058 else if ((x
& MODE
) == PCREL
)
1060 /* Size doesn't matter. */
1061 p
->type
= X (OP_PCREL
, SB
);
1062 p
->literal
= cst
[opnum
];
1064 else if (x
& ABSJMP
)
1066 p
->type
= X (OP_IMM
, SP
);
1067 p
->literal
= cst
[opnum
];
1069 else if ((x
& MODE
) == INDEXB
)
1071 p
->type
= X (OP_INDEXB
, OP_SIZE (q
->how
));
1072 p
->literal
= cst
[opnum
];
1073 p
->reg
= rdisp
[opnum
];
1075 else if ((x
& MODE
) == INDEXW
)
1077 p
->type
= X (OP_INDEXW
, OP_SIZE (q
->how
));
1078 p
->literal
= cst
[opnum
];
1079 p
->reg
= rdisp
[opnum
];
1081 else if ((x
& MODE
) == INDEXL
)
1083 p
->type
= X (OP_INDEXL
, OP_SIZE (q
->how
));
1084 p
->literal
= cst
[opnum
];
1085 p
->reg
= rdisp
[opnum
];
1087 else if ((x
& MODE
) == DISP
)
1089 /* Yuck -- special for mova args. */
1090 if (strncmp (q
->name
, "mova", 4) == 0 &&
1093 /* Mova can have a DISP2 dest, with an
1094 INDEXB or INDEXW src. The multiplier
1095 for the displacement value is determined
1096 by the src operand, not by the insn. */
1098 switch (OP_KIND (dst
->src
.type
))
1101 p
->type
= X (OP_DISP
, SB
);
1102 p
->literal
= cst
[opnum
];
1105 p
->type
= X (OP_DISP
, SW
);
1106 p
->literal
= cst
[opnum
] * 2;
1114 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1115 p
->literal
= cst
[opnum
];
1116 /* DISP2 is special. */
1117 if ((x
& SIZE
) == L_2
)
1118 switch (OP_SIZE (q
->how
))
1121 case SW
: p
->literal
*= 2; break;
1122 case SL
: p
->literal
*= 4; break;
1125 p
->reg
= rdisp
[opnum
];
1132 p
->type
= X (OP_CCR
, SB
);
1135 p
->type
= X (OP_EXR
, SB
);
1138 p
->type
= X (OP_MACH
, SL
);
1141 p
->type
= X (OP_MACL
, SL
);
1144 p
->type
= X (OP_VBR
, SL
);
1147 p
->type
= X (OP_SBR
, SL
);
1151 else if ((x
& MODE
) == CCR
)
1155 else if ((x
& MODE
) == EXR
)
1160 printf ("Hmmmm 0x%x...\n", x
);
1166 /* Unary operators: treat src and dst as equivalent. */
1167 if (dst
->dst
.type
== -1)
1168 dst
->dst
= dst
->src
;
1169 if (dst
->src
.type
== -1)
1170 dst
->src
= dst
->dst
;
1172 dst
->opcode
= q
->how
;
1173 dst
->cycles
= q
->time
;
1175 /* And jsr's to these locations are turned into
1178 if (OP_KIND (dst
->opcode
) == O_JSR
)
1180 switch (dst
->src
.literal
)
1183 dst
->opcode
= O (O_SYS_OPEN
, SB
);
1186 dst
->opcode
= O (O_SYS_READ
, SB
);
1189 dst
->opcode
= O (O_SYS_WRITE
, SB
);
1192 dst
->opcode
= O (O_SYS_LSEEK
, SB
);
1195 dst
->opcode
= O (O_SYS_CLOSE
, SB
);
1198 dst
->opcode
= O (O_SYS_STAT
, SB
);
1201 dst
->opcode
= O (O_SYS_FSTAT
, SB
);
1204 dst
->opcode
= O (O_SYS_CMDLINE
, SB
);
1207 /* End of Processing for system calls. */
1210 dst
->next_pc
= addr
+ len
/ 2;
1214 printf ("Don't understand 0x%x \n", looking_for
);
1225 /* Fell off the end. */
1226 dst
->opcode
= O (O_ILL
, SB
);
1230 compile (SIM_DESC sd
, int pc
)
1234 /* Find the next cache entry to use. */
1235 idx
= h8_get_cache_top (sd
) + 1;
1236 h8_increment_compiles (sd
);
1237 if (idx
>= sd
->sim_cache_size
)
1241 h8_set_cache_top (sd
, idx
);
1243 /* Throw away its old meaning. */
1244 h8_set_cache_idx (sd
, sd
->sim_cache
[idx
].oldpc
, 0);
1246 /* Set to new address. */
1247 sd
->sim_cache
[idx
].oldpc
= pc
;
1249 /* Fill in instruction info. */
1250 decode (sd
, pc
, h8_get_memory_buf (sd
) + pc
, sd
->sim_cache
+ idx
);
1252 /* Point to new cache entry. */
1253 h8_set_cache_idx (sd
, pc
, idx
);
1257 static unsigned char *breg
[32];
1258 static unsigned short *wreg
[16];
1259 static unsigned int *lreg
[18];
1261 #define GET_B_REG(X) *(breg[X])
1262 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1263 #define GET_W_REG(X) *(wreg[X])
1264 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1265 #define GET_L_REG(X) h8_get_reg (sd, X)
1266 #define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1268 #define GET_MEMORY_L(X) \
1269 ((X) < memory_size \
1270 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1271 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1272 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 24) \
1273 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 16) \
1274 | (h8_get_eightbit (sd, ((X)+2) & 0xff) << 8) \
1275 | (h8_get_eightbit (sd, ((X)+3) & 0xff) << 0)))
1277 #define GET_MEMORY_W(X) \
1278 ((X) < memory_size \
1279 ? ((h8_get_memory (sd, (X)+0) << 8) \
1280 | (h8_get_memory (sd, (X)+1) << 0)) \
1281 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 8) \
1282 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 0)))
1285 #define GET_MEMORY_B(X) \
1286 ((X) < memory_size ? (h8_get_memory (sd, (X))) \
1287 : (h8_get_eightbit (sd, (X) & 0xff)))
1289 #define SET_MEMORY_L(X, Y) \
1290 { register unsigned char *_p; register int __y = (Y); \
1291 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1292 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1293 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1294 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1297 #define SET_MEMORY_W(X, Y) \
1298 { register unsigned char *_p; register int __y = (Y); \
1299 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1300 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1301 _p[0] = __y >> 8; _p[1] = __y; \
1304 #define SET_MEMORY_B(X, Y) \
1305 ((X) < memory_size ? (h8_set_memory (sd, (X), (Y))) \
1306 : (h8_set_eightbit (sd, (X) & 0xff, (Y))))
1308 /* Simulate a memory fetch.
1309 Return 0 for success, -1 for failure.
1313 fetch_1 (SIM_DESC sd
, ea_type
*arg
, int *val
, int twice
)
1316 int abs
= arg
->literal
;
1321 return -1; /* Paranoia. */
1325 /* Indexed register plus displacement mode:
1327 This new family of addressing modes are similar to OP_DISP
1328 (register plus displacement), with two differences:
1329 1) INDEXB uses only the least significant byte of the register,
1330 INDEXW uses only the least significant word, and
1331 INDEXL uses the entire register (just like OP_DISP).
1333 2) The displacement value in abs is multiplied by two
1334 for SW-sized operations, and by four for SL-size.
1336 This gives nine possible variations.
1339 case X (OP_INDEXB
, SB
):
1340 case X (OP_INDEXB
, SW
):
1341 case X (OP_INDEXB
, SL
):
1342 case X (OP_INDEXW
, SB
):
1343 case X (OP_INDEXW
, SW
):
1344 case X (OP_INDEXW
, SL
):
1345 case X (OP_INDEXL
, SB
):
1346 case X (OP_INDEXL
, SW
):
1347 case X (OP_INDEXL
, SL
):
1349 switch (OP_KIND (arg
->type
)) {
1350 case OP_INDEXB
: t
&= 0xff; break;
1351 case OP_INDEXW
: t
&= 0xffff; break;
1355 switch (OP_SIZE (arg
->type
)) {
1357 *val
= GET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
));
1360 *val
= GET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
));
1363 *val
= GET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
));
1368 case X (OP_LOWREG
, SB
):
1369 *val
= GET_L_REG (rn
) & 0xff;
1371 case X (OP_LOWREG
, SW
):
1372 *val
= GET_L_REG (rn
) & 0xffff;
1375 case X (OP_REG
, SB
): /* Register direct, byte. */
1376 *val
= GET_B_REG (rn
);
1378 case X (OP_REG
, SW
): /* Register direct, word. */
1379 *val
= GET_W_REG (rn
);
1381 case X (OP_REG
, SL
): /* Register direct, long. */
1382 *val
= GET_L_REG (rn
);
1384 case X (OP_IMM
, SB
): /* Immediate, byte. */
1385 case X (OP_IMM
, SW
): /* Immediate, word. */
1386 case X (OP_IMM
, SL
): /* Immediate, long. */
1389 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr: byte. */
1391 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1397 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr: word. */
1399 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1405 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr: long. */
1407 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1414 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr: byte. */
1416 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1422 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr: word. */
1424 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1430 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr: long. */
1432 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1439 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr: byte. */
1440 t
= GET_L_REG (rn
) - 1;
1442 t
&= h8_get_mask (sd
);
1443 *val
= GET_MEMORY_B (t
);
1446 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr: word. */
1447 t
= GET_L_REG (rn
) - 2;
1449 t
&= h8_get_mask (sd
);
1450 *val
= GET_MEMORY_W (t
);
1453 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr: long. */
1454 t
= GET_L_REG (rn
) - 4;
1456 t
&= h8_get_mask (sd
);
1457 *val
= GET_MEMORY_L (t
);
1460 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr: byte. */
1461 t
= GET_L_REG (rn
) + 1;
1463 t
&= h8_get_mask (sd
);
1464 *val
= GET_MEMORY_B (t
);
1467 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr: long. */
1468 t
= GET_L_REG (rn
) + 2;
1470 t
&= h8_get_mask (sd
);
1471 *val
= GET_MEMORY_W (t
);
1474 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr: long. */
1475 t
= GET_L_REG (rn
) + 4;
1477 t
&= h8_get_mask (sd
);
1478 *val
= GET_MEMORY_L (t
);
1481 case X (OP_DISP
, SB
): /* Register indirect w/displacement: byte. */
1482 t
= GET_L_REG (rn
) + abs
;
1483 t
&= h8_get_mask (sd
);
1484 *val
= GET_MEMORY_B (t
);
1487 case X (OP_DISP
, SW
): /* Register indirect w/displacement: word. */
1488 t
= GET_L_REG (rn
) + abs
;
1489 t
&= h8_get_mask (sd
);
1490 *val
= GET_MEMORY_W (t
);
1493 case X (OP_DISP
, SL
): /* Register indirect w/displacement: long. */
1494 t
= GET_L_REG (rn
) + abs
;
1495 t
&= h8_get_mask (sd
);
1496 *val
=GET_MEMORY_L (t
);
1499 case X (OP_MEM
, SL
): /* Absolute memory address, long. */
1500 t
= GET_MEMORY_L (abs
);
1501 t
&= h8_get_mask (sd
);
1505 case X (OP_MEM
, SW
): /* Absolute memory address, word. */
1506 t
= GET_MEMORY_W (abs
);
1507 t
&= h8_get_mask (sd
);
1511 case X (OP_PCREL
, SB
): /* PC relative (for jump, branch etc). */
1512 case X (OP_PCREL
, SW
):
1513 case X (OP_PCREL
, SL
):
1514 case X (OP_PCREL
, SN
):
1518 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1520 sim_engine_set_run_state (sd
, sim_stopped
, SIGSEGV
);
1523 return 0; /* Success. */
1529 fetch (SIM_DESC sd
, ea_type
*arg
, int *val
)
1531 return fetch_1 (sd
, arg
, val
, 0);
1534 /* Fetch which will be followed by a store to the same location.
1535 The difference being that we don't want to do a post-increment
1536 or post-decrement at this time: we'll do it when we store. */
1539 fetch2 (SIM_DESC sd
, ea_type
*arg
, int *val
)
1541 return fetch_1 (sd
, arg
, val
, 1);
1544 /* Simulate a memory store.
1545 Return 0 for success, -1 for failure.
1549 store_1 (SIM_DESC sd
, ea_type
*arg
, int n
, int twice
)
1552 int abs
= arg
->literal
;
1557 /* Indexed register plus displacement mode:
1559 This new family of addressing modes are similar to OP_DISP
1560 (register plus displacement), with two differences:
1561 1) INDEXB uses only the least significant byte of the register,
1562 INDEXW uses only the least significant word, and
1563 INDEXL uses the entire register (just like OP_DISP).
1565 2) The displacement value in abs is multiplied by two
1566 for SW-sized operations, and by four for SL-size.
1568 This gives nine possible variations.
1571 case X (OP_INDEXB
, SB
):
1572 case X (OP_INDEXB
, SW
):
1573 case X (OP_INDEXB
, SL
):
1574 case X (OP_INDEXW
, SB
):
1575 case X (OP_INDEXW
, SW
):
1576 case X (OP_INDEXW
, SL
):
1577 case X (OP_INDEXL
, SB
):
1578 case X (OP_INDEXL
, SW
):
1579 case X (OP_INDEXL
, SL
):
1581 switch (OP_KIND (arg
->type
)) {
1582 case OP_INDEXB
: t
&= 0xff; break;
1583 case OP_INDEXW
: t
&= 0xffff; break;
1587 switch (OP_SIZE (arg
->type
)) {
1589 SET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
), n
);
1592 SET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
), n
);
1595 SET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
), n
);
1600 case X (OP_REG
, SB
): /* Register direct, byte. */
1603 case X (OP_REG
, SW
): /* Register direct, word. */
1606 case X (OP_REG
, SL
): /* Register direct, long. */
1610 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr, byte. */
1615 t
&= h8_get_mask (sd
);
1616 SET_MEMORY_B (t
, n
);
1619 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr, word. */
1624 t
&= h8_get_mask (sd
);
1625 SET_MEMORY_W (t
, n
);
1628 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr, long. */
1633 t
&= h8_get_mask (sd
);
1634 SET_MEMORY_L (t
, n
);
1637 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr, byte. */
1642 t
&= h8_get_mask (sd
);
1643 SET_MEMORY_B (t
, n
);
1646 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr, word. */
1651 t
&= h8_get_mask (sd
);
1652 SET_MEMORY_W (t
, n
);
1655 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr, long. */
1660 t
&= h8_get_mask (sd
);
1661 SET_MEMORY_L (t
, n
);
1664 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr, byte. */
1666 SET_L_REG (rn
, t
- 1);
1667 t
&= h8_get_mask (sd
);
1668 SET_MEMORY_B (t
, n
);
1671 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr, word. */
1673 SET_L_REG (rn
, t
- 2);
1674 t
&= h8_get_mask (sd
);
1675 SET_MEMORY_W (t
, n
);
1678 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr, long. */
1680 SET_L_REG (rn
, t
- 4);
1681 t
&= h8_get_mask (sd
);
1682 SET_MEMORY_L (t
, n
);
1685 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr, byte. */
1687 SET_L_REG (rn
, t
+ 1);
1688 t
&= h8_get_mask (sd
);
1689 SET_MEMORY_B (t
, n
);
1692 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr, word. */
1694 SET_L_REG (rn
, t
+ 2);
1695 t
&= h8_get_mask (sd
);
1696 SET_MEMORY_W (t
, n
);
1699 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr, long. */
1701 SET_L_REG (rn
, t
+ 4);
1702 t
&= h8_get_mask (sd
);
1703 SET_MEMORY_L (t
, n
);
1706 case X (OP_DISP
, SB
): /* Register indirect w/displacement, byte. */
1707 t
= GET_L_REG (rn
) + abs
;
1708 t
&= h8_get_mask (sd
);
1709 SET_MEMORY_B (t
, n
);
1712 case X (OP_DISP
, SW
): /* Register indirect w/displacement, word. */
1713 t
= GET_L_REG (rn
) + abs
;
1714 t
&= h8_get_mask (sd
);
1715 SET_MEMORY_W (t
, n
);
1718 case X (OP_DISP
, SL
): /* Register indirect w/displacement, long. */
1719 t
= GET_L_REG (rn
) + abs
;
1720 t
&= h8_get_mask (sd
);
1721 SET_MEMORY_L (t
, n
);
1725 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1726 case X (OP_MEM
, SW
): /* Why isn't this implemented? */
1727 case X (OP_MEM
, SL
): /* Why isn't this implemented? */
1729 sim_engine_set_run_state (sd
, sim_stopped
, SIGSEGV
);
1738 store (SIM_DESC sd
, ea_type
*arg
, int n
)
1740 return store_1 (sd
, arg
, n
, 0);
1743 /* Store which follows a fetch from the same location.
1744 The difference being that we don't want to do a pre-increment
1745 or pre-decrement at this time: it was already done when we fetched. */
1748 store2 (SIM_DESC sd
, ea_type
*arg
, int n
)
1750 return store_1 (sd
, arg
, n
, 1);
1753 /* Flag to be set whenever a new SIM_DESC object is created. */
1754 static int init_pointers_needed
= 1;
1757 init_pointers (SIM_DESC sd
)
1759 if (init_pointers_needed
)
1763 if (h8300smode
&& !h8300_normal_mode
)
1764 memory_size
= H8300S_MSIZE
;
1765 else if (h8300hmode
&& !h8300_normal_mode
)
1766 memory_size
= H8300H_MSIZE
;
1768 memory_size
= H8300_MSIZE
;
1769 /* `msize' must be a power of two. */
1770 if ((memory_size
& (memory_size
- 1)) != 0)
1772 (*sim_callback
->printf_filtered
)
1774 "init_pointers: bad memory size %d, defaulting to %d.\n",
1775 memory_size
, memory_size
= H8300S_MSIZE
);
1778 if (h8_get_memory_buf (sd
))
1779 free (h8_get_memory_buf (sd
));
1780 if (h8_get_cache_idx_buf (sd
))
1781 free (h8_get_cache_idx_buf (sd
));
1782 if (h8_get_eightbit_buf (sd
))
1783 free (h8_get_eightbit_buf (sd
));
1785 h8_set_memory_buf (sd
, (unsigned char *)
1786 calloc (sizeof (char), memory_size
));
1787 h8_set_cache_idx_buf (sd
, (unsigned short *)
1788 calloc (sizeof (short), memory_size
));
1789 sd
->memory_size
= memory_size
;
1790 h8_set_eightbit_buf (sd
, (unsigned char *) calloc (sizeof (char), 256));
1792 h8_set_mask (sd
, memory_size
- 1);
1794 memset (h8_get_reg_buf (sd
), 0, sizeof (((STATE_CPU (sd
, 0))->regs
)));
1796 for (i
= 0; i
< 8; i
++)
1798 /* FIXME: rewrite using local buffer. */
1799 unsigned char *p
= (unsigned char *) (h8_get_reg_buf (sd
) + i
);
1800 unsigned char *e
= (unsigned char *) (h8_get_reg_buf (sd
) + i
+ 1);
1801 unsigned short *q
= (unsigned short *) (h8_get_reg_buf (sd
) + i
);
1802 unsigned short *u
= (unsigned short *) (h8_get_reg_buf (sd
) + i
+ 1);
1803 h8_set_reg (sd
, i
, 0x00112233);
1818 wreg
[i
] = wreg
[i
+ 8] = 0;
1832 if (wreg
[i
] == 0 || wreg
[i
+ 8] == 0)
1833 (*sim_callback
->printf_filtered
) (sim_callback
,
1834 "init_pointers: internal error.\n");
1836 h8_set_reg (sd
, i
, 0);
1837 lreg
[i
] = h8_get_reg_buf (sd
) + i
;
1840 /* Note: sim uses pseudo-register ZERO as a zero register. */
1841 lreg
[ZERO_REGNUM
] = h8_get_reg_buf (sd
) + ZERO_REGNUM
;
1842 init_pointers_needed
= 0;
1844 /* Initialize the seg registers. */
1846 set_simcache_size (sd
, CSIZE
);
1851 sim_stop (SIM_DESC sd
)
1853 /* FIXME: use a real signal value. */
1854 sim_engine_set_run_state (sd
, sim_stopped
, SIGINT
);
1858 #define OBITOP(name, f, s, op) \
1859 case O (name, SB): \
1864 if (fetch (sd, &code->dst, &ea)) \
1866 if (fetch (sd, &code->src, &tmp)) \
1868 m = 1 << (tmp & 7); \
1871 if (store (sd, &code->dst,ea)) \
1877 sim_resume (SIM_DESC sd
, int step
, int siggnal
)
1882 int tick_start
= get_now ();
1890 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
1893 enum sim_stop reason
;
1900 sim_engine_set_run_state (sd
, sim_stopped
, SIGTRAP
);
1904 sim_engine_set_run_state (sd
, sim_running
, 0);
1907 pc
= h8_get_pc (sd
);
1909 /* The PC should never be odd. */
1912 sim_engine_set_run_state (sd
, sim_stopped
, SIGBUS
);
1916 /* Get Status Register (flags). */
1919 if (h8300smode
) /* Get exr. */
1921 trace
= (h8_get_exr (sd
) >> 7) & 1;
1922 intMask
= h8_get_exr (sd
) & 7;
1925 oldmask
= h8_get_mask (sd
);
1926 if (!h8300hmode
|| h8300_normal_mode
)
1927 h8_set_mask (sd
, 0xffff);
1930 unsigned short cidx
;
1934 cidx
= h8_get_cache_idx (sd
, pc
);
1935 if (cidx
== (unsigned short) -1 ||
1936 cidx
>= sd
->sim_cache_size
)
1939 code
= sd
->sim_cache
+ cidx
;
1944 printf ("%x %d %s\n", pc
, code
->opcode
,
1945 code
->op
? code
->op
->name
: "**");
1947 h8_increment_stats (sd
, code
->opcode
);
1952 cycles
+= code
->cycles
;
1956 switch (code
->opcode
)
1960 * This opcode is a fake for when we get to an
1961 * instruction which hasnt been compiled
1967 case O (O_MOVAB
, SL
):
1968 case O (O_MOVAW
, SL
):
1969 case O (O_MOVAL
, SL
):
1970 /* 1) Evaluate 2nd argument (dst).
1971 2) Mask / zero extend according to whether 1st argument (src)
1972 is INDEXB, INDEXW, or INDEXL.
1973 3) Left-shift the result by 0, 1 or 2, according to size of mova
1974 (mova/b, mova/w, mova/l).
1975 4) Add literal value of 1st argument (src).
1976 5) Store result in 3rd argument (op3).
1979 /* Alas, since this is the only instruction with 3 arguments,
1980 decode doesn't handle them very well. Some fix-up is required.
1982 a) The size of dst is determined by whether src is
1983 INDEXB or INDEXW. */
1985 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1986 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SB
);
1987 else if (OP_KIND (code
->src
.type
) == OP_INDEXW
)
1988 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SW
);
1990 /* b) If op3 == null, then this is the short form of the insn.
1991 Dst is the dispreg of src, and op3 is the 32-bit form
1992 of the same register.
1995 if (code
->op3
.type
== 0)
1997 /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
1998 We get to compose dst and op3 as follows:
2000 op3 is a 32-bit register, ID == src.reg.
2001 dst is the same register, but 8 or 16 bits
2002 depending on whether src is INDEXB or INDEXW.
2005 code
->op3
.type
= X (OP_REG
, SL
);
2006 code
->op3
.reg
= code
->src
.reg
;
2007 code
->op3
.literal
= 0;
2009 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
2011 code
->dst
.type
= X (OP_REG
, SB
);
2012 code
->dst
.reg
= code
->op3
.reg
+ 8;
2015 code
->dst
.type
= X (OP_REG
, SW
);
2018 if (fetch (sd
, &code
->dst
, &ea
))
2021 switch (OP_KIND (code
->src
.type
)) {
2022 case OP_INDEXB
: ea
= ea
& 0xff; break;
2023 case OP_INDEXW
: ea
= ea
& 0xffff; break;
2024 case OP_INDEXL
: break;
2025 default: goto illegal
;
2028 switch (code
->opcode
) {
2029 case O (O_MOVAB
, SL
): break;
2030 case O (O_MOVAW
, SL
): ea
= ea
<< 1; break;
2031 case O (O_MOVAL
, SL
): ea
= ea
<< 2; break;
2032 default: goto illegal
;
2035 ea
= ea
+ code
->src
.literal
;
2037 if (store (sd
, &code
->op3
, ea
))
2042 case O (O_SUBX
, SB
): /* subx, extended sub */
2043 if (fetch2 (sd
, &code
->dst
, &rd
))
2045 if (fetch (sd
, &code
->src
, &ea
))
2051 case O (O_SUBX
, SW
): /* subx, extended sub */
2052 if (fetch2 (sd
, &code
->dst
, &rd
))
2054 if (fetch (sd
, &code
->src
, &ea
))
2060 case O (O_SUBX
, SL
): /* subx, extended sub */
2061 if (fetch2 (sd
, &code
->dst
, &rd
))
2063 if (fetch (sd
, &code
->src
, &ea
))
2069 case O (O_ADDX
, SB
): /* addx, extended add */
2070 if (fetch2 (sd
, &code
->dst
, &rd
))
2072 if (fetch (sd
, &code
->src
, &ea
))
2078 case O (O_ADDX
, SW
): /* addx, extended add */
2079 if (fetch2 (sd
, &code
->dst
, &rd
))
2081 if (fetch (sd
, &code
->src
, &ea
))
2087 case O (O_ADDX
, SL
): /* addx, extended add */
2088 if (fetch2 (sd
, &code
->dst
, &rd
))
2090 if (fetch (sd
, &code
->src
, &ea
))
2096 case O (O_SUB
, SB
): /* sub.b */
2097 /* Fetch rd and ea. */
2098 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2104 case O (O_SUB
, SW
): /* sub.w */
2105 /* Fetch rd and ea. */
2106 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2112 case O (O_SUB
, SL
): /* sub.l */
2113 /* Fetch rd and ea. */
2114 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2120 case O (O_NEG
, SB
): /* neg.b */
2122 if (fetch2 (sd
, &code
->src
, &ea
))
2129 case O (O_NEG
, SW
): /* neg.w */
2131 if (fetch2 (sd
, &code
->src
, &ea
))
2138 case O (O_NEG
, SL
): /* neg.l */
2140 if (fetch2 (sd
, &code
->src
, &ea
))
2147 case O (O_ADD
, SB
): /* add.b */
2148 if (fetch2 (sd
, &code
->dst
, &rd
))
2150 if (fetch (sd
, &code
->src
, &ea
))
2155 case O (O_ADD
, SW
): /* add.w */
2156 if (fetch2 (sd
, &code
->dst
, &rd
))
2158 if (fetch (sd
, &code
->src
, &ea
))
2163 case O (O_ADD
, SL
): /* add.l */
2164 if (fetch2 (sd
, &code
->dst
, &rd
))
2166 if (fetch (sd
, &code
->src
, &ea
))
2171 case O (O_AND
, SB
): /* and.b */
2172 /* Fetch rd and ea. */
2173 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2178 case O (O_AND
, SW
): /* and.w */
2179 /* Fetch rd and ea. */
2180 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2185 case O (O_AND
, SL
): /* and.l */
2186 /* Fetch rd and ea. */
2187 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2192 case O (O_OR
, SB
): /* or.b */
2193 /* Fetch rd and ea. */
2194 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2199 case O (O_OR
, SW
): /* or.w */
2200 /* Fetch rd and ea. */
2201 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2206 case O (O_OR
, SL
): /* or.l */
2207 /* Fetch rd and ea. */
2208 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2213 case O (O_XOR
, SB
): /* xor.b */
2214 /* Fetch rd and ea. */
2215 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2220 case O (O_XOR
, SW
): /* xor.w */
2221 /* Fetch rd and ea. */
2222 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2227 case O (O_XOR
, SL
): /* xor.l */
2228 /* Fetch rd and ea. */
2229 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2235 if (fetch (sd
, &code
->src
, &res
))
2237 if (store (sd
, &code
->dst
, res
))
2239 goto just_flags_log8
;
2241 if (fetch (sd
, &code
->src
, &res
))
2243 if (store (sd
, &code
->dst
, res
))
2245 goto just_flags_log16
;
2247 if (fetch (sd
, &code
->src
, &res
))
2249 if (store (sd
, &code
->dst
, res
))
2251 goto just_flags_log32
;
2253 case O (O_MOVMD
, SB
): /* movmd.b */
2260 rd
= GET_MEMORY_B (GET_L_REG (5));
2261 SET_MEMORY_B (GET_L_REG (6), rd
);
2262 SET_L_REG (5, GET_L_REG (5) + 1);
2263 SET_L_REG (6, GET_L_REG (6) + 1);
2268 case O (O_MOVMD
, SW
): /* movmd.w */
2275 rd
= GET_MEMORY_W (GET_L_REG (5));
2276 SET_MEMORY_W (GET_L_REG (6), rd
);
2277 SET_L_REG (5, GET_L_REG (5) + 2);
2278 SET_L_REG (6, GET_L_REG (6) + 2);
2283 case O (O_MOVMD
, SL
): /* movmd.l */
2290 rd
= GET_MEMORY_L (GET_L_REG (5));
2291 SET_MEMORY_L (GET_L_REG (6), rd
);
2292 SET_L_REG (5, GET_L_REG (5) + 4);
2293 SET_L_REG (6, GET_L_REG (6) + 4);
2298 case O (O_MOVSD
, SB
): /* movsd.b */
2299 /* This instruction implements strncpy, with a conditional branch.
2300 r4 contains n, r5 contains src, and r6 contains dst.
2301 The 16-bit displacement operand is added to the pc
2302 if and only if the end of string is reached before
2303 n bytes are transferred. */
2305 ea
= GET_L_REG (4) & 0xffff;
2311 rd
= GET_MEMORY_B (GET_L_REG (5));
2312 SET_MEMORY_B (GET_L_REG (6), rd
);
2313 SET_L_REG (5, GET_L_REG (5) + 1);
2314 SET_L_REG (6, GET_L_REG (6) + 1);
2321 case O (O_EEPMOV
, SB
): /* eepmov.b */
2322 case O (O_EEPMOV
, SW
): /* eepmov.w */
2323 if (h8300hmode
|| h8300smode
)
2325 register unsigned char *_src
, *_dst
;
2326 unsigned int count
= ((code
->opcode
== O (O_EEPMOV
, SW
))
2327 ? h8_get_reg (sd
, R4_REGNUM
) & 0xffff
2328 : h8_get_reg (sd
, R4_REGNUM
) & 0xff);
2330 _src
= (h8_get_reg (sd
, R5_REGNUM
) < memory_size
2331 ? h8_get_memory_buf (sd
) + h8_get_reg (sd
, R5_REGNUM
)
2332 : h8_get_eightbit_buf (sd
) +
2333 (h8_get_reg (sd
, R5_REGNUM
) & 0xff));
2334 if ((_src
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2336 if ((_src
+ count
) >= (h8_get_eightbit_buf (sd
) + 0x100))
2339 _dst
= (h8_get_reg (sd
, R6_REGNUM
) < memory_size
2340 ? h8_get_memory_buf (sd
) + h8_get_reg (sd
, R6_REGNUM
)
2341 : h8_get_eightbit_buf (sd
) +
2342 (h8_get_reg (sd
, R6_REGNUM
) & 0xff));
2344 if ((_dst
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2346 if ((_dst
+ count
) >= (h8_get_eightbit_buf (sd
) + 0x100))
2349 memcpy (_dst
, _src
, count
);
2351 h8_set_reg (sd
, R5_REGNUM
, h8_get_reg (sd
, R5_REGNUM
) + count
);
2352 h8_set_reg (sd
, R6_REGNUM
, h8_get_reg (sd
, R6_REGNUM
) + count
);
2353 h8_set_reg (sd
, R4_REGNUM
, h8_get_reg (sd
, R4_REGNUM
) &
2354 ((code
->opcode
== O (O_EEPMOV
, SW
))
2355 ? (~0xffff) : (~0xff)));
2356 cycles
+= 2 * count
;
2361 case O (O_ADDS
, SL
): /* adds (.l) */
2363 * This insn only uses register operands, but still
2364 * it would be cleaner to use fetch and store... */
2365 SET_L_REG (code
->dst
.reg
,
2366 GET_L_REG (code
->dst
.reg
)
2367 + code
->src
.literal
);
2371 case O (O_SUBS
, SL
): /* subs (.l) */
2373 * This insn only uses register operands, but still
2374 * it would be cleaner to use fetch and store... */
2375 SET_L_REG (code
->dst
.reg
,
2376 GET_L_REG (code
->dst
.reg
)
2377 - code
->src
.literal
);
2380 case O (O_CMP
, SB
): /* cmp.b */
2381 if (fetch (sd
, &code
->dst
, &rd
))
2383 if (fetch (sd
, &code
->src
, &ea
))
2387 goto just_flags_alu8
;
2389 case O (O_CMP
, SW
): /* cmp.w */
2390 if (fetch (sd
, &code
->dst
, &rd
))
2392 if (fetch (sd
, &code
->src
, &ea
))
2396 goto just_flags_alu16
;
2398 case O (O_CMP
, SL
): /* cmp.l */
2399 if (fetch (sd
, &code
->dst
, &rd
))
2401 if (fetch (sd
, &code
->src
, &ea
))
2405 goto just_flags_alu32
;
2407 case O (O_DEC
, SB
): /* dec.b */
2409 * This insn only uses register operands, but still
2410 * it would be cleaner to use fetch and store... */
2411 rd
= GET_B_REG (code
->src
.reg
);
2414 SET_B_REG (code
->src
.reg
, res
);
2415 goto just_flags_inc8
;
2417 case O (O_DEC
, SW
): /* dec.w */
2419 * This insn only uses register operands, but still
2420 * it would be cleaner to use fetch and store... */
2421 rd
= GET_W_REG (code
->dst
.reg
);
2422 ea
= -code
->src
.literal
;
2424 SET_W_REG (code
->dst
.reg
, res
);
2425 goto just_flags_inc16
;
2427 case O (O_DEC
, SL
): /* dec.l */
2429 * This insn only uses register operands, but still
2430 * it would be cleaner to use fetch and store... */
2431 rd
= GET_L_REG (code
->dst
.reg
);
2432 ea
= -code
->src
.literal
;
2434 SET_L_REG (code
->dst
.reg
, res
);
2435 goto just_flags_inc32
;
2437 case O (O_INC
, SB
): /* inc.b */
2439 * This insn only uses register operands, but still
2440 * it would be cleaner to use fetch and store... */
2441 rd
= GET_B_REG (code
->src
.reg
);
2444 SET_B_REG (code
->src
.reg
, res
);
2445 goto just_flags_inc8
;
2447 case O (O_INC
, SW
): /* inc.w */
2449 * This insn only uses register operands, but still
2450 * it would be cleaner to use fetch and store... */
2451 rd
= GET_W_REG (code
->dst
.reg
);
2452 ea
= code
->src
.literal
;
2454 SET_W_REG (code
->dst
.reg
, res
);
2455 goto just_flags_inc16
;
2457 case O (O_INC
, SL
): /* inc.l */
2459 * This insn only uses register operands, but still
2460 * it would be cleaner to use fetch and store... */
2461 rd
= GET_L_REG (code
->dst
.reg
);
2462 ea
= code
->src
.literal
;
2464 SET_L_REG (code
->dst
.reg
, res
);
2465 goto just_flags_inc32
;
2467 case O (O_LDC
, SB
): /* ldc.b */
2468 if (fetch (sd
, &code
->src
, &res
))
2472 case O (O_LDC
, SW
): /* ldc.w */
2473 if (fetch (sd
, &code
->src
, &res
))
2476 /* Word operand, value from MSB, must be shifted. */
2480 case O (O_LDC
, SL
): /* ldc.l */
2481 if (fetch (sd
, &code
->src
, &res
))
2483 switch (code
->dst
.type
) {
2484 case X (OP_SBR
, SL
):
2485 h8_set_sbr (sd
, res
);
2487 case X (OP_VBR
, SL
):
2488 h8_set_vbr (sd
, res
);
2495 case O (O_STC
, SW
): /* stc.w */
2496 case O (O_STC
, SB
): /* stc.b */
2497 if (code
->src
.type
== X (OP_CCR
, SB
))
2500 res
= h8_get_ccr (sd
);
2502 else if (code
->src
.type
== X (OP_EXR
, SB
) && h8300smode
)
2505 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2506 res
= h8_get_exr (sd
);
2511 /* Word operand, value to MSB, must be shifted. */
2512 if (code
->opcode
== X (O_STC
, SW
))
2514 if (store (sd
, &code
->dst
, res
))
2517 case O (O_STC
, SL
): /* stc.l */
2518 switch (code
->src
.type
) {
2519 case X (OP_SBR
, SL
):
2520 res
= h8_get_sbr (sd
);
2522 case X (OP_VBR
, SL
):
2523 res
= h8_get_vbr (sd
);
2528 if (store (sd
, &code
->dst
, res
))
2532 case O (O_ANDC
, SB
): /* andc.b */
2533 if (code
->dst
.type
== X (OP_CCR
, SB
))
2536 rd
= h8_get_ccr (sd
);
2538 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2541 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2542 rd
= h8_get_exr (sd
);
2546 ea
= code
->src
.literal
;
2550 case O (O_ORC
, SB
): /* orc.b */
2551 if (code
->dst
.type
== X (OP_CCR
, SB
))
2554 rd
= h8_get_ccr (sd
);
2556 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2559 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2560 rd
= h8_get_exr (sd
);
2564 ea
= code
->src
.literal
;
2568 case O (O_XORC
, SB
): /* xorc.b */
2569 if (code
->dst
.type
== X (OP_CCR
, SB
))
2572 rd
= h8_get_ccr (sd
);
2574 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2577 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2578 rd
= h8_get_exr (sd
);
2582 ea
= code
->src
.literal
;
2586 case O (O_BRAS
, SB
): /* bra/s */
2587 /* This is basically an ordinary branch, with a delay slot. */
2588 if (fetch (sd
, &code
->src
, &res
))
2596 /* Execution continues at next instruction, but
2597 delayed_branch is set up for next cycle. */
2598 h8_set_delayed_branch (sd
, code
->next_pc
+ res
);
2602 case O (O_BRAB
, SB
): /* bra rd.b */
2603 case O (O_BRAW
, SW
): /* bra rd.w */
2604 case O (O_BRAL
, SL
): /* bra erd.l */
2605 if (fetch (sd
, &code
->src
, &rd
))
2607 switch (OP_SIZE (code
->opcode
)) {
2608 case SB
: rd
&= 0xff; break;
2609 case SW
: rd
&= 0xffff; break;
2610 case SL
: rd
&= 0xffffffff; break;
2612 pc
= code
->next_pc
+ rd
;
2615 case O (O_BRABC
, SB
): /* bra/bc, branch if bit clear */
2616 case O (O_BRABS
, SB
): /* bra/bs, branch if bit set */
2617 case O (O_BSRBC
, SB
): /* bsr/bc, call if bit clear */
2618 case O (O_BSRBS
, SB
): /* bsr/bs, call if bit set */
2619 if (fetch (sd
, &code
->dst
, &rd
) ||
2620 fetch (sd
, &code
->src
, &bit
))
2623 if (code
->opcode
== O (O_BRABC
, SB
) || /* branch if clear */
2624 code
->opcode
== O (O_BSRBC
, SB
)) /* call if clear */
2626 if ((rd
& (1 << bit
))) /* no branch */
2629 else /* branch/call if set */
2631 if (!(rd
& (1 << bit
))) /* no branch */
2635 if (fetch (sd
, &code
->op3
, &res
)) /* branch */
2637 pc
= code
->next_pc
+ res
;
2639 if (code
->opcode
== O (O_BRABC
, SB
) ||
2640 code
->opcode
== O (O_BRABS
, SB
)) /* branch */
2648 case O (O_BRA
, SB
): /* bra, branch always */
2653 case O (O_BRN
, SB
): /* brn, ;-/ branch never? */
2658 case O (O_BHI
, SB
): /* bhi */
2664 case O (O_BLS
, SB
): /* bls */
2669 case O (O_BCS
, SB
): /* bcs, branch if carry set */
2674 case O (O_BCC
, SB
): /* bcc, branch if carry clear */
2679 case O (O_BEQ
, SB
): /* beq, branch if zero set */
2683 case O (O_BGT
, SB
): /* bgt */
2684 if (((Z
|| (N
^ V
)) == 0))
2688 case O (O_BLE
, SB
): /* ble */
2689 if (((Z
|| (N
^ V
)) == 1))
2693 case O (O_BGE
, SB
): /* bge */
2697 case O (O_BLT
, SB
): /* blt */
2701 case O (O_BMI
, SB
): /* bmi */
2705 case O (O_BNE
, SB
): /* bne, branch if zero clear */
2710 case O (O_BPL
, SB
): /* bpl */
2714 case O (O_BVC
, SB
): /* bvc */
2718 case O (O_BVS
, SB
): /* bvs */
2723 /* Trap for Command Line setup. */
2724 case O (O_SYS_CMDLINE
, SB
):
2726 int i
= 0; /* Loop counter. */
2727 int j
= 0; /* Loop counter. */
2728 int ind_arg_len
= 0; /* Length of each argument. */
2729 int no_of_args
= 0; /* The no. or cmdline args. */
2730 int current_location
= 0; /* Location of string. */
2731 int old_sp
= 0; /* The Initial Stack Pointer. */
2732 int no_of_slots
= 0; /* No. of slots required on the stack
2733 for storing cmdline args. */
2734 int sp_move
= 0; /* No. of locations by which the stack needs
2736 int new_sp
= 0; /* The final stack pointer location passed
2738 int *argv_ptrs
; /* Pointers of argv strings to be stored. */
2739 int argv_ptrs_location
= 0; /* Location of pointers to cmdline
2740 args on the stack. */
2741 int char_ptr_size
= 0; /* Size of a character pointer on
2743 int addr_cmdline
= 0; /* Memory location where cmdline has
2745 int size_cmdline
= 0; /* Size of cmdline. */
2747 /* Set the address of 256 free locations where command line is
2749 addr_cmdline
= cmdline_location();
2750 h8_set_reg (sd
, 0, addr_cmdline
);
2752 /* Counting the no. of commandline arguments. */
2753 for (i
= 0; h8_get_cmdline_arg (sd
, i
) != NULL
; i
++)
2756 /* No. of arguments in the command line. */
2759 /* Current location is just a temporary variable,which we are
2760 setting to the point to the start of our commandline string. */
2761 current_location
= addr_cmdline
;
2763 /* Allocating space for storing pointers of the command line
2765 argv_ptrs
= (int *) malloc (sizeof (int) * no_of_args
);
2767 /* Setting char_ptr_size to the sizeof (char *) on the different
2769 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2778 for (i
= 0; i
< no_of_args
; i
++)
2782 /* The size of the commandline argument. */
2783 ind_arg_len
= strlen (h8_get_cmdline_arg (sd
, i
)) + 1;
2785 /* The total size of the command line string. */
2786 size_cmdline
+= ind_arg_len
;
2788 /* As we have only 256 bytes, we need to provide a graceful
2789 exit. Anyways, a program using command line arguments
2790 where we cannot store all the command line arguments
2791 given may behave unpredictably. */
2792 if (size_cmdline
>= 256)
2794 h8_set_reg (sd
, 0, 0);
2799 /* current_location points to the memory where the next
2800 commandline argument is stored. */
2801 argv_ptrs
[i
] = current_location
;
2802 for (j
= 0; j
< ind_arg_len
; j
++)
2804 SET_MEMORY_B ((current_location
+
2805 (sizeof (char) * j
)),
2806 *(h8_get_cmdline_arg (sd
, i
) +
2807 sizeof (char) * j
));
2810 /* Setting current_location to the starting of next
2812 current_location
+= ind_arg_len
;
2816 /* This is the original position of the stack pointer. */
2817 old_sp
= h8_get_reg (sd
, SP_REGNUM
);
2819 /* We need space from the stack to store the pointers to argvs. */
2820 /* As we will infringe on the stack, we need to shift the stack
2821 pointer so that the data is not overwritten. We calculate how
2822 much space is required. */
2823 sp_move
= (no_of_args
) * (char_ptr_size
);
2825 /* The final position of stack pointer, we have thus taken some
2826 space from the stack. */
2827 new_sp
= old_sp
- sp_move
;
2829 /* Temporary variable holding value where the argv pointers need
2831 argv_ptrs_location
= new_sp
;
2833 /* The argv pointers are stored at sequential locations. As per
2835 for (i
= 0; i
< no_of_args
; i
++)
2837 /* Saving the argv pointer. */
2838 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2840 SET_MEMORY_L (argv_ptrs_location
, argv_ptrs
[i
]);
2844 SET_MEMORY_W (argv_ptrs_location
, argv_ptrs
[i
]);
2847 /* The next location where the pointer to the next argv
2848 string has to be stored. */
2849 argv_ptrs_location
+= char_ptr_size
;
2852 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2854 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2856 SET_MEMORY_L (old_sp
, 0x0);
2860 SET_MEMORY_W (old_sp
, 0x0);
2863 /* Freeing allocated memory. */
2865 for (i
= 0; i
<= no_of_args
; i
++)
2867 free (h8_get_cmdline_arg (sd
, i
));
2869 free (h8_get_command_line (sd
));
2871 /* The no. of argv arguments are returned in Reg 0. */
2872 h8_set_reg (sd
, 0, no_of_args
);
2873 /* The Pointer to argv in Register 1. */
2874 h8_set_reg (sd
, 1, new_sp
);
2875 /* Setting the stack pointer to the new value. */
2876 h8_set_reg (sd
, SP_REGNUM
, new_sp
);
2880 /* System call processing starts. */
2881 case O (O_SYS_OPEN
, SB
):
2883 int len
= 0; /* Length of filename. */
2884 char *filename
; /* Filename would go here. */
2885 char temp_char
; /* Temporary character */
2886 int mode
= 0; /* Mode bits for the file. */
2887 int open_return
; /* Return value of open, file descriptor. */
2888 int i
; /* Loop counter */
2889 int filename_ptr
; /* Pointer to filename in cpu memory. */
2891 /* Setting filename_ptr to first argument of open, */
2892 /* and trying to get mode. */
2893 if ((h8300sxmode
|| h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2895 filename_ptr
= GET_L_REG (0);
2896 mode
= GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
) + 4);
2900 filename_ptr
= GET_W_REG (0);
2901 mode
= GET_MEMORY_W (h8_get_reg (sd
, SP_REGNUM
) + 2);
2904 /* Trying to find the length of the filename. */
2905 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2908 while (temp_char
!= '\0')
2910 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2914 /* Allocating space for the filename. */
2915 filename
= (char *) malloc (sizeof (char) * len
);
2917 /* String copying the filename from memory. */
2918 for (i
= 0; i
< len
; i
++)
2920 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2921 filename
[i
] = temp_char
;
2924 /* Callback to open and return the file descriptor. */
2925 open_return
= sim_callback
->open (sim_callback
, filename
, mode
);
2927 /* Return value in register 0. */
2928 h8_set_reg (sd
, 0, open_return
);
2930 /* Freeing memory used for filename. */
2935 case O (O_SYS_READ
, SB
):
2937 char *char_ptr
; /* Where characters read would be stored. */
2938 int fd
; /* File descriptor */
2939 int buf_size
; /* BUF_SIZE parameter in read. */
2940 int i
= 0; /* Temporary Loop counter */
2941 int read_return
= 0; /* Return value from callback to
2944 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2945 buf_size
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2947 char_ptr
= (char *) malloc (sizeof (char) * buf_size
);
2949 /* Callback to read and return the no. of characters read. */
2951 sim_callback
->read (sim_callback
, fd
, char_ptr
, buf_size
);
2953 /* The characters read are stored in cpu memory. */
2954 for (i
= 0; i
< buf_size
; i
++)
2956 SET_MEMORY_B ((h8_get_reg (sd
, 1) + (sizeof (char) * i
)),
2957 *(char_ptr
+ (sizeof (char) * i
)));
2960 /* Return value in Register 0. */
2961 h8_set_reg (sd
, 0, read_return
);
2963 /* Freeing memory used as buffer. */
2968 case O (O_SYS_WRITE
, SB
):
2970 int fd
; /* File descriptor */
2971 char temp_char
; /* Temporary character */
2972 int len
; /* Length of write, Parameter II to write. */
2973 int char_ptr
; /* Character Pointer, Parameter I of write. */
2974 char *ptr
; /* Where characters to be written are stored.
2976 int write_return
; /* Return value from callback to write. */
2977 int i
= 0; /* Loop counter */
2979 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2980 char_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2981 len
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2983 /* Allocating space for the characters to be written. */
2984 ptr
= (char *) malloc (sizeof (char) * len
);
2986 /* Fetching the characters from cpu memory. */
2987 for (i
= 0; i
< len
; i
++)
2989 temp_char
= GET_MEMORY_B (char_ptr
+ i
);
2993 /* Callback write and return the no. of characters written. */
2994 write_return
= sim_callback
->write (sim_callback
, fd
, ptr
, len
);
2996 /* Return value in Register 0. */
2997 h8_set_reg (sd
, 0, write_return
);
2999 /* Freeing memory used as buffer. */
3004 case O (O_SYS_LSEEK
, SB
):
3006 int fd
; /* File descriptor */
3007 int offset
; /* Offset */
3008 int origin
; /* Origin */
3009 int lseek_return
; /* Return value from callback to lseek. */
3011 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
3012 offset
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
3013 origin
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
3015 /* Callback lseek and return offset. */
3017 sim_callback
->lseek (sim_callback
, fd
, offset
, origin
);
3019 /* Return value in register 0. */
3020 h8_set_reg (sd
, 0, lseek_return
);
3024 case O (O_SYS_CLOSE
, SB
):
3026 int fd
; /* File descriptor */
3027 int close_return
; /* Return value from callback to close. */
3029 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
3031 /* Callback close and return. */
3032 close_return
= sim_callback
->close (sim_callback
, fd
);
3034 /* Return value in register 0. */
3035 h8_set_reg (sd
, 0, close_return
);
3039 case O (O_SYS_FSTAT
, SB
):
3041 int fd
; /* File descriptor */
3042 struct stat stat_rec
; /* Stat record */
3043 int fstat_return
; /* Return value from callback to stat. */
3044 int stat_ptr
; /* Pointer to stat record. */
3045 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
3047 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
3049 /* Setting stat_ptr to second argument of stat. */
3050 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
3052 /* Callback stat and return. */
3053 fstat_return
= sim_callback
->to_fstat (sim_callback
, fd
,
3056 /* Have stat_ptr point to starting of stat_rec. */
3057 temp_stat_ptr
= (char *) (&stat_rec
);
3059 /* Setting up the stat structure returned. */
3060 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
3062 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
3064 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
3066 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
3068 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
3070 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
3072 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
3074 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
3076 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
3078 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
3080 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
3082 /* Return value in register 0. */
3083 h8_set_reg (sd
, 0, fstat_return
);
3087 case O (O_SYS_STAT
, SB
):
3089 int len
= 0; /* Length of filename. */
3090 char *filename
; /* Filename would go here. */
3091 char temp_char
; /* Temporary character */
3092 int filename_ptr
; /* Pointer to filename in cpu memory. */
3093 struct stat stat_rec
; /* Stat record */
3094 int stat_return
; /* Return value from callback to stat */
3095 int stat_ptr
; /* Pointer to stat record. */
3096 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
3097 int i
= 0; /* Loop Counter */
3099 /* Setting filename_ptr to first argument of open. */
3100 filename_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
3102 /* Trying to find the length of the filename. */
3103 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
3106 while (temp_char
!= '\0')
3108 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
3112 /* Allocating space for the filename. */
3113 filename
= (char *) malloc (sizeof (char) * len
);
3115 /* String copying the filename from memory. */
3116 for (i
= 0; i
< len
; i
++)
3118 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
3119 filename
[i
] = temp_char
;
3122 /* Setting stat_ptr to second argument of stat. */
3123 /* stat_ptr = h8_get_reg (sd, 1); */
3124 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
3126 /* Callback stat and return. */
3128 sim_callback
->to_stat (sim_callback
, filename
, &stat_rec
);
3130 /* Have stat_ptr point to starting of stat_rec. */
3131 temp_stat_ptr
= (char *) (&stat_rec
);
3133 /* Freeing memory used for filename. */
3136 /* Setting up the stat structure returned. */
3137 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
3139 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
3141 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
3143 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
3145 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
3147 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
3149 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
3151 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
3153 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
3155 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
3157 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
3159 /* Return value in register 0. */
3160 h8_set_reg (sd
, 0, stat_return
);
3163 /* End of system call processing. */
3165 case O (O_NOT
, SB
): /* not.b */
3166 if (fetch2 (sd
, &code
->src
, &rd
))
3172 case O (O_NOT
, SW
): /* not.w */
3173 if (fetch2 (sd
, &code
->src
, &rd
))
3179 case O (O_NOT
, SL
): /* not.l */
3180 if (fetch2 (sd
, &code
->src
, &rd
))
3186 case O (O_SHLL
, SB
): /* shll.b */
3187 case O (O_SHLR
, SB
): /* shlr.b */
3188 if (fetch2 (sd
, &code
->dst
, &rd
))
3191 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3192 ea
= 1; /* unary op */
3193 else /* binary op */
3194 fetch (sd
, &code
->src
, &ea
);
3196 if (code
->opcode
== O (O_SHLL
, SB
))
3199 c
= rd
& (0x80 >> (ea
- 1));
3205 c
= rd
& (1 << (ea
- 1));
3206 rd
= (unsigned char) rd
>> ea
;
3210 case O (O_SHLL
, SW
): /* shll.w */
3211 case O (O_SHLR
, SW
): /* shlr.w */
3212 if (fetch2 (sd
, &code
->dst
, &rd
))
3215 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3216 ea
= 1; /* unary op */
3218 fetch (sd
, &code
->src
, &ea
);
3220 if (code
->opcode
== O (O_SHLL
, SW
))
3223 c
= rd
& (0x8000 >> (ea
- 1));
3229 c
= rd
& (1 << (ea
- 1));
3230 rd
= (unsigned short) rd
>> ea
;
3234 case O (O_SHLL
, SL
): /* shll.l */
3235 case O (O_SHLR
, SL
): /* shlr.l */
3236 if (fetch2 (sd
, &code
->dst
, &rd
))
3239 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3240 ea
= 1; /* unary op */
3242 fetch (sd
, &code
->src
, &ea
);
3244 if (code
->opcode
== O (O_SHLL
, SL
))
3247 c
= rd
& (0x80000000 >> (ea
- 1));
3253 c
= rd
& (1 << (ea
- 1));
3254 rd
= (unsigned int) rd
>> ea
;
3258 case O (O_SHAL
, SB
):
3259 case O (O_SHAR
, SB
):
3260 if (fetch2 (sd
, &code
->dst
, &rd
))
3263 if (code
->src
.type
== X (OP_IMM
, SB
))
3264 fetch (sd
, &code
->src
, &ea
);
3268 if (code
->opcode
== O (O_SHAL
, SB
))
3270 c
= rd
& (0x80 >> (ea
- 1));
3271 res
= rd
>> (7 - ea
);
3272 v
= ((res
& 1) && !(res
& 2))
3273 || (!(res
& 1) && (res
& 2));
3278 c
= rd
& (1 << (ea
- 1));
3280 rd
= ((signed char) rd
) >> ea
;
3284 case O (O_SHAL
, SW
):
3285 case O (O_SHAR
, SW
):
3286 if (fetch2 (sd
, &code
->dst
, &rd
))
3289 if (code
->src
.type
== X (OP_IMM
, SW
))
3290 fetch (sd
, &code
->src
, &ea
);
3294 if (code
->opcode
== O (O_SHAL
, SW
))
3296 c
= rd
& (0x8000 >> (ea
- 1));
3297 res
= rd
>> (15 - ea
);
3298 v
= ((res
& 1) && !(res
& 2))
3299 || (!(res
& 1) && (res
& 2));
3304 c
= rd
& (1 << (ea
- 1));
3306 rd
= ((signed short) rd
) >> ea
;
3310 case O (O_SHAL
, SL
):
3311 case O (O_SHAR
, SL
):
3312 if (fetch2 (sd
, &code
->dst
, &rd
))
3315 if (code
->src
.type
== X (OP_IMM
, SL
))
3316 fetch (sd
, &code
->src
, &ea
);
3320 if (code
->opcode
== O (O_SHAL
, SL
))
3322 c
= rd
& (0x80000000 >> (ea
- 1));
3323 res
= rd
>> (31 - ea
);
3324 v
= ((res
& 1) && !(res
& 2))
3325 || (!(res
& 1) && (res
& 2));
3330 c
= rd
& (1 << (ea
- 1));
3332 rd
= ((signed int) rd
) >> ea
;
3336 case O (O_ROTL
, SB
):
3337 case O (O_ROTR
, SB
):
3338 if (fetch2 (sd
, &code
->dst
, &rd
))
3341 if (code
->src
.type
== X (OP_IMM
, SB
))
3342 fetch (sd
, &code
->src
, &ea
);
3347 if (code
->opcode
== O (O_ROTL
, SB
))
3357 rd
= ((unsigned char) rd
) >> 1;
3365 case O (O_ROTL
, SW
):
3366 case O (O_ROTR
, SW
):
3367 if (fetch2 (sd
, &code
->dst
, &rd
))
3370 if (code
->src
.type
== X (OP_IMM
, SW
))
3371 fetch (sd
, &code
->src
, &ea
);
3376 if (code
->opcode
== O (O_ROTL
, SW
))
3386 rd
= ((unsigned short) rd
) >> 1;
3394 case O (O_ROTL
, SL
):
3395 case O (O_ROTR
, SL
):
3396 if (fetch2 (sd
, &code
->dst
, &rd
))
3399 if (code
->src
.type
== X (OP_IMM
, SL
))
3400 fetch (sd
, &code
->src
, &ea
);
3405 if (code
->opcode
== O (O_ROTL
, SL
))
3407 c
= rd
& 0x80000000;
3415 rd
= ((unsigned int) rd
) >> 1;
3423 case O (O_ROTXL
, SB
):
3424 case O (O_ROTXR
, SB
):
3425 if (fetch2 (sd
, &code
->dst
, &rd
))
3428 if (code
->src
.type
== X (OP_IMM
, SB
))
3429 fetch (sd
, &code
->src
, &ea
);
3434 if (code
->opcode
== O (O_ROTXL
, SB
))
3445 rd
= ((unsigned char) rd
) >> 1;
3454 case O (O_ROTXL
, SW
):
3455 case O (O_ROTXR
, SW
):
3456 if (fetch2 (sd
, &code
->dst
, &rd
))
3459 if (code
->src
.type
== X (OP_IMM
, SW
))
3460 fetch (sd
, &code
->src
, &ea
);
3465 if (code
->opcode
== O (O_ROTXL
, SW
))
3476 rd
= ((unsigned short) rd
) >> 1;
3485 case O (O_ROTXL
, SL
):
3486 case O (O_ROTXR
, SL
):
3487 if (fetch2 (sd
, &code
->dst
, &rd
))
3490 if (code
->src
.type
== X (OP_IMM
, SL
))
3491 fetch (sd
, &code
->src
, &ea
);
3496 if (code
->opcode
== O (O_ROTXL
, SL
))
3498 res
= rd
& 0x80000000;
3507 rd
= ((unsigned int) rd
) >> 1;
3518 case O (O_JMP
, SB
): /* jmp */
3520 fetch (sd
, &code
->src
, &pc
);
3525 case O (O_JSR
, SB
): /* jsr, jump to subroutine */
3527 if (fetch (sd
, &code
->src
, &pc
))
3530 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3532 if (h8300hmode
&& !h8300_normal_mode
)
3535 SET_MEMORY_L (tmp
, code
->next_pc
);
3540 SET_MEMORY_W (tmp
, code
->next_pc
);
3542 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3548 case O (O_BSR
, SB
): /* bsr, branch to subroutine */
3549 if (fetch (sd
, &code
->src
, &res
))
3551 pc
= code
->next_pc
+ res
;
3554 case O (O_RTE
, SN
): /* rte, return from exception */
3556 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3557 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3559 if (h8300smode
) /* pop exr */
3561 h8_set_exr (sd
, GET_MEMORY_L (tmp
));
3564 if (h8300hmode
&& !h8300_normal_mode
)
3566 h8_set_ccr (sd
, GET_MEMORY_L (tmp
));
3568 pc
= GET_MEMORY_L (tmp
);
3573 h8_set_ccr (sd
, GET_MEMORY_W (tmp
));
3575 pc
= GET_MEMORY_W (tmp
);
3580 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3583 case O (O_RTS
, SN
): /* rts, return from subroutine */
3585 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3587 if (h8300hmode
&& !h8300_normal_mode
)
3589 pc
= GET_MEMORY_L (tmp
);
3594 pc
= GET_MEMORY_W (tmp
);
3598 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3601 case O (O_ILL
, SB
): /* illegal */
3602 sim_engine_set_run_state (sd
, sim_stopped
, SIGILL
);
3605 case O (O_SLEEP
, SN
): /* sleep */
3606 /* Check for magic numbers in r1 and r2. */
3607 if ((h8_get_reg (sd
, R1_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC1
&&
3608 (h8_get_reg (sd
, R2_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC2
&&
3609 SIM_WIFEXITED (h8_get_reg (sd
, 0)))
3611 /* This trap comes from _exit, not from gdb. */
3612 sim_engine_set_run_state (sd
, sim_exited
,
3613 SIM_WEXITSTATUS (h8_get_reg (sd
, 0)));
3616 /* Unfortunately this won't really work, because
3617 when we take a breakpoint trap, R0 has a "random",
3618 user-defined value. Don't see any immediate solution. */
3619 else if (SIM_WIFSTOPPED (h8_get_reg (sd
, 0)))
3621 /* Pass the stop signal up to gdb. */
3622 sim_engine_set_run_state (sd
, sim_stopped
,
3623 SIM_WSTOPSIG (h8_get_reg (sd
, 0)));
3628 /* Treat it as a sigtrap. */
3629 sim_engine_set_run_state (sd
, sim_stopped
, SIGTRAP
);
3633 case O (O_TRAPA
, SB
): /* trapa */
3634 if (fetch (sd
, &code
->src
, &res
))
3635 goto end
; /* res is vector number. */
3637 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3638 if(h8300_normal_mode
)
3641 SET_MEMORY_W (tmp
, code
->next_pc
);
3643 SET_MEMORY_W (tmp
, h8_get_ccr (sd
));
3648 SET_MEMORY_L (tmp
, code
->next_pc
);
3650 SET_MEMORY_L (tmp
, h8_get_ccr (sd
));
3658 SET_MEMORY_L (tmp
, h8_get_exr (sd
));
3661 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3663 if(h8300_normal_mode
)
3664 pc
= GET_MEMORY_L (0x10 + res
* 2); /* Vector addresses are 0x10,0x12,0x14 and 0x16 */
3666 pc
= GET_MEMORY_L (0x20 + res
* 4);
3670 sim_engine_set_run_state (sd
, sim_stopped
, SIGTRAP
);
3673 case O (O_BSETEQ
, SB
):
3678 case O (O_BSETNE
, SB
):
3683 case O (O_BCLREQ
, SB
):
3688 case O (O_BCLRNE
, SB
):
3693 OBITOP (O_BNOT
, 1, 1, ea
^= m
); /* bnot */
3694 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
); /* btst */
3696 OBITOP (O_BSET
, 1, 1, ea
|= m
); /* bset */
3698 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
); /* bclr */
3699 OBITOP (O_BLD
, 1, 0, c
= ea
& m
); /* bld */
3700 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
)); /* bild */
3701 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
3702 if (C
) ea
|= m
); /* bst */
3703 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
3704 if (!C
) ea
|= m
); /* bist */
3705 OBITOP (O_BSTZ
, 1, 1, ea
&= ~m
;
3706 if (Z
) ea
|= m
); /* bstz */
3707 OBITOP (O_BISTZ
, 1, 1, ea
&= ~m
;
3708 if (!Z
) ea
|= m
); /* bistz */
3709 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
); /* band */
3710 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
); /* biand */
3711 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
); /* bor */
3712 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
); /* bior */
3713 OBITOP (O_BXOR
, 1, 0, c
= ((ea
& m
) != 0)!= C
); /* bxor */
3714 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
); /* bixor */
3716 case O (O_BFLD
, SB
): /* bfld */
3719 if (fetch (sd
, &code
->src
, &bit
))
3724 if (fetch (sd
, &code
->dst
, &ea
))
3734 if (store (sd
, &code
->op3
, ea
))
3739 case O(O_BFST
, SB
): /* bfst */
3740 /* bitfield store */
3741 /* NOTE: the imm8 value is in dst, and the ea value
3742 (which is actually the destination) is in op3.
3743 It has to be that way, to avoid breaking the assembler. */
3745 if (fetch (sd
, &code
->dst
, &bit
)) /* imm8 */
3747 if (bit
== 0) /* noop -- nothing to do. */
3750 if (fetch (sd
, &code
->src
, &rd
)) /* reg8 src */
3753 if (fetch2 (sd
, &code
->op3
, &ea
)) /* ea dst */
3756 /* Left-shift the register data into position. */
3757 for (tmp
= bit
; !(tmp
& 1); tmp
>>= 1)
3760 /* Combine it with the neighboring bits. */
3761 ea
= (ea
& ~bit
) | (rd
& bit
);
3764 if (store2 (sd
, &code
->op3
, ea
))
3768 case O (O_CLRMAC
, SN
): /* clrmac */
3769 h8_set_mach (sd
, 0);
3770 h8_set_macl (sd
, 0);
3771 h8_set_macZ (sd
, 1);
3772 h8_set_macV (sd
, 0);
3773 h8_set_macN (sd
, 0);
3776 case O (O_STMAC
, SL
): /* stmac, 260 */
3777 switch (code
->src
.type
) {
3778 case X (OP_MACH
, SL
):
3779 res
= h8_get_mach (sd
);
3780 if (res
& 0x200) /* sign extend */
3783 case X (OP_MACL
, SL
):
3784 res
= h8_get_macl (sd
);
3786 default: goto illegal
;
3788 nz
= !h8_get_macZ (sd
);
3789 n
= h8_get_macN (sd
);
3790 v
= h8_get_macV (sd
);
3792 if (store (sd
, &code
->dst
, res
))
3797 case O (O_LDMAC
, SL
): /* ldmac, 179 */
3798 if (fetch (sd
, &code
->src
, &rd
))
3801 switch (code
->dst
.type
) {
3802 case X (OP_MACH
, SL
):
3803 rd
&= 0x3ff; /* Truncate to 10 bits */
3804 h8_set_mach (sd
, rd
);
3806 case X (OP_MACL
, SL
):
3807 h8_set_macl (sd
, rd
);
3809 default: goto illegal
;
3811 h8_set_macV (sd
, 0);
3815 if (fetch (sd
, &code
->src
, &rd
) ||
3816 fetch (sd
, &code
->dst
, &res
))
3819 /* Ye gods, this is non-portable!
3820 However, the existing mul/div code is similar. */
3821 res
= SEXTSHORT (res
) * SEXTSHORT (rd
);
3823 if (h8_get_macS (sd
)) /* Saturating mode */
3825 long long mac
= h8_get_macl (sd
);
3827 if (mac
& 0x80000000) /* sign extend */
3828 mac
|= 0xffffffff00000000LL
;
3831 if (mac
> 0x7fffffff || mac
< 0xffffffff80000000LL
)
3832 h8_set_macV (sd
, 1);
3833 h8_set_macZ (sd
, (mac
== 0));
3834 h8_set_macN (sd
, (mac
< 0));
3835 h8_set_macl (sd
, (int) mac
);
3837 else /* "Less Saturating" mode */
3839 long long mac
= h8_get_mach (sd
);
3841 mac
+= h8_get_macl (sd
);
3843 if (mac
& 0x20000000000LL
) /* sign extend */
3844 mac
|= 0xfffffc0000000000LL
;
3847 if (mac
> 0x1ffffffffffLL
||
3848 mac
< (long long) 0xfffffe0000000000LL
)
3849 h8_set_macV (sd
, 1);
3850 h8_set_macZ (sd
, (mac
== 0));
3851 h8_set_macN (sd
, (mac
< 0));
3852 h8_set_macl (sd
, (int) mac
);
3854 h8_set_mach (sd
, (int) (mac
& 0x3ff));
3858 case O (O_MULS
, SW
): /* muls.w */
3859 if (fetch (sd
, &code
->src
, &ea
) ||
3860 fetch (sd
, &code
->dst
, &rd
))
3863 ea
= SEXTSHORT (ea
);
3864 res
= SEXTSHORT (ea
* SEXTSHORT (rd
));
3868 if (store (sd
, &code
->dst
, res
))
3873 case O (O_MULS
, SL
): /* muls.l */
3874 if (fetch (sd
, &code
->src
, &ea
) ||
3875 fetch (sd
, &code
->dst
, &rd
))
3880 n
= res
& 0x80000000;
3881 nz
= res
& 0xffffffff;
3882 if (store (sd
, &code
->dst
, res
))
3886 case O (O_MULSU
, SL
): /* muls/u.l */
3887 if (fetch (sd
, &code
->src
, &ea
) ||
3888 fetch (sd
, &code
->dst
, &rd
))
3891 /* Compute upper 32 bits of the 64-bit result. */
3892 res
= (((long long) ea
) * ((long long) rd
)) >> 32;
3894 n
= res
& 0x80000000;
3895 nz
= res
& 0xffffffff;
3896 if (store (sd
, &code
->dst
, res
))
3900 case O (O_MULU
, SW
): /* mulu.w */
3901 if (fetch (sd
, &code
->src
, &ea
) ||
3902 fetch (sd
, &code
->dst
, &rd
))
3905 res
= UEXTSHORT ((UEXTSHORT (ea
) * UEXTSHORT (rd
)));
3907 /* Don't set Z or N. */
3908 if (store (sd
, &code
->dst
, res
))
3913 case O (O_MULU
, SL
): /* mulu.l */
3914 if (fetch (sd
, &code
->src
, &ea
) ||
3915 fetch (sd
, &code
->dst
, &rd
))
3920 /* Don't set Z or N. */
3921 if (store (sd
, &code
->dst
, res
))
3926 case O (O_MULUU
, SL
): /* mulu/u.l */
3927 if (fetch (sd
, &code
->src
, &ea
) ||
3928 fetch (sd
, &code
->dst
, &rd
))
3931 /* Compute upper 32 bits of the 64-bit result. */
3932 res
= (((unsigned long long) (unsigned) ea
) *
3933 ((unsigned long long) (unsigned) rd
)) >> 32;
3935 /* Don't set Z or N. */
3936 if (store (sd
, &code
->dst
, res
))
3941 case O (O_MULXS
, SB
): /* mulxs.b */
3942 if (fetch (sd
, &code
->src
, &ea
) ||
3943 fetch (sd
, &code
->dst
, &rd
))
3947 res
= ea
* SEXTCHAR (rd
);
3951 if (store (sd
, &code
->dst
, res
))
3956 case O (O_MULXS
, SW
): /* mulxs.w */
3957 if (fetch (sd
, &code
->src
, &ea
) ||
3958 fetch (sd
, &code
->dst
, &rd
))
3961 ea
= SEXTSHORT (ea
);
3962 res
= ea
* SEXTSHORT (rd
& 0xffff);
3964 n
= res
& 0x80000000;
3965 nz
= res
& 0xffffffff;
3966 if (store (sd
, &code
->dst
, res
))
3971 case O (O_MULXU
, SB
): /* mulxu.b */
3972 if (fetch (sd
, &code
->src
, &ea
) ||
3973 fetch (sd
, &code
->dst
, &rd
))
3976 res
= UEXTCHAR (ea
) * UEXTCHAR (rd
);
3978 if (store (sd
, &code
->dst
, res
))
3983 case O (O_MULXU
, SW
): /* mulxu.w */
3984 if (fetch (sd
, &code
->src
, &ea
) ||
3985 fetch (sd
, &code
->dst
, &rd
))
3988 res
= UEXTSHORT (ea
) * UEXTSHORT (rd
);
3990 if (store (sd
, &code
->dst
, res
))
3995 case O (O_TAS
, SB
): /* tas (test and set) */
3996 if (!h8300sxmode
) /* h8sx can use any register. */
3997 switch (code
->src
.reg
)
4008 if (fetch (sd
, &code
->src
, &res
))
4010 if (store (sd
, &code
->src
, res
| 0x80))
4013 goto just_flags_log8
;
4015 case O (O_DIVU
, SW
): /* divu.w */
4016 if (fetch (sd
, &code
->src
, &ea
) ||
4017 fetch (sd
, &code
->dst
, &rd
))
4023 res
= (unsigned) (UEXTSHORT (rd
) / UEXTSHORT (ea
));
4027 if (store (sd
, &code
->dst
, res
))
4031 case O (O_DIVU
, SL
): /* divu.l */
4032 if (fetch (sd
, &code
->src
, &ea
) ||
4033 fetch (sd
, &code
->dst
, &rd
))
4036 n
= ea
& 0x80000000;
4037 nz
= ea
& 0xffffffff;
4039 res
= (unsigned) rd
/ ea
;
4043 if (store (sd
, &code
->dst
, res
))
4047 case O (O_DIVS
, SW
): /* divs.w */
4048 if (fetch (sd
, &code
->src
, &ea
) ||
4049 fetch (sd
, &code
->dst
, &rd
))
4054 res
= SEXTSHORT (rd
) / SEXTSHORT (ea
);
4064 if (store (sd
, &code
->dst
, res
))
4068 case O (O_DIVS
, SL
): /* divs.l */
4069 if (fetch (sd
, &code
->src
, &ea
) ||
4070 fetch (sd
, &code
->dst
, &rd
))
4084 n
= res
& 0x80000000;
4085 if (store (sd
, &code
->dst
, res
))
4089 case O (O_DIVXU
, SB
): /* divxu.b */
4090 if (fetch (sd
, &code
->src
, &ea
) ||
4091 fetch (sd
, &code
->dst
, &rd
))
4094 rd
= UEXTSHORT (rd
);
4101 tmp
= (unsigned) rd
% ea
;
4102 res
= (unsigned) rd
/ ea
;
4110 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
4114 case O (O_DIVXU
, SW
): /* divxu.w */
4115 if (fetch (sd
, &code
->src
, &ea
) ||
4116 fetch (sd
, &code
->dst
, &rd
))
4119 ea
= UEXTSHORT (ea
);
4125 tmp
= (unsigned) rd
% ea
;
4126 res
= (unsigned) rd
/ ea
;
4134 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
4138 case O (O_DIVXS
, SB
): /* divxs.b */
4139 if (fetch (sd
, &code
->src
, &ea
) ||
4140 fetch (sd
, &code
->dst
, &rd
))
4143 rd
= SEXTSHORT (rd
);
4148 tmp
= (int) rd
% (int) ea
;
4149 res
= (int) rd
/ (int) ea
;
4160 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
4164 case O (O_DIVXS
, SW
): /* divxs.w */
4165 if (fetch (sd
, &code
->src
, &ea
) ||
4166 fetch (sd
, &code
->dst
, &rd
))
4169 ea
= SEXTSHORT (ea
);
4173 tmp
= (int) rd
% (int) ea
;
4174 res
= (int) rd
/ (int) ea
;
4184 n
= res
& 0x80000000;
4185 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
4189 case O (O_EXTS
, SW
): /* exts.w, signed extend */
4190 if (fetch2 (sd
, &code
->dst
, &rd
))
4192 ea
= rd
& 0x80 ? -256 : 0;
4193 res
= (rd
& 0xff) + ea
;
4196 case O (O_EXTS
, SL
): /* exts.l, signed extend */
4197 if (fetch2 (sd
, &code
->dst
, &rd
))
4199 if (code
->src
.type
== X (OP_IMM
, SL
))
4201 if (fetch (sd
, &code
->src
, &ea
))
4204 if (ea
== 2) /* exts.l #2, nn */
4206 /* Sign-extend from 8-bit to 32-bit. */
4207 ea
= rd
& 0x80 ? -256 : 0;
4208 res
= (rd
& 0xff) + ea
;
4212 /* Sign-extend from 16-bit to 32-bit. */
4213 ea
= rd
& 0x8000 ? -65536 : 0;
4214 res
= (rd
& 0xffff) + ea
;
4217 case O (O_EXTU
, SW
): /* extu.w, unsigned extend */
4218 if (fetch2 (sd
, &code
->dst
, &rd
))
4221 res
= (rd
& 0xff) + ea
;
4224 case O (O_EXTU
, SL
): /* extu.l, unsigned extend */
4225 if (fetch2 (sd
, &code
->dst
, &rd
))
4227 if (code
->src
.type
== X (OP_IMM
, SL
))
4229 if (fetch (sd
, &code
->src
, &ea
))
4232 if (ea
== 2) /* extu.l #2, nn */
4234 /* Zero-extend from 8-bit to 32-bit. */
4236 res
= (rd
& 0xff) + ea
;
4240 /* Zero-extend from 16-bit to 32-bit. */
4242 res
= (rd
& 0xffff) + ea
;
4245 case O (O_NOP
, SN
): /* nop */
4248 case O (O_STM
, SL
): /* stm, store to memory */
4250 int nregs
, firstreg
, i
;
4252 nregs
= GET_MEMORY_B (pc
+ 1);
4255 firstreg
= code
->src
.reg
;
4257 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
4259 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) - 4);
4260 SET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
), h8_get_reg (sd
, i
));
4265 case O (O_LDM
, SL
): /* ldm, load from memory */
4266 case O (O_RTEL
, SN
): /* rte/l, ldm plus rte */
4267 case O (O_RTSL
, SN
): /* rts/l, ldm plus rts */
4269 int nregs
, firstreg
, i
;
4271 nregs
= ((GET_MEMORY_B (pc
+ 1) >> 4) & 0xf);
4272 firstreg
= code
->dst
.reg
& 0xf;
4273 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
4275 h8_set_reg (sd
, i
, GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
)));
4276 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) + 4);
4279 switch (code
->opcode
) {
4280 case O (O_RTEL
, SN
):
4282 case O (O_RTSL
, SN
):
4291 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4292 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch? */
4293 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4294 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4295 res
= res
; /* Value added == 0. */
4296 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4297 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4298 res
= res
+ 0x6; /* Value added == 6. */
4299 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4300 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4301 res
= res
+ 0x6; /* Value added == 6. */
4302 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4303 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4304 res
= res
+ 0x60; /* Value added == 60. */
4305 else if (!c
&& (9 <= (res
>> 4) && (res
>> 4) <= 15) &&
4306 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4307 res
= res
+ 0x66; /* Value added == 66. */
4308 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4309 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4310 res
= res
+ 0x66; /* Value added == 66. */
4311 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4312 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4313 res
= res
+ 0x60; /* Value added == 60. */
4314 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4315 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4316 res
= res
+ 0x66; /* Value added == 66. */
4317 else if (c
&& (1 <= (res
>> 4) && (res
>> 4) <= 3) &&
4318 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4319 res
= res
+ 0x66; /* Value added == 66. */
4324 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4325 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch, fetch2... */
4326 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4327 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4328 res
= res
; /* Value added == 0. */
4329 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4330 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4331 res
= res
+ 0xfa; /* Value added == 0xfa. */
4332 else if ( c
&& (7 <= (res
>> 4) && (res
>> 4) <= 15) &&
4333 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4334 res
= res
+ 0xa0; /* Value added == 0xa0. */
4335 else if (c
&& (6 <= (res
>> 4) && (res
>> 4) <= 15) &&
4336 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4337 res
= res
+ 0x9a; /* Value added == 0x9a. */
4343 sim_engine_set_run_state (sd
, sim_stopped
, SIGILL
);
4348 (*sim_callback
->printf_filtered
) (sim_callback
,
4349 "sim_resume: internal error.\n");
4350 sim_engine_set_run_state (sd
, sim_stopped
, SIGILL
);
4354 if (code
->dst
.type
== X (OP_CCR
, SB
) ||
4355 code
->dst
.type
== X (OP_CCR
, SW
))
4357 h8_set_ccr (sd
, res
);
4360 else if (h8300smode
&&
4361 (code
->dst
.type
== X (OP_EXR
, SB
) ||
4362 code
->dst
.type
== X (OP_EXR
, SW
)))
4364 h8_set_exr (sd
, res
);
4365 if (h8300smode
) /* Get exr. */
4367 trace
= (h8_get_exr (sd
) >> 7) & 1;
4368 intMask
= h8_get_exr (sd
) & 7;
4377 /* When a branch works */
4378 if (fetch (sd
, &code
->src
, &res
))
4380 if (res
& 1) /* bad address */
4382 pc
= code
->next_pc
+ res
;
4385 /* Set the cond codes from res */
4388 /* Set the flags after an 8 bit inc/dec operation */
4392 v
= (rd
& 0x7f) == 0x7f;
4395 /* Set the flags after an 16 bit inc/dec operation */
4399 v
= (rd
& 0x7fff) == 0x7fff;
4402 /* Set the flags after an 32 bit inc/dec operation */
4404 n
= res
& 0x80000000;
4405 nz
= res
& 0xffffffff;
4406 v
= (rd
& 0x7fffffff) == 0x7fffffff;
4410 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4413 if (store2 (sd
, &code
->dst
, rd
))
4418 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4421 if (store2 (sd
, &code
->dst
, rd
))
4426 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4427 n
= (rd
& 0x80000000);
4428 nz
= rd
& 0xffffffff;
4429 if (store2 (sd
, &code
->dst
, rd
))
4434 if (store2 (sd
, &code
->dst
, res
))
4438 /* flags after a 32bit logical operation */
4439 n
= res
& 0x80000000;
4440 nz
= res
& 0xffffffff;
4445 if (store2 (sd
, &code
->dst
, res
))
4449 /* flags after a 16bit logical operation */
4456 if (store2 (sd
, &code
->dst
, res
))
4466 if (store2 (sd
, &code
->dst
, res
))
4473 switch (code
->opcode
/ 4)
4477 v
= ((rd
& 0x80) == (ea
& 0x80)
4478 && (rd
& 0x80) != (res
& 0x80));
4483 v
= ((rd
& 0x80) != (-ea
& 0x80)
4484 && (rd
& 0x80) != (res
& 0x80));
4491 break; /* No effect on v flag. */
4496 if (store2 (sd
, &code
->dst
, res
))
4502 c
= (res
& 0x10000);
4503 switch (code
->opcode
/ 4)
4507 v
= ((rd
& 0x8000) == (ea
& 0x8000)
4508 && (rd
& 0x8000) != (res
& 0x8000));
4513 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
4514 && (rd
& 0x8000) != (res
& 0x8000));
4523 if (store2 (sd
, &code
->dst
, res
))
4527 n
= res
& 0x80000000;
4528 nz
= res
& 0xffffffff;
4529 switch (code
->opcode
/ 4)
4533 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
4534 && (rd
& 0x80000000) != (res
& 0x80000000));
4535 c
= ((unsigned) res
< (unsigned) rd
) ||
4536 ((unsigned) res
< (unsigned) ea
);
4541 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
4542 && (rd
& 0x80000000) != (res
& 0x80000000));
4543 c
= (unsigned) rd
< (unsigned) -ea
;
4546 v
= (rd
== 0x80000000);
4553 if ((res
= h8_get_delayed_branch (sd
)) != 0)
4556 h8_set_delayed_branch (sd
, 0);
4563 if (--poll_count
< 0)
4565 poll_count
= POLL_QUIT_INTERVAL
;
4566 if ((*sim_callback
->poll_quit
) != NULL
4567 && (*sim_callback
->poll_quit
) (sim_callback
))
4568 sim_engine_set_run_state (sd
, sim_stopped
, SIGINT
);
4570 sim_engine_get_run_state (sd
, &reason
, &sigrc
);
4571 } while (reason
== sim_running
);
4573 h8_set_ticks (sd
, h8_get_ticks (sd
) + get_now () - tick_start
);
4574 h8_set_cycles (sd
, h8_get_cycles (sd
) + cycles
);
4575 h8_set_insts (sd
, h8_get_insts (sd
) + insts
);
4580 h8_set_exr (sd
, (trace
<<7) | intMask
);
4582 h8_set_mask (sd
, oldmask
);
4586 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
4593 for (i
= 0; i
< size
; i
++)
4595 if (addr
< memory_size
)
4597 h8_set_memory (sd
, addr
+ i
, buffer
[i
]);
4598 h8_set_cache_idx (sd
, addr
+ i
, 0);
4602 h8_set_eightbit (sd
, (addr
+ i
) & 0xff, buffer
[i
]);
4609 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
4614 if (addr
< memory_size
)
4615 memcpy (buffer
, h8_get_memory_buf (sd
) + addr
, size
);
4617 memcpy (buffer
, h8_get_eightbit_buf (sd
) + (addr
& 0xff), size
);
4623 sim_store_register (SIM_DESC sd
, int rn
, unsigned char *value
, int length
)
4628 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
4629 shortval
= (value
[0] << 8) | (value
[1]);
4630 intval
= h8300hmode
? longval
: shortval
;
4636 if(h8300_normal_mode
)
4637 h8_set_pc (sd
, shortval
); /* PC for Normal mode is 2 bytes */
4639 h8_set_pc (sd
, intval
);
4642 (*sim_callback
->printf_filtered
) (sim_callback
,
4643 "sim_store_register: bad regnum %d.\n",
4653 h8_set_reg (sd
, rn
, intval
);
4656 h8_set_ccr (sd
, intval
);
4659 h8_set_exr (sd
, intval
);
4662 h8_set_sbr (sd
, intval
);
4665 h8_set_vbr (sd
, intval
);
4668 h8_set_mach (sd
, intval
);
4671 h8_set_macl (sd
, intval
);
4674 h8_set_cycles (sd
, longval
);
4678 h8_set_insts (sd
, longval
);
4682 h8_set_ticks (sd
, longval
);
4689 sim_fetch_register (SIM_DESC sd
, int rn
, unsigned char *buf
, int length
)
4696 if (!h8300smode
&& rn
>= EXR_REGNUM
)
4701 (*sim_callback
->printf_filtered
) (sim_callback
,
4702 "sim_fetch_register: bad regnum %d.\n",
4707 v
= h8_get_ccr (sd
);
4710 v
= h8_get_exr (sd
);
4716 v
= h8_get_sbr (sd
);
4719 v
= h8_get_vbr (sd
);
4722 v
= h8_get_mach (sd
);
4725 v
= h8_get_macl (sd
);
4735 v
= h8_get_reg (sd
, rn
);
4738 v
= h8_get_cycles (sd
);
4742 v
= h8_get_ticks (sd
);
4746 v
= h8_get_insts (sd
);
4750 /* In Normal mode PC is 2 byte, but other registers are 4 byte */
4751 if ((h8300hmode
|| longreg
) && !(rn
== PC_REGNUM
&& h8300_normal_mode
))
4767 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason
, int *sigrc
)
4769 sim_engine_get_run_state (sd
, reason
, sigrc
);
4773 set_simcache_size (SIM_DESC sd
, int n
)
4776 free (sd
->sim_cache
);
4779 sd
->sim_cache
= (decoded_inst
*) malloc (sizeof (decoded_inst
) * n
);
4780 memset (sd
->sim_cache
, 0, sizeof (decoded_inst
) * n
);
4781 sd
->sim_cache_size
= n
;
4786 sim_info (SIM_DESC sd
, int verbose
)
4788 double timetaken
= (double) h8_get_ticks (sd
) / (double) now_persec ();
4789 double virttime
= h8_get_cycles (sd
) / 10.0e6
;
4791 (*sim_callback
->printf_filtered
) (sim_callback
,
4792 "\n\n#instructions executed %10d\n",
4794 (*sim_callback
->printf_filtered
) (sim_callback
,
4795 "#cycles (v approximate) %10d\n",
4796 h8_get_cycles (sd
));
4797 (*sim_callback
->printf_filtered
) (sim_callback
,
4798 "#real time taken %10.4f\n",
4800 (*sim_callback
->printf_filtered
) (sim_callback
,
4801 "#virtual time taken %10.4f\n",
4803 if (timetaken
!= 0.0)
4804 (*sim_callback
->printf_filtered
) (sim_callback
,
4805 "#simulation ratio %10.4f\n",
4806 virttime
/ timetaken
);
4807 (*sim_callback
->printf_filtered
) (sim_callback
,
4809 h8_get_compiles (sd
));
4810 (*sim_callback
->printf_filtered
) (sim_callback
,
4811 "#cache size %10d\n",
4812 sd
->sim_cache_size
);
4815 /* This to be conditional on `what' (aka `verbose'),
4816 however it was never passed as non-zero. */
4820 for (i
= 0; i
< O_LAST
; i
++)
4822 if (h8_get_stats (sd
, i
))
4823 (*sim_callback
->printf_filtered
) (sim_callback
, "%d: %d\n",
4824 i
, h8_get_stats (sd
, i
));
4830 /* Indicate whether the cpu is an H8/300 or H8/300H.
4831 FLAG is non-zero for the H8/300H. */
4834 set_h8300h (unsigned long machine
)
4836 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4837 This function being replaced by a sim_open:ARGV configuration
4840 h8300hmode
= h8300smode
= h8300sxmode
= h8300_normal_mode
= 0;
4842 if (machine
== bfd_mach_h8300sx
|| machine
== bfd_mach_h8300sxn
)
4845 if (machine
== bfd_mach_h8300s
|| machine
== bfd_mach_h8300sn
|| h8300sxmode
)
4848 if (machine
== bfd_mach_h8300h
|| machine
== bfd_mach_h8300hn
|| h8300smode
)
4851 if(machine
== bfd_mach_h8300hn
|| machine
== bfd_mach_h8300sn
|| machine
== bfd_mach_h8300sxn
)
4852 h8300_normal_mode
= 1;
4856 h8300_pc_get (sim_cpu
*cpu
)
4862 h8300_pc_set (sim_cpu
*cpu
, sim_cia pc
)
4867 /* Cover function of sim_state_free to free the cpu buffers as well. */
4870 free_state (SIM_DESC sd
)
4872 if (STATE_MODULES (sd
) != NULL
)
4873 sim_module_uninstall (sd
);
4875 /* Fixme: free buffers in _sim_cpu. */
4876 sim_state_free (sd
);
4880 sim_open (SIM_OPEN_KIND kind
,
4881 struct host_callback_struct
*callback
,
4889 sd
= sim_state_alloc (kind
, callback
);
4891 /* The cpu data is kept in a separately allocated chunk of memory. */
4892 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
4898 cpu
= STATE_CPU (sd
, 0);
4899 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4900 sim_state_initialize (sd
, cpu
);
4901 /* sim_cpu object is new, so some initialization is needed. */
4902 init_pointers_needed
= 1;
4904 /* For compatibility (FIXME: is this right?). */
4905 current_alignment
= NONSTRICT_ALIGNMENT
;
4906 current_target_byte_order
= BIG_ENDIAN
;
4908 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
4914 /* getopt will print the error message so we just have to exit if
4915 this fails. FIXME: Hmmm... in the case of gdb we need getopt
4916 to call print_filtered. */
4917 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
4919 /* Uninstall the modules to avoid memory leaks,
4920 file descriptor leaks, etc. */
4925 /* Check for/establish the a reference program image. */
4926 if (sim_analyze_program (sd
,
4927 (STATE_PROG_ARGV (sd
) != NULL
4928 ? *STATE_PROG_ARGV (sd
)
4929 : NULL
), abfd
) != SIM_RC_OK
)
4935 /* Establish any remaining configuration options. */
4936 if (sim_config (sd
) != SIM_RC_OK
)
4942 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
4944 /* Uninstall the modules to avoid memory leaks,
4945 file descriptor leaks, etc. */
4950 /* CPU specific initialization. */
4951 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
4953 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
4955 CPU_PC_FETCH (cpu
) = h8300_pc_get
;
4956 CPU_PC_STORE (cpu
) = h8300_pc_set
;
4959 /* sim_hw_configure (sd); */
4961 /* FIXME: Much of the code in sim_load can be moved here. */
4965 sim_callback
= callback
;
4969 /* Called by gdb to load a program into memory. */
4972 sim_load (SIM_DESC sd
, const char *prog
, bfd
*abfd
, int from_tty
)
4976 /* FIXME: The code below that sets a specific variant of the H8/300
4977 being simulated should be moved to sim_open(). */
4979 /* See if the file is for the H8/300 or H8/300H. */
4980 /* ??? This may not be the most efficient way. The z8k simulator
4981 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
4985 prog_bfd
= bfd_openr (prog
, NULL
);
4986 if (prog_bfd
!= NULL
)
4988 /* Set the cpu type. We ignore failure from bfd_check_format
4989 and bfd_openr as sim_load_file checks too. */
4990 if (bfd_check_format (prog_bfd
, bfd_object
))
4992 set_h8300h (bfd_get_mach (prog_bfd
));
4996 /* If we're using gdb attached to the simulator, then we have to
4997 reallocate memory for the simulator.
4999 When gdb first starts, it calls fetch_registers (among other
5000 functions), which in turn calls init_pointers, which allocates
5003 The problem is when we do that, we don't know whether we're
5004 debugging an H8/300 or H8/300H program.
5006 This is the first point at which we can make that determination,
5007 so we just reallocate memory now; this will also allow us to handle
5008 switching between H8/300 and H8/300H programs without exiting
5011 if (h8300smode
&& !h8300_normal_mode
)
5012 memory_size
= H8300S_MSIZE
;
5013 else if (h8300hmode
&& !h8300_normal_mode
)
5014 memory_size
= H8300H_MSIZE
;
5016 memory_size
= H8300_MSIZE
;
5018 if (h8_get_memory_buf (sd
))
5019 free (h8_get_memory_buf (sd
));
5020 if (h8_get_cache_idx_buf (sd
))
5021 free (h8_get_cache_idx_buf (sd
));
5022 if (h8_get_eightbit_buf (sd
))
5023 free (h8_get_eightbit_buf (sd
));
5025 h8_set_memory_buf (sd
, (unsigned char *)
5026 calloc (sizeof (char), memory_size
));
5027 h8_set_cache_idx_buf (sd
, (unsigned short *)
5028 calloc (sizeof (short), memory_size
));
5029 sd
->memory_size
= memory_size
;
5030 h8_set_eightbit_buf (sd
, (unsigned char *) calloc (sizeof (char), 256));
5032 /* `msize' must be a power of two. */
5033 if ((memory_size
& (memory_size
- 1)) != 0)
5035 (*sim_callback
->printf_filtered
) (sim_callback
,
5036 "sim_load: bad memory size.\n");
5039 h8_set_mask (sd
, memory_size
- 1);
5041 if (sim_load_file (sd
, myname
, sim_callback
, prog
, prog_bfd
,
5042 sim_kind
== SIM_OPEN_DEBUG
,
5046 /* Close the bfd if we opened it. */
5047 if (abfd
== NULL
&& prog_bfd
!= NULL
)
5048 bfd_close (prog_bfd
);
5052 /* Close the bfd if we opened it. */
5053 if (abfd
== NULL
&& prog_bfd
!= NULL
)
5054 bfd_close (prog_bfd
);
5059 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
, char **argv
, char **env
)
5066 h8_set_pc (sd
, bfd_get_start_address (abfd
));
5070 /* Command Line support. */
5073 /* Counting the no. of commandline arguments. */
5074 for (no_of_args
= 0; argv
[no_of_args
] != NULL
; no_of_args
++)
5077 /* Allocating memory for the argv pointers. */
5078 h8_set_command_line (sd
, (char **) malloc ((sizeof (char *))
5079 * (no_of_args
+ 1)));
5081 for (i
= 0; i
< no_of_args
; i
++)
5083 /* Copying the argument string. */
5084 h8_set_cmdline_arg (sd
, i
, (char *) strdup (argv
[i
]));
5086 h8_set_cmdline_arg (sd
, i
, NULL
);