2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
27 #ifdef HAVE_SYS_PARAM_H
28 #include <sys/param.h>
33 #include "gdb/sim-h8300.h"
35 #include "sys/types.h"
43 host_callback
*sim_callback
;
45 static SIM_OPEN_KIND sim_kind
;
48 /* FIXME: Needs to live in header file.
49 This header should also include the things in remote-sim.h.
50 One could move this to remote-sim.h but this function isn't needed
52 static void set_simcache_size (SIM_DESC
, int);
54 #define X(op, size) (op * 4 + size)
56 #define SP (h8300hmode ? SL : SW)
58 #define h8_opcodes ops
60 #include "opcode/h8300.h"
62 /* CPU data object: */
65 sim_state_initialize (SIM_DESC sd
, sim_cpu
*cpu
)
67 /* FIXME: not really necessary, since sim_cpu_alloc calls zalloc. */
69 memset (&cpu
->regs
, 0, sizeof(cpu
->regs
));
70 cpu
->regs
[SBR_REGNUM
] = 0xFFFFFF00;
72 cpu
->delayed_branch
= 0;
77 /* Initialize local simulator state. */
79 sd
->sim_cache_size
= 0;
85 memset (&cpu
->stats
, 0, sizeof (cpu
->stats
));
91 h8_get_pc (SIM_DESC sd
)
93 return (STATE_CPU (sd
, 0)) -> pc
;
97 h8_set_pc (SIM_DESC sd
, unsigned int val
)
99 (STATE_CPU (sd
, 0)) -> pc
= val
;
103 h8_get_ccr (SIM_DESC sd
)
105 return (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
];
109 h8_set_ccr (SIM_DESC sd
, unsigned int val
)
111 (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
] = val
;
115 h8_get_exr (SIM_DESC sd
)
117 return (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
];
121 h8_set_exr (SIM_DESC sd
, unsigned int val
)
123 (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
] = val
;
127 h8_get_sbr (SIM_DESC sd
)
129 return (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
];
133 h8_set_sbr (SIM_DESC sd
, int val
)
135 (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
] = val
;
139 h8_get_vbr (SIM_DESC sd
)
141 return (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
];
145 h8_set_vbr (SIM_DESC sd
, int val
)
147 (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
] = val
;
151 h8_get_cache_top (SIM_DESC sd
)
153 return sd
-> cache_top
;
157 h8_set_cache_top (SIM_DESC sd
, int val
)
159 sd
-> cache_top
= val
;
163 h8_get_mask (SIM_DESC sd
)
165 return (STATE_CPU (sd
, 0)) -> mask
;
169 h8_set_mask (SIM_DESC sd
, int val
)
171 (STATE_CPU (sd
, 0)) -> mask
= val
;
175 h8_get_exception (SIM_DESC sd
)
177 return (STATE_CPU (sd
, 0)) -> exception
;
181 h8_set_exception (SIM_DESC sd
, int val
)
183 (STATE_CPU (sd
, 0)) -> exception
= val
;
186 static enum h8300_sim_state
187 h8_get_state (SIM_DESC sd
)
193 h8_set_state (SIM_DESC sd
, enum h8300_sim_state val
)
199 h8_get_cycles (SIM_DESC sd
)
201 return (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
];
205 h8_set_cycles (SIM_DESC sd
, unsigned int val
)
207 (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
] = val
;
211 h8_get_insts (SIM_DESC sd
)
213 return (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
];
217 h8_set_insts (SIM_DESC sd
, unsigned int val
)
219 (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
] = val
;
223 h8_get_ticks (SIM_DESC sd
)
225 return (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
];
229 h8_set_ticks (SIM_DESC sd
, unsigned int val
)
231 (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
] = val
;
235 h8_get_mach (SIM_DESC sd
)
237 return (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
];
241 h8_set_mach (SIM_DESC sd
, unsigned int val
)
243 (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
] = val
;
247 h8_get_macl (SIM_DESC sd
)
249 return (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
];
253 h8_set_macl (SIM_DESC sd
, unsigned int val
)
255 (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
] = val
;
259 h8_get_compiles (SIM_DESC sd
)
261 return sd
-> compiles
;
265 h8_increment_compiles (SIM_DESC sd
)
270 static unsigned int *
271 h8_get_reg_buf (SIM_DESC sd
)
273 return &(((STATE_CPU (sd
, 0)) -> regs
)[0]);
277 h8_get_reg (SIM_DESC sd
, int regnum
)
279 return (STATE_CPU (sd
, 0)) -> regs
[regnum
];
283 h8_set_reg (SIM_DESC sd
, int regnum
, int val
)
285 (STATE_CPU (sd
, 0)) -> regs
[regnum
] = val
;
290 h8_get_stats (SIM_DESC sd
, int idx
)
292 return sd
-> stats
[idx
];
296 h8_increment_stats (SIM_DESC sd
, int idx
)
302 static unsigned short *
303 h8_get_cache_idx_buf (SIM_DESC sd
)
305 return sd
-> cache_idx
;
309 h8_set_cache_idx_buf (SIM_DESC sd
, unsigned short *ptr
)
311 sd
-> cache_idx
= ptr
;
314 static unsigned short
315 h8_get_cache_idx (SIM_DESC sd
, unsigned int idx
)
317 if (idx
> sd
->memory_size
)
318 return (unsigned short) -1;
319 return sd
-> cache_idx
[idx
];
323 h8_set_cache_idx (SIM_DESC sd
, int idx
, unsigned int val
)
325 sd
-> cache_idx
[idx
] = (unsigned short) val
;
328 static unsigned char *
329 h8_get_memory_buf (SIM_DESC sd
)
331 return (STATE_CPU (sd
, 0)) -> memory
;
335 h8_set_memory_buf (SIM_DESC sd
, unsigned char *ptr
)
337 (STATE_CPU (sd
, 0)) -> memory
= ptr
;
341 h8_get_memory (SIM_DESC sd
, int idx
)
343 return (STATE_CPU (sd
, 0)) -> memory
[idx
];
347 h8_set_memory (SIM_DESC sd
, int idx
, unsigned int val
)
349 (STATE_CPU (sd
, 0)) -> memory
[idx
] = (unsigned char) val
;
352 static unsigned char *
353 h8_get_eightbit_buf (SIM_DESC sd
)
355 return (STATE_CPU (sd
, 0)) -> eightbit
;
359 h8_set_eightbit_buf (SIM_DESC sd
, unsigned char *ptr
)
361 (STATE_CPU (sd
, 0)) -> eightbit
= ptr
;
365 h8_get_eightbit (SIM_DESC sd
, int idx
)
367 return (STATE_CPU (sd
, 0)) -> eightbit
[idx
];
371 h8_set_eightbit (SIM_DESC sd
, int idx
, unsigned int val
)
373 (STATE_CPU (sd
, 0)) -> eightbit
[idx
] = (unsigned char) val
;
377 h8_get_delayed_branch (SIM_DESC sd
)
379 return (STATE_CPU (sd
, 0)) -> delayed_branch
;
383 h8_set_delayed_branch (SIM_DESC sd
, unsigned int dest
)
385 (STATE_CPU (sd
, 0)) -> delayed_branch
= dest
;
389 h8_get_command_line (SIM_DESC sd
)
391 return (STATE_CPU (sd
, 0)) -> command_line
;
395 h8_set_command_line (SIM_DESC sd
, char ** val
)
397 (STATE_CPU (sd
, 0)) -> command_line
= val
;
401 h8_get_cmdline_arg (SIM_DESC sd
, int index
)
403 return (STATE_CPU (sd
, 0)) -> command_line
[index
];
407 h8_set_cmdline_arg (SIM_DESC sd
, int index
, char * val
)
409 (STATE_CPU (sd
, 0)) -> command_line
[index
] = val
;
412 /* MAC Saturation Mode */
414 h8_get_macS (SIM_DESC sd
)
416 return (STATE_CPU (sd
, 0)) -> macS
;
420 h8_set_macS (SIM_DESC sd
, int val
)
422 (STATE_CPU (sd
, 0)) -> macS
= (val
!= 0);
427 h8_get_macZ (SIM_DESC sd
)
429 return (STATE_CPU (sd
, 0)) -> macZ
;
433 h8_set_macZ (SIM_DESC sd
, int val
)
435 (STATE_CPU (sd
, 0)) -> macZ
= (val
!= 0);
438 /* MAC Negative Flag */
440 h8_get_macN (SIM_DESC sd
)
442 return (STATE_CPU (sd
, 0)) -> macN
;
446 h8_set_macN (SIM_DESC sd
, int val
)
448 (STATE_CPU (sd
, 0)) -> macN
= (val
!= 0);
451 /* MAC Overflow Flag */
453 h8_get_macV (SIM_DESC sd
)
455 return (STATE_CPU (sd
, 0)) -> macV
;
459 h8_set_macV (SIM_DESC sd
, int val
)
461 (STATE_CPU (sd
, 0)) -> macV
= (val
!= 0);
464 /* End CPU data object. */
466 /* The rate at which to call the host's poll_quit callback. */
468 enum { POLL_QUIT_INTERVAL
= 0x80000 };
470 #define LOW_BYTE(x) ((x) & 0xff)
471 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
472 #define P(X, Y) ((X << 8) | Y)
481 #define I (intMaskBit != 0)
483 #define BUILDSR(SD) \
484 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
485 | (N << 3) | (Z << 2) | (V << 1) | C)
487 #ifdef __CHAR_IS_SIGNED__
488 #define SEXTCHAR(x) ((char) (x))
492 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
495 #define UEXTCHAR(x) ((x) & 0xff)
496 #define UEXTSHORT(x) ((x) & 0xffff)
497 #define SEXTSHORT(x) ((short) (x))
503 static int memory_size
;
508 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
530 return h8300hmode
? SL
: SW
;
535 /* Simulate an indirection / dereference.
536 return 0 for success, -1 for failure.
540 lvalue (SIM_DESC sd
, int x
, int rn
, unsigned int *val
)
542 if (val
== NULL
) /* Paranoia. */
548 if (rn
== ZERO_REGNUM
)
549 *val
= X (OP_IMM
, SP
);
551 *val
= X (OP_REG
, SP
);
554 *val
= X (OP_MEM
, SP
);
557 sim_engine_set_run_state (sd
, sim_stopped
, SIGSEGV
);
575 decode (SIM_DESC sd
, int addr
, unsigned char *data
, decoded_inst
*dst
)
577 int cst
[3] = {0, 0, 0};
578 int reg
[3] = {0, 0, 0};
579 int rdisp
[3] = {0, 0, 0};
581 const struct h8_opcode
*q
;
586 /* Find the exact opcode/arg combo. */
587 for (q
= h8_opcodes
; q
->name
; q
++)
589 op_type
*nib
= q
->data
.nib
;
590 unsigned int len
= 0;
592 if ((q
->available
== AV_H8SX
&& !h8300sxmode
) ||
593 (q
->available
== AV_H8H
&& !h8300hmode
))
598 op_type looking_for
= *nib
;
599 int thisnib
= data
[len
/ 2];
601 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
602 opnum
= ((looking_for
& OP3
) ? 2 :
603 (looking_for
& DST
) ? 1 : 0);
605 if (looking_for
< 16 && looking_for
>= 0)
607 if (looking_for
!= thisnib
)
612 if (looking_for
& B31
)
614 if (!((thisnib
& 0x8) != 0))
617 looking_for
= (op_type
) (looking_for
& ~B31
);
620 else if (looking_for
& B30
)
622 if (!((thisnib
& 0x8) == 0))
625 looking_for
= (op_type
) (looking_for
& ~B30
);
628 if (looking_for
& B21
)
630 if (!((thisnib
& 0x4) != 0))
633 looking_for
= (op_type
) (looking_for
& ~B21
);
636 else if (looking_for
& B20
)
638 if (!((thisnib
& 0x4) == 0))
641 looking_for
= (op_type
) (looking_for
& ~B20
);
644 if (looking_for
& B11
)
646 if (!((thisnib
& 0x2) != 0))
649 looking_for
= (op_type
) (looking_for
& ~B11
);
652 else if (looking_for
& B10
)
654 if (!((thisnib
& 0x2) == 0))
657 looking_for
= (op_type
) (looking_for
& ~B10
);
660 if (looking_for
& B01
)
662 if (!((thisnib
& 0x1) != 0))
665 looking_for
= (op_type
) (looking_for
& ~B01
);
668 else if (looking_for
& B00
)
670 if (!((thisnib
& 0x1) == 0))
673 looking_for
= (op_type
) (looking_for
& ~B00
);
676 if (looking_for
& IGNORE
)
678 /* Hitachi has declared that IGNORE must be zero. */
682 else if ((looking_for
& MODE
) == DATA
)
684 ; /* Skip embedded data. */
686 else if ((looking_for
& MODE
) == DBIT
)
688 /* Exclude adds/subs by looking at bit 0 and 2, and
689 make sure the operand size, either w or l,
690 matches by looking at bit 1. */
691 if ((looking_for
& 7) != (thisnib
& 7))
694 cst
[opnum
] = (thisnib
& 0x8) ? 2 : 1;
696 else if ((looking_for
& MODE
) == REG
||
697 (looking_for
& MODE
) == LOWREG
||
698 (looking_for
& MODE
) == IND
||
699 (looking_for
& MODE
) == PREINC
||
700 (looking_for
& MODE
) == POSTINC
||
701 (looking_for
& MODE
) == PREDEC
||
702 (looking_for
& MODE
) == POSTDEC
)
704 reg
[opnum
] = thisnib
;
706 else if (looking_for
& CTRL
)
709 if (((looking_for
& MODE
) == CCR
&& (thisnib
!= C_CCR
)) ||
710 ((looking_for
& MODE
) == EXR
&& (thisnib
!= C_EXR
)) ||
711 ((looking_for
& MODE
) == MACH
&& (thisnib
!= C_MACH
)) ||
712 ((looking_for
& MODE
) == MACL
&& (thisnib
!= C_MACL
)) ||
713 ((looking_for
& MODE
) == VBR
&& (thisnib
!= C_VBR
)) ||
714 ((looking_for
& MODE
) == SBR
&& (thisnib
!= C_SBR
)))
716 if (((looking_for
& MODE
) == CCR_EXR
&&
717 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
)) ||
718 ((looking_for
& MODE
) == VBR_SBR
&&
719 (thisnib
!= C_VBR
&& thisnib
!= C_SBR
)) ||
720 ((looking_for
& MODE
) == MACREG
&&
721 (thisnib
!= C_MACH
&& thisnib
!= C_MACL
)))
723 if (((looking_for
& MODE
) == CC_EX_VB_SB
&&
724 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
&&
725 thisnib
!= C_VBR
&& thisnib
!= C_SBR
)))
728 reg
[opnum
] = thisnib
;
730 else if ((looking_for
& MODE
) == ABS
)
732 /* Absolute addresses are unsigned. */
733 switch (looking_for
& SIZE
)
736 cst
[opnum
] = UEXTCHAR (data
[len
/ 2]);
740 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
744 (data
[len
/ 2 + 0] << 24) +
745 (data
[len
/ 2 + 1] << 16) +
746 (data
[len
/ 2 + 2] << 8) +
750 printf ("decode: bad size ABS: %d\n",
751 (looking_for
& SIZE
));
755 else if ((looking_for
& MODE
) == DISP
||
756 (looking_for
& MODE
) == PCREL
||
757 (looking_for
& MODE
) == INDEXB
||
758 (looking_for
& MODE
) == INDEXW
||
759 (looking_for
& MODE
) == INDEXL
)
762 switch (looking_for
& SIZE
)
765 cst
[opnum
] = thisnib
& 3;
767 /* DISP2 special treatment. */
768 if ((looking_for
& MODE
) == DISP
)
770 switch (OP_SIZE (q
->how
)) {
782 cst
[opnum
] = SEXTCHAR (data
[len
/ 2]);
785 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
786 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
789 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
793 (data
[len
/ 2 + 0] << 24) +
794 (data
[len
/ 2 + 1] << 16) +
795 (data
[len
/ 2 + 2] << 8) +
799 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
800 (looking_for
& SIZE
));
804 else if ((looking_for
& SIZE
) == L_16
||
805 (looking_for
& SIZE
) == L_16U
)
807 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
808 if ((looking_for
& SIZE
) != L_16U
)
809 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
811 else if (looking_for
& ABSJMP
)
813 switch (looking_for
& SIZE
) {
815 cst
[opnum
] = (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
819 (data
[len
/ 2 + 0] << 24) +
820 (data
[len
/ 2 + 1] << 16) +
821 (data
[len
/ 2 + 2] << 8) +
825 printf ("decode: bad size ABSJMP: %d\n",
826 (looking_for
& SIZE
));
830 else if ((looking_for
& MODE
) == MEMIND
)
832 cst
[opnum
] = data
[1];
834 else if ((looking_for
& SIZE
) == L_32
)
839 (data
[i
+ 0] << 24) |
840 (data
[i
+ 1] << 16) |
844 else if ((looking_for
& SIZE
) == L_24
)
849 (data
[i
+ 0] << 16) |
853 else if (looking_for
& DISPREG
)
855 rdisp
[opnum
] = thisnib
& 0x7;
857 else if ((looking_for
& MODE
) == KBIT
)
874 else if ((looking_for
& SIZE
) == L_8
)
876 if ((looking_for
& MODE
) == ABS
)
878 /* Will be combined with contents of SBR_REGNUM
879 by fetch (). For all modes except h8sx, this
880 will always contain the value 0xFFFFFF00. */
881 cst
[opnum
] = data
[len
/ 2] & 0xff;
885 cst
[opnum
] = data
[len
/ 2] & 0xff;
888 else if ((looking_for
& SIZE
) == L_3
||
889 (looking_for
& SIZE
) == L_3NZ
)
891 cst
[opnum
] = thisnib
& 7;
892 if (cst
[opnum
] == 0 && (looking_for
& SIZE
) == L_3NZ
)
895 else if ((looking_for
& SIZE
) == L_4
)
897 cst
[opnum
] = thisnib
& 15;
899 else if ((looking_for
& SIZE
) == L_5
)
901 cst
[opnum
] = data
[len
/ 2] & 0x1f;
903 else if (looking_for
== E
)
908 /* Fill in the args. */
910 op_type
*args
= q
->args
.nib
;
915 nargs
< 3 && *args
!= E
;
921 opnum
= ((x
& OP3
) ? 2 :
930 if ((x
& MODE
) == IMM
||
931 (x
& MODE
) == KBIT
||
934 /* Use the instruction to determine
936 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
937 p
->literal
= cst
[opnum
];
939 else if ((x
& MODE
) == CONST_2
||
940 (x
& MODE
) == CONST_4
||
941 (x
& MODE
) == CONST_8
||
942 (x
& MODE
) == CONST_16
)
944 /* Use the instruction to determine
946 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
948 case CONST_2
: p
->literal
= 2; break;
949 case CONST_4
: p
->literal
= 4; break;
950 case CONST_8
: p
->literal
= 8; break;
951 case CONST_16
: p
->literal
= 16; break;
954 else if ((x
& MODE
) == REG
)
956 p
->type
= X (OP_REG
, bitfrom (x
));
959 else if ((x
& MODE
) == LOWREG
)
961 p
->type
= X (OP_LOWREG
, bitfrom (x
));
964 else if ((x
& MODE
) == PREINC
)
966 /* Use the instruction to determine
968 p
->type
= X (OP_PREINC
, OP_SIZE (q
->how
));
969 p
->reg
= reg
[opnum
] & 0x7;
971 else if ((x
& MODE
) == POSTINC
)
973 /* Use the instruction to determine
975 p
->type
= X (OP_POSTINC
, OP_SIZE (q
->how
));
976 p
->reg
= reg
[opnum
] & 0x7;
978 else if ((x
& MODE
) == PREDEC
)
980 /* Use the instruction to determine
982 p
->type
= X (OP_PREDEC
, OP_SIZE (q
->how
));
983 p
->reg
= reg
[opnum
] & 0x7;
985 else if ((x
& MODE
) == POSTDEC
)
987 /* Use the instruction to determine
989 p
->type
= X (OP_POSTDEC
, OP_SIZE (q
->how
));
990 p
->reg
= reg
[opnum
] & 0x7;
992 else if ((x
& MODE
) == IND
)
994 /* Note: an indirect is transformed into
995 a displacement of zero.
997 /* Use the instruction to determine
999 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1000 p
->reg
= reg
[opnum
] & 0x7;
1002 if (OP_KIND (q
->how
) == O_JSR
||
1003 OP_KIND (q
->how
) == O_JMP
)
1004 if (lvalue (sd
, p
->type
, p
->reg
, &p
->type
))
1007 else if ((x
& MODE
) == ABS
)
1009 /* Note: a 16 or 32 bit ABS is transformed into a
1010 displacement from pseudo-register ZERO_REGNUM,
1011 which is always zero. An 8 bit ABS becomes
1012 a displacement from SBR_REGNUM.
1014 /* Use the instruction to determine
1015 the operand size. */
1016 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1017 p
->literal
= cst
[opnum
];
1019 /* 8-bit ABS is displacement from SBR.
1020 16 and 32-bit ABS are displacement from ZERO.
1021 (SBR will always be zero except for h8/sx)
1023 if ((x
& SIZE
) == L_8
)
1024 p
->reg
= SBR_REGNUM
;
1026 p
->reg
= ZERO_REGNUM
;;
1028 else if ((x
& MODE
) == MEMIND
)
1030 /* Size doesn't matter. */
1031 p
->type
= X (OP_MEM
, SB
);
1032 p
->literal
= cst
[opnum
];
1033 if (OP_KIND (q
->how
) == O_JSR
||
1034 OP_KIND (q
->how
) == O_JMP
)
1035 if (lvalue (sd
, p
->type
, p
->reg
, &p
->type
))
1038 else if ((x
& MODE
) == PCREL
)
1040 /* Size doesn't matter. */
1041 p
->type
= X (OP_PCREL
, SB
);
1042 p
->literal
= cst
[opnum
];
1044 else if (x
& ABSJMP
)
1046 p
->type
= X (OP_IMM
, SP
);
1047 p
->literal
= cst
[opnum
];
1049 else if ((x
& MODE
) == INDEXB
||
1050 (x
& MODE
) == INDEXW
||
1051 (x
& MODE
) == INDEXL
||
1054 /* Use the instruction to determine
1055 the operand size. */
1058 p
->type
= X (OP_INDEXB
, OP_SIZE (q
->how
));
1061 p
->type
= X (OP_INDEXW
, OP_SIZE (q
->how
));
1064 p
->type
= X (OP_INDEXL
, OP_SIZE (q
->how
));
1067 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1071 p
->literal
= cst
[opnum
];
1072 p
->reg
= rdisp
[opnum
];
1079 p
->type
= X (OP_CCR
, SB
);
1082 p
->type
= X (OP_EXR
, SB
);
1085 p
->type
= X (OP_MACH
, SL
);
1088 p
->type
= X (OP_MACL
, SL
);
1091 p
->type
= X (OP_VBR
, SL
);
1094 p
->type
= X (OP_SBR
, SL
);
1098 else if ((x
& MODE
) == CCR
)
1102 else if ((x
& MODE
) == EXR
)
1107 printf ("Hmmmm %x...\n", x
);
1113 /* Unary operators: treat src and dst as equivalent. */
1114 if (dst
->dst
.type
== -1)
1115 dst
->dst
= dst
->src
;
1116 if (dst
->src
.type
== -1)
1117 dst
->src
= dst
->dst
;
1119 dst
->opcode
= q
->how
;
1120 dst
->cycles
= q
->time
;
1122 /* And jsr's to these locations are turned into
1125 if (OP_KIND (dst
->opcode
) == O_JSR
)
1127 switch (dst
->src
.literal
)
1130 dst
->opcode
= O (O_SYS_OPEN
, SB
);
1133 dst
->opcode
= O (O_SYS_READ
, SB
);
1136 dst
->opcode
= O (O_SYS_WRITE
, SB
);
1139 dst
->opcode
= O (O_SYS_LSEEK
, SB
);
1142 dst
->opcode
= O (O_SYS_CLOSE
, SB
);
1145 dst
->opcode
= O (O_SYS_STAT
, SB
);
1148 dst
->opcode
= O (O_SYS_FSTAT
, SB
);
1151 dst
->opcode
= O (O_SYS_CMDLINE
, SB
);
1154 /* End of Processing for system calls. */
1157 dst
->next_pc
= addr
+ len
/ 2;
1161 printf ("Don't understand %x \n", looking_for
);
1172 /* Fell off the end. */
1173 dst
->opcode
= O (O_ILL
, SB
);
1177 compile (SIM_DESC sd
, int pc
)
1181 /* Find the next cache entry to use. */
1182 idx
= h8_get_cache_top (sd
) + 1;
1183 h8_increment_compiles (sd
);
1184 if (idx
>= sd
->sim_cache_size
)
1188 h8_set_cache_top (sd
, idx
);
1190 /* Throw away its old meaning. */
1191 h8_set_cache_idx (sd
, sd
->sim_cache
[idx
].oldpc
, 0);
1193 /* Set to new address. */
1194 sd
->sim_cache
[idx
].oldpc
= pc
;
1196 /* Fill in instruction info. */
1197 decode (sd
, pc
, h8_get_memory_buf (sd
) + pc
, sd
->sim_cache
+ idx
);
1199 /* Point to new cache entry. */
1200 h8_set_cache_idx (sd
, pc
, idx
);
1204 static unsigned char *breg
[32];
1205 static unsigned short *wreg
[16];
1206 static unsigned int *lreg
[18];
1208 #define GET_B_REG(X) *(breg[X])
1209 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1210 #define GET_W_REG(X) *(wreg[X])
1211 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1212 #define GET_L_REG(X) h8_get_reg (sd, X)
1213 #define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1215 #define GET_MEMORY_L(X) \
1216 ((X) < memory_size \
1217 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1218 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1219 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 24) \
1220 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 16) \
1221 | (h8_get_eightbit (sd, ((X)+2) & 0xff) << 8) \
1222 | (h8_get_eightbit (sd, ((X)+3) & 0xff) << 0)))
1224 #define GET_MEMORY_W(X) \
1225 ((X) < memory_size \
1226 ? ((h8_get_memory (sd, (X)+0) << 8) \
1227 | (h8_get_memory (sd, (X)+1) << 0)) \
1228 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 8) \
1229 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 0)))
1232 #define GET_MEMORY_B(X) \
1233 ((X) < memory_size ? (h8_get_memory (sd, (X))) \
1234 : (h8_get_eightbit (sd, (X) & 0xff)))
1236 #define SET_MEMORY_L(X, Y) \
1237 { register unsigned char *_p; register int __y = (Y); \
1238 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1239 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1240 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1241 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1244 #define SET_MEMORY_W(X, Y) \
1245 { register unsigned char *_p; register int __y = (Y); \
1246 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1247 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1248 _p[0] = __y >> 8; _p[1] = __y; \
1251 #define SET_MEMORY_B(X, Y) \
1252 ((X) < memory_size ? (h8_set_memory (sd, (X), (Y))) \
1253 : (h8_set_eightbit (sd, (X) & 0xff, (Y))))
1255 /* Simulate a memory fetch.
1256 Return 0 for success, -1 for failure.
1260 fetch_1 (SIM_DESC sd
, ea_type
*arg
, int *val
, int twice
)
1263 int abs
= arg
->literal
;
1268 return -1; /* Paranoia. */
1272 /* Indexed register plus displacement mode:
1274 This new family of addressing modes are similar to OP_DISP
1275 (register plus displacement), with two differences:
1276 1) INDEXB uses only the least significant byte of the register,
1277 INDEXW uses only the least significant word, and
1278 INDEXL uses the entire register (just like OP_DISP).
1280 2) The displacement value in abs is multiplied by two
1281 for SW-sized operations, and by four for SL-size.
1283 This gives nine possible variations.
1286 case X (OP_INDEXB
, SB
):
1287 case X (OP_INDEXB
, SW
):
1288 case X (OP_INDEXB
, SL
):
1289 case X (OP_INDEXW
, SB
):
1290 case X (OP_INDEXW
, SW
):
1291 case X (OP_INDEXW
, SL
):
1292 case X (OP_INDEXL
, SB
):
1293 case X (OP_INDEXL
, SW
):
1294 case X (OP_INDEXL
, SL
):
1296 switch (OP_KIND (arg
->type
)) {
1297 case OP_INDEXB
: t
&= 0xff; break;
1298 case OP_INDEXW
: t
&= 0xffff; break;
1302 switch (OP_SIZE (arg
->type
)) {
1304 *val
= GET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
));
1307 *val
= GET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
));
1310 *val
= GET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
));
1315 case X (OP_LOWREG
, SB
):
1316 *val
= GET_L_REG (rn
) & 0xff;
1318 case X (OP_LOWREG
, SW
):
1319 *val
= GET_L_REG (rn
) & 0xffff;
1322 case X (OP_REG
, SB
): /* Register direct, byte. */
1323 *val
= GET_B_REG (rn
);
1325 case X (OP_REG
, SW
): /* Register direct, word. */
1326 *val
= GET_W_REG (rn
);
1328 case X (OP_REG
, SL
): /* Register direct, long. */
1329 *val
= GET_L_REG (rn
);
1331 case X (OP_IMM
, SB
): /* Immediate, byte. */
1332 case X (OP_IMM
, SW
): /* Immediate, word. */
1333 case X (OP_IMM
, SL
): /* Immediate, long. */
1336 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr: byte. */
1338 t
&= h8_get_mask (sd
);
1339 r
= GET_MEMORY_B (t
);
1342 t
= t
& h8_get_mask (sd
);
1346 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr: word. */
1348 t
&= h8_get_mask (sd
);
1349 r
= GET_MEMORY_W (t
);
1352 t
= t
& h8_get_mask (sd
);
1356 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr: long. */
1358 t
&= h8_get_mask (sd
);
1359 r
= GET_MEMORY_L (t
);
1362 t
= t
& h8_get_mask (sd
);
1367 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr: byte. */
1369 t
&= h8_get_mask (sd
);
1370 r
= GET_MEMORY_B (t
);
1373 t
= t
& h8_get_mask (sd
);
1377 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr: word. */
1379 t
&= h8_get_mask (sd
);
1380 r
= GET_MEMORY_W (t
);
1383 t
= t
& h8_get_mask (sd
);
1387 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr: long. */
1389 t
&= h8_get_mask (sd
);
1390 r
= GET_MEMORY_L (t
);
1393 t
= t
& h8_get_mask (sd
);
1398 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr: byte. */
1399 t
= GET_L_REG (rn
) - 1;
1400 t
&= h8_get_mask (sd
);
1402 *val
= GET_MEMORY_B (t
);
1405 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr: word. */
1406 t
= GET_L_REG (rn
) - 2;
1407 t
&= h8_get_mask (sd
);
1409 *val
= GET_MEMORY_W (t
);
1412 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr: long. */
1413 t
= GET_L_REG (rn
) - 4;
1414 t
&= h8_get_mask (sd
);
1416 *val
= GET_MEMORY_L (t
);
1419 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr: byte. */
1420 t
= GET_L_REG (rn
) + 1;
1421 t
&= h8_get_mask (sd
);
1423 *val
= GET_MEMORY_B (t
);
1426 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr: long. */
1427 t
= GET_L_REG (rn
) + 2;
1428 t
&= h8_get_mask (sd
);
1430 *val
= GET_MEMORY_W (t
);
1433 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr: long. */
1434 t
= GET_L_REG (rn
) + 4;
1435 t
&= h8_get_mask (sd
);
1437 *val
= GET_MEMORY_L (t
);
1440 case X (OP_DISP
, SB
): /* Register indirect w/displacement: byte. */
1441 t
= GET_L_REG (rn
) + abs
;
1442 t
&= h8_get_mask (sd
);
1443 *val
= GET_MEMORY_B (t
);
1446 case X (OP_DISP
, SW
): /* Register indirect w/displacement: word. */
1447 t
= GET_L_REG (rn
) + abs
;
1448 t
&= h8_get_mask (sd
);
1449 *val
= GET_MEMORY_W (t
);
1452 case X (OP_DISP
, SL
): /* Register indirect w/displacement: long. */
1453 t
= GET_L_REG (rn
) + abs
;
1454 t
&= h8_get_mask (sd
);
1455 *val
=GET_MEMORY_L (t
);
1458 case X (OP_MEM
, SL
): /* Absolute memory address, long. */
1459 t
= GET_MEMORY_L (abs
);
1460 t
&= h8_get_mask (sd
);
1464 case X (OP_MEM
, SW
): /* Absolute memory address, word. */
1465 t
= GET_MEMORY_W (abs
);
1466 t
&= h8_get_mask (sd
);
1470 case X (OP_PCREL
, SB
): /* PC relative (for jump, branch etc). */
1471 case X (OP_PCREL
, SW
):
1472 case X (OP_PCREL
, SL
):
1473 case X (OP_PCREL
, SN
):
1477 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1479 sim_engine_set_run_state (sd
, sim_stopped
, SIGSEGV
);
1482 return 0; /* Success. */
1488 fetch (SIM_DESC sd
, ea_type
*arg
, int *val
)
1490 return fetch_1 (sd
, arg
, val
, 0);
1493 /* Fetch which will be followed by a store to the same location.
1494 The difference being that we don't want to do a post-increment
1495 or post-decrement at this time: we'll do it when we store. */
1498 fetch2 (SIM_DESC sd
, ea_type
*arg
, int *val
)
1500 return fetch_1 (sd
, arg
, val
, 1);
1503 /* Simulate a memory store.
1504 Return 0 for success, -1 for failure.
1508 store_1 (SIM_DESC sd
, ea_type
*arg
, int n
, int twice
)
1511 int abs
= arg
->literal
;
1516 /* Indexed register plus displacement mode:
1518 This new family of addressing modes are similar to OP_DISP
1519 (register plus displacement), with two differences:
1520 1) INDEXB uses only the least significant byte of the register,
1521 INDEXW uses only the least significant word, and
1522 INDEXL uses the entire register (just like OP_DISP).
1524 2) The displacement value in abs is multiplied by two
1525 for SW-sized operations, and by four for SL-size.
1527 This gives nine possible variations.
1530 case X (OP_INDEXB
, SB
):
1531 case X (OP_INDEXB
, SW
):
1532 case X (OP_INDEXB
, SL
):
1533 case X (OP_INDEXW
, SB
):
1534 case X (OP_INDEXW
, SW
):
1535 case X (OP_INDEXW
, SL
):
1536 case X (OP_INDEXL
, SB
):
1537 case X (OP_INDEXL
, SW
):
1538 case X (OP_INDEXL
, SL
):
1540 switch (OP_KIND (arg
->type
)) {
1541 case OP_INDEXB
: t
&= 0xff; break;
1542 case OP_INDEXW
: t
&= 0xffff; break;
1546 switch (OP_SIZE (arg
->type
)) {
1548 SET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
), n
);
1551 SET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
), n
);
1554 SET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
), n
);
1559 case X (OP_REG
, SB
): /* Register direct, byte. */
1562 case X (OP_REG
, SW
): /* Register direct, word. */
1565 case X (OP_REG
, SL
): /* Register direct, long. */
1569 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr, byte. */
1573 t
&= h8_get_mask (sd
);
1575 SET_MEMORY_B (t
, n
);
1578 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr, word. */
1582 t
&= h8_get_mask (sd
);
1584 SET_MEMORY_W (t
, n
);
1587 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr, long. */
1591 t
&= h8_get_mask (sd
);
1593 SET_MEMORY_L (t
, n
);
1596 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr, byte. */
1600 t
&= h8_get_mask (sd
);
1602 SET_MEMORY_B (t
, n
);
1605 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr, word. */
1609 t
&= h8_get_mask (sd
);
1611 SET_MEMORY_W (t
, n
);
1614 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr, long. */
1618 t
&= h8_get_mask (sd
);
1620 SET_MEMORY_L (t
, n
);
1623 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr, byte. */
1624 t
= GET_L_REG (rn
) & h8_get_mask (sd
);
1625 SET_MEMORY_B (t
, n
);
1626 SET_L_REG (rn
, t
- 1);
1629 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr, word. */
1630 t
= GET_L_REG (rn
) & h8_get_mask (sd
);
1631 SET_MEMORY_W (t
, n
);
1632 SET_L_REG (rn
, t
- 2);
1635 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr, long. */
1636 t
= GET_L_REG (rn
) & h8_get_mask (sd
);
1637 SET_MEMORY_L (t
, n
);
1638 SET_L_REG (rn
, t
- 4);
1641 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr, byte. */
1642 t
= GET_L_REG (rn
) & h8_get_mask (sd
);
1643 SET_MEMORY_B (t
, n
);
1644 SET_L_REG (rn
, t
+ 1);
1647 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr, word. */
1648 t
= GET_L_REG (rn
) & h8_get_mask (sd
);
1649 SET_MEMORY_W (t
, n
);
1650 SET_L_REG (rn
, t
+ 2);
1653 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr, long. */
1654 t
= GET_L_REG (rn
) & h8_get_mask (sd
);
1655 SET_MEMORY_L (t
, n
);
1656 SET_L_REG (rn
, t
+ 4);
1659 case X (OP_DISP
, SB
): /* Register indirect w/displacement, byte. */
1660 t
= GET_L_REG (rn
) + abs
;
1661 t
&= h8_get_mask (sd
);
1662 SET_MEMORY_B (t
, n
);
1665 case X (OP_DISP
, SW
): /* Register indirect w/displacement, word. */
1666 t
= GET_L_REG (rn
) + abs
;
1667 t
&= h8_get_mask (sd
);
1668 SET_MEMORY_W (t
, n
);
1671 case X (OP_DISP
, SL
): /* Register indirect w/displacement, long. */
1672 t
= GET_L_REG (rn
) + abs
;
1673 t
&= h8_get_mask (sd
);
1674 SET_MEMORY_L (t
, n
);
1678 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1679 case X (OP_MEM
, SW
): /* Why isn't this implemented? */
1680 case X (OP_MEM
, SL
): /* Why isn't this implemented? */
1682 sim_engine_set_run_state (sd
, sim_stopped
, SIGSEGV
);
1691 store (SIM_DESC sd
, ea_type
*arg
, int n
)
1693 return store_1 (sd
, arg
, n
, 0);
1696 /* Store which follows a fetch from the same location.
1697 The difference being that we don't want to do a pre-increment
1698 or pre-decrement at this time: it was already done when we fetched. */
1701 store2 (SIM_DESC sd
, ea_type
*arg
, int n
)
1703 return store_1 (sd
, arg
, n
, 1);
1717 /* Flag to be set whenever a new SIM_DESC object is created. */
1718 static int init_pointers_needed
= 1;
1721 init_pointers (SIM_DESC sd
)
1723 if (init_pointers_needed
)
1730 memory_size
= H8300S_MSIZE
;
1731 else if (h8300hmode
)
1732 memory_size
= H8300H_MSIZE
;
1734 memory_size
= H8300_MSIZE
;
1735 /* `msize' must be a power of two. */
1736 if ((memory_size
& (memory_size
- 1)) != 0)
1738 (*sim_callback
->printf_filtered
)
1740 "init_pointers: bad memory size %d, defaulting to %d.\n",
1741 memory_size
, memory_size
= H8300S_MSIZE
);
1744 if (h8_get_memory_buf (sd
))
1745 free (h8_get_memory_buf (sd
));
1746 if (h8_get_cache_idx_buf (sd
))
1747 free (h8_get_cache_idx_buf (sd
));
1748 if (h8_get_eightbit_buf (sd
))
1749 free (h8_get_eightbit_buf (sd
));
1751 h8_set_memory_buf (sd
, (unsigned char *)
1752 calloc (sizeof (char), memory_size
));
1753 h8_set_cache_idx_buf (sd
, (unsigned short *)
1754 calloc (sizeof (short), memory_size
));
1755 sd
->memory_size
= memory_size
;
1756 h8_set_eightbit_buf (sd
, (unsigned char *) calloc (sizeof (char), 256));
1758 h8_set_mask (sd
, memory_size
- 1);
1760 memset (h8_get_reg_buf (sd
), 0, sizeof (((STATE_CPU (sd
, 0))->regs
)));
1762 for (i
= 0; i
< 8; i
++)
1764 /* FIXME: rewrite using local buffer. */
1765 unsigned char *p
= (unsigned char *) (h8_get_reg_buf (sd
) + i
);
1766 unsigned char *e
= (unsigned char *) (h8_get_reg_buf (sd
) + i
+ 1);
1767 unsigned short *q
= (unsigned short *) (h8_get_reg_buf (sd
) + i
);
1768 unsigned short *u
= (unsigned short *) (h8_get_reg_buf (sd
) + i
+ 1);
1769 h8_set_reg (sd
, i
, 0x00112233);
1784 wreg
[i
] = wreg
[i
+ 8] = 0;
1798 if (wreg
[i
] == 0 || wreg
[i
+ 8] == 0)
1799 (*sim_callback
->printf_filtered
) (sim_callback
,
1800 "init_pointers: internal error.\n");
1802 h8_set_reg (sd
, i
, 0);
1803 lreg
[i
] = h8_get_reg_buf (sd
) + i
;
1806 /* Note: sim uses pseudo-register ZERO as a zero register. */
1807 lreg
[ZERO_REGNUM
] = h8_get_reg_buf (sd
) + ZERO_REGNUM
;
1808 init_pointers_needed
= 0;
1810 /* Initialize the seg registers. */
1812 set_simcache_size (sd
, CSIZE
);
1816 /* Grotty global variable for use by control_c signal handler. */
1817 static SIM_DESC control_c_sim_desc
;
1822 sim_engine_set_run_state (control_c_sim_desc
, sim_stopped
, SIGINT
);
1826 sim_stop (SIM_DESC sd
)
1828 /* FIXME: use a real signal value. */
1829 sim_engine_set_run_state (sd
, sim_stopped
, SIGINT
);
1833 #define OBITOP(name, f, s, op) \
1834 case O (name, SB): \
1839 if (fetch (sd, &code->dst, &ea)) \
1841 if (fetch (sd, &code->src, &tmp)) \
1846 if (store (sd, &code->dst,ea)) \
1852 sim_resume (SIM_DESC sd
, int step
, int siggnal
)
1857 int tick_start
= get_now ();
1866 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
1869 enum sim_stop reason
;
1874 control_c_sim_desc
= sd
;
1875 prev
= signal (SIGINT
, control_c
);
1879 sim_engine_set_run_state (sd
, sim_stopped
, SIGTRAP
);
1883 sim_engine_set_run_state (sd
, sim_running
, 0);
1886 pc
= h8_get_pc (sd
);
1888 /* The PC should never be odd. */
1891 sim_engine_set_run_state (sd
, sim_stopped
, SIGBUS
);
1895 /* Get Status Register (flags). */
1896 c
= (h8_get_ccr (sd
) >> 0) & 1;
1897 v
= (h8_get_ccr (sd
) >> 1) & 1;
1898 nz
= !((h8_get_ccr (sd
) >> 2) & 1);
1899 n
= (h8_get_ccr (sd
) >> 3) & 1;
1900 u
= (h8_get_ccr (sd
) >> 4) & 1;
1901 h
= (h8_get_ccr (sd
) >> 5) & 1;
1902 ui
= ((h8_get_ccr (sd
) >> 6) & 1);
1903 intMaskBit
= (h8_get_ccr (sd
) >> 7) & 1;
1905 if (h8300smode
) /* Get exr. */
1907 trace
= (h8_get_exr (sd
) >> 7) & 1;
1908 intMask
= h8_get_exr (sd
) & 7;
1911 oldmask
= h8_get_mask (sd
);
1913 h8_set_mask (sd
, 0xffff);
1916 unsigned short cidx
;
1920 cidx
= h8_get_cache_idx (sd
, pc
);
1921 if (cidx
== (unsigned short) -1 ||
1922 cidx
>= sd
->sim_cache_size
)
1925 code
= sd
->sim_cache
+ cidx
;
1930 printf ("%x %d %s\n", pc
, code
->opcode
,
1931 code
->op
? code
->op
->name
: "**");
1933 h8_increment_stats (sd
, code
->opcode
);
1938 cycles
+= code
->cycles
;
1942 switch (code
->opcode
)
1946 * This opcode is a fake for when we get to an
1947 * instruction which hasnt been compiled
1953 case O (O_MOVAB
, SL
):
1954 case O (O_MOVAW
, SL
):
1955 case O (O_MOVAL
, SL
):
1956 /* 1) Evaluate 2nd argument (dst).
1957 2) Mask / zero extend according to whether 1st argument (src)
1958 is INDEXB, INDEXW, or INDEXL.
1959 3) Left-shift the result by 0, 1 or 2, according to size of mova
1960 (mova/b, mova/w, mova/l).
1961 4) Add literal value of 1st argument (src).
1962 5) Store result in 3rd argument (op3).
1965 if (fetch (sd
, &code
->dst
, &ea
))
1968 switch (OP_KIND (code
->src
.type
)) {
1969 case OP_INDEXB
: ea
= ea
& 0xff; break;
1970 case OP_INDEXW
: ea
= ea
& 0xffff; break;
1971 case OP_INDEXL
: break;
1972 default: goto illegal
;
1975 switch (code
->opcode
) {
1976 case O (O_MOVAB
, SL
): break;
1977 case O (O_MOVAW
, SL
): ea
= ea
<< 1; break;
1978 case O (O_MOVAL
, SL
): ea
= ea
<< 2; break;
1979 default: goto illegal
;
1982 ea
= ea
+ code
->src
.literal
;
1984 if (store (sd
, &code
->op3
, ea
))
1989 case O (O_SUBX
, SB
): /* subx, extended sub */
1990 if (fetch2 (sd
, &code
->dst
, &rd
))
1992 if (fetch (sd
, &code
->src
, &ea
))
1998 case O (O_SUBX
, SW
): /* subx, extended sub */
1999 if (fetch2 (sd
, &code
->dst
, &rd
))
2001 if (fetch (sd
, &code
->src
, &ea
))
2007 case O (O_SUBX
, SL
): /* subx, extended sub */
2008 if (fetch2 (sd
, &code
->dst
, &rd
))
2010 if (fetch (sd
, &code
->src
, &ea
))
2016 case O (O_ADDX
, SB
): /* addx, extended add */
2017 if (fetch2 (sd
, &code
->dst
, &rd
))
2019 if (fetch (sd
, &code
->src
, &ea
))
2025 case O (O_ADDX
, SW
): /* addx, extended add */
2026 if (fetch2 (sd
, &code
->dst
, &rd
))
2028 if (fetch (sd
, &code
->src
, &ea
))
2034 case O (O_ADDX
, SL
): /* addx, extended add */
2035 if (fetch2 (sd
, &code
->dst
, &rd
))
2037 if (fetch (sd
, &code
->src
, &ea
))
2043 case O (O_SUB
, SB
): /* sub.b */
2044 /* Fetch rd and ea. */
2045 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2051 case O (O_SUB
, SW
): /* sub.w */
2052 /* Fetch rd and ea. */
2053 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2059 case O (O_SUB
, SL
): /* sub.l */
2060 /* Fetch rd and ea. */
2061 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2067 case O (O_NEG
, SB
): /* neg.b */
2069 if (fetch2 (sd
, &code
->src
, &ea
))
2076 case O (O_NEG
, SW
): /* neg.w */
2078 if (fetch2 (sd
, &code
->src
, &ea
))
2085 case O (O_NEG
, SL
): /* neg.l */
2087 if (fetch2 (sd
, &code
->src
, &ea
))
2094 case O (O_ADD
, SB
): /* add.b */
2095 if (fetch2 (sd
, &code
->dst
, &rd
))
2097 if (fetch (sd
, &code
->src
, &ea
))
2102 case O (O_ADD
, SW
): /* add.w */
2103 if (fetch2 (sd
, &code
->dst
, &rd
))
2105 if (fetch (sd
, &code
->src
, &ea
))
2110 case O (O_ADD
, SL
): /* add.l */
2111 if (fetch2 (sd
, &code
->dst
, &rd
))
2113 if (fetch (sd
, &code
->src
, &ea
))
2118 case O (O_AND
, SB
): /* and.b */
2119 /* Fetch rd and ea. */
2120 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2125 case O (O_AND
, SW
): /* and.w */
2126 /* Fetch rd and ea. */
2127 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2132 case O (O_AND
, SL
): /* and.l */
2133 /* Fetch rd and ea. */
2134 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2139 case O (O_OR
, SB
): /* or.b */
2140 /* Fetch rd and ea. */
2141 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2146 case O (O_OR
, SW
): /* or.w */
2147 /* Fetch rd and ea. */
2148 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2153 case O (O_OR
, SL
): /* or.l */
2154 /* Fetch rd and ea. */
2155 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2160 case O (O_XOR
, SB
): /* xor.b */
2161 /* Fetch rd and ea. */
2162 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2167 case O (O_XOR
, SW
): /* xor.w */
2168 /* Fetch rd and ea. */
2169 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2174 case O (O_XOR
, SL
): /* xor.l */
2175 /* Fetch rd and ea. */
2176 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2182 if (fetch (sd
, &code
->src
, &res
))
2184 if (store (sd
, &code
->dst
, res
))
2186 goto just_flags_log8
;
2188 if (fetch (sd
, &code
->src
, &res
))
2190 if (store (sd
, &code
->dst
, res
))
2192 goto just_flags_log16
;
2194 if (fetch (sd
, &code
->src
, &res
))
2196 if (store (sd
, &code
->dst
, res
))
2198 goto just_flags_log32
;
2200 case O (O_MOVMD
, SB
): /* movsd.b */
2207 rd
= GET_MEMORY_B (GET_L_REG (5));
2208 SET_MEMORY_B (GET_L_REG (6), rd
);
2209 SET_L_REG (5, GET_L_REG (5) + 1);
2210 SET_L_REG (6, GET_L_REG (6) + 1);
2215 case O (O_MOVMD
, SW
): /* movsd.b */
2222 rd
= GET_MEMORY_W (GET_L_REG (5));
2223 SET_MEMORY_W (GET_L_REG (6), rd
);
2224 SET_L_REG (5, GET_L_REG (5) + 2);
2225 SET_L_REG (6, GET_L_REG (6) + 2);
2230 case O (O_MOVMD
, SL
): /* movsd.b */
2237 rd
= GET_MEMORY_L (GET_L_REG (5));
2238 SET_MEMORY_L (GET_L_REG (6), rd
);
2239 SET_L_REG (5, GET_L_REG (5) + 4);
2240 SET_L_REG (6, GET_L_REG (6) + 4);
2245 case O (O_MOVSD
, SB
): /* movsd.b */
2246 /* This instruction implements strncpy, with a conditional branch.
2247 r4 contains n, r5 contains src, and r6 contains dst.
2248 The 16-bit displacement operand is added to the pc
2249 if and only if the end of string is reached before
2250 n bytes are transferred. */
2252 ea
= GET_L_REG (4) & 0xffff;
2258 rd
= GET_MEMORY_B (GET_L_REG (5));
2259 SET_MEMORY_B (GET_L_REG (6), rd
);
2260 SET_L_REG (5, GET_L_REG (5) + 1);
2261 SET_L_REG (6, GET_L_REG (6) + 1);
2268 case O (O_EEPMOV
, SB
): /* eepmov.b */
2269 case O (O_EEPMOV
, SW
): /* eepmov.w */
2270 if (h8300hmode
|| h8300smode
)
2272 register unsigned char *_src
, *_dst
;
2273 unsigned int count
= ((code
->opcode
== O (O_EEPMOV
, SW
))
2274 ? h8_get_reg (sd
, R4_REGNUM
) & 0xffff
2275 : h8_get_reg (sd
, R4_REGNUM
) & 0xff);
2277 _src
= (h8_get_reg (sd
, R5_REGNUM
) < memory_size
2278 ? h8_get_memory_buf (sd
) + h8_get_reg (sd
, R5_REGNUM
)
2279 : h8_get_eightbit_buf (sd
) +
2280 (h8_get_reg (sd
, R5_REGNUM
) & 0xff));
2281 if ((_src
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2283 if ((_src
+ count
) >= (h8_get_eightbit_buf (sd
) + 0x100))
2286 _dst
= (h8_get_reg (sd
, R6_REGNUM
) < memory_size
2287 ? h8_get_memory_buf (sd
) + h8_get_reg (sd
, R6_REGNUM
)
2288 : h8_get_eightbit_buf (sd
) +
2289 (h8_get_reg (sd
, R6_REGNUM
) & 0xff));
2291 if ((_dst
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2293 if ((_dst
+ count
) >= (h8_get_eightbit_buf (sd
) + 0x100))
2296 memcpy (_dst
, _src
, count
);
2298 h8_set_reg (sd
, R5_REGNUM
, h8_get_reg (sd
, R5_REGNUM
) + count
);
2299 h8_set_reg (sd
, R6_REGNUM
, h8_get_reg (sd
, R6_REGNUM
) + count
);
2300 h8_set_reg (sd
, R4_REGNUM
, h8_get_reg (sd
, R4_REGNUM
) &
2301 ((code
->opcode
== O (O_EEPMOV
, SW
))
2302 ? (~0xffff) : (~0xff)));
2303 cycles
+= 2 * count
;
2308 case O (O_ADDS
, SL
): /* adds (.l) */
2310 * This insn only uses register operands, but still
2311 * it would be cleaner to use fetch and store... */
2312 SET_L_REG (code
->dst
.reg
,
2313 GET_L_REG (code
->dst
.reg
)
2314 + code
->src
.literal
);
2318 case O (O_SUBS
, SL
): /* subs (.l) */
2320 * This insn only uses register operands, but still
2321 * it would be cleaner to use fetch and store... */
2322 SET_L_REG (code
->dst
.reg
,
2323 GET_L_REG (code
->dst
.reg
)
2324 - code
->src
.literal
);
2327 case O (O_CMP
, SB
): /* cmp.b */
2328 if (fetch (sd
, &code
->dst
, &rd
))
2330 if (fetch (sd
, &code
->src
, &ea
))
2334 goto just_flags_alu8
;
2336 case O (O_CMP
, SW
): /* cmp.w */
2337 if (fetch (sd
, &code
->dst
, &rd
))
2339 if (fetch (sd
, &code
->src
, &ea
))
2343 goto just_flags_alu16
;
2345 case O (O_CMP
, SL
): /* cmp.l */
2346 if (fetch (sd
, &code
->dst
, &rd
))
2348 if (fetch (sd
, &code
->src
, &ea
))
2352 goto just_flags_alu32
;
2354 case O (O_DEC
, SB
): /* dec.b */
2356 * This insn only uses register operands, but still
2357 * it would be cleaner to use fetch and store... */
2358 rd
= GET_B_REG (code
->src
.reg
);
2361 SET_B_REG (code
->src
.reg
, res
);
2362 goto just_flags_inc8
;
2364 case O (O_DEC
, SW
): /* dec.w */
2366 * This insn only uses register operands, but still
2367 * it would be cleaner to use fetch and store... */
2368 rd
= GET_W_REG (code
->dst
.reg
);
2369 ea
= -code
->src
.literal
;
2371 SET_W_REG (code
->dst
.reg
, res
);
2372 goto just_flags_inc16
;
2374 case O (O_DEC
, SL
): /* dec.l */
2376 * This insn only uses register operands, but still
2377 * it would be cleaner to use fetch and store... */
2378 rd
= GET_L_REG (code
->dst
.reg
);
2379 ea
= -code
->src
.literal
;
2381 SET_L_REG (code
->dst
.reg
, res
);
2382 goto just_flags_inc32
;
2384 case O (O_INC
, SB
): /* inc.b */
2386 * This insn only uses register operands, but still
2387 * it would be cleaner to use fetch and store... */
2388 rd
= GET_B_REG (code
->src
.reg
);
2391 SET_B_REG (code
->src
.reg
, res
);
2392 goto just_flags_inc8
;
2394 case O (O_INC
, SW
): /* inc.w */
2396 * This insn only uses register operands, but still
2397 * it would be cleaner to use fetch and store... */
2398 rd
= GET_W_REG (code
->dst
.reg
);
2399 ea
= code
->src
.literal
;
2401 SET_W_REG (code
->dst
.reg
, res
);
2402 goto just_flags_inc16
;
2404 case O (O_INC
, SL
): /* inc.l */
2406 * This insn only uses register operands, but still
2407 * it would be cleaner to use fetch and store... */
2408 rd
= GET_L_REG (code
->dst
.reg
);
2409 ea
= code
->src
.literal
;
2411 SET_L_REG (code
->dst
.reg
, res
);
2412 goto just_flags_inc32
;
2414 case O (O_LDC
, SB
): /* ldc.b */
2415 if (fetch (sd
, &code
->src
, &res
))
2419 case O (O_LDC
, SW
): /* ldc.w */
2420 if (fetch (sd
, &code
->src
, &res
))
2423 /* Word operand, value from MSB, must be shifted. */
2427 case O (O_LDC
, SL
): /* ldc.l */
2428 if (fetch (sd
, &code
->src
, &res
))
2430 switch (code
->dst
.type
) {
2431 case X (OP_SBR
, SL
):
2432 h8_set_sbr (sd
, res
);
2434 case X (OP_VBR
, SL
):
2435 h8_set_vbr (sd
, res
);
2442 case O (O_STC
, SW
): /* stc.w */
2443 case O (O_STC
, SB
): /* stc.b */
2444 if (code
->src
.type
== X (OP_CCR
, SB
))
2447 res
= h8_get_ccr (sd
);
2449 else if (code
->src
.type
== X (OP_EXR
, SB
) && h8300smode
)
2452 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2453 res
= h8_get_exr (sd
);
2458 /* Word operand, value to MSB, must be shifted. */
2459 if (code
->opcode
== X (O_STC
, SW
))
2461 if (store (sd
, &code
->dst
, res
))
2464 case O (O_STC
, SL
): /* stc.l */
2465 switch (code
->src
.type
) {
2466 case X (OP_SBR
, SL
):
2467 res
= h8_get_sbr (sd
);
2469 case X (OP_VBR
, SL
):
2470 res
= h8_get_vbr (sd
);
2475 if (store (sd
, &code
->dst
, res
))
2479 case O (O_ANDC
, SB
): /* andc.b */
2480 if (code
->dst
.type
== X (OP_CCR
, SB
))
2483 rd
= h8_get_ccr (sd
);
2485 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2488 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2489 res
= h8_get_exr (sd
);
2493 ea
= code
->src
.literal
;
2497 case O (O_ORC
, SB
): /* orc.b */
2498 if (code
->dst
.type
== X (OP_CCR
, SB
))
2501 rd
= h8_get_ccr (sd
);
2503 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2506 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2507 rd
= h8_get_exr (sd
);
2511 ea
= code
->src
.literal
;
2515 case O (O_XORC
, SB
): /* xorc.b */
2516 if (code
->dst
.type
== X (OP_CCR
, SB
))
2519 rd
= h8_get_ccr (sd
);
2521 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2524 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2525 rd
= h8_get_exr (sd
);
2529 ea
= code
->src
.literal
;
2533 case O (O_BRAS
, SB
): /* bra/s */
2534 /* This is basically an ordinary branch, with a delay slot. */
2535 if (fetch (sd
, &code
->src
, &res
))
2543 /* Execution continues at next instruction, but
2544 delayed_branch is set up for next cycle. */
2545 h8_set_delayed_branch (sd
, code
->next_pc
+ res
);
2549 case O (O_BRAB
, SB
): /* bra rd.b */
2550 case O (O_BRAW
, SW
): /* bra rd.w */
2551 case O (O_BRAL
, SL
): /* bra erd.l */
2552 if (fetch (sd
, &code
->src
, &rd
))
2554 switch (OP_SIZE (code
->opcode
)) {
2555 case SB
: rd
&= 0xff; break;
2556 case SW
: rd
&= 0xffff; break;
2557 case SL
: rd
&= 0xffffffff; break;
2559 pc
= code
->next_pc
+ rd
;
2562 case O (O_BRABC
, SB
): /* bra/bc, branch if bit clear */
2563 case O (O_BRABS
, SB
): /* bra/bs, branch if bit set */
2564 case O (O_BSRBC
, SB
): /* bsr/bc, call if bit clear */
2565 case O (O_BSRBS
, SB
): /* bsr/bs, call if bit set */
2566 if (fetch (sd
, &code
->dst
, &rd
) ||
2567 fetch (sd
, &code
->src
, &bit
))
2570 if (code
->opcode
== O (O_BRABC
, SB
) || /* branch if clear */
2571 code
->opcode
== O (O_BSRBC
, SB
)) /* call if clear */
2573 if ((rd
& (1 << bit
))) /* no branch */
2576 else /* branch/call if set */
2578 if (!(rd
& (1 << bit
))) /* no branch */
2582 if (fetch (sd
, &code
->op3
, &res
)) /* branch */
2584 pc
= code
->next_pc
+ res
;
2586 if (code
->opcode
== O (O_BRABC
, SB
) ||
2587 code
->opcode
== O (O_BRABS
, SB
)) /* branch */
2595 case O (O_BRA
, SB
): /* bra, branch always */
2600 case O (O_BRN
, SB
): /* brn, ;-/ branch never? */
2605 case O (O_BHI
, SB
): /* bhi */
2611 case O (O_BLS
, SB
): /* bls */
2616 case O (O_BCS
, SB
): /* bcs, branch if carry set */
2621 case O (O_BCC
, SB
): /* bcc, branch if carry clear */
2626 case O (O_BEQ
, SB
): /* beq, branch if zero set */
2630 case O (O_BGT
, SB
): /* bgt */
2631 if (((Z
|| (N
^ V
)) == 0))
2635 case O (O_BLE
, SB
): /* ble */
2636 if (((Z
|| (N
^ V
)) == 1))
2640 case O (O_BGE
, SB
): /* bge */
2644 case O (O_BLT
, SB
): /* blt */
2648 case O (O_BMI
, SB
): /* bmi */
2652 case O (O_BNE
, SB
): /* bne, branch if zero clear */
2657 case O (O_BPL
, SB
): /* bpl */
2661 case O (O_BVC
, SB
): /* bvc */
2665 case O (O_BVS
, SB
): /* bvs */
2670 /* Trap for Command Line setup. */
2671 case O (O_SYS_CMDLINE
, SB
):
2673 int i
= 0; /* Loop counter. */
2674 int j
= 0; /* Loop counter. */
2675 int ind_arg_len
= 0; /* Length of each argument. */
2676 int no_of_args
= 0; /* The no. or cmdline args. */
2677 int current_location
= 0; /* Location of string. */
2678 int old_sp
= 0; /* The Initial Stack Pointer. */
2679 int no_of_slots
= 0; /* No. of slots required on the stack
2680 for storing cmdline args. */
2681 int sp_move
= 0; /* No. of locations by which the stack needs
2683 int new_sp
= 0; /* The final stack pointer location passed
2685 int *argv_ptrs
; /* Pointers of argv strings to be stored. */
2686 int argv_ptrs_location
= 0; /* Location of pointers to cmdline
2687 args on the stack. */
2688 int char_ptr_size
= 0; /* Size of a character pointer on
2690 int addr_cmdline
= 0; /* Memory location where cmdline has
2692 int size_cmdline
= 0; /* Size of cmdline. */
2694 /* Set the address of 256 free locations where command line is
2696 addr_cmdline
= cmdline_location();
2697 h8_set_reg (sd
, 0, addr_cmdline
);
2699 /* Counting the no. of commandline arguments. */
2700 for (i
= 0; h8_get_cmdline_arg (sd
, i
) != NULL
; i
++)
2703 /* No. of arguments in the command line. */
2706 /* Current location is just a temporary variable,which we are
2707 setting to the point to the start of our commandline string. */
2708 current_location
= addr_cmdline
;
2710 /* Allocating space for storing pointers of the command line
2712 argv_ptrs
= (int *) malloc (sizeof (int) * no_of_args
);
2714 /* Setting char_ptr_size to the sizeof (char *) on the different
2716 if (h8300hmode
|| h8300smode
)
2725 for (i
= 0; i
< no_of_args
; i
++)
2729 /* The size of the commandline argument. */
2730 ind_arg_len
= strlen (h8_get_cmdline_arg (sd
, i
) + 1);
2732 /* The total size of the command line string. */
2733 size_cmdline
+= ind_arg_len
;
2735 /* As we have only 256 bytes, we need to provide a graceful
2736 exit. Anyways, a program using command line arguments
2737 where we cannot store all the command line arguments
2738 given may behave unpredictably. */
2739 if (size_cmdline
>= 256)
2741 h8_set_reg (sd
, 0, 0);
2746 /* current_location points to the memory where the next
2747 commandline argument is stored. */
2748 argv_ptrs
[i
] = current_location
;
2749 for (j
= 0; j
< ind_arg_len
; j
++)
2751 SET_MEMORY_B ((current_location
+
2752 (sizeof (char) * j
)),
2753 *(h8_get_cmdline_arg (sd
, i
) +
2754 sizeof (char) * j
));
2757 /* Setting current_location to the starting of next
2759 current_location
+= ind_arg_len
;
2763 /* This is the original position of the stack pointer. */
2764 old_sp
= h8_get_reg (sd
, SP_REGNUM
);
2766 /* We need space from the stack to store the pointers to argvs. */
2767 /* As we will infringe on the stack, we need to shift the stack
2768 pointer so that the data is not overwritten. We calculate how
2769 much space is required. */
2770 sp_move
= (no_of_args
) * (char_ptr_size
);
2772 /* The final position of stack pointer, we have thus taken some
2773 space from the stack. */
2774 new_sp
= old_sp
- sp_move
;
2776 /* Temporary variable holding value where the argv pointers need
2778 argv_ptrs_location
= new_sp
;
2780 /* The argv pointers are stored at sequential locations. As per
2782 for (i
= 0; i
< no_of_args
; i
++)
2784 /* Saving the argv pointer. */
2785 if (h8300hmode
|| h8300smode
)
2787 SET_MEMORY_L (argv_ptrs_location
, argv_ptrs
[i
]);
2791 SET_MEMORY_W (argv_ptrs_location
, argv_ptrs
[i
]);
2794 /* The next location where the pointer to the next argv
2795 string has to be stored. */
2796 argv_ptrs_location
+= char_ptr_size
;
2799 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2801 if (h8300hmode
|| h8300smode
)
2803 SET_MEMORY_L (old_sp
, 0x0);
2807 SET_MEMORY_W (old_sp
, 0x0);
2810 /* Freeing allocated memory. */
2812 for (i
= 0; i
<= no_of_args
; i
++)
2814 free (h8_get_cmdline_arg (sd
, i
));
2816 free (h8_get_command_line (sd
));
2818 /* The no. of argv arguments are returned in Reg 0. */
2819 h8_set_reg (sd
, 0, no_of_args
);
2820 /* The Pointer to argv in Register 1. */
2821 h8_set_reg (sd
, 1, new_sp
);
2822 /* Setting the stack pointer to the new value. */
2823 h8_set_reg (sd
, SP_REGNUM
, new_sp
);
2827 /* System call processing starts. */
2828 case O (O_SYS_OPEN
, SB
):
2830 int len
= 0; /* Length of filename. */
2831 char *filename
; /* Filename would go here. */
2832 char temp_char
; /* Temporary character */
2833 int mode
= 0; /* Mode bits for the file. */
2834 int open_return
; /* Return value of open, file descriptor. */
2835 int i
; /* Loop counter */
2836 int filename_ptr
; /* Pointer to filename in cpu memory. */
2838 /* Setting filename_ptr to first argument of open, */
2839 /* and trying to get mode. */
2840 if (h8300sxmode
|| h8300hmode
|| h8300smode
)
2842 filename_ptr
= GET_L_REG (0);
2843 mode
= GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
) + 4);
2847 filename_ptr
= GET_W_REG (0);
2848 mode
= GET_MEMORY_W (h8_get_reg (sd
, SP_REGNUM
) + 2);
2851 /* Trying to find the length of the filename. */
2852 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2855 while (temp_char
!= '\0')
2857 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2861 /* Allocating space for the filename. */
2862 filename
= (char *) malloc (sizeof (char) * len
);
2864 /* String copying the filename from memory. */
2865 for (i
= 0; i
< len
; i
++)
2867 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2868 filename
[i
] = temp_char
;
2871 /* Callback to open and return the file descriptor. */
2872 open_return
= sim_callback
->open (sim_callback
, filename
, mode
);
2874 /* Return value in register 0. */
2875 h8_set_reg (sd
, 0, open_return
);
2877 /* Freeing memory used for filename. */
2882 case O (O_SYS_READ
, SB
):
2884 char *char_ptr
; /* Where characters read would be stored. */
2885 int fd
; /* File descriptor */
2886 int buf_size
; /* BUF_SIZE parameter in read. */
2887 int i
= 0; /* Temporary Loop counter */
2888 int read_return
= 0; /* Return value from callback to
2891 fd
= h8300hmode
? GET_L_REG (0) : GET_W_REG (0);
2892 buf_size
= h8300hmode
? GET_L_REG (2) : GET_W_REG (2);
2894 char_ptr
= (char *) malloc (sizeof (char) * buf_size
);
2896 /* Callback to read and return the no. of characters read. */
2898 sim_callback
->read (sim_callback
, fd
, char_ptr
, buf_size
);
2900 /* The characters read are stored in cpu memory. */
2901 for (i
= 0; i
< buf_size
; i
++)
2903 SET_MEMORY_B ((h8_get_reg (sd
, 1) + (sizeof (char) * i
)),
2904 *(char_ptr
+ (sizeof (char) * i
)));
2907 /* Return value in Register 0. */
2908 h8_set_reg (sd
, 0, read_return
);
2910 /* Freeing memory used as buffer. */
2915 case O (O_SYS_WRITE
, SB
):
2917 int fd
; /* File descriptor */
2918 char temp_char
; /* Temporary character */
2919 int len
; /* Length of write, Parameter II to write. */
2920 int char_ptr
; /* Character Pointer, Parameter I of write. */
2921 char *ptr
; /* Where characters to be written are stored.
2923 int write_return
; /* Return value from callback to write. */
2924 int i
= 0; /* Loop counter */
2926 fd
= h8300hmode
? GET_L_REG (0) : GET_W_REG (0);
2927 char_ptr
= h8300hmode
? GET_L_REG (1) : GET_W_REG (1);
2928 len
= h8300hmode
? GET_L_REG (2) : GET_W_REG (2);
2930 /* Allocating space for the characters to be written. */
2931 ptr
= (char *) malloc (sizeof (char) * len
);
2933 /* Fetching the characters from cpu memory. */
2934 for (i
= 0; i
< len
; i
++)
2936 temp_char
= GET_MEMORY_B (char_ptr
+ i
);
2940 /* Callback write and return the no. of characters written. */
2941 write_return
= sim_callback
->write (sim_callback
, fd
, ptr
, len
);
2943 /* Return value in Register 0. */
2944 h8_set_reg (sd
, 0, write_return
);
2946 /* Freeing memory used as buffer. */
2951 case O (O_SYS_LSEEK
, SB
):
2953 int fd
; /* File descriptor */
2954 int offset
; /* Offset */
2955 int origin
; /* Origin */
2956 int lseek_return
; /* Return value from callback to lseek. */
2958 fd
= h8300hmode
? GET_L_REG (0) : GET_W_REG (0);
2959 offset
= h8300hmode
? GET_L_REG (1) : GET_W_REG (1);
2960 origin
= h8300hmode
? GET_L_REG (2) : GET_W_REG (2);
2962 /* Callback lseek and return offset. */
2964 sim_callback
->lseek (sim_callback
, fd
, offset
, origin
);
2966 /* Return value in register 0. */
2967 h8_set_reg (sd
, 0, lseek_return
);
2971 case O (O_SYS_CLOSE
, SB
):
2973 int fd
; /* File descriptor */
2974 int close_return
; /* Return value from callback to close. */
2976 fd
= h8300hmode
? GET_L_REG (0) : GET_W_REG (0);
2978 /* Callback close and return. */
2979 close_return
= sim_callback
->close (sim_callback
, fd
);
2981 /* Return value in register 0. */
2982 h8_set_reg (sd
, 0, close_return
);
2986 case O (O_SYS_FSTAT
, SB
):
2988 int fd
; /* File descriptor */
2989 struct stat stat_rec
; /* Stat record */
2990 int fstat_return
; /* Return value from callback to stat. */
2991 int stat_ptr
; /* Pointer to stat record. */
2992 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2994 fd
= h8300hmode
? GET_L_REG (0) : GET_W_REG (0);
2996 /* Setting stat_ptr to second argument of stat. */
2997 stat_ptr
= h8300hmode
? GET_L_REG (1) : GET_W_REG (1);
2999 /* Callback stat and return. */
3000 fstat_return
= sim_callback
->fstat (sim_callback
, fd
, &stat_rec
);
3002 /* Have stat_ptr point to starting of stat_rec. */
3003 temp_stat_ptr
= (char *) (&stat_rec
);
3005 /* Setting up the stat structure returned. */
3006 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
3008 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
3010 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
3012 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
3014 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
3016 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
3018 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
3020 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
3022 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
3024 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
3026 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
3028 /* Return value in register 0. */
3029 h8_set_reg (sd
, 0, fstat_return
);
3033 case O (O_SYS_STAT
, SB
):
3035 int len
= 0; /* Length of filename. */
3036 char *filename
; /* Filename would go here. */
3037 char temp_char
; /* Temporary character */
3038 int filename_ptr
; /* Pointer to filename in cpu memory. */
3039 struct stat stat_rec
; /* Stat record */
3040 int stat_return
; /* Return value from callback to stat */
3041 int stat_ptr
; /* Pointer to stat record. */
3042 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
3043 int i
= 0; /* Loop Counter */
3045 /* Setting filename_ptr to first argument of open. */
3046 filename_ptr
= h8300hmode
? GET_L_REG (0) : GET_W_REG (0);
3048 /* Trying to find the length of the filename. */
3049 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
3052 while (temp_char
!= '\0')
3054 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
3058 /* Allocating space for the filename. */
3059 filename
= (char *) malloc (sizeof (char) * len
);
3061 /* String copying the filename from memory. */
3062 for (i
= 0; i
< len
; i
++)
3064 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
3065 filename
[i
] = temp_char
;
3068 /* Setting stat_ptr to second argument of stat. */
3069 /* stat_ptr = h8_get_reg (sd, 1); */
3070 stat_ptr
= h8300hmode
? GET_L_REG (1) : GET_W_REG (1);
3072 /* Callback stat and return. */
3074 sim_callback
->stat (sim_callback
, filename
, &stat_rec
);
3076 /* Have stat_ptr point to starting of stat_rec. */
3077 temp_stat_ptr
= (char *) (&stat_rec
);
3079 /* Freeing memory used for filename. */
3082 /* Setting up the stat structure returned. */
3083 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
3085 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
3087 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
3089 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
3091 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
3093 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
3095 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
3097 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
3099 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
3101 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
3103 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
3105 /* Return value in register 0. */
3106 h8_set_reg (sd
, 0, stat_return
);
3109 /* End of system call processing. */
3111 case O (O_NOT
, SB
): /* not.b */
3112 if (fetch2 (sd
, &code
->src
, &rd
))
3118 case O (O_NOT
, SW
): /* not.w */
3119 if (fetch2 (sd
, &code
->src
, &rd
))
3125 case O (O_NOT
, SL
): /* not.l */
3126 if (fetch2 (sd
, &code
->src
, &rd
))
3132 case O (O_SHLL
, SB
): /* shll.b */
3133 case O (O_SHLR
, SB
): /* shlr.b */
3134 if (fetch2 (sd
, &code
->dst
, &rd
))
3137 if (code
->src
.type
== X (OP_IMM
, SB
))
3138 fetch (sd
, &code
->src
, &ea
);
3142 if (code
->opcode
== O (O_SHLL
, SB
))
3145 c
= rd
& (0x80 >> (ea
- 1));
3151 c
= rd
& (1 << (ea
- 1));
3152 rd
= (unsigned char) rd
>> ea
;
3156 case O (O_SHLL
, SW
): /* shll.w */
3157 case O (O_SHLR
, SW
): /* shlr.w */
3158 if (fetch2 (sd
, &code
->dst
, &rd
))
3161 if (code
->src
.type
== X (OP_IMM
, SW
))
3162 fetch (sd
, &code
->src
, &ea
);
3166 if (code
->opcode
== O (O_SHLL
, SW
))
3169 c
= rd
& (0x8000 >> (ea
- 1));
3175 c
= rd
& (1 << (ea
- 1));
3176 rd
= (unsigned short) rd
>> ea
;
3180 case O (O_SHLL
, SL
): /* shll.l */
3181 case O (O_SHLR
, SL
): /* shlr.l */
3182 if (fetch2 (sd
, &code
->dst
, &rd
))
3185 if (code
->src
.type
== X (OP_IMM
, SL
))
3186 fetch (sd
, &code
->src
, &ea
);
3190 if (code
->opcode
== O (O_SHLL
, SL
))
3193 c
= rd
& (0x80000000 >> (ea
- 1));
3199 c
= rd
& (1 << (ea
- 1));
3200 rd
= (unsigned int) rd
>> ea
;
3204 case O (O_SHAL
, SB
):
3205 case O (O_SHAR
, SB
):
3206 if (fetch2 (sd
, &code
->dst
, &rd
))
3209 if (code
->src
.type
== X (OP_IMM
, SB
))
3210 fetch (sd
, &code
->src
, &ea
);
3214 if (code
->opcode
== O (O_SHAL
, SB
))
3216 c
= rd
& (0x80 >> (ea
- 1));
3217 res
= rd
>> (7 - ea
);
3218 v
= ((res
& 1) && !(res
& 2))
3219 || (!(res
& 1) && (res
& 2));
3224 c
= rd
& (1 << (ea
- 1));
3226 rd
= ((signed char) rd
) >> ea
;
3230 case O (O_SHAL
, SW
):
3231 case O (O_SHAR
, SW
):
3232 if (fetch2 (sd
, &code
->dst
, &rd
))
3235 if (code
->src
.type
== X (OP_IMM
, SW
))
3236 fetch (sd
, &code
->src
, &ea
);
3240 if (code
->opcode
== O (O_SHAL
, SW
))
3242 c
= rd
& (0x8000 >> (ea
- 1));
3243 res
= rd
>> (15 - ea
);
3244 v
= ((res
& 1) && !(res
& 2))
3245 || (!(res
& 1) && (res
& 2));
3250 c
= rd
& (1 << (ea
- 1));
3252 rd
= ((signed short) rd
) >> ea
;
3256 case O (O_SHAL
, SL
):
3257 case O (O_SHAR
, SL
):
3258 if (fetch2 (sd
, &code
->dst
, &rd
))
3261 if (code
->src
.type
== X (OP_IMM
, SL
))
3262 fetch (sd
, &code
->src
, &ea
);
3266 if (code
->opcode
== O (O_SHAL
, SL
))
3268 c
= rd
& (0x80000000 >> (ea
- 1));
3269 res
= rd
>> (31 - ea
);
3270 v
= ((res
& 1) && !(res
& 2))
3271 || (!(res
& 1) && (res
& 2));
3276 c
= rd
& (1 << (ea
- 1));
3278 rd
= ((signed int) rd
) >> ea
;
3282 case O (O_ROTL
, SB
):
3283 case O (O_ROTR
, SB
):
3284 if (fetch2 (sd
, &code
->dst
, &rd
))
3287 if (code
->src
.type
== X (OP_IMM
, SB
))
3288 fetch (sd
, &code
->src
, &ea
);
3293 if (code
->opcode
== O (O_ROTL
, SB
))
3303 rd
= ((unsigned char) rd
) >> 1;
3311 case O (O_ROTL
, SW
):
3312 case O (O_ROTR
, SW
):
3313 if (fetch2 (sd
, &code
->dst
, &rd
))
3316 if (code
->src
.type
== X (OP_IMM
, SW
))
3317 fetch (sd
, &code
->src
, &ea
);
3322 if (code
->opcode
== O (O_ROTL
, SW
))
3332 rd
= ((unsigned short) rd
) >> 1;
3340 case O (O_ROTL
, SL
):
3341 case O (O_ROTR
, SL
):
3342 if (fetch2 (sd
, &code
->dst
, &rd
))
3345 if (code
->src
.type
== X (OP_IMM
, SL
))
3346 fetch (sd
, &code
->src
, &ea
);
3351 if (code
->opcode
== O (O_ROTL
, SL
))
3353 c
= rd
& 0x80000000;
3361 rd
= ((unsigned int) rd
) >> 1;
3369 case O (O_ROTXL
, SB
):
3370 case O (O_ROTXR
, SB
):
3371 if (fetch2 (sd
, &code
->dst
, &rd
))
3374 if (code
->src
.type
== X (OP_IMM
, SB
))
3375 fetch (sd
, &code
->src
, &ea
);
3380 if (code
->opcode
== O (O_ROTXL
, SB
))
3391 rd
= ((unsigned char) rd
) >> 1;
3400 case O (O_ROTXL
, SW
):
3401 case O (O_ROTXR
, SW
):
3402 if (fetch2 (sd
, &code
->dst
, &rd
))
3405 if (code
->src
.type
== X (OP_IMM
, SW
))
3406 fetch (sd
, &code
->src
, &ea
);
3411 if (code
->opcode
== O (O_ROTXL
, SW
))
3422 rd
= ((unsigned short) rd
) >> 1;
3431 case O (O_ROTXL
, SL
):
3432 case O (O_ROTXR
, SL
):
3433 if (fetch2 (sd
, &code
->dst
, &rd
))
3436 if (code
->src
.type
== X (OP_IMM
, SL
))
3437 fetch (sd
, &code
->src
, &ea
);
3442 if (code
->opcode
== O (O_ROTXL
, SL
))
3444 res
= rd
& 0x80000000;
3453 rd
= ((unsigned int) rd
) >> 1;
3464 case O (O_JMP
, SB
): /* jmp */
3467 fetch (sd
, &code
->src
, &pc
);
3473 case O (O_JSR
, SB
): /* jsr, jump to subroutine */
3477 if (fetch (sd
, &code
->src
, &pc
))
3480 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3485 SET_MEMORY_L (tmp
, code
->next_pc
);
3490 SET_MEMORY_W (tmp
, code
->next_pc
);
3492 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3499 case O (O_BSR
, SB
): /* bsr, branch to subroutine */
3500 if (fetch (sd
, &code
->src
, &res
))
3502 pc
= code
->next_pc
+ res
;
3505 case O (O_RTS
, SN
): /* rts, return from subroutine */
3509 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3513 pc
= GET_MEMORY_L (tmp
);
3518 pc
= GET_MEMORY_W (tmp
);
3522 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3526 case O (O_ILL
, SB
): /* illegal */
3527 sim_engine_set_run_state (sd
, sim_stopped
, SIGILL
);
3530 case O (O_SLEEP
, SN
): /* sleep */
3531 /* Check for magic numbers in r1 and r2. */
3532 if ((h8_get_reg (sd
, R1_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC1
&&
3533 (h8_get_reg (sd
, R2_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC2
&&
3534 SIM_WIFEXITED (h8_get_reg (sd
, 0)))
3536 /* This trap comes from _exit, not from gdb. */
3537 sim_engine_set_run_state (sd
, sim_exited
,
3538 SIM_WEXITSTATUS (h8_get_reg (sd
, 0)));
3542 /* Treat it as a sigtrap. */
3543 sim_engine_set_run_state (sd
, sim_stopped
, SIGTRAP
);
3548 sim_engine_set_run_state (sd
, sim_stopped
, SIGTRAP
);
3551 case O (O_BSETEQ
, SB
):
3556 case O (O_BSETNE
, SB
):
3561 case O (O_BCLREQ
, SB
):
3566 case O (O_BCLRNE
, SB
):
3571 OBITOP (O_BNOT
, 1, 1, ea
^= m
); /* bnot */
3572 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
); /* btst */
3574 OBITOP (O_BSET
, 1, 1, ea
|= m
); /* bset */
3576 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
); /* bclr */
3577 OBITOP (O_BLD
, 1, 0, c
= ea
& m
); /* bld */
3578 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
)); /* bild */
3579 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
3580 if (C
) ea
|= m
); /* bst */
3581 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
3582 if (!C
) ea
|= m
); /* bist */
3583 OBITOP (O_BSTZ
, 1, 1, ea
&= ~m
;
3584 if (Z
) ea
|= m
); /* bstz */
3585 OBITOP (O_BISTZ
, 1, 1, ea
&= ~m
;
3586 if (!Z
) ea
|= m
); /* bistz */
3587 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
); /* band */
3588 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
); /* biand */
3589 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
); /* bor */
3590 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
); /* bior */
3591 OBITOP (O_BXOR
, 1, 0, c
= ((ea
& m
) != 0)!= C
); /* bxor */
3592 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
); /* bixor */
3594 case O (O_BFLD
, SB
): /* bfld */
3597 if (fetch (sd
, &code
->src
, &bit
))
3602 if (fetch (sd
, &code
->dst
, &ea
))
3612 if (store (sd
, &code
->op3
, ea
))
3617 case O(O_BFST
, SB
): /* bfst */
3618 /* bitfield store */
3619 /* NOTE: the imm8 value is in dst, and the ea value
3620 (which is actually the destination) is in op3.
3621 It has to be that way, to avoid breaking the assembler. */
3623 if (fetch (sd
, &code
->dst
, &bit
)) /* imm8 */
3625 if (bit
== 0) /* noop -- nothing to do. */
3628 if (fetch (sd
, &code
->src
, &rd
)) /* reg8 src */
3631 if (fetch2 (sd
, &code
->op3
, &ea
)) /* ea dst */
3634 /* Left-shift the register data into position. */
3635 for (tmp
= bit
; !(tmp
& 1); tmp
>>= 1)
3638 /* Combine it with the neighboring bits. */
3639 ea
= (ea
& ~bit
) | (rd
& bit
);
3642 if (store2 (sd
, &code
->op3
, ea
))
3646 case O (O_CLRMAC
, SN
): /* clrmac */
3647 h8_set_mach (sd
, 0);
3648 h8_set_macl (sd
, 0);
3649 h8_set_macZ (sd
, 1);
3650 h8_set_macV (sd
, 0);
3651 h8_set_macN (sd
, 0);
3654 case O (O_STMAC
, SL
): /* stmac, 260 */
3655 switch (code
->src
.type
) {
3656 case X (OP_MACH
, SL
):
3657 res
= h8_get_mach (sd
);
3658 if (res
& 0x200) /* sign extend */
3661 case X (OP_MACL
, SL
):
3662 res
= h8_get_macl (sd
);
3664 default: goto illegal
;
3666 nz
= !h8_get_macZ (sd
);
3667 n
= h8_get_macN (sd
);
3668 v
= h8_get_macV (sd
);
3670 if (store (sd
, &code
->dst
, res
))
3675 case O (O_LDMAC
, SL
): /* ldmac, 179 */
3676 if (fetch (sd
, &code
->src
, &rd
))
3679 switch (code
->dst
.type
) {
3680 case X (OP_MACH
, SL
):
3681 rd
&= 0x3ff; /* Truncate to 10 bits */
3682 h8_set_mach (sd
, rd
);
3684 case X (OP_MACL
, SL
):
3685 h8_set_macl (sd
, rd
);
3687 default: goto illegal
;
3689 h8_set_macV (sd
, 0);
3693 if (fetch (sd
, &code
->src
, &rd
) ||
3694 fetch (sd
, &code
->dst
, &res
))
3697 /* Ye gods, this is non-portable!
3698 However, the existing mul/div code is similar. */
3699 res
= SEXTSHORT (res
) * SEXTSHORT (rd
);
3701 if (h8_get_macS (sd
)) /* Saturating mode */
3703 long long mac
= h8_get_macl (sd
);
3705 if (mac
& 0x80000000) /* sign extend */
3706 mac
|= 0xffffffff00000000LL
;
3709 if (mac
> 0x7fffffff || mac
< 0xffffffff80000000LL
)
3710 h8_set_macV (sd
, 1);
3711 h8_set_macZ (sd
, (mac
== 0));
3712 h8_set_macN (sd
, (mac
< 0));
3713 h8_set_macl (sd
, (int) mac
);
3715 else /* "Less Saturating" mode */
3717 long long mac
= h8_get_mach (sd
);
3719 mac
+= h8_get_macl (sd
);
3721 if (mac
& 0x20000000000LL
) /* sign extend */
3722 mac
|= 0xfffffc0000000000LL
;
3725 if (mac
> 0x1ffffffffffLL
||
3726 mac
< (long long) 0xfffffe0000000000LL
)
3727 h8_set_macV (sd
, 1);
3728 h8_set_macZ (sd
, (mac
== 0));
3729 h8_set_macN (sd
, (mac
< 0));
3730 h8_set_macl (sd
, (int) mac
);
3732 h8_set_mach (sd
, (int) (mac
& 0x3ff));
3736 case O (O_MULS
, SW
): /* muls.w */
3737 if (fetch (sd
, &code
->src
, &ea
) ||
3738 fetch (sd
, &code
->dst
, &rd
))
3741 /* FIXME: is this the right place to be doing sign extend? */
3742 if (OP_KIND (code
->src
.type
) == OP_IMM
&&
3746 ea
= SEXTSHORT (ea
);
3748 res
= SEXTSHORT (ea
* SEXTSHORT (rd
));
3752 if (store (sd
, &code
->dst
, res
))
3757 case O (O_MULS
, SL
): /* muls.l */
3758 if (fetch (sd
, &code
->src
, &ea
) ||
3759 fetch (sd
, &code
->dst
, &rd
))
3762 /* FIXME: is this the right place to be doing sign extend? */
3763 if (OP_KIND (code
->src
.type
) == OP_IMM
&&
3769 n
= res
& 0x80000000;
3770 nz
= res
& 0xffffffff;
3771 if (store (sd
, &code
->dst
, res
))
3775 case O (O_MULSU
, SL
): /* muls/u.l */
3776 if (fetch (sd
, &code
->src
, &ea
) ||
3777 fetch (sd
, &code
->dst
, &rd
))
3780 /* FIXME: is this the right place to be doing sign extend? */
3781 if (OP_KIND (code
->src
.type
) == OP_IMM
&&
3785 /* Compute upper 32 bits of the 64-bit result. */
3786 res
= (((long long) ea
) * ((long long) rd
)) >> 32;
3788 n
= res
& 0x80000000;
3789 nz
= res
& 0xffffffff;
3790 if (store (sd
, &code
->dst
, res
))
3794 case O (O_MULU
, SW
): /* mulu.w */
3795 if (fetch (sd
, &code
->src
, &ea
) ||
3796 fetch (sd
, &code
->dst
, &rd
))
3799 res
= UEXTSHORT ((UEXTSHORT (ea
) * UEXTSHORT (rd
)));
3801 /* Don't set Z or N. */
3802 if (store (sd
, &code
->dst
, res
))
3807 case O (O_MULU
, SL
): /* mulu.l */
3808 if (fetch (sd
, &code
->src
, &ea
) ||
3809 fetch (sd
, &code
->dst
, &rd
))
3814 /* Don't set Z or N. */
3815 if (store (sd
, &code
->dst
, res
))
3820 case O (O_MULUU
, SL
): /* mulu/u.l */
3821 if (fetch (sd
, &code
->src
, &ea
) ||
3822 fetch (sd
, &code
->dst
, &rd
))
3825 /* Compute upper 32 bits of the 64-bit result. */
3826 res
= (((unsigned long long) (unsigned) ea
) *
3827 ((unsigned long long) (unsigned) rd
)) >> 32;
3829 /* Don't set Z or N. */
3830 if (store (sd
, &code
->dst
, res
))
3835 case O (O_MULXS
, SB
): /* mulxs.b */
3836 if (fetch (sd
, &code
->src
, &ea
) ||
3837 fetch (sd
, &code
->dst
, &rd
))
3840 /* FIXME: is this the right place to be doing sign extend? */
3841 if (OP_KIND (code
->src
.type
) == OP_IMM
&&
3847 res
= ea
* SEXTCHAR (rd
);
3851 if (store (sd
, &code
->dst
, res
))
3856 case O (O_MULXS
, SW
): /* mulxs.w */
3857 if (fetch (sd
, &code
->src
, &ea
) ||
3858 fetch (sd
, &code
->dst
, &rd
))
3861 /* FIXME: is this the right place to be doing sign extend? */
3862 if (OP_KIND (code
->src
.type
) == OP_IMM
&&
3866 ea
= SEXTSHORT (ea
);
3868 res
= ea
* SEXTSHORT (rd
& 0xffff);
3870 n
= res
& 0x80000000;
3871 nz
= res
& 0xffffffff;
3872 if (store (sd
, &code
->dst
, res
))
3877 case O (O_MULXU
, SB
): /* mulxu.b */
3878 if (fetch (sd
, &code
->src
, &ea
) ||
3879 fetch (sd
, &code
->dst
, &rd
))
3882 res
= UEXTCHAR (ea
) * UEXTCHAR (rd
);
3884 if (store (sd
, &code
->dst
, res
))
3889 case O (O_MULXU
, SW
): /* mulxu.w */
3890 if (fetch (sd
, &code
->src
, &ea
) ||
3891 fetch (sd
, &code
->dst
, &rd
))
3894 res
= UEXTSHORT (ea
) * UEXTSHORT (rd
);
3896 if (store (sd
, &code
->dst
, res
))
3901 case O (O_TAS
, SB
): /* tas, (test and set?) */
3902 if (!h8300smode
|| code
->src
.type
!= X (OP_REG
, SL
))
3904 switch (code
->src
.reg
)
3914 if (fetch (sd
, &code
->src
, &res
))
3916 if (store (sd
, &code
->src
, res
| 0x80))
3919 goto just_flags_log8
;
3921 case O (O_DIVU
, SW
): /* divu.w */
3922 if (fetch (sd
, &code
->src
, &ea
) ||
3923 fetch (sd
, &code
->dst
, &rd
))
3929 res
= (unsigned) (UEXTSHORT (rd
) / UEXTSHORT (ea
));
3933 if (store (sd
, &code
->dst
, res
))
3937 case O (O_DIVU
, SL
): /* divu.l */
3938 if (fetch (sd
, &code
->src
, &ea
) ||
3939 fetch (sd
, &code
->dst
, &rd
))
3942 n
= ea
& 0x80000000;
3943 nz
= ea
& 0xffffffff;
3945 res
= (unsigned) rd
/ ea
;
3949 if (store (sd
, &code
->dst
, res
))
3953 case O (O_DIVS
, SW
): /* divs.w */
3954 if (fetch (sd
, &code
->src
, &ea
) ||
3955 fetch (sd
, &code
->dst
, &rd
))
3958 /* FIXME: is this the right place to be doing sign extend? */
3959 if (OP_KIND (code
->src
.type
) == OP_IMM
&&
3965 res
= SEXTSHORT (rd
) / SEXTSHORT (ea
);
3975 if (store (sd
, &code
->dst
, res
))
3979 case O (O_DIVS
, SL
): /* divs.l */
3980 if (fetch (sd
, &code
->src
, &ea
) ||
3981 fetch (sd
, &code
->dst
, &rd
))
3984 /* FIXME: is this the right place to be doing sign extend? */
3985 if (OP_KIND (code
->src
.type
) == OP_IMM
&&
4000 n
= res
& 0x80000000;
4001 if (store (sd
, &code
->dst
, res
))
4005 case O (O_DIVXU
, SB
): /* divxu.b */
4006 if (fetch (sd
, &code
->src
, &ea
) ||
4007 fetch (sd
, &code
->dst
, &rd
))
4010 rd
= UEXTSHORT (rd
);
4017 tmp
= (unsigned) rd
% ea
;
4018 res
= (unsigned) rd
/ ea
;
4026 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 8)))
4030 case O (O_DIVXU
, SW
): /* divxu.w */
4031 if (fetch (sd
, &code
->src
, &ea
) ||
4032 fetch (sd
, &code
->dst
, &rd
))
4035 ea
= UEXTSHORT (ea
);
4041 tmp
= (unsigned) rd
% ea
;
4042 res
= (unsigned) rd
/ ea
;
4050 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
4054 case O (O_DIVXS
, SB
): /* divxs.b */
4055 if (fetch (sd
, &code
->src
, &ea
) ||
4056 fetch (sd
, &code
->dst
, &rd
))
4059 rd
= SEXTSHORT (rd
);
4061 /* FIXME: is this the right place to be doing sign extend? */
4062 if (OP_KIND (code
->src
.type
) == OP_IMM
&&
4070 tmp
= (int) rd
% (int) ea
;
4071 res
= (int) rd
/ (int) ea
;
4082 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
4086 case O (O_DIVXS
, SW
): /* divxs.w */
4087 if (fetch (sd
, &code
->src
, &ea
) ||
4088 fetch (sd
, &code
->dst
, &rd
))
4091 /* FIXME: is this the right place to be doing sign extend? */
4092 if (OP_KIND (code
->src
.type
) == OP_IMM
&&
4096 ea
= SEXTSHORT (ea
);
4100 tmp
= (int) rd
% (int) ea
;
4101 res
= (int) rd
/ (int) ea
;
4111 n
= res
& 0x80000000;
4112 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
4116 case O (O_EXTS
, SW
): /* exts.w, signed extend */
4117 if (fetch2 (sd
, &code
->dst
, &rd
))
4119 ea
= rd
& 0x80 ? -256 : 0;
4120 res
= (rd
& 0xff) + ea
;
4123 case O (O_EXTS
, SL
): /* exts.l, signed extend */
4124 if (fetch2 (sd
, &code
->dst
, &rd
))
4126 if (code
->src
.type
== X (OP_IMM
, SL
))
4128 if (fetch (sd
, &code
->src
, &ea
))
4131 if (ea
== 2) /* exts.l #2, nn */
4133 /* Sign-extend from 8-bit to 32-bit. */
4134 ea
= rd
& 0x80 ? -256 : 0;
4135 res
= (rd
& 0xff) + ea
;
4139 /* Sign-extend from 16-bit to 32-bit. */
4140 ea
= rd
& 0x8000 ? -65536 : 0;
4141 res
= (rd
& 0xffff) + ea
;
4144 case O (O_EXTU
, SW
): /* extu.w, unsigned extend */
4145 if (fetch2 (sd
, &code
->dst
, &rd
))
4148 res
= (rd
& 0xff) + ea
;
4151 case O (O_EXTU
, SL
): /* extu.l, unsigned extend */
4152 if (fetch2 (sd
, &code
->dst
, &rd
))
4154 if (code
->src
.type
== X (OP_IMM
, SL
))
4156 if (fetch (sd
, &code
->src
, &ea
))
4159 if (ea
== 2) /* extu.l #2, nn */
4161 /* Zero-extend from 8-bit to 32-bit. */
4163 res
= (rd
& 0xff) + ea
;
4167 /* Zero-extend from 16-bit to 32-bit. */
4169 res
= (rd
& 0xffff) + ea
;
4172 case O (O_NOP
, SN
): /* nop */
4175 case O (O_STM
, SL
): /* stm, store to memory */
4177 int nregs
, firstreg
, i
;
4179 nregs
= GET_MEMORY_B (pc
+ 1);
4182 firstreg
= code
->src
.reg
;
4184 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
4186 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) - 4);
4187 SET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
), h8_get_reg (sd
, i
));
4192 case O (O_LDM
, SL
): /* ldm, load from memory */
4194 int nregs
, firstreg
, i
;
4196 nregs
= GET_MEMORY_B (pc
+ 1);
4199 firstreg
= code
->dst
.reg
;
4201 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
4203 h8_set_reg (sd
, i
, GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
)));
4204 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) + 4);
4210 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4211 res
= GET_B_REG (code
->src
.reg
);
4212 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4213 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4214 res
= res
; /* Value added == 0. */
4215 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4216 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4217 res
= res
+ 0x6; /* Value added == 6. */
4218 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4219 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4220 res
= res
+ 0x6; /* Value added == 6. */
4221 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4222 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4223 res
= res
+ 0x60; /* Value added == 60. */
4224 else if (!c
&& (9 <= (res
>> 4) && (res
>> 4) <= 15) &&
4225 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4226 res
= res
+ 0x66; /* Value added == 66. */
4227 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4228 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4229 res
= res
+ 0x66; /* Value added == 66. */
4230 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4231 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4232 res
= res
+ 0x60; /* Value added == 60. */
4233 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4234 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4235 res
= res
+ 0x66; /* Value added == 66. */
4236 else if (c
&& (1 <= (res
>> 4) && (res
>> 4) <= 3) &&
4237 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4238 res
= res
+ 0x66; /* Value added == 66. */
4243 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4244 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch, fetch2... */
4245 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4246 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4247 res
= res
; /* Value added == 0. */
4248 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4249 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4250 res
= res
+ 0xfa; /* Value added == 0xfa. */
4251 else if ( c
&& (7 <= (res
>> 4) && (res
>> 4) <= 15) &&
4252 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4253 res
= res
+ 0xa0; /* Value added == 0xa0. */
4254 else if (c
&& (6 <= (res
>> 4) && (res
>> 4) <= 15) &&
4255 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4256 res
= res
+ 0x9a; /* Value added == 0x9a. */
4262 sim_engine_set_run_state (sd
, sim_stopped
, SIGILL
);
4267 (*sim_callback
->printf_filtered
) (sim_callback
,
4268 "sim_resume: internal error.\n");
4269 sim_engine_set_run_state (sd
, sim_stopped
, SIGILL
);
4273 if (code
->dst
.type
== X (OP_CCR
, SB
) ||
4274 code
->dst
.type
== X (OP_CCR
, SW
))
4276 h8_set_ccr (sd
, res
);
4277 /* Get Status Register (flags). */
4278 c
= (h8_get_ccr (sd
) >> 0) & 1;
4279 v
= (h8_get_ccr (sd
) >> 1) & 1;
4280 nz
= !((h8_get_ccr (sd
) >> 2) & 1);
4281 n
= (h8_get_ccr (sd
) >> 3) & 1;
4282 u
= (h8_get_ccr (sd
) >> 4) & 1;
4283 h
= (h8_get_ccr (sd
) >> 5) & 1;
4284 ui
= ((h8_get_ccr (sd
) >> 6) & 1);
4285 intMaskBit
= (h8_get_ccr (sd
) >> 7) & 1;
4287 else if (h8300smode
&&
4288 (code
->dst
.type
== X (OP_EXR
, SB
) ||
4289 code
->dst
.type
== X (OP_EXR
, SW
)))
4291 h8_set_exr (sd
, res
);
4292 if (h8300smode
) /* Get exr. */
4294 trace
= (h8_get_exr (sd
) >> 7) & 1;
4295 intMask
= h8_get_exr (sd
) & 7;
4304 /* When a branch works */
4305 if (fetch (sd
, &code
->src
, &res
))
4307 if (res
& 1) /* bad address */
4309 pc
= code
->next_pc
+ res
;
4312 /* Set the cond codes from res */
4315 /* Set the flags after an 8 bit inc/dec operation */
4319 v
= (rd
& 0x7f) == 0x7f;
4322 /* Set the flags after an 16 bit inc/dec operation */
4326 v
= (rd
& 0x7fff) == 0x7fff;
4329 /* Set the flags after an 32 bit inc/dec operation */
4331 n
= res
& 0x80000000;
4332 nz
= res
& 0xffffffff;
4333 v
= (rd
& 0x7fffffff) == 0x7fffffff;
4337 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4340 if (store2 (sd
, &code
->dst
, rd
))
4345 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4348 if (store2 (sd
, &code
->dst
, rd
))
4353 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4354 n
= (rd
& 0x80000000);
4355 nz
= rd
& 0xffffffff;
4356 if (store2 (sd
, &code
->dst
, rd
))
4361 if (store2 (sd
, &code
->dst
, res
))
4365 /* flags after a 32bit logical operation */
4366 n
= res
& 0x80000000;
4367 nz
= res
& 0xffffffff;
4372 if (store2 (sd
, &code
->dst
, res
))
4376 /* flags after a 16bit logical operation */
4383 if (store2 (sd
, &code
->dst
, res
))
4393 if (store2 (sd
, &code
->dst
, res
))
4400 switch (code
->opcode
/ 4)
4404 v
= ((rd
& 0x80) == (ea
& 0x80)
4405 && (rd
& 0x80) != (res
& 0x80));
4410 v
= ((rd
& 0x80) != (-ea
& 0x80)
4411 && (rd
& 0x80) != (res
& 0x80));
4418 break; /* No effect on v flag. */
4423 if (store2 (sd
, &code
->dst
, res
))
4429 c
= (res
& 0x10000);
4430 switch (code
->opcode
/ 4)
4434 v
= ((rd
& 0x8000) == (ea
& 0x8000)
4435 && (rd
& 0x8000) != (res
& 0x8000));
4440 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
4441 && (rd
& 0x8000) != (res
& 0x8000));
4450 if (store2 (sd
, &code
->dst
, res
))
4454 n
= res
& 0x80000000;
4455 nz
= res
& 0xffffffff;
4456 switch (code
->opcode
/ 4)
4460 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
4461 && (rd
& 0x80000000) != (res
& 0x80000000));
4462 c
= ((unsigned) res
< (unsigned) rd
) ||
4463 ((unsigned) res
< (unsigned) ea
);
4468 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
4469 && (rd
& 0x80000000) != (res
& 0x80000000));
4470 c
= (unsigned) rd
< (unsigned) -ea
;
4473 v
= (rd
== 0x80000000);
4480 if ((res
= h8_get_delayed_branch (sd
)) != 0)
4483 h8_set_delayed_branch (sd
, 0);
4490 if (--poll_count
< 0)
4492 poll_count
= POLL_QUIT_INTERVAL
;
4493 if ((*sim_callback
->poll_quit
) != NULL
4494 && (*sim_callback
->poll_quit
) (sim_callback
))
4495 sim_engine_set_run_state (sd
, sim_stopped
, SIGINT
);
4497 sim_engine_get_run_state (sd
, &reason
, &sigrc
);
4498 } while (reason
== sim_running
);
4500 h8_set_ticks (sd
, h8_get_ticks (sd
) + get_now () - tick_start
);
4501 h8_set_cycles (sd
, h8_get_cycles (sd
) + cycles
);
4502 h8_set_insts (sd
, h8_get_insts (sd
) + insts
);
4507 h8_set_exr (sd
, (trace
<<7) | intMask
);
4509 h8_set_mask (sd
, oldmask
);
4510 signal (SIGINT
, prev
);
4514 sim_trace (SIM_DESC sd
)
4516 /* FIXME: Unfinished. */
4517 (*sim_callback
->printf_filtered
) (sim_callback
,
4518 "sim_trace: trace not supported.\n");
4519 return 1; /* Done. */
4523 sim_write (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
4530 for (i
= 0; i
< size
; i
++)
4532 if (addr
< memory_size
)
4534 h8_set_memory (sd
, addr
+ i
, buffer
[i
]);
4535 h8_set_cache_idx (sd
, addr
+ i
, 0);
4539 h8_set_eightbit (sd
, (addr
+ i
) & 0xff, buffer
[i
]);
4546 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
4551 if (addr
< memory_size
)
4552 memcpy (buffer
, h8_get_memory_buf (sd
) + addr
, size
);
4554 memcpy (buffer
, h8_get_eightbit_buf (sd
) + (addr
& 0xff), size
);
4560 sim_store_register (SIM_DESC sd
, int rn
, unsigned char *value
, int length
)
4565 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
4566 shortval
= (value
[0] << 8) | (value
[1]);
4567 intval
= h8300hmode
? longval
: shortval
;
4573 (*sim_callback
->printf_filtered
) (sim_callback
,
4574 "sim_store_register: bad regnum %d.\n",
4584 h8_set_reg (sd
, rn
, intval
);
4587 h8_set_pc (sd
, intval
);
4590 h8_set_ccr (sd
, intval
);
4593 h8_set_exr (sd
, intval
);
4596 h8_set_sbr (sd
, intval
);
4599 h8_set_vbr (sd
, intval
);
4602 h8_set_mach (sd
, intval
);
4605 h8_set_macl (sd
, intval
);
4608 h8_set_cycles (sd
, longval
);
4611 h8_set_insts (sd
, longval
);
4614 h8_set_ticks (sd
, longval
);
4621 sim_fetch_register (SIM_DESC sd
, int rn
, unsigned char *buf
, int length
)
4628 if (!h8300smode
&& rn
>= EXR_REGNUM
)
4633 (*sim_callback
->printf_filtered
) (sim_callback
,
4634 "sim_fetch_register: bad regnum %d.\n",
4639 v
= h8_get_ccr (sd
);
4642 v
= h8_get_exr (sd
);
4648 v
= h8_get_sbr (sd
);
4651 v
= h8_get_vbr (sd
);
4654 v
= h8_get_mach (sd
);
4657 v
= h8_get_macl (sd
);
4667 v
= h8_get_reg (sd
, rn
);
4670 v
= h8_get_cycles (sd
);
4674 v
= h8_get_ticks (sd
);
4678 v
= h8_get_insts (sd
);
4682 if (h8300hmode
|| longreg
)
4698 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason
, int *sigrc
)
4700 sim_engine_get_run_state (sd
, reason
, sigrc
);
4703 /* FIXME: Rename to sim_set_mem_size. */
4708 /* Memory size is fixed. */
4712 set_simcache_size (SIM_DESC sd
, int n
)
4715 free (sd
->sim_cache
);
4718 sd
->sim_cache
= (decoded_inst
*) malloc (sizeof (decoded_inst
) * n
);
4719 memset (sd
->sim_cache
, 0, sizeof (decoded_inst
) * n
);
4720 sd
->sim_cache_size
= n
;
4725 sim_info (SIM_DESC sd
, int verbose
)
4727 double timetaken
= (double) h8_get_ticks (sd
) / (double) now_persec ();
4728 double virttime
= h8_get_cycles (sd
) / 10.0e6
;
4730 (*sim_callback
->printf_filtered
) (sim_callback
,
4731 "\n\n#instructions executed %10d\n",
4733 (*sim_callback
->printf_filtered
) (sim_callback
,
4734 "#cycles (v approximate) %10d\n",
4735 h8_get_cycles (sd
));
4736 (*sim_callback
->printf_filtered
) (sim_callback
,
4737 "#real time taken %10.4f\n",
4739 (*sim_callback
->printf_filtered
) (sim_callback
,
4740 "#virtual time taken %10.4f\n",
4742 if (timetaken
!= 0.0)
4743 (*sim_callback
->printf_filtered
) (sim_callback
,
4744 "#simulation ratio %10.4f\n",
4745 virttime
/ timetaken
);
4746 (*sim_callback
->printf_filtered
) (sim_callback
,
4748 h8_get_compiles (sd
));
4749 (*sim_callback
->printf_filtered
) (sim_callback
,
4750 "#cache size %10d\n",
4751 sd
->sim_cache_size
);
4754 /* This to be conditional on `what' (aka `verbose'),
4755 however it was never passed as non-zero. */
4759 for (i
= 0; i
< O_LAST
; i
++)
4761 if (h8_get_stats (sd
, i
))
4762 (*sim_callback
->printf_filtered
) (sim_callback
, "%d: %d\n",
4763 i
, h8_get_stats (sd
, i
));
4769 /* Indicate whether the cpu is an H8/300 or H8/300H.
4770 FLAG is non-zero for the H8/300H. */
4773 set_h8300h (unsigned long machine
)
4775 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4776 This function being replaced by a sim_open:ARGV configuration
4779 if (machine
== bfd_mach_h8300sx
)
4782 if (machine
== bfd_mach_h8300s
|| machine
== bfd_mach_h8300sn
|| h8300sxmode
)
4785 if (machine
== bfd_mach_h8300h
|| machine
== bfd_mach_h8300hn
|| h8300smode
)
4789 /* Cover function of sim_state_free to free the cpu buffers as well. */
4792 free_state (SIM_DESC sd
)
4794 if (STATE_MODULES (sd
) != NULL
)
4795 sim_module_uninstall (sd
);
4797 /* Fixme: free buffers in _sim_cpu. */
4798 sim_state_free (sd
);
4802 sim_open (SIM_OPEN_KIND kind
,
4803 struct host_callback_struct
*callback
,
4810 sd
= sim_state_alloc (kind
, callback
);
4811 sd
->cpu
= sim_cpu_alloc (sd
, 0);
4812 cpu
= STATE_CPU (sd
, 0);
4813 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4814 sim_state_initialize (sd
, cpu
);
4815 /* sim_cpu object is new, so some initialization is needed. */
4816 init_pointers_needed
= 1;
4818 /* For compatibility (FIXME: is this right?). */
4819 current_alignment
= NONSTRICT_ALIGNMENT
;
4820 current_target_byte_order
= BIG_ENDIAN
;
4822 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
4828 /* getopt will print the error message so we just have to exit if
4829 this fails. FIXME: Hmmm... in the case of gdb we need getopt
4830 to call print_filtered. */
4831 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
4833 /* Uninstall the modules to avoid memory leaks,
4834 file descriptor leaks, etc. */
4839 /* Check for/establish the a reference program image. */
4840 if (sim_analyze_program (sd
,
4841 (STATE_PROG_ARGV (sd
) != NULL
4842 ? *STATE_PROG_ARGV (sd
)
4843 : NULL
), abfd
) != SIM_RC_OK
)
4849 /* Establish any remaining configuration options. */
4850 if (sim_config (sd
) != SIM_RC_OK
)
4856 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
4858 /* Uninstall the modules to avoid memory leaks,
4859 file descriptor leaks, etc. */
4864 /* sim_hw_configure (sd); */
4866 /* FIXME: Much of the code in sim_load can be moved here. */
4870 sim_callback
= callback
;
4875 sim_close (SIM_DESC sd
, int quitting
)
4877 /* Nothing to do. */
4880 /* Called by gdb to load a program into memory. */
4883 sim_load (SIM_DESC sd
, char *prog
, bfd
*abfd
, int from_tty
)
4887 /* FIXME: The code below that sets a specific variant of the H8/300
4888 being simulated should be moved to sim_open(). */
4890 /* See if the file is for the H8/300 or H8/300H. */
4891 /* ??? This may not be the most efficient way. The z8k simulator
4892 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
4896 prog_bfd
= bfd_openr (prog
, "coff-h8300");
4897 if (prog_bfd
!= NULL
)
4899 /* Set the cpu type. We ignore failure from bfd_check_format
4900 and bfd_openr as sim_load_file checks too. */
4901 if (bfd_check_format (prog_bfd
, bfd_object
))
4903 set_h8300h (bfd_get_mach (prog_bfd
));
4907 /* If we're using gdb attached to the simulator, then we have to
4908 reallocate memory for the simulator.
4910 When gdb first starts, it calls fetch_registers (among other
4911 functions), which in turn calls init_pointers, which allocates
4914 The problem is when we do that, we don't know whether we're
4915 debugging an H8/300 or H8/300H program.
4917 This is the first point at which we can make that determination,
4918 so we just reallocate memory now; this will also allow us to handle
4919 switching between H8/300 and H8/300H programs without exiting
4923 memory_size
= H8300S_MSIZE
;
4924 else if (h8300hmode
)
4925 memory_size
= H8300H_MSIZE
;
4927 memory_size
= H8300_MSIZE
;
4929 if (h8_get_memory_buf (sd
))
4930 free (h8_get_memory_buf (sd
));
4931 if (h8_get_cache_idx_buf (sd
))
4932 free (h8_get_cache_idx_buf (sd
));
4933 if (h8_get_eightbit_buf (sd
))
4934 free (h8_get_eightbit_buf (sd
));
4936 h8_set_memory_buf (sd
, (unsigned char *)
4937 calloc (sizeof (char), memory_size
));
4938 h8_set_cache_idx_buf (sd
, (unsigned short *)
4939 calloc (sizeof (short), memory_size
));
4940 h8_set_eightbit_buf (sd
, (unsigned char *) calloc (sizeof (char), 256));
4942 /* `msize' must be a power of two. */
4943 if ((memory_size
& (memory_size
- 1)) != 0)
4945 (*sim_callback
->printf_filtered
) (sim_callback
,
4946 "sim_load: bad memory size.\n");
4949 h8_set_mask (sd
, memory_size
- 1);
4951 if (sim_load_file (sd
, myname
, sim_callback
, prog
, prog_bfd
,
4952 sim_kind
== SIM_OPEN_DEBUG
,
4956 /* Close the bfd if we opened it. */
4957 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4958 bfd_close (prog_bfd
);
4962 /* Close the bfd if we opened it. */
4963 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4964 bfd_close (prog_bfd
);
4969 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
, char **argv
, char **env
)
4976 h8_set_pc (sd
, bfd_get_start_address (abfd
));
4980 /* Command Line support. */
4983 /* Counting the no. of commandline arguments. */
4984 for (no_of_args
= 0; argv
[no_of_args
] != NULL
; no_of_args
++)
4987 /* Allocating memory for the argv pointers. */
4988 h8_set_command_line (sd
, (char **) malloc ((sizeof (char *))
4989 * (no_of_args
+ 1)));
4991 for (i
= 0; i
< no_of_args
; i
++)
4993 /* Copying the argument string. */
4994 h8_set_cmdline_arg (sd
, i
, (char *) strdup (argv
[i
]));
4996 h8_set_cmdline_arg (sd
, i
, NULL
);
5003 sim_do_command (SIM_DESC sd
, char *cmd
)
5005 (*sim_callback
->printf_filtered
) (sim_callback
,
5006 "This simulator does not accept any commands.\n");
5010 sim_set_callbacks (struct host_callback_struct
*ptr
)