]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/h8300/compile.c
2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
30 #ifdef HAVE_SYS_PARAM_H
31 #include <sys/param.h>
36 #include "remote-sim.h"
44 host_callback
*sim_callback
;
46 static SIM_OPEN_KIND sim_kind
;
49 /* FIXME: Needs to live in header file.
50 This header should also include the things in remote-sim.h.
51 One could move this to remote-sim.h but this function isn't needed
53 void sim_set_simcache_size
PARAMS ((int));
55 #define X(op, size) op*4+size
57 #define SP (h8300hmode ? SL:SW)
70 #define h8_opcodes ops
72 #include "opcode/h8300.h"
76 /* The rate at which to call the host's poll_quit callback. */
78 #define POLL_QUIT_INTERVAL 0x80000
80 #define LOW_BYTE(x) ((x) & 0xff)
81 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
82 #define P(X,Y) ((X<<8) | Y)
84 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
87 c = (cpu.ccr >> 0) & 1;\
88 v = (cpu.ccr >> 1) & 1;\
89 nz = !((cpu.ccr >> 2) & 1);\
90 n = (cpu.ccr >> 3) & 1;
92 #ifdef __CHAR_IS_SIGNED__
93 #define SEXTCHAR(x) ((char)(x))
97 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
100 #define UEXTCHAR(x) ((x) & 0xff)
101 #define UEXTSHORT(x) ((x) & 0xffff)
102 #define SEXTSHORT(x) ((short)(x))
104 static cpu_state_type cpu
;
109 static int memory_size
;
138 return h8300hmode
? SL
: SW
;
150 return X (OP_IMM
, SP
);
152 return X (OP_REG
, SP
);
155 return X (OP_MEM
, SP
);
163 decode (addr
, data
, dst
)
175 struct h8_opcode
*q
= h8_opcodes
;
181 /* Find the exact opcode/arg combo. */
185 unsigned int len
= 0;
191 op_type looking_for
= *nib
;
192 int thisnib
= data
[len
>> 1];
194 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
196 if (looking_for
< 16 && looking_for
>= 0)
198 if (looking_for
!= thisnib
)
203 if ((int) looking_for
& (int) B31
)
205 if (!(((int) thisnib
& 0x8) != 0))
208 looking_for
= (op_type
) ((int) looking_for
& ~(int) B31
);
212 if ((int) looking_for
& (int) B30
)
214 if (!(((int) thisnib
& 0x8) == 0))
217 looking_for
= (op_type
) ((int) looking_for
& ~(int) B30
);
220 if (looking_for
& DBIT
)
222 if ((looking_for
& 5) != (thisnib
& 5))
225 abs
= (thisnib
& 0x8) ? 2 : 1;
227 else if (looking_for
& (REG
| IND
| INC
| DEC
))
229 if (looking_for
& REG
)
231 /* Can work out size from the register. */
232 size
= bitfrom (looking_for
);
234 if (looking_for
& SRC
)
239 else if (looking_for
& L_16
)
241 abs
= (data
[len
>> 1]) * 256 + data
[(len
+ 2) >> 1];
243 if (looking_for
& (PCREL
| DISP
))
248 else if (looking_for
& ABSJMP
)
250 abs
= (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
252 else if (looking_for
& MEMIND
)
256 else if (looking_for
& L_32
)
260 abs
= (data
[i
] << 24)
261 | (data
[i
+ 1] << 16)
267 else if (looking_for
& L_24
)
271 abs
= (data
[i
] << 16) | (data
[i
+ 1] << 8) | (data
[i
+ 2]);
274 else if (looking_for
& IGNORE
)
278 else if (looking_for
& DISPREG
)
280 rdisp
= thisnib
& 0x7;
282 else if (looking_for
& KBIT
)
297 else if (looking_for
& L_8
)
301 if (looking_for
& PCREL
)
303 abs
= SEXTCHAR (data
[len
>> 1]);
305 else if (looking_for
& ABS8MEM
)
308 abs
= h8300hmode
? ~0xff0000ff : ~0xffff00ff;
309 abs
|= data
[len
>> 1] & 0xff;
313 abs
= data
[len
>> 1] & 0xff;
316 else if (looking_for
& L_3
)
322 else if (looking_for
== E
)
326 /* Fill in the args. */
328 op_type
*args
= q
->args
.nib
;
334 int rn
= (x
& DST
) ? rd
: rs
;
344 p
->type
= X (OP_IMM
, size
);
347 else if (x
& (IMM
| KBIT
| DBIT
))
349 p
->type
= X (OP_IMM
, size
);
354 /* Reset the size, some
355 ops (like mul) have two sizes */
358 p
->type
= X (OP_REG
, size
);
363 p
->type
= X (OP_INC
, size
);
368 p
->type
= X (OP_DEC
, size
);
373 p
->type
= X (OP_DISP
, size
);
377 else if (x
& (ABS
| ABSJMP
| ABS8MEM
))
379 p
->type
= X (OP_DISP
, size
);
385 p
->type
= X (OP_MEM
, size
);
390 p
->type
= X (OP_PCREL
, size
);
391 p
->literal
= abs
+ addr
+ 2;
397 p
->type
= X (OP_IMM
, SP
);
402 p
->type
= X (OP_DISP
, size
);
404 p
->reg
= rdisp
& 0x7;
411 printf ("Hmmmm %x", x
);
417 /* But a jmp or a jsr gets automagically lvalued,
418 since we branch to their address not their
420 if (q
->how
== O (O_JSR
, SB
)
421 || q
->how
== O (O_JMP
, SB
))
423 dst
->src
.type
= lvalue (dst
->src
.type
, dst
->src
.reg
);
426 if (dst
->dst
.type
== -1)
429 dst
->opcode
= q
->how
;
430 dst
->cycles
= q
->time
;
432 /* And a jsr to 0xc4 is turned into a magic trap. */
434 if (dst
->opcode
== O (O_JSR
, SB
))
436 if (dst
->src
.literal
== 0xc4)
438 dst
->opcode
= O (O_SYSCALL
, SB
);
442 dst
->next_pc
= addr
+ len
/ 2;
446 printf ("Don't understand %x \n", looking_for
);
457 /* Fell off the end. */
458 dst
->opcode
= O (O_ILL
, SB
);
466 /* find the next cache entry to use */
468 idx
= cpu
.cache_top
+ 1;
470 if (idx
>= cpu
.csize
)
476 /* Throw away its old meaning */
477 cpu
.cache_idx
[cpu
.cache
[idx
].oldpc
] = 0;
479 /* set to new address */
480 cpu
.cache
[idx
].oldpc
= pc
;
482 /* fill in instruction info */
483 decode (pc
, cpu
.memory
+ pc
, cpu
.cache
+ idx
);
485 /* point to new cache entry */
486 cpu
.cache_idx
[pc
] = idx
;
490 static unsigned char *breg
[18];
491 static unsigned short *wreg
[18];
492 static unsigned int *lreg
[18];
494 #define GET_B_REG(x) *(breg[x])
495 #define SET_B_REG(x,y) (*(breg[x])) = (y)
496 #define GET_W_REG(x) *(wreg[x])
497 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
499 #define GET_L_REG(x) *(lreg[x])
500 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
502 #define GET_MEMORY_L(x) \
504 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
505 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
506 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
507 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
509 #define GET_MEMORY_W(x) \
511 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
512 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
515 #define GET_MEMORY_B(x) \
516 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
518 #define SET_MEMORY_L(x,y) \
519 { register unsigned char *_p; register int __y = y; \
520 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
521 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
522 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
524 #define SET_MEMORY_W(x,y) \
525 { register unsigned char *_p; register int __y = y; \
526 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
527 _p[0] = (__y)>>8; _p[1] =(__y);}
529 #define SET_MEMORY_B(x,y) \
530 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
537 int abs
= arg
->literal
;
544 return GET_B_REG (rn
);
546 return GET_W_REG (rn
);
548 return GET_L_REG (rn
);
559 r
= GET_MEMORY_B (t
);
568 r
= GET_MEMORY_W (t
);
576 r
= GET_MEMORY_L (t
);
583 case X (OP_DISP
, SB
):
584 t
= GET_L_REG (rn
) + abs
;
586 return GET_MEMORY_B (t
);
588 case X (OP_DISP
, SW
):
589 t
= GET_L_REG (rn
) + abs
;
591 return GET_MEMORY_W (t
);
593 case X (OP_DISP
, SL
):
594 t
= GET_L_REG (rn
) + abs
;
596 return GET_MEMORY_L (t
);
599 t
= GET_MEMORY_L (abs
);
604 t
= GET_MEMORY_W (abs
);
622 int abs
= arg
->literal
;
638 t
= GET_L_REG (rn
) - 1;
645 t
= (GET_L_REG (rn
) - 2) & cpu
.mask
;
651 t
= (GET_L_REG (rn
) - 4) & cpu
.mask
;
656 case X (OP_DISP
, SB
):
657 t
= GET_L_REG (rn
) + abs
;
662 case X (OP_DISP
, SW
):
663 t
= GET_L_REG (rn
) + abs
;
668 case X (OP_DISP
, SL
):
669 t
= GET_L_REG (rn
) + abs
;
706 memory_size
= H8300H_MSIZE
;
708 memory_size
= H8300_MSIZE
;
709 cpu
.memory
= (unsigned char *) calloc (sizeof (char), memory_size
);
710 cpu
.cache_idx
= (unsigned short *) calloc (sizeof (short), memory_size
);
711 cpu
.eightbit
= (unsigned char *) calloc (sizeof (char), 256);
713 /* `msize' must be a power of two */
714 if ((memory_size
& (memory_size
- 1)) != 0)
716 cpu
.mask
= memory_size
- 1;
718 for (i
= 0; i
< 9; i
++)
723 for (i
= 0; i
< 8; i
++)
725 unsigned char *p
= (unsigned char *) (cpu
.regs
+ i
);
726 unsigned char *e
= (unsigned char *) (cpu
.regs
+ i
+ 1);
727 unsigned short *q
= (unsigned short *) (cpu
.regs
+ i
);
728 unsigned short *u
= (unsigned short *) (cpu
.regs
+ i
+ 1);
729 cpu
.regs
[i
] = 0x00112233;
755 lreg
[i
] = &cpu
.regs
[i
];
758 lreg
[8] = &cpu
.regs
[8];
760 /* initialize the seg registers */
762 sim_set_simcache_size (CSIZE
);
767 control_c (sig
, code
, scp
, addr
)
773 cpu
.state
= SIM_STATE_STOPPED
;
774 cpu
.exception
= SIGINT
;
783 mop (code
, bsize
, sign
)
796 bsize
? SEXTCHAR (GET_W_REG (code
->dst
.reg
)) :
797 SEXTSHORT (GET_W_REG (code
->dst
.reg
));
799 bsize
? SEXTCHAR (GET_B_REG (code
->src
.reg
)) :
800 SEXTSHORT (GET_W_REG (code
->src
.reg
));
804 multiplicand
= bsize
? UEXTCHAR (GET_W_REG (code
->dst
.reg
)) :
805 UEXTSHORT (GET_W_REG (code
->dst
.reg
));
807 bsize
? UEXTCHAR (GET_B_REG (code
->src
.reg
)) :
808 UEXTSHORT (GET_W_REG (code
->src
.reg
));
811 result
= multiplier
* multiplicand
;
815 n
= result
& (bsize
? 0x8000 : 0x80000000);
816 nz
= result
& (bsize
? 0xffff : 0xffffffff);
820 SET_W_REG (code
->dst
.reg
, result
);
824 SET_L_REG (code
->dst
.reg
, result
);
826 /* return ((n==1) << 1) | (nz==1); */
830 #define ONOT(name, how) \
835 rd = GET_B_REG (code->src.reg); \
843 rd = GET_W_REG (code->src.reg); \
850 int hm = 0x80000000; \
851 rd = GET_L_REG (code->src.reg); \
856 #define OSHIFTS(name, how1, how2) \
861 rd = GET_B_REG (code->src.reg); \
862 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
876 rd = GET_W_REG (code->src.reg); \
877 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
890 int hm = 0x80000000; \
891 rd = GET_L_REG (code->src.reg); \
892 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
903 #define OBITOP(name,f, s, op) \
908 if (f) ea = fetch (&code->dst); \
909 m=1<< fetch(&code->src); \
911 if(s) store (&code->dst,ea); goto next; \
918 cpu
.state
= SIM_STATE_STOPPED
;
919 cpu
.exception
= SIGINT
;
924 sim_resume (sd
, step
, siggnal
)
930 int tick_start
= get_now ();
943 prev
= signal (SIGINT
, control_c
);
947 cpu
.state
= SIM_STATE_STOPPED
;
948 cpu
.exception
= SIGTRAP
;
952 cpu
.state
= SIM_STATE_RUNNING
;
958 /* The PC should never be odd. */
972 cidx
= cpu
.cache_idx
[pc
];
973 code
= cpu
.cache
+ cidx
;
976 #define ALUOP(STORE, NAME, HOW) \
977 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
978 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
979 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
982 #define LOGOP(NAME, HOW) \
983 case O(NAME,SB): HOW; goto log8;\
984 case O(NAME, SW): HOW; goto log16;\
985 case O(NAME,SL): HOW; goto log32;
992 printf ("%x %d %s\n", pc
, code
->opcode
,
993 code
->op
? code
->op
->name
: "**");
995 cpu
.stats
[code
->opcode
]++;
999 cycles
+= code
->cycles
;
1001 switch (code
->opcode
)
1005 * This opcode is a fake for when we get to an
1006 * instruction which hasnt been compiled
1013 case O (O_SUBX
, SB
):
1014 rd
= fetch (&code
->dst
);
1015 ea
= fetch (&code
->src
);
1020 case O (O_ADDX
, SB
):
1021 rd
= fetch (&code
->dst
);
1022 ea
= fetch (&code
->src
);
1027 #define EA ea = fetch(&code->src);
1028 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
1030 ALUOP (1, O_SUB
, RD_EA
;
1033 ALUOP (1, O_NEG
, EA
;
1039 rd
= GET_B_REG (code
->dst
.reg
);
1040 ea
= fetch (&code
->src
);
1044 rd
= GET_W_REG (code
->dst
.reg
);
1045 ea
= fetch (&code
->src
);
1049 rd
= GET_L_REG (code
->dst
.reg
);
1050 ea
= fetch (&code
->src
);
1055 LOGOP (O_AND
, RD_EA
;
1061 LOGOP (O_XOR
, RD_EA
;
1065 case O (O_MOV_TO_MEM
, SB
):
1066 res
= GET_B_REG (code
->src
.reg
);
1068 case O (O_MOV_TO_MEM
, SW
):
1069 res
= GET_W_REG (code
->src
.reg
);
1071 case O (O_MOV_TO_MEM
, SL
):
1072 res
= GET_L_REG (code
->src
.reg
);
1076 case O (O_MOV_TO_REG
, SB
):
1077 res
= fetch (&code
->src
);
1078 SET_B_REG (code
->dst
.reg
, res
);
1079 goto just_flags_log8
;
1080 case O (O_MOV_TO_REG
, SW
):
1081 res
= fetch (&code
->src
);
1082 SET_W_REG (code
->dst
.reg
, res
);
1083 goto just_flags_log16
;
1084 case O (O_MOV_TO_REG
, SL
):
1085 res
= fetch (&code
->src
);
1086 SET_L_REG (code
->dst
.reg
, res
);
1087 goto just_flags_log32
;
1090 case O (O_ADDS
, SL
):
1091 SET_L_REG (code
->dst
.reg
,
1092 GET_L_REG (code
->dst
.reg
)
1093 + code
->src
.literal
);
1097 case O (O_SUBS
, SL
):
1098 SET_L_REG (code
->dst
.reg
,
1099 GET_L_REG (code
->dst
.reg
)
1100 - code
->src
.literal
);
1104 rd
= fetch (&code
->dst
);
1105 ea
= fetch (&code
->src
);
1108 goto just_flags_alu8
;
1111 rd
= fetch (&code
->dst
);
1112 ea
= fetch (&code
->src
);
1115 goto just_flags_alu16
;
1118 rd
= fetch (&code
->dst
);
1119 ea
= fetch (&code
->src
);
1122 goto just_flags_alu32
;
1126 rd
= GET_B_REG (code
->src
.reg
);
1129 SET_B_REG (code
->src
.reg
, res
);
1130 goto just_flags_inc8
;
1133 rd
= GET_W_REG (code
->dst
.reg
);
1134 ea
= -code
->src
.literal
;
1136 SET_W_REG (code
->dst
.reg
, res
);
1137 goto just_flags_inc16
;
1140 rd
= GET_L_REG (code
->dst
.reg
);
1141 ea
= -code
->src
.literal
;
1143 SET_L_REG (code
->dst
.reg
, res
);
1144 goto just_flags_inc32
;
1148 rd
= GET_B_REG (code
->src
.reg
);
1151 SET_B_REG (code
->src
.reg
, res
);
1152 goto just_flags_inc8
;
1155 rd
= GET_W_REG (code
->dst
.reg
);
1156 ea
= code
->src
.literal
;
1158 SET_W_REG (code
->dst
.reg
, res
);
1159 goto just_flags_inc16
;
1162 rd
= GET_L_REG (code
->dst
.reg
);
1163 ea
= code
->src
.literal
;
1165 SET_L_REG (code
->dst
.reg
, res
);
1166 goto just_flags_inc32
;
1169 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1171 case O (O_ANDC
, SB
):
1173 ea
= code
->src
.literal
;
1179 ea
= code
->src
.literal
;
1183 case O (O_XORC
, SB
):
1185 ea
= code
->src
.literal
;
1226 if (((Z
|| (N
^ V
)) == 0))
1232 if (((Z
|| (N
^ V
)) == 1))
1266 case O (O_SYSCALL
, SB
):
1268 char c
= cpu
.regs
[2];
1269 sim_callback
->write_stdout (sim_callback
, &c
, 1);
1273 ONOT (O_NOT
, rd
= ~rd
; v
= 0;);
1275 c
= rd
& hm
; v
= 0; rd
<<= 1,
1276 c
= rd
& (hm
>> 1); v
= 0; rd
<<= 2);
1278 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1,
1279 c
= rd
& 2; v
= 0; rd
= (unsigned int) rd
>> 2);
1281 c
= rd
& hm
; v
= (rd
& hm
) != ((rd
& (hm
>> 1)) << 1); rd
<<= 1,
1282 c
= rd
& (hm
>> 1); v
= (rd
& (hm
>> 1)) != ((rd
& (hm
>> 2)) << 2); rd
<<= 2);
1284 t
= rd
& hm
; c
= rd
& 1; v
= 0; rd
>>= 1; rd
|= t
,
1285 t
= rd
& hm
; c
= rd
& 2; v
= 0; rd
>>= 2; rd
|= t
| t
>> 1 );
1287 c
= rd
& hm
; v
= 0; rd
<<= 1; rd
|= C
,
1288 c
= rd
& hm
; v
= 0; rd
<<= 1; rd
|= C
; c
= rd
& hm
; rd
<<= 1; rd
|= C
);
1290 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
,
1291 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
; c
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
);
1293 t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
; v
= 0,
1294 t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
; v
= 0; t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
);
1296 t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
; v
= 0,
1297 t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
; v
= 0; t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
);
1301 pc
= fetch (&code
->src
);
1309 pc
= fetch (&code
->src
);
1316 SET_MEMORY_L (tmp
, code
->next_pc
);
1321 SET_MEMORY_W (tmp
, code
->next_pc
);
1328 pc
= code
->src
.literal
;
1339 pc
= GET_MEMORY_L (tmp
);
1344 pc
= GET_MEMORY_W (tmp
);
1353 cpu
.state
= SIM_STATE_STOPPED
;
1354 cpu
.exception
= SIGILL
;
1356 case O (O_SLEEP
, SN
):
1357 /* FIXME: Doesn't this break for breakpoints when r0
1358 contains just the right (er, wrong) value? */
1359 cpu
.state
= SIM_STATE_STOPPED
;
1360 /* The format of r0 is defined by target newlib. Expand
1361 the macros here instead of looking for .../sys/wait.h. */
1362 #define SIM_WIFEXITED(v) (((v) & 0xff) == 0)
1363 #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f))
1364 if (! SIM_WIFEXITED (cpu
.regs
[0]) && SIM_WIFSIGNALED (cpu
.regs
[0]))
1365 cpu
.exception
= SIGILL
;
1367 cpu
.exception
= SIGTRAP
;
1370 cpu
.state
= SIM_STATE_STOPPED
;
1371 cpu
.exception
= SIGTRAP
;
1374 OBITOP (O_BNOT
, 1, 1, ea
^= m
);
1375 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
);
1376 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
);
1377 OBITOP (O_BSET
, 1, 1, ea
|= m
);
1378 OBITOP (O_BLD
, 1, 0, c
= ea
& m
);
1379 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
));
1380 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
1382 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
1384 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
);
1385 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
);
1386 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
);
1387 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
);
1388 OBITOP (O_BXOR
, 1, 0, c
= (ea
& m
) != C
);
1389 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
);
1392 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1394 case O (O_MULS
, SB
):
1397 case O (O_MULS
, SW
):
1400 case O (O_MULU
, SB
):
1403 case O (O_MULU
, SW
):
1408 case O (O_DIVU
, SB
):
1410 rd
= GET_W_REG (code
->dst
.reg
);
1411 ea
= GET_B_REG (code
->src
.reg
);
1414 tmp
= (unsigned)rd
% ea
;
1415 rd
= (unsigned)rd
/ ea
;
1417 SET_W_REG (code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1423 case O (O_DIVU
, SW
):
1425 rd
= GET_L_REG (code
->dst
.reg
);
1426 ea
= GET_W_REG (code
->src
.reg
);
1431 tmp
= (unsigned)rd
% ea
;
1432 rd
= (unsigned)rd
/ ea
;
1434 SET_L_REG (code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1438 case O (O_DIVS
, SB
):
1441 rd
= SEXTSHORT (GET_W_REG (code
->dst
.reg
));
1442 ea
= SEXTCHAR (GET_B_REG (code
->src
.reg
));
1445 tmp
= (int) rd
% (int) ea
;
1446 rd
= (int) rd
/ (int) ea
;
1452 SET_W_REG (code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1455 case O (O_DIVS
, SW
):
1457 rd
= GET_L_REG (code
->dst
.reg
);
1458 ea
= SEXTSHORT (GET_W_REG (code
->src
.reg
));
1461 tmp
= (int) rd
% (int) ea
;
1462 rd
= (int) rd
/ (int) ea
;
1463 n
= rd
& 0x80000000;
1468 SET_L_REG (code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1471 case O (O_EXTS
, SW
):
1472 rd
= GET_B_REG (code
->src
.reg
+ 8) & 0xff; /* Yes, src, not dst. */
1473 ea
= rd
& 0x80 ? -256 : 0;
1476 case O (O_EXTS
, SL
):
1477 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1478 ea
= rd
& 0x8000 ? -65536 : 0;
1481 case O (O_EXTU
, SW
):
1482 rd
= GET_B_REG (code
->src
.reg
+ 8) & 0xff;
1486 case O (O_EXTU
, SL
):
1487 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1497 int nregs
, firstreg
, i
;
1499 nregs
= GET_MEMORY_B (pc
+ 1);
1502 firstreg
= GET_MEMORY_B (pc
+ 3);
1504 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
1507 SET_MEMORY_L (cpu
.regs
[7], cpu
.regs
[i
]);
1514 int nregs
, firstreg
, i
;
1516 nregs
= GET_MEMORY_B (pc
+ 1);
1519 firstreg
= GET_MEMORY_B (pc
+ 3);
1521 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
1523 cpu
.regs
[i
] = GET_MEMORY_L (cpu
.regs
[7]);
1530 cpu
.state
= SIM_STATE_STOPPED
;
1531 cpu
.exception
= SIGILL
;
1543 /* When a branch works */
1544 pc
= code
->src
.literal
;
1547 /* Set the cond codes from res */
1550 /* Set the flags after an 8 bit inc/dec operation */
1554 v
= (rd
& 0x7f) == 0x7f;
1558 /* Set the flags after an 16 bit inc/dec operation */
1562 v
= (rd
& 0x7fff) == 0x7fff;
1566 /* Set the flags after an 32 bit inc/dec operation */
1568 n
= res
& 0x80000000;
1569 nz
= res
& 0xffffffff;
1570 v
= (rd
& 0x7fffffff) == 0x7fffffff;
1575 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1578 SET_B_REG (code
->src
.reg
, rd
);
1582 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1585 SET_W_REG (code
->src
.reg
, rd
);
1589 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1590 n
= (rd
& 0x80000000);
1591 nz
= rd
& 0xffffffff;
1592 SET_L_REG (code
->src
.reg
, rd
);
1596 store (&code
->dst
, res
);
1598 /* flags after a 32bit logical operation */
1599 n
= res
& 0x80000000;
1600 nz
= res
& 0xffffffff;
1605 store (&code
->dst
, res
);
1607 /* flags after a 16bit logical operation */
1615 store (&code
->dst
, res
);
1623 SET_B_REG (code
->dst
.reg
, res
);
1628 switch (code
->opcode
/ 4)
1631 v
= ((rd
& 0x80) == (ea
& 0x80)
1632 && (rd
& 0x80) != (res
& 0x80));
1636 v
= ((rd
& 0x80) != (-ea
& 0x80)
1637 && (rd
& 0x80) != (res
& 0x80));
1646 SET_W_REG (code
->dst
.reg
, res
);
1650 c
= (res
& 0x10000);
1651 switch (code
->opcode
/ 4)
1654 v
= ((rd
& 0x8000) == (ea
& 0x8000)
1655 && (rd
& 0x8000) != (res
& 0x8000));
1659 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
1660 && (rd
& 0x8000) != (res
& 0x8000));
1669 SET_L_REG (code
->dst
.reg
, res
);
1671 n
= res
& 0x80000000;
1672 nz
= res
& 0xffffffff;
1673 switch (code
->opcode
/ 4)
1676 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
1677 && (rd
& 0x80000000) != (res
& 0x80000000));
1678 c
= ((unsigned) res
< (unsigned) rd
) || ((unsigned) res
< (unsigned) ea
);
1682 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
1683 && (rd
& 0x80000000) != (res
& 0x80000000));
1684 c
= (unsigned) rd
< (unsigned) -ea
;
1687 v
= (rd
== 0x80000000);
1698 /* if (cpu.regs[8] ) abort(); */
1700 if (--poll_count
< 0)
1702 poll_count
= POLL_QUIT_INTERVAL
;
1703 if ((*sim_callback
->poll_quit
) != NULL
1704 && (*sim_callback
->poll_quit
) (sim_callback
))
1709 while (cpu
.state
== SIM_STATE_RUNNING
);
1710 cpu
.ticks
+= get_now () - tick_start
;
1711 cpu
.cycles
+= cycles
;
1717 signal (SIGINT
, prev
);
1724 /* FIXME: unfinished */
1729 sim_write (sd
, addr
, buffer
, size
)
1732 unsigned char *buffer
;
1740 for (i
= 0; i
< size
; i
++)
1742 if (addr
< memory_size
)
1744 cpu
.memory
[addr
+ i
] = buffer
[i
];
1745 cpu
.cache_idx
[addr
+ i
] = 0;
1748 cpu
.eightbit
[(addr
+ i
) & 0xff] = buffer
[i
];
1754 sim_read (sd
, addr
, buffer
, size
)
1757 unsigned char *buffer
;
1763 if (addr
< memory_size
)
1764 memcpy (buffer
, cpu
.memory
+ addr
, size
);
1766 memcpy (buffer
, cpu
.eightbit
+ (addr
& 0xff), size
);
1780 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1781 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1784 #define CCR_REGNUM 8 /* Contains processor status */
1785 #define PC_REGNUM 9 /* Contains program counter */
1787 #define CYCLE_REGNUM 10
1788 #define INST_REGNUM 11
1789 #define TICK_REGNUM 12
1793 sim_store_register (sd
, rn
, value
, length
)
1796 unsigned char *value
;
1802 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
1803 shortval
= (value
[0] << 8) | (value
[1]);
1804 intval
= h8300hmode
? longval
: shortval
;
1822 cpu
.regs
[rn
] = intval
;
1828 cpu
.cycles
= longval
;
1832 cpu
.insts
= longval
;
1836 cpu
.ticks
= longval
;
1843 sim_fetch_register (sd
, rn
, buf
, length
)
1887 if (h8300hmode
|| longreg
)
1903 sim_stop_reason (sd
, reason
, sigrc
)
1905 enum sim_stop
*reason
;
1908 #if 0 /* FIXME: This should work but we can't use it.
1909 grep for SLEEP above. */
1912 case SIM_STATE_EXITED
: *reason
= sim_exited
; break;
1913 case SIM_STATE_SIGNALLED
: *reason
= sim_signalled
; break;
1914 case SIM_STATE_STOPPED
: *reason
= sim_stopped
; break;
1918 *reason
= sim_stopped
;
1920 *sigrc
= cpu
.exception
;
1923 /* FIXME: Rename to sim_set_mem_size. */
1929 /* Memory size is fixed. */
1933 sim_set_simcache_size (n
)
1939 cpu
.cache
= (decoded_inst
*) malloc (sizeof (decoded_inst
) * n
);
1940 memset (cpu
.cache
, 0, sizeof (decoded_inst
) * n
);
1946 sim_info (sd
, verbose
)
1950 double timetaken
= (double) cpu
.ticks
/ (double) now_persec ();
1951 double virttime
= cpu
.cycles
/ 10.0e6
;
1953 (*sim_callback
->printf_filtered
) (sim_callback
,
1954 "\n\n#instructions executed %10d\n",
1956 (*sim_callback
->printf_filtered
) (sim_callback
,
1957 "#cycles (v approximate) %10d\n",
1959 (*sim_callback
->printf_filtered
) (sim_callback
,
1960 "#real time taken %10.4f\n",
1962 (*sim_callback
->printf_filtered
) (sim_callback
,
1963 "#virtual time taked %10.4f\n",
1965 if (timetaken
!= 0.0)
1966 (*sim_callback
->printf_filtered
) (sim_callback
,
1967 "#simulation ratio %10.4f\n",
1968 virttime
/ timetaken
);
1969 (*sim_callback
->printf_filtered
) (sim_callback
,
1972 (*sim_callback
->printf_filtered
) (sim_callback
,
1973 "#cache size %10d\n",
1977 /* This to be conditional on `what' (aka `verbose'),
1978 however it was never passed as non-zero. */
1982 for (i
= 0; i
< O_LAST
; i
++)
1985 (*sim_callback
->printf_filtered
) (sim_callback
,
1986 "%d: %d\n", i
, cpu
.stats
[i
]);
1992 /* Indicate whether the cpu is an h8/300 or h8/300h.
1993 FLAG is non-zero for the h8/300h. */
1999 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2000 This function being replaced by a sim_open:ARGV configuration
2006 sim_open (kind
, ptr
, abfd
, argv
)
2008 struct host_callback_struct
*ptr
;
2012 /* FIXME: Much of the code in sim_load can be moved here */
2017 /* fudge our descriptor */
2018 return (SIM_DESC
) 1;
2022 sim_close (sd
, quitting
)
2029 /* Called by gdb to load a program into memory. */
2032 sim_load (sd
, prog
, abfd
, from_tty
)
2040 /* FIXME: The code below that sets a specific variant of the h8/300
2041 being simulated should be moved to sim_open(). */
2043 /* See if the file is for the h8/300 or h8/300h. */
2044 /* ??? This may not be the most efficient way. The z8k simulator
2045 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2049 prog_bfd
= bfd_openr (prog
, "coff-h8300");
2050 if (prog_bfd
!= NULL
)
2052 /* Set the cpu type. We ignore failure from bfd_check_format
2053 and bfd_openr as sim_load_file checks too. */
2054 if (bfd_check_format (prog_bfd
, bfd_object
))
2056 unsigned long mach
= bfd_get_mach (prog_bfd
);
2057 set_h8300h (mach
== bfd_mach_h8300h
2058 || mach
== bfd_mach_h8300s
);
2062 /* If we're using gdb attached to the simulator, then we have to
2063 reallocate memory for the simulator.
2065 When gdb first starts, it calls fetch_registers (among other
2066 functions), which in turn calls init_pointers, which allocates
2069 The problem is when we do that, we don't know whether we're
2070 debugging an h8/300 or h8/300h program.
2072 This is the first point at which we can make that determination,
2073 so we just reallocate memory now; this will also allow us to handle
2074 switching between h8/300 and h8/300h programs without exiting
2077 memory_size
= H8300H_MSIZE
;
2079 memory_size
= H8300_MSIZE
;
2084 free (cpu
.cache_idx
);
2086 free (cpu
.eightbit
);
2088 cpu
.memory
= (unsigned char *) calloc (sizeof (char), memory_size
);
2089 cpu
.cache_idx
= (unsigned short *) calloc (sizeof (short), memory_size
);
2090 cpu
.eightbit
= (unsigned char *) calloc (sizeof (char), 256);
2092 /* `msize' must be a power of two */
2093 if ((memory_size
& (memory_size
- 1)) != 0)
2095 cpu
.mask
= memory_size
- 1;
2097 if (sim_load_file (sd
, myname
, sim_callback
, prog
, prog_bfd
,
2098 sim_kind
== SIM_OPEN_DEBUG
,
2102 /* Close the bfd if we opened it. */
2103 if (abfd
== NULL
&& prog_bfd
!= NULL
)
2104 bfd_close (prog_bfd
);
2108 /* Close the bfd if we opened it. */
2109 if (abfd
== NULL
&& prog_bfd
!= NULL
)
2110 bfd_close (prog_bfd
);
2115 sim_create_inferior (sd
, abfd
, argv
, env
)
2122 cpu
.pc
= bfd_get_start_address (abfd
);
2129 sim_do_command (sd
, cmd
)
2133 (*sim_callback
->printf_filtered
) (sim_callback
,
2134 "This simulator does not accept any commands.\n");
2138 sim_set_callbacks (ptr
)
2139 struct host_callback_struct
*ptr
;