2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
24 #ifdef HAVE_SYS_PARAM_H
25 #include <sys/param.h>
30 #include "gdb/sim-h8300.h"
32 #include "sys/types.h"
33 #include "sim-options.h"
41 static int memory_size
;
43 #define X(op, size) (op * 4 + size)
45 #define SP (h8300hmode && !h8300_normal_mode ? SL : SW)
47 #define h8_opcodes ops
49 #include "opcode/h8300.h"
51 /* CPU data object: */
54 h8_get_pc (SIM_DESC sd
)
56 return (STATE_CPU (sd
, 0)) -> pc
;
60 h8_set_pc (SIM_DESC sd
, unsigned int val
)
62 (STATE_CPU (sd
, 0)) -> pc
= val
;
66 h8_get_ccr (SIM_DESC sd
)
68 return (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
];
72 h8_set_ccr (SIM_DESC sd
, unsigned int val
)
74 (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
] = val
;
78 h8_get_exr (SIM_DESC sd
)
80 return (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
];
84 h8_set_exr (SIM_DESC sd
, unsigned int val
)
86 (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
] = val
;
90 h8_get_sbr (SIM_DESC sd
)
92 return (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
];
96 h8_set_sbr (SIM_DESC sd
, int val
)
98 (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
] = val
;
102 h8_get_vbr (SIM_DESC sd
)
104 return (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
];
108 h8_set_vbr (SIM_DESC sd
, int val
)
110 (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
] = val
;
114 h8_get_mask (SIM_DESC sd
)
116 return (STATE_CPU (sd
, 0)) -> mask
;
120 h8_set_mask (SIM_DESC sd
, int val
)
122 (STATE_CPU (sd
, 0)) -> mask
= val
;
126 h8_get_exception (SIM_DESC sd
)
128 return (STATE_CPU (sd
, 0)) -> exception
;
132 h8_set_exception (SIM_DESC sd
, int val
)
134 (STATE_CPU (sd
, 0)) -> exception
= val
;
137 static enum h8300_sim_state
138 h8_get_state (SIM_DESC sd
)
144 h8_set_state (SIM_DESC sd
, enum h8300_sim_state val
)
150 h8_get_cycles (SIM_DESC sd
)
152 return (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
];
156 h8_set_cycles (SIM_DESC sd
, unsigned int val
)
158 (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
] = val
;
162 h8_get_insts (SIM_DESC sd
)
164 return (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
];
168 h8_set_insts (SIM_DESC sd
, unsigned int val
)
170 (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
] = val
;
174 h8_get_ticks (SIM_DESC sd
)
176 return (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
];
180 h8_set_ticks (SIM_DESC sd
, unsigned int val
)
182 (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
] = val
;
186 h8_get_mach (SIM_DESC sd
)
188 return (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
];
192 h8_set_mach (SIM_DESC sd
, unsigned int val
)
194 (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
] = val
;
198 h8_get_macl (SIM_DESC sd
)
200 return (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
];
204 h8_set_macl (SIM_DESC sd
, unsigned int val
)
206 (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
] = val
;
209 static unsigned int *
210 h8_get_reg_buf (SIM_DESC sd
)
212 return &(((STATE_CPU (sd
, 0)) -> regs
)[0]);
216 h8_get_reg (SIM_DESC sd
, int regnum
)
218 return (STATE_CPU (sd
, 0)) -> regs
[regnum
];
222 h8_set_reg (SIM_DESC sd
, int regnum
, int val
)
224 (STATE_CPU (sd
, 0)) -> regs
[regnum
] = val
;
229 h8_get_stats (SIM_DESC sd
, int idx
)
231 return sd
-> stats
[idx
];
235 h8_increment_stats (SIM_DESC sd
, int idx
)
241 static unsigned char *
242 h8_get_memory_buf (SIM_DESC sd
)
244 return (STATE_CPU (sd
, 0)) -> memory
;
248 h8_set_memory_buf (SIM_DESC sd
, unsigned char *ptr
)
250 (STATE_CPU (sd
, 0)) -> memory
= ptr
;
254 h8_get_memory (SIM_DESC sd
, int idx
)
256 ASSERT (idx
< memory_size
);
257 return (STATE_CPU (sd
, 0)) -> memory
[idx
];
261 h8_set_memory (SIM_DESC sd
, int idx
, unsigned int val
)
263 ASSERT (idx
< memory_size
);
264 (STATE_CPU (sd
, 0)) -> memory
[idx
] = (unsigned char) val
;
268 h8_get_delayed_branch (SIM_DESC sd
)
270 return (STATE_CPU (sd
, 0)) -> delayed_branch
;
274 h8_set_delayed_branch (SIM_DESC sd
, unsigned int dest
)
276 (STATE_CPU (sd
, 0)) -> delayed_branch
= dest
;
280 h8_get_command_line (SIM_DESC sd
)
282 return (STATE_CPU (sd
, 0)) -> command_line
;
286 h8_set_command_line (SIM_DESC sd
, char ** val
)
288 (STATE_CPU (sd
, 0)) -> command_line
= val
;
292 h8_get_cmdline_arg (SIM_DESC sd
, int index
)
294 return (STATE_CPU (sd
, 0)) -> command_line
[index
];
298 h8_set_cmdline_arg (SIM_DESC sd
, int index
, char * val
)
300 (STATE_CPU (sd
, 0)) -> command_line
[index
] = val
;
303 /* MAC Saturation Mode */
305 h8_get_macS (SIM_DESC sd
)
307 return (STATE_CPU (sd
, 0)) -> macS
;
311 h8_set_macS (SIM_DESC sd
, int val
)
313 (STATE_CPU (sd
, 0)) -> macS
= (val
!= 0);
318 h8_get_macZ (SIM_DESC sd
)
320 return (STATE_CPU (sd
, 0)) -> macZ
;
324 h8_set_macZ (SIM_DESC sd
, int val
)
326 (STATE_CPU (sd
, 0)) -> macZ
= (val
!= 0);
329 /* MAC Negative Flag */
331 h8_get_macN (SIM_DESC sd
)
333 return (STATE_CPU (sd
, 0)) -> macN
;
337 h8_set_macN (SIM_DESC sd
, int val
)
339 (STATE_CPU (sd
, 0)) -> macN
= (val
!= 0);
342 /* MAC Overflow Flag */
344 h8_get_macV (SIM_DESC sd
)
346 return (STATE_CPU (sd
, 0)) -> macV
;
350 h8_set_macV (SIM_DESC sd
, int val
)
352 (STATE_CPU (sd
, 0)) -> macV
= (val
!= 0);
355 /* End CPU data object. */
357 /* The rate at which to call the host's poll_quit callback. */
359 enum { POLL_QUIT_INTERVAL
= 0x80000 };
361 #define LOW_BYTE(x) ((x) & 0xff)
362 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
363 #define P(X, Y) ((X << 8) | Y)
372 #define I (intMaskBit != 0)
374 #define BUILDSR(SD) \
375 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
376 | (N << 3) | (Z << 2) | (V << 1) | C)
379 /* Get Status Register (flags). */ \
380 c = (h8_get_ccr (sd) >> 0) & 1; \
381 v = (h8_get_ccr (sd) >> 1) & 1; \
382 nz = !((h8_get_ccr (sd) >> 2) & 1); \
383 n = (h8_get_ccr (sd) >> 3) & 1; \
384 u = (h8_get_ccr (sd) >> 4) & 1; \
385 h = (h8_get_ccr (sd) >> 5) & 1; \
386 ui = ((h8_get_ccr (sd) >> 6) & 1); \
387 intMaskBit = (h8_get_ccr (sd) >> 7) & 1
390 #ifdef __CHAR_IS_SIGNED__
391 #define SEXTCHAR(x) ((char) (x))
395 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
398 #define UEXTCHAR(x) ((x) & 0xff)
399 #define UEXTSHORT(x) ((x) & 0xffff)
400 #define SEXTSHORT(x) ((short) (x))
404 int h8300_normal_mode
= 0;
410 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
432 return (h8300hmode
&& !h8300_normal_mode
)? SL
: SW
;
437 /* Simulate an indirection / dereference.
438 return 0 for success, -1 for failure.
442 lvalue (SIM_DESC sd
, int x
, int rn
, unsigned int *val
)
444 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
446 if (val
== NULL
) /* Paranoia. */
452 if (rn
== ZERO_REGNUM
)
453 *val
= X (OP_IMM
, SP
);
455 *val
= X (OP_REG
, SP
);
458 *val
= X (OP_MEM
, SP
);
461 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
470 if (h8300smode
&& !h8300_normal_mode
)
472 else if (h8300hmode
&& !h8300_normal_mode
)
479 decode (SIM_DESC sd
, int addr
, unsigned char *data
, decoded_inst
*dst
)
481 int cst
[3] = {0, 0, 0};
482 int reg
[3] = {0, 0, 0};
483 int rdisp
[3] = {0, 0, 0};
485 const struct h8_opcode
*q
;
490 /* Find the exact opcode/arg combo. */
491 for (q
= h8_opcodes
; q
->name
; q
++)
493 const op_type
*nib
= q
->data
.nib
;
494 unsigned int len
= 0;
496 if ((q
->available
== AV_H8SX
&& !h8300sxmode
) ||
497 (q
->available
== AV_H8S
&& !h8300smode
) ||
498 (q
->available
== AV_H8H
&& !h8300hmode
))
501 cst
[0] = cst
[1] = cst
[2] = 0;
502 reg
[0] = reg
[1] = reg
[2] = 0;
503 rdisp
[0] = rdisp
[1] = rdisp
[2] = 0;
507 op_type looking_for
= *nib
;
508 int thisnib
= data
[len
/ 2];
510 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
511 opnum
= ((looking_for
& OP3
) ? 2 :
512 (looking_for
& DST
) ? 1 : 0);
514 if (looking_for
< 16 && looking_for
>= 0)
516 if (looking_for
!= thisnib
)
521 if (looking_for
& B31
)
523 if (!((thisnib
& 0x8) != 0))
526 looking_for
= (op_type
) (looking_for
& ~B31
);
529 else if (looking_for
& B30
)
531 if (!((thisnib
& 0x8) == 0))
534 looking_for
= (op_type
) (looking_for
& ~B30
);
537 if (looking_for
& B21
)
539 if (!((thisnib
& 0x4) != 0))
542 looking_for
= (op_type
) (looking_for
& ~B21
);
545 else if (looking_for
& B20
)
547 if (!((thisnib
& 0x4) == 0))
550 looking_for
= (op_type
) (looking_for
& ~B20
);
553 if (looking_for
& B11
)
555 if (!((thisnib
& 0x2) != 0))
558 looking_for
= (op_type
) (looking_for
& ~B11
);
561 else if (looking_for
& B10
)
563 if (!((thisnib
& 0x2) == 0))
566 looking_for
= (op_type
) (looking_for
& ~B10
);
569 if (looking_for
& B01
)
571 if (!((thisnib
& 0x1) != 0))
574 looking_for
= (op_type
) (looking_for
& ~B01
);
577 else if (looking_for
& B00
)
579 if (!((thisnib
& 0x1) == 0))
582 looking_for
= (op_type
) (looking_for
& ~B00
);
585 if (looking_for
& IGNORE
)
587 /* Hitachi has declared that IGNORE must be zero. */
591 else if ((looking_for
& MODE
) == DATA
)
593 ; /* Skip embedded data. */
595 else if ((looking_for
& MODE
) == DBIT
)
597 /* Exclude adds/subs by looking at bit 0 and 2, and
598 make sure the operand size, either w or l,
599 matches by looking at bit 1. */
600 if ((looking_for
& 7) != (thisnib
& 7))
603 cst
[opnum
] = (thisnib
& 0x8) ? 2 : 1;
605 else if ((looking_for
& MODE
) == REG
||
606 (looking_for
& MODE
) == LOWREG
||
607 (looking_for
& MODE
) == IND
||
608 (looking_for
& MODE
) == PREINC
||
609 (looking_for
& MODE
) == POSTINC
||
610 (looking_for
& MODE
) == PREDEC
||
611 (looking_for
& MODE
) == POSTDEC
)
613 reg
[opnum
] = thisnib
;
615 else if (looking_for
& CTRL
)
618 if (((looking_for
& MODE
) == CCR
&& (thisnib
!= C_CCR
)) ||
619 ((looking_for
& MODE
) == EXR
&& (thisnib
!= C_EXR
)) ||
620 ((looking_for
& MODE
) == MACH
&& (thisnib
!= C_MACH
)) ||
621 ((looking_for
& MODE
) == MACL
&& (thisnib
!= C_MACL
)) ||
622 ((looking_for
& MODE
) == VBR
&& (thisnib
!= C_VBR
)) ||
623 ((looking_for
& MODE
) == SBR
&& (thisnib
!= C_SBR
)))
625 if (((looking_for
& MODE
) == CCR_EXR
&&
626 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
)) ||
627 ((looking_for
& MODE
) == VBR_SBR
&&
628 (thisnib
!= C_VBR
&& thisnib
!= C_SBR
)) ||
629 ((looking_for
& MODE
) == MACREG
&&
630 (thisnib
!= C_MACH
&& thisnib
!= C_MACL
)))
632 if (((looking_for
& MODE
) == CC_EX_VB_SB
&&
633 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
&&
634 thisnib
!= C_VBR
&& thisnib
!= C_SBR
)))
637 reg
[opnum
] = thisnib
;
639 else if ((looking_for
& MODE
) == ABS
)
641 /* Absolute addresses are unsigned. */
642 switch (looking_for
& SIZE
)
645 cst
[opnum
] = UEXTCHAR (data
[len
/ 2]);
649 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
653 (data
[len
/ 2 + 0] << 24) +
654 (data
[len
/ 2 + 1] << 16) +
655 (data
[len
/ 2 + 2] << 8) +
659 printf ("decode: bad size ABS: %d\n",
660 (looking_for
& SIZE
));
664 else if ((looking_for
& MODE
) == DISP
||
665 (looking_for
& MODE
) == PCREL
||
666 (looking_for
& MODE
) == INDEXB
||
667 (looking_for
& MODE
) == INDEXW
||
668 (looking_for
& MODE
) == INDEXL
)
670 switch (looking_for
& SIZE
)
673 cst
[opnum
] = thisnib
& 3;
676 cst
[opnum
] = SEXTCHAR (data
[len
/ 2]);
679 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
680 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
683 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
687 (data
[len
/ 2 + 0] << 24) +
688 (data
[len
/ 2 + 1] << 16) +
689 (data
[len
/ 2 + 2] << 8) +
693 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
694 (looking_for
& SIZE
));
698 else if ((looking_for
& SIZE
) == L_16
||
699 (looking_for
& SIZE
) == L_16U
)
701 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
702 /* Immediates are always unsigned. */
703 if ((looking_for
& SIZE
) != L_16U
&&
704 (looking_for
& MODE
) != IMM
)
705 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
707 else if (looking_for
& ABSJMP
)
709 switch (looking_for
& SIZE
) {
711 cst
[opnum
] = (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
715 (data
[len
/ 2 + 0] << 24) +
716 (data
[len
/ 2 + 1] << 16) +
717 (data
[len
/ 2 + 2] << 8) +
721 printf ("decode: bad size ABSJMP: %d\n",
722 (looking_for
& SIZE
));
726 else if ((looking_for
& MODE
) == MEMIND
)
728 cst
[opnum
] = data
[1];
730 else if ((looking_for
& MODE
) == VECIND
)
732 if(h8300_normal_mode
)
733 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 2;
735 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 4;
736 cst
[opnum
] += h8_get_vbr (sd
); /* Add vector base reg. */
738 else if ((looking_for
& SIZE
) == L_32
)
743 (data
[i
+ 0] << 24) |
744 (data
[i
+ 1] << 16) |
748 else if ((looking_for
& SIZE
) == L_24
)
753 (data
[i
+ 0] << 16) |
757 else if (looking_for
& DISPREG
)
759 rdisp
[opnum
] = thisnib
& 0x7;
761 else if ((looking_for
& MODE
) == KBIT
)
778 else if ((looking_for
& SIZE
) == L_8
)
780 if ((looking_for
& MODE
) == ABS
)
782 /* Will be combined with contents of SBR_REGNUM
783 by fetch (). For all modes except h8sx, this
784 will always contain the value 0xFFFFFF00. */
785 cst
[opnum
] = data
[len
/ 2] & 0xff;
789 cst
[opnum
] = data
[len
/ 2] & 0xff;
792 else if ((looking_for
& SIZE
) == L_2
)
794 cst
[opnum
] = thisnib
& 3;
796 else if ((looking_for
& SIZE
) == L_3
||
797 (looking_for
& SIZE
) == L_3NZ
)
799 cst
[opnum
] = thisnib
& 7;
800 if (cst
[opnum
] == 0 && (looking_for
& SIZE
) == L_3NZ
)
803 else if ((looking_for
& SIZE
) == L_4
)
805 cst
[opnum
] = thisnib
& 15;
807 else if ((looking_for
& SIZE
) == L_5
)
809 cst
[opnum
] = data
[len
/ 2] & 0x1f;
811 else if (looking_for
== E
)
816 /* Fill in the args. */
818 const op_type
*args
= q
->args
.nib
;
823 nargs
< 3 && *args
!= E
;
829 opnum
= ((x
& OP3
) ? 2 :
838 if ((x
& MODE
) == IMM
||
839 (x
& MODE
) == KBIT
||
842 /* Use the instruction to determine
844 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
845 p
->literal
= cst
[opnum
];
847 else if ((x
& MODE
) == CONST_2
||
848 (x
& MODE
) == CONST_4
||
849 (x
& MODE
) == CONST_8
||
850 (x
& MODE
) == CONST_16
)
852 /* Use the instruction to determine
854 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
856 case CONST_2
: p
->literal
= 2; break;
857 case CONST_4
: p
->literal
= 4; break;
858 case CONST_8
: p
->literal
= 8; break;
859 case CONST_16
: p
->literal
= 16; break;
862 else if ((x
& MODE
) == REG
)
864 p
->type
= X (OP_REG
, bitfrom (x
));
867 else if ((x
& MODE
) == LOWREG
)
869 p
->type
= X (OP_LOWREG
, bitfrom (x
));
872 else if ((x
& MODE
) == PREINC
)
874 /* Use the instruction to determine
876 p
->type
= X (OP_PREINC
, OP_SIZE (q
->how
));
877 p
->reg
= reg
[opnum
] & 0x7;
879 else if ((x
& MODE
) == POSTINC
)
881 /* Use the instruction to determine
883 p
->type
= X (OP_POSTINC
, OP_SIZE (q
->how
));
884 p
->reg
= reg
[opnum
] & 0x7;
886 else if ((x
& MODE
) == PREDEC
)
888 /* Use the instruction to determine
890 p
->type
= X (OP_PREDEC
, OP_SIZE (q
->how
));
891 p
->reg
= reg
[opnum
] & 0x7;
893 else if ((x
& MODE
) == POSTDEC
)
895 /* Use the instruction to determine
897 p
->type
= X (OP_POSTDEC
, OP_SIZE (q
->how
));
898 p
->reg
= reg
[opnum
] & 0x7;
900 else if ((x
& MODE
) == IND
)
902 /* Note: an indirect is transformed into
903 a displacement of zero.
905 /* Use the instruction to determine
907 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
908 p
->reg
= reg
[opnum
] & 0x7;
910 if (OP_KIND (q
->how
) == O_JSR
||
911 OP_KIND (q
->how
) == O_JMP
)
912 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
915 else if ((x
& MODE
) == ABS
)
917 /* Note: a 16 or 32 bit ABS is transformed into a
918 displacement from pseudo-register ZERO_REGNUM,
919 which is always zero. An 8 bit ABS becomes
920 a displacement from SBR_REGNUM.
922 /* Use the instruction to determine
924 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
925 p
->literal
= cst
[opnum
];
927 /* 8-bit ABS is displacement from SBR.
928 16 and 32-bit ABS are displacement from ZERO.
929 (SBR will always be zero except for h8/sx)
931 if ((x
& SIZE
) == L_8
)
934 p
->reg
= ZERO_REGNUM
;;
936 else if ((x
& MODE
) == MEMIND
||
937 (x
& MODE
) == VECIND
)
939 /* Size doesn't matter. */
940 p
->type
= X (OP_MEM
, SB
);
941 p
->literal
= cst
[opnum
];
942 if (OP_KIND (q
->how
) == O_JSR
||
943 OP_KIND (q
->how
) == O_JMP
)
944 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
947 else if ((x
& MODE
) == PCREL
)
949 /* Size doesn't matter. */
950 p
->type
= X (OP_PCREL
, SB
);
951 p
->literal
= cst
[opnum
];
955 p
->type
= X (OP_IMM
, SP
);
956 p
->literal
= cst
[opnum
];
958 else if ((x
& MODE
) == INDEXB
)
960 p
->type
= X (OP_INDEXB
, OP_SIZE (q
->how
));
961 p
->literal
= cst
[opnum
];
962 p
->reg
= rdisp
[opnum
];
964 else if ((x
& MODE
) == INDEXW
)
966 p
->type
= X (OP_INDEXW
, OP_SIZE (q
->how
));
967 p
->literal
= cst
[opnum
];
968 p
->reg
= rdisp
[opnum
];
970 else if ((x
& MODE
) == INDEXL
)
972 p
->type
= X (OP_INDEXL
, OP_SIZE (q
->how
));
973 p
->literal
= cst
[opnum
];
974 p
->reg
= rdisp
[opnum
];
976 else if ((x
& MODE
) == DISP
)
978 /* Yuck -- special for mova args. */
979 if (strncmp (q
->name
, "mova", 4) == 0 &&
982 /* Mova can have a DISP2 dest, with an
983 INDEXB or INDEXW src. The multiplier
984 for the displacement value is determined
985 by the src operand, not by the insn. */
987 switch (OP_KIND (dst
->src
.type
))
990 p
->type
= X (OP_DISP
, SB
);
991 p
->literal
= cst
[opnum
];
994 p
->type
= X (OP_DISP
, SW
);
995 p
->literal
= cst
[opnum
] * 2;
1003 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1004 p
->literal
= cst
[opnum
];
1005 /* DISP2 is special. */
1006 if ((x
& SIZE
) == L_2
)
1007 switch (OP_SIZE (q
->how
))
1010 case SW
: p
->literal
*= 2; break;
1011 case SL
: p
->literal
*= 4; break;
1014 p
->reg
= rdisp
[opnum
];
1021 p
->type
= X (OP_CCR
, SB
);
1024 p
->type
= X (OP_EXR
, SB
);
1027 p
->type
= X (OP_MACH
, SL
);
1030 p
->type
= X (OP_MACL
, SL
);
1033 p
->type
= X (OP_VBR
, SL
);
1036 p
->type
= X (OP_SBR
, SL
);
1040 else if ((x
& MODE
) == CCR
)
1044 else if ((x
& MODE
) == EXR
)
1049 printf ("Hmmmm 0x%x...\n", x
);
1055 /* Unary operators: treat src and dst as equivalent. */
1056 if (dst
->dst
.type
== -1)
1057 dst
->dst
= dst
->src
;
1058 if (dst
->src
.type
== -1)
1059 dst
->src
= dst
->dst
;
1061 dst
->opcode
= q
->how
;
1062 dst
->cycles
= q
->time
;
1064 /* And jsr's to these locations are turned into
1067 if (OP_KIND (dst
->opcode
) == O_JSR
)
1069 switch (dst
->src
.literal
)
1072 dst
->opcode
= O (O_SYS_OPEN
, SB
);
1075 dst
->opcode
= O (O_SYS_READ
, SB
);
1078 dst
->opcode
= O (O_SYS_WRITE
, SB
);
1081 dst
->opcode
= O (O_SYS_LSEEK
, SB
);
1084 dst
->opcode
= O (O_SYS_CLOSE
, SB
);
1087 dst
->opcode
= O (O_SYS_STAT
, SB
);
1090 dst
->opcode
= O (O_SYS_FSTAT
, SB
);
1093 dst
->opcode
= O (O_SYS_CMDLINE
, SB
);
1096 /* End of Processing for system calls. */
1099 dst
->next_pc
= addr
+ len
/ 2;
1103 printf ("Don't understand 0x%x \n", looking_for
);
1114 /* Fell off the end. */
1115 dst
->opcode
= O (O_ILL
, SB
);
1118 static unsigned char *breg
[32];
1119 static unsigned short *wreg
[16];
1121 #define GET_B_REG(X) *(breg[X])
1122 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1123 #define GET_W_REG(X) *(wreg[X])
1124 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1125 #define GET_L_REG(X) h8_get_reg (sd, X)
1126 #define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1128 #define GET_MEMORY_L(X) \
1129 ((X) < memory_size \
1130 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1131 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1134 #define GET_MEMORY_W(X) \
1135 ((X) < memory_size \
1136 ? ((h8_get_memory (sd, (X)+0) << 8) | (h8_get_memory (sd, (X)+1) << 0)) \
1139 #define GET_MEMORY_B(X) \
1140 ((X) < memory_size ? h8_get_memory (sd, (X)) : 0)
1142 #define SET_MEMORY_L(X, Y) \
1143 { register unsigned char *_p; register int __y = (Y); \
1144 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : 0); \
1145 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1146 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1149 #define SET_MEMORY_W(X, Y) \
1150 { register unsigned char *_p; register int __y = (Y); \
1151 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : 0); \
1152 _p[0] = __y >> 8; _p[1] = __y; \
1155 #define SET_MEMORY_B(X, Y) \
1156 ((X) < memory_size ? h8_set_memory (sd, (X), (Y)) : 0)
1158 /* Simulate a memory fetch.
1159 Return 0 for success, -1 for failure.
1163 fetch_1 (SIM_DESC sd
, ea_type
*arg
, int *val
, int twice
)
1165 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1167 int abs
= arg
->literal
;
1172 return -1; /* Paranoia. */
1176 /* Indexed register plus displacement mode:
1178 This new family of addressing modes are similar to OP_DISP
1179 (register plus displacement), with two differences:
1180 1) INDEXB uses only the least significant byte of the register,
1181 INDEXW uses only the least significant word, and
1182 INDEXL uses the entire register (just like OP_DISP).
1184 2) The displacement value in abs is multiplied by two
1185 for SW-sized operations, and by four for SL-size.
1187 This gives nine possible variations.
1190 case X (OP_INDEXB
, SB
):
1191 case X (OP_INDEXB
, SW
):
1192 case X (OP_INDEXB
, SL
):
1193 case X (OP_INDEXW
, SB
):
1194 case X (OP_INDEXW
, SW
):
1195 case X (OP_INDEXW
, SL
):
1196 case X (OP_INDEXL
, SB
):
1197 case X (OP_INDEXL
, SW
):
1198 case X (OP_INDEXL
, SL
):
1200 switch (OP_KIND (arg
->type
)) {
1201 case OP_INDEXB
: t
&= 0xff; break;
1202 case OP_INDEXW
: t
&= 0xffff; break;
1206 switch (OP_SIZE (arg
->type
)) {
1208 *val
= GET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
));
1211 *val
= GET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
));
1214 *val
= GET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
));
1219 case X (OP_LOWREG
, SB
):
1220 *val
= GET_L_REG (rn
) & 0xff;
1222 case X (OP_LOWREG
, SW
):
1223 *val
= GET_L_REG (rn
) & 0xffff;
1226 case X (OP_REG
, SB
): /* Register direct, byte. */
1227 *val
= GET_B_REG (rn
);
1229 case X (OP_REG
, SW
): /* Register direct, word. */
1230 *val
= GET_W_REG (rn
);
1232 case X (OP_REG
, SL
): /* Register direct, long. */
1233 *val
= GET_L_REG (rn
);
1235 case X (OP_IMM
, SB
): /* Immediate, byte. */
1236 case X (OP_IMM
, SW
): /* Immediate, word. */
1237 case X (OP_IMM
, SL
): /* Immediate, long. */
1240 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr: byte. */
1242 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1248 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr: word. */
1250 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1256 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr: long. */
1258 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1265 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr: byte. */
1267 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1273 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr: word. */
1275 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1281 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr: long. */
1283 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1290 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr: byte. */
1291 t
= GET_L_REG (rn
) - 1;
1293 t
&= h8_get_mask (sd
);
1294 *val
= GET_MEMORY_B (t
);
1297 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr: word. */
1298 t
= GET_L_REG (rn
) - 2;
1300 t
&= h8_get_mask (sd
);
1301 *val
= GET_MEMORY_W (t
);
1304 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr: long. */
1305 t
= GET_L_REG (rn
) - 4;
1307 t
&= h8_get_mask (sd
);
1308 *val
= GET_MEMORY_L (t
);
1311 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr: byte. */
1312 t
= GET_L_REG (rn
) + 1;
1314 t
&= h8_get_mask (sd
);
1315 *val
= GET_MEMORY_B (t
);
1318 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr: long. */
1319 t
= GET_L_REG (rn
) + 2;
1321 t
&= h8_get_mask (sd
);
1322 *val
= GET_MEMORY_W (t
);
1325 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr: long. */
1326 t
= GET_L_REG (rn
) + 4;
1328 t
&= h8_get_mask (sd
);
1329 *val
= GET_MEMORY_L (t
);
1332 case X (OP_DISP
, SB
): /* Register indirect w/displacement: byte. */
1333 t
= GET_L_REG (rn
) + abs
;
1334 t
&= h8_get_mask (sd
);
1335 *val
= GET_MEMORY_B (t
);
1338 case X (OP_DISP
, SW
): /* Register indirect w/displacement: word. */
1339 t
= GET_L_REG (rn
) + abs
;
1340 t
&= h8_get_mask (sd
);
1341 *val
= GET_MEMORY_W (t
);
1344 case X (OP_DISP
, SL
): /* Register indirect w/displacement: long. */
1345 t
= GET_L_REG (rn
) + abs
;
1346 t
&= h8_get_mask (sd
);
1347 *val
=GET_MEMORY_L (t
);
1350 case X (OP_MEM
, SL
): /* Absolute memory address, long. */
1351 t
= GET_MEMORY_L (abs
);
1352 t
&= h8_get_mask (sd
);
1356 case X (OP_MEM
, SW
): /* Absolute memory address, word. */
1357 t
= GET_MEMORY_W (abs
);
1358 t
&= h8_get_mask (sd
);
1362 case X (OP_PCREL
, SB
): /* PC relative (for jump, branch etc). */
1363 case X (OP_PCREL
, SW
):
1364 case X (OP_PCREL
, SL
):
1365 case X (OP_PCREL
, SN
):
1369 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1371 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1374 return 0; /* Success. */
1380 fetch (SIM_DESC sd
, ea_type
*arg
, int *val
)
1382 return fetch_1 (sd
, arg
, val
, 0);
1385 /* Fetch which will be followed by a store to the same location.
1386 The difference being that we don't want to do a post-increment
1387 or post-decrement at this time: we'll do it when we store. */
1390 fetch2 (SIM_DESC sd
, ea_type
*arg
, int *val
)
1392 return fetch_1 (sd
, arg
, val
, 1);
1395 /* Simulate a memory store.
1396 Return 0 for success, -1 for failure.
1400 store_1 (SIM_DESC sd
, ea_type
*arg
, int n
, int twice
)
1402 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1404 int abs
= arg
->literal
;
1409 /* Indexed register plus displacement mode:
1411 This new family of addressing modes are similar to OP_DISP
1412 (register plus displacement), with two differences:
1413 1) INDEXB uses only the least significant byte of the register,
1414 INDEXW uses only the least significant word, and
1415 INDEXL uses the entire register (just like OP_DISP).
1417 2) The displacement value in abs is multiplied by two
1418 for SW-sized operations, and by four for SL-size.
1420 This gives nine possible variations.
1423 case X (OP_INDEXB
, SB
):
1424 case X (OP_INDEXB
, SW
):
1425 case X (OP_INDEXB
, SL
):
1426 case X (OP_INDEXW
, SB
):
1427 case X (OP_INDEXW
, SW
):
1428 case X (OP_INDEXW
, SL
):
1429 case X (OP_INDEXL
, SB
):
1430 case X (OP_INDEXL
, SW
):
1431 case X (OP_INDEXL
, SL
):
1433 switch (OP_KIND (arg
->type
)) {
1434 case OP_INDEXB
: t
&= 0xff; break;
1435 case OP_INDEXW
: t
&= 0xffff; break;
1439 switch (OP_SIZE (arg
->type
)) {
1441 SET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
), n
);
1444 SET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
), n
);
1447 SET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
), n
);
1452 case X (OP_REG
, SB
): /* Register direct, byte. */
1455 case X (OP_REG
, SW
): /* Register direct, word. */
1458 case X (OP_REG
, SL
): /* Register direct, long. */
1462 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr, byte. */
1467 t
&= h8_get_mask (sd
);
1468 SET_MEMORY_B (t
, n
);
1471 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr, word. */
1476 t
&= h8_get_mask (sd
);
1477 SET_MEMORY_W (t
, n
);
1480 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr, long. */
1485 t
&= h8_get_mask (sd
);
1486 SET_MEMORY_L (t
, n
);
1489 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr, byte. */
1494 t
&= h8_get_mask (sd
);
1495 SET_MEMORY_B (t
, n
);
1498 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr, word. */
1503 t
&= h8_get_mask (sd
);
1504 SET_MEMORY_W (t
, n
);
1507 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr, long. */
1512 t
&= h8_get_mask (sd
);
1513 SET_MEMORY_L (t
, n
);
1516 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr, byte. */
1518 SET_L_REG (rn
, t
- 1);
1519 t
&= h8_get_mask (sd
);
1520 SET_MEMORY_B (t
, n
);
1523 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr, word. */
1525 SET_L_REG (rn
, t
- 2);
1526 t
&= h8_get_mask (sd
);
1527 SET_MEMORY_W (t
, n
);
1530 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr, long. */
1532 SET_L_REG (rn
, t
- 4);
1533 t
&= h8_get_mask (sd
);
1534 SET_MEMORY_L (t
, n
);
1537 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr, byte. */
1539 SET_L_REG (rn
, t
+ 1);
1540 t
&= h8_get_mask (sd
);
1541 SET_MEMORY_B (t
, n
);
1544 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr, word. */
1546 SET_L_REG (rn
, t
+ 2);
1547 t
&= h8_get_mask (sd
);
1548 SET_MEMORY_W (t
, n
);
1551 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr, long. */
1553 SET_L_REG (rn
, t
+ 4);
1554 t
&= h8_get_mask (sd
);
1555 SET_MEMORY_L (t
, n
);
1558 case X (OP_DISP
, SB
): /* Register indirect w/displacement, byte. */
1559 t
= GET_L_REG (rn
) + abs
;
1560 t
&= h8_get_mask (sd
);
1561 SET_MEMORY_B (t
, n
);
1564 case X (OP_DISP
, SW
): /* Register indirect w/displacement, word. */
1565 t
= GET_L_REG (rn
) + abs
;
1566 t
&= h8_get_mask (sd
);
1567 SET_MEMORY_W (t
, n
);
1570 case X (OP_DISP
, SL
): /* Register indirect w/displacement, long. */
1571 t
= GET_L_REG (rn
) + abs
;
1572 t
&= h8_get_mask (sd
);
1573 SET_MEMORY_L (t
, n
);
1577 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1578 case X (OP_MEM
, SW
): /* Why isn't this implemented? */
1579 case X (OP_MEM
, SL
): /* Why isn't this implemented? */
1581 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1590 store (SIM_DESC sd
, ea_type
*arg
, int n
)
1592 return store_1 (sd
, arg
, n
, 0);
1595 /* Store which follows a fetch from the same location.
1596 The difference being that we don't want to do a pre-increment
1597 or pre-decrement at this time: it was already done when we fetched. */
1600 store2 (SIM_DESC sd
, ea_type
*arg
, int n
)
1602 return store_1 (sd
, arg
, n
, 1);
1605 /* Flag to be set whenever a new SIM_DESC object is created. */
1606 static int init_pointers_needed
= 1;
1609 init_pointers (SIM_DESC sd
)
1611 if (init_pointers_needed
)
1615 if (h8300smode
&& !h8300_normal_mode
)
1616 memory_size
= H8300S_MSIZE
;
1617 else if (h8300hmode
&& !h8300_normal_mode
)
1618 memory_size
= H8300H_MSIZE
;
1620 memory_size
= H8300_MSIZE
;
1621 /* `msize' must be a power of two. */
1622 if ((memory_size
& (memory_size
- 1)) != 0)
1626 "init_pointers: bad memory size %d, defaulting to %d.\n",
1627 memory_size
, memory_size
= H8300S_MSIZE
);
1630 if (h8_get_memory_buf (sd
))
1631 free (h8_get_memory_buf (sd
));
1633 h8_set_memory_buf (sd
, (unsigned char *)
1634 calloc (sizeof (char), memory_size
));
1635 sd
->memory_size
= memory_size
;
1637 h8_set_mask (sd
, memory_size
- 1);
1639 memset (h8_get_reg_buf (sd
), 0, sizeof (((STATE_CPU (sd
, 0))->regs
)));
1641 for (i
= 0; i
< 8; i
++)
1643 /* FIXME: rewrite using local buffer. */
1644 unsigned char *p
= (unsigned char *) (h8_get_reg_buf (sd
) + i
);
1645 unsigned char *e
= (unsigned char *) (h8_get_reg_buf (sd
) + i
+ 1);
1646 unsigned short *q
= (unsigned short *) (h8_get_reg_buf (sd
) + i
);
1647 unsigned short *u
= (unsigned short *) (h8_get_reg_buf (sd
) + i
+ 1);
1648 h8_set_reg (sd
, i
, 0x00112233);
1663 wreg
[i
] = wreg
[i
+ 8] = 0;
1677 if (wreg
[i
] == 0 || wreg
[i
+ 8] == 0)
1678 sim_io_printf (sd
, "init_pointers: internal error.\n");
1680 h8_set_reg (sd
, i
, 0);
1683 init_pointers_needed
= 0;
1687 #define OBITOP(name, f, s, op) \
1688 case O (name, SB): \
1693 if (fetch (sd, &code->dst, &ea)) \
1695 if (fetch (sd, &code->src, &tmp)) \
1697 m = 1 << (tmp & 7); \
1700 if (store (sd, &code->dst,ea)) \
1706 step_once (SIM_DESC sd
, SIM_CPU
*cpu
)
1710 int tick_start
= get_now ();
1717 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
1720 host_callback
*sim_callback
= STATE_CALLBACK (sd
);
1724 pc
= h8_get_pc (sd
);
1726 /* The PC should never be odd. */
1729 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGBUS
);
1733 /* Get Status Register (flags). */
1736 if (h8300smode
) /* Get exr. */
1738 trace
= (h8_get_exr (sd
) >> 7) & 1;
1739 intMask
= h8_get_exr (sd
) & 7;
1742 oldmask
= h8_get_mask (sd
);
1743 if (!h8300hmode
|| h8300_normal_mode
)
1744 h8_set_mask (sd
, 0xffff);
1747 decoded_inst _code
, *code
= &_code
;
1748 memset (code
, 0, sizeof (*code
));
1749 decode (sd
, pc
, h8_get_memory_buf (sd
) + pc
, code
);
1755 printf ("%x %d %s\n", pc
, code
->opcode
,
1756 code
->op
? code
->op
->name
: "**");
1758 h8_increment_stats (sd
, code
->opcode
);
1763 cycles
+= code
->cycles
;
1767 switch (code
->opcode
)
1769 case O (O_MOVAB
, SL
):
1770 case O (O_MOVAW
, SL
):
1771 case O (O_MOVAL
, SL
):
1772 /* 1) Evaluate 2nd argument (dst).
1773 2) Mask / zero extend according to whether 1st argument (src)
1774 is INDEXB, INDEXW, or INDEXL.
1775 3) Left-shift the result by 0, 1 or 2, according to size of mova
1776 (mova/b, mova/w, mova/l).
1777 4) Add literal value of 1st argument (src).
1778 5) Store result in 3rd argument (op3).
1781 /* Alas, since this is the only instruction with 3 arguments,
1782 decode doesn't handle them very well. Some fix-up is required.
1784 a) The size of dst is determined by whether src is
1785 INDEXB or INDEXW. */
1787 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1788 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SB
);
1789 else if (OP_KIND (code
->src
.type
) == OP_INDEXW
)
1790 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SW
);
1792 /* b) If op3 == null, then this is the short form of the insn.
1793 Dst is the dispreg of src, and op3 is the 32-bit form
1794 of the same register.
1797 if (code
->op3
.type
== 0)
1799 /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
1800 We get to compose dst and op3 as follows:
1802 op3 is a 32-bit register, ID == src.reg.
1803 dst is the same register, but 8 or 16 bits
1804 depending on whether src is INDEXB or INDEXW.
1807 code
->op3
.type
= X (OP_REG
, SL
);
1808 code
->op3
.reg
= code
->src
.reg
;
1809 code
->op3
.literal
= 0;
1811 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1813 code
->dst
.type
= X (OP_REG
, SB
);
1814 code
->dst
.reg
= code
->op3
.reg
+ 8;
1817 code
->dst
.type
= X (OP_REG
, SW
);
1820 if (fetch (sd
, &code
->dst
, &ea
))
1823 switch (OP_KIND (code
->src
.type
)) {
1824 case OP_INDEXB
: ea
= ea
& 0xff; break;
1825 case OP_INDEXW
: ea
= ea
& 0xffff; break;
1826 case OP_INDEXL
: break;
1827 default: goto illegal
;
1830 switch (code
->opcode
) {
1831 case O (O_MOVAB
, SL
): break;
1832 case O (O_MOVAW
, SL
): ea
= ea
<< 1; break;
1833 case O (O_MOVAL
, SL
): ea
= ea
<< 2; break;
1834 default: goto illegal
;
1837 ea
= ea
+ code
->src
.literal
;
1839 if (store (sd
, &code
->op3
, ea
))
1844 case O (O_SUBX
, SB
): /* subx, extended sub */
1845 if (fetch2 (sd
, &code
->dst
, &rd
))
1847 if (fetch (sd
, &code
->src
, &ea
))
1853 case O (O_SUBX
, SW
): /* subx, extended sub */
1854 if (fetch2 (sd
, &code
->dst
, &rd
))
1856 if (fetch (sd
, &code
->src
, &ea
))
1862 case O (O_SUBX
, SL
): /* subx, extended sub */
1863 if (fetch2 (sd
, &code
->dst
, &rd
))
1865 if (fetch (sd
, &code
->src
, &ea
))
1871 case O (O_ADDX
, SB
): /* addx, extended add */
1872 if (fetch2 (sd
, &code
->dst
, &rd
))
1874 if (fetch (sd
, &code
->src
, &ea
))
1880 case O (O_ADDX
, SW
): /* addx, extended add */
1881 if (fetch2 (sd
, &code
->dst
, &rd
))
1883 if (fetch (sd
, &code
->src
, &ea
))
1889 case O (O_ADDX
, SL
): /* addx, extended add */
1890 if (fetch2 (sd
, &code
->dst
, &rd
))
1892 if (fetch (sd
, &code
->src
, &ea
))
1898 case O (O_SUB
, SB
): /* sub.b */
1899 /* Fetch rd and ea. */
1900 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1906 case O (O_SUB
, SW
): /* sub.w */
1907 /* Fetch rd and ea. */
1908 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1914 case O (O_SUB
, SL
): /* sub.l */
1915 /* Fetch rd and ea. */
1916 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1922 case O (O_NEG
, SB
): /* neg.b */
1924 if (fetch2 (sd
, &code
->src
, &ea
))
1931 case O (O_NEG
, SW
): /* neg.w */
1933 if (fetch2 (sd
, &code
->src
, &ea
))
1940 case O (O_NEG
, SL
): /* neg.l */
1942 if (fetch2 (sd
, &code
->src
, &ea
))
1949 case O (O_ADD
, SB
): /* add.b */
1950 if (fetch2 (sd
, &code
->dst
, &rd
))
1952 if (fetch (sd
, &code
->src
, &ea
))
1957 case O (O_ADD
, SW
): /* add.w */
1958 if (fetch2 (sd
, &code
->dst
, &rd
))
1960 if (fetch (sd
, &code
->src
, &ea
))
1965 case O (O_ADD
, SL
): /* add.l */
1966 if (fetch2 (sd
, &code
->dst
, &rd
))
1968 if (fetch (sd
, &code
->src
, &ea
))
1973 case O (O_AND
, SB
): /* and.b */
1974 /* Fetch rd and ea. */
1975 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1980 case O (O_AND
, SW
): /* and.w */
1981 /* Fetch rd and ea. */
1982 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1987 case O (O_AND
, SL
): /* and.l */
1988 /* Fetch rd and ea. */
1989 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1994 case O (O_OR
, SB
): /* or.b */
1995 /* Fetch rd and ea. */
1996 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2001 case O (O_OR
, SW
): /* or.w */
2002 /* Fetch rd and ea. */
2003 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2008 case O (O_OR
, SL
): /* or.l */
2009 /* Fetch rd and ea. */
2010 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2015 case O (O_XOR
, SB
): /* xor.b */
2016 /* Fetch rd and ea. */
2017 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2022 case O (O_XOR
, SW
): /* xor.w */
2023 /* Fetch rd and ea. */
2024 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2029 case O (O_XOR
, SL
): /* xor.l */
2030 /* Fetch rd and ea. */
2031 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2037 if (fetch (sd
, &code
->src
, &res
))
2039 if (store (sd
, &code
->dst
, res
))
2041 goto just_flags_log8
;
2043 if (fetch (sd
, &code
->src
, &res
))
2045 if (store (sd
, &code
->dst
, res
))
2047 goto just_flags_log16
;
2049 if (fetch (sd
, &code
->src
, &res
))
2051 if (store (sd
, &code
->dst
, res
))
2053 goto just_flags_log32
;
2055 case O (O_MOVMD
, SB
): /* movmd.b */
2062 rd
= GET_MEMORY_B (GET_L_REG (5));
2063 SET_MEMORY_B (GET_L_REG (6), rd
);
2064 SET_L_REG (5, GET_L_REG (5) + 1);
2065 SET_L_REG (6, GET_L_REG (6) + 1);
2070 case O (O_MOVMD
, SW
): /* movmd.w */
2077 rd
= GET_MEMORY_W (GET_L_REG (5));
2078 SET_MEMORY_W (GET_L_REG (6), rd
);
2079 SET_L_REG (5, GET_L_REG (5) + 2);
2080 SET_L_REG (6, GET_L_REG (6) + 2);
2085 case O (O_MOVMD
, SL
): /* movmd.l */
2092 rd
= GET_MEMORY_L (GET_L_REG (5));
2093 SET_MEMORY_L (GET_L_REG (6), rd
);
2094 SET_L_REG (5, GET_L_REG (5) + 4);
2095 SET_L_REG (6, GET_L_REG (6) + 4);
2100 case O (O_MOVSD
, SB
): /* movsd.b */
2101 /* This instruction implements strncpy, with a conditional branch.
2102 r4 contains n, r5 contains src, and r6 contains dst.
2103 The 16-bit displacement operand is added to the pc
2104 if and only if the end of string is reached before
2105 n bytes are transferred. */
2107 ea
= GET_L_REG (4) & 0xffff;
2113 rd
= GET_MEMORY_B (GET_L_REG (5));
2114 SET_MEMORY_B (GET_L_REG (6), rd
);
2115 SET_L_REG (5, GET_L_REG (5) + 1);
2116 SET_L_REG (6, GET_L_REG (6) + 1);
2123 case O (O_EEPMOV
, SB
): /* eepmov.b */
2124 case O (O_EEPMOV
, SW
): /* eepmov.w */
2125 if (h8300hmode
|| h8300smode
)
2127 register unsigned char *_src
, *_dst
;
2128 unsigned int count
= ((code
->opcode
== O (O_EEPMOV
, SW
))
2129 ? h8_get_reg (sd
, R4_REGNUM
) & 0xffff
2130 : h8_get_reg (sd
, R4_REGNUM
) & 0xff);
2132 _src
= h8_get_memory_buf (sd
) + h8_get_reg (sd
, R5_REGNUM
);
2133 if ((_src
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2135 _dst
= h8_get_memory_buf (sd
) + h8_get_reg (sd
, R6_REGNUM
);
2136 if ((_dst
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2138 memcpy (_dst
, _src
, count
);
2140 h8_set_reg (sd
, R5_REGNUM
, h8_get_reg (sd
, R5_REGNUM
) + count
);
2141 h8_set_reg (sd
, R6_REGNUM
, h8_get_reg (sd
, R6_REGNUM
) + count
);
2142 h8_set_reg (sd
, R4_REGNUM
, h8_get_reg (sd
, R4_REGNUM
) &
2143 ((code
->opcode
== O (O_EEPMOV
, SW
))
2144 ? (~0xffff) : (~0xff)));
2145 cycles
+= 2 * count
;
2150 case O (O_ADDS
, SL
): /* adds (.l) */
2152 * This insn only uses register operands, but still
2153 * it would be cleaner to use fetch and store... */
2154 SET_L_REG (code
->dst
.reg
,
2155 GET_L_REG (code
->dst
.reg
)
2156 + code
->src
.literal
);
2160 case O (O_SUBS
, SL
): /* subs (.l) */
2162 * This insn only uses register operands, but still
2163 * it would be cleaner to use fetch and store... */
2164 SET_L_REG (code
->dst
.reg
,
2165 GET_L_REG (code
->dst
.reg
)
2166 - code
->src
.literal
);
2169 case O (O_CMP
, SB
): /* cmp.b */
2170 if (fetch (sd
, &code
->dst
, &rd
))
2172 if (fetch (sd
, &code
->src
, &ea
))
2176 goto just_flags_alu8
;
2178 case O (O_CMP
, SW
): /* cmp.w */
2179 if (fetch (sd
, &code
->dst
, &rd
))
2181 if (fetch (sd
, &code
->src
, &ea
))
2185 goto just_flags_alu16
;
2187 case O (O_CMP
, SL
): /* cmp.l */
2188 if (fetch (sd
, &code
->dst
, &rd
))
2190 if (fetch (sd
, &code
->src
, &ea
))
2194 goto just_flags_alu32
;
2196 case O (O_DEC
, SB
): /* dec.b */
2198 * This insn only uses register operands, but still
2199 * it would be cleaner to use fetch and store... */
2200 rd
= GET_B_REG (code
->src
.reg
);
2203 SET_B_REG (code
->src
.reg
, res
);
2204 goto just_flags_inc8
;
2206 case O (O_DEC
, SW
): /* dec.w */
2208 * This insn only uses register operands, but still
2209 * it would be cleaner to use fetch and store... */
2210 rd
= GET_W_REG (code
->dst
.reg
);
2211 ea
= -code
->src
.literal
;
2213 SET_W_REG (code
->dst
.reg
, res
);
2214 goto just_flags_inc16
;
2216 case O (O_DEC
, SL
): /* dec.l */
2218 * This insn only uses register operands, but still
2219 * it would be cleaner to use fetch and store... */
2220 rd
= GET_L_REG (code
->dst
.reg
);
2221 ea
= -code
->src
.literal
;
2223 SET_L_REG (code
->dst
.reg
, res
);
2224 goto just_flags_inc32
;
2226 case O (O_INC
, SB
): /* inc.b */
2228 * This insn only uses register operands, but still
2229 * it would be cleaner to use fetch and store... */
2230 rd
= GET_B_REG (code
->src
.reg
);
2233 SET_B_REG (code
->src
.reg
, res
);
2234 goto just_flags_inc8
;
2236 case O (O_INC
, SW
): /* inc.w */
2238 * This insn only uses register operands, but still
2239 * it would be cleaner to use fetch and store... */
2240 rd
= GET_W_REG (code
->dst
.reg
);
2241 ea
= code
->src
.literal
;
2243 SET_W_REG (code
->dst
.reg
, res
);
2244 goto just_flags_inc16
;
2246 case O (O_INC
, SL
): /* inc.l */
2248 * This insn only uses register operands, but still
2249 * it would be cleaner to use fetch and store... */
2250 rd
= GET_L_REG (code
->dst
.reg
);
2251 ea
= code
->src
.literal
;
2253 SET_L_REG (code
->dst
.reg
, res
);
2254 goto just_flags_inc32
;
2256 case O (O_LDC
, SB
): /* ldc.b */
2257 if (fetch (sd
, &code
->src
, &res
))
2261 case O (O_LDC
, SW
): /* ldc.w */
2262 if (fetch (sd
, &code
->src
, &res
))
2265 /* Word operand, value from MSB, must be shifted. */
2269 case O (O_LDC
, SL
): /* ldc.l */
2270 if (fetch (sd
, &code
->src
, &res
))
2272 switch (code
->dst
.type
) {
2273 case X (OP_SBR
, SL
):
2274 h8_set_sbr (sd
, res
);
2276 case X (OP_VBR
, SL
):
2277 h8_set_vbr (sd
, res
);
2284 case O (O_STC
, SW
): /* stc.w */
2285 case O (O_STC
, SB
): /* stc.b */
2286 if (code
->src
.type
== X (OP_CCR
, SB
))
2289 res
= h8_get_ccr (sd
);
2291 else if (code
->src
.type
== X (OP_EXR
, SB
) && h8300smode
)
2294 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2295 res
= h8_get_exr (sd
);
2300 /* Word operand, value to MSB, must be shifted. */
2301 if (code
->opcode
== X (O_STC
, SW
))
2303 if (store (sd
, &code
->dst
, res
))
2306 case O (O_STC
, SL
): /* stc.l */
2307 switch (code
->src
.type
) {
2308 case X (OP_SBR
, SL
):
2309 res
= h8_get_sbr (sd
);
2311 case X (OP_VBR
, SL
):
2312 res
= h8_get_vbr (sd
);
2317 if (store (sd
, &code
->dst
, res
))
2321 case O (O_ANDC
, SB
): /* andc.b */
2322 if (code
->dst
.type
== X (OP_CCR
, SB
))
2325 rd
= h8_get_ccr (sd
);
2327 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2330 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2331 rd
= h8_get_exr (sd
);
2335 ea
= code
->src
.literal
;
2339 case O (O_ORC
, SB
): /* orc.b */
2340 if (code
->dst
.type
== X (OP_CCR
, SB
))
2343 rd
= h8_get_ccr (sd
);
2345 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2348 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2349 rd
= h8_get_exr (sd
);
2353 ea
= code
->src
.literal
;
2357 case O (O_XORC
, SB
): /* xorc.b */
2358 if (code
->dst
.type
== X (OP_CCR
, SB
))
2361 rd
= h8_get_ccr (sd
);
2363 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2366 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2367 rd
= h8_get_exr (sd
);
2371 ea
= code
->src
.literal
;
2375 case O (O_BRAS
, SB
): /* bra/s */
2376 /* This is basically an ordinary branch, with a delay slot. */
2377 if (fetch (sd
, &code
->src
, &res
))
2385 /* Execution continues at next instruction, but
2386 delayed_branch is set up for next cycle. */
2387 h8_set_delayed_branch (sd
, code
->next_pc
+ res
);
2391 case O (O_BRAB
, SB
): /* bra rd.b */
2392 case O (O_BRAW
, SW
): /* bra rd.w */
2393 case O (O_BRAL
, SL
): /* bra erd.l */
2394 if (fetch (sd
, &code
->src
, &rd
))
2396 switch (OP_SIZE (code
->opcode
)) {
2397 case SB
: rd
&= 0xff; break;
2398 case SW
: rd
&= 0xffff; break;
2399 case SL
: rd
&= 0xffffffff; break;
2401 pc
= code
->next_pc
+ rd
;
2404 case O (O_BRABC
, SB
): /* bra/bc, branch if bit clear */
2405 case O (O_BRABS
, SB
): /* bra/bs, branch if bit set */
2406 case O (O_BSRBC
, SB
): /* bsr/bc, call if bit clear */
2407 case O (O_BSRBS
, SB
): /* bsr/bs, call if bit set */
2408 if (fetch (sd
, &code
->dst
, &rd
) ||
2409 fetch (sd
, &code
->src
, &bit
))
2412 if (code
->opcode
== O (O_BRABC
, SB
) || /* branch if clear */
2413 code
->opcode
== O (O_BSRBC
, SB
)) /* call if clear */
2415 if ((rd
& (1 << bit
))) /* no branch */
2418 else /* branch/call if set */
2420 if (!(rd
& (1 << bit
))) /* no branch */
2424 if (fetch (sd
, &code
->op3
, &res
)) /* branch */
2426 pc
= code
->next_pc
+ res
;
2428 if (code
->opcode
== O (O_BRABC
, SB
) ||
2429 code
->opcode
== O (O_BRABS
, SB
)) /* branch */
2437 case O (O_BRA
, SB
): /* bra, branch always */
2442 case O (O_BRN
, SB
): /* brn, ;-/ branch never? */
2447 case O (O_BHI
, SB
): /* bhi */
2453 case O (O_BLS
, SB
): /* bls */
2458 case O (O_BCS
, SB
): /* bcs, branch if carry set */
2463 case O (O_BCC
, SB
): /* bcc, branch if carry clear */
2468 case O (O_BEQ
, SB
): /* beq, branch if zero set */
2472 case O (O_BGT
, SB
): /* bgt */
2473 if (((Z
|| (N
^ V
)) == 0))
2477 case O (O_BLE
, SB
): /* ble */
2478 if (((Z
|| (N
^ V
)) == 1))
2482 case O (O_BGE
, SB
): /* bge */
2486 case O (O_BLT
, SB
): /* blt */
2490 case O (O_BMI
, SB
): /* bmi */
2494 case O (O_BNE
, SB
): /* bne, branch if zero clear */
2499 case O (O_BPL
, SB
): /* bpl */
2503 case O (O_BVC
, SB
): /* bvc */
2507 case O (O_BVS
, SB
): /* bvs */
2512 /* Trap for Command Line setup. */
2513 case O (O_SYS_CMDLINE
, SB
):
2515 int i
= 0; /* Loop counter. */
2516 int j
= 0; /* Loop counter. */
2517 int ind_arg_len
= 0; /* Length of each argument. */
2518 int no_of_args
= 0; /* The no. or cmdline args. */
2519 int current_location
= 0; /* Location of string. */
2520 int old_sp
= 0; /* The Initial Stack Pointer. */
2521 int no_of_slots
= 0; /* No. of slots required on the stack
2522 for storing cmdline args. */
2523 int sp_move
= 0; /* No. of locations by which the stack needs
2525 int new_sp
= 0; /* The final stack pointer location passed
2527 int *argv_ptrs
; /* Pointers of argv strings to be stored. */
2528 int argv_ptrs_location
= 0; /* Location of pointers to cmdline
2529 args on the stack. */
2530 int char_ptr_size
= 0; /* Size of a character pointer on
2532 int addr_cmdline
= 0; /* Memory location where cmdline has
2534 int size_cmdline
= 0; /* Size of cmdline. */
2536 /* Set the address of 256 free locations where command line is
2538 addr_cmdline
= cmdline_location();
2539 h8_set_reg (sd
, 0, addr_cmdline
);
2541 /* Counting the no. of commandline arguments. */
2542 for (i
= 0; h8_get_cmdline_arg (sd
, i
) != NULL
; i
++)
2545 /* No. of arguments in the command line. */
2548 /* Current location is just a temporary variable,which we are
2549 setting to the point to the start of our commandline string. */
2550 current_location
= addr_cmdline
;
2552 /* Allocating space for storing pointers of the command line
2554 argv_ptrs
= (int *) malloc (sizeof (int) * no_of_args
);
2556 /* Setting char_ptr_size to the sizeof (char *) on the different
2558 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2567 for (i
= 0; i
< no_of_args
; i
++)
2571 /* The size of the commandline argument. */
2572 ind_arg_len
= strlen (h8_get_cmdline_arg (sd
, i
)) + 1;
2574 /* The total size of the command line string. */
2575 size_cmdline
+= ind_arg_len
;
2577 /* As we have only 256 bytes, we need to provide a graceful
2578 exit. Anyways, a program using command line arguments
2579 where we cannot store all the command line arguments
2580 given may behave unpredictably. */
2581 if (size_cmdline
>= 256)
2583 h8_set_reg (sd
, 0, 0);
2588 /* current_location points to the memory where the next
2589 commandline argument is stored. */
2590 argv_ptrs
[i
] = current_location
;
2591 for (j
= 0; j
< ind_arg_len
; j
++)
2593 SET_MEMORY_B ((current_location
+
2594 (sizeof (char) * j
)),
2595 *(h8_get_cmdline_arg (sd
, i
) +
2596 sizeof (char) * j
));
2599 /* Setting current_location to the starting of next
2601 current_location
+= ind_arg_len
;
2605 /* This is the original position of the stack pointer. */
2606 old_sp
= h8_get_reg (sd
, SP_REGNUM
);
2608 /* We need space from the stack to store the pointers to argvs. */
2609 /* As we will infringe on the stack, we need to shift the stack
2610 pointer so that the data is not overwritten. We calculate how
2611 much space is required. */
2612 sp_move
= (no_of_args
) * (char_ptr_size
);
2614 /* The final position of stack pointer, we have thus taken some
2615 space from the stack. */
2616 new_sp
= old_sp
- sp_move
;
2618 /* Temporary variable holding value where the argv pointers need
2620 argv_ptrs_location
= new_sp
;
2622 /* The argv pointers are stored at sequential locations. As per
2624 for (i
= 0; i
< no_of_args
; i
++)
2626 /* Saving the argv pointer. */
2627 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2629 SET_MEMORY_L (argv_ptrs_location
, argv_ptrs
[i
]);
2633 SET_MEMORY_W (argv_ptrs_location
, argv_ptrs
[i
]);
2636 /* The next location where the pointer to the next argv
2637 string has to be stored. */
2638 argv_ptrs_location
+= char_ptr_size
;
2641 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2643 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2645 SET_MEMORY_L (old_sp
, 0x0);
2649 SET_MEMORY_W (old_sp
, 0x0);
2652 /* Freeing allocated memory. */
2654 for (i
= 0; i
<= no_of_args
; i
++)
2656 free (h8_get_cmdline_arg (sd
, i
));
2658 free (h8_get_command_line (sd
));
2660 /* The no. of argv arguments are returned in Reg 0. */
2661 h8_set_reg (sd
, 0, no_of_args
);
2662 /* The Pointer to argv in Register 1. */
2663 h8_set_reg (sd
, 1, new_sp
);
2664 /* Setting the stack pointer to the new value. */
2665 h8_set_reg (sd
, SP_REGNUM
, new_sp
);
2669 /* System call processing starts. */
2670 case O (O_SYS_OPEN
, SB
):
2672 int len
= 0; /* Length of filename. */
2673 char *filename
; /* Filename would go here. */
2674 char temp_char
; /* Temporary character */
2675 int mode
= 0; /* Mode bits for the file. */
2676 int open_return
; /* Return value of open, file descriptor. */
2677 int i
; /* Loop counter */
2678 int filename_ptr
; /* Pointer to filename in cpu memory. */
2680 /* Setting filename_ptr to first argument of open, */
2681 /* and trying to get mode. */
2682 if ((h8300sxmode
|| h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2684 filename_ptr
= GET_L_REG (0);
2685 mode
= GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
) + 4);
2689 filename_ptr
= GET_W_REG (0);
2690 mode
= GET_MEMORY_W (h8_get_reg (sd
, SP_REGNUM
) + 2);
2693 /* Trying to find the length of the filename. */
2694 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2697 while (temp_char
!= '\0')
2699 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2703 /* Allocating space for the filename. */
2704 filename
= (char *) malloc (sizeof (char) * len
);
2706 /* String copying the filename from memory. */
2707 for (i
= 0; i
< len
; i
++)
2709 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2710 filename
[i
] = temp_char
;
2713 /* Callback to open and return the file descriptor. */
2714 open_return
= sim_callback
->open (sim_callback
, filename
, mode
);
2716 /* Return value in register 0. */
2717 h8_set_reg (sd
, 0, open_return
);
2719 /* Freeing memory used for filename. */
2724 case O (O_SYS_READ
, SB
):
2726 char *char_ptr
; /* Where characters read would be stored. */
2727 int fd
; /* File descriptor */
2728 int buf_size
; /* BUF_SIZE parameter in read. */
2729 int i
= 0; /* Temporary Loop counter */
2730 int read_return
= 0; /* Return value from callback to
2733 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2734 buf_size
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2736 char_ptr
= (char *) malloc (sizeof (char) * buf_size
);
2738 /* Callback to read and return the no. of characters read. */
2740 sim_callback
->read (sim_callback
, fd
, char_ptr
, buf_size
);
2742 /* The characters read are stored in cpu memory. */
2743 for (i
= 0; i
< buf_size
; i
++)
2745 SET_MEMORY_B ((h8_get_reg (sd
, 1) + (sizeof (char) * i
)),
2746 *(char_ptr
+ (sizeof (char) * i
)));
2749 /* Return value in Register 0. */
2750 h8_set_reg (sd
, 0, read_return
);
2752 /* Freeing memory used as buffer. */
2757 case O (O_SYS_WRITE
, SB
):
2759 int fd
; /* File descriptor */
2760 char temp_char
; /* Temporary character */
2761 int len
; /* Length of write, Parameter II to write. */
2762 int char_ptr
; /* Character Pointer, Parameter I of write. */
2763 char *ptr
; /* Where characters to be written are stored.
2765 int write_return
; /* Return value from callback to write. */
2766 int i
= 0; /* Loop counter */
2768 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2769 char_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2770 len
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2772 /* Allocating space for the characters to be written. */
2773 ptr
= (char *) malloc (sizeof (char) * len
);
2775 /* Fetching the characters from cpu memory. */
2776 for (i
= 0; i
< len
; i
++)
2778 temp_char
= GET_MEMORY_B (char_ptr
+ i
);
2782 /* Callback write and return the no. of characters written. */
2783 write_return
= sim_callback
->write (sim_callback
, fd
, ptr
, len
);
2785 /* Return value in Register 0. */
2786 h8_set_reg (sd
, 0, write_return
);
2788 /* Freeing memory used as buffer. */
2793 case O (O_SYS_LSEEK
, SB
):
2795 int fd
; /* File descriptor */
2796 int offset
; /* Offset */
2797 int origin
; /* Origin */
2798 int lseek_return
; /* Return value from callback to lseek. */
2800 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2801 offset
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2802 origin
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2804 /* Callback lseek and return offset. */
2806 sim_callback
->lseek (sim_callback
, fd
, offset
, origin
);
2808 /* Return value in register 0. */
2809 h8_set_reg (sd
, 0, lseek_return
);
2813 case O (O_SYS_CLOSE
, SB
):
2815 int fd
; /* File descriptor */
2816 int close_return
; /* Return value from callback to close. */
2818 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2820 /* Callback close and return. */
2821 close_return
= sim_callback
->close (sim_callback
, fd
);
2823 /* Return value in register 0. */
2824 h8_set_reg (sd
, 0, close_return
);
2828 case O (O_SYS_FSTAT
, SB
):
2830 int fd
; /* File descriptor */
2831 struct stat stat_rec
; /* Stat record */
2832 int fstat_return
; /* Return value from callback to stat. */
2833 int stat_ptr
; /* Pointer to stat record. */
2834 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2836 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2838 /* Setting stat_ptr to second argument of stat. */
2839 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2841 /* Callback stat and return. */
2842 fstat_return
= sim_callback
->to_fstat (sim_callback
, fd
,
2845 /* Have stat_ptr point to starting of stat_rec. */
2846 temp_stat_ptr
= (char *) (&stat_rec
);
2848 /* Setting up the stat structure returned. */
2849 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
2851 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
2853 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
2855 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
2857 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
2859 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
2861 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
2863 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
2865 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
2867 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
2869 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
2871 /* Return value in register 0. */
2872 h8_set_reg (sd
, 0, fstat_return
);
2876 case O (O_SYS_STAT
, SB
):
2878 int len
= 0; /* Length of filename. */
2879 char *filename
; /* Filename would go here. */
2880 char temp_char
; /* Temporary character */
2881 int filename_ptr
; /* Pointer to filename in cpu memory. */
2882 struct stat stat_rec
; /* Stat record */
2883 int stat_return
; /* Return value from callback to stat */
2884 int stat_ptr
; /* Pointer to stat record. */
2885 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2886 int i
= 0; /* Loop Counter */
2888 /* Setting filename_ptr to first argument of open. */
2889 filename_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2891 /* Trying to find the length of the filename. */
2892 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2895 while (temp_char
!= '\0')
2897 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2901 /* Allocating space for the filename. */
2902 filename
= (char *) malloc (sizeof (char) * len
);
2904 /* String copying the filename from memory. */
2905 for (i
= 0; i
< len
; i
++)
2907 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2908 filename
[i
] = temp_char
;
2911 /* Setting stat_ptr to second argument of stat. */
2912 /* stat_ptr = h8_get_reg (sd, 1); */
2913 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2915 /* Callback stat and return. */
2917 sim_callback
->to_stat (sim_callback
, filename
, &stat_rec
);
2919 /* Have stat_ptr point to starting of stat_rec. */
2920 temp_stat_ptr
= (char *) (&stat_rec
);
2922 /* Freeing memory used for filename. */
2925 /* Setting up the stat structure returned. */
2926 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
2928 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
2930 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
2932 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
2934 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
2936 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
2938 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
2940 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
2942 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
2944 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
2946 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
2948 /* Return value in register 0. */
2949 h8_set_reg (sd
, 0, stat_return
);
2952 /* End of system call processing. */
2954 case O (O_NOT
, SB
): /* not.b */
2955 if (fetch2 (sd
, &code
->src
, &rd
))
2961 case O (O_NOT
, SW
): /* not.w */
2962 if (fetch2 (sd
, &code
->src
, &rd
))
2968 case O (O_NOT
, SL
): /* not.l */
2969 if (fetch2 (sd
, &code
->src
, &rd
))
2975 case O (O_SHLL
, SB
): /* shll.b */
2976 case O (O_SHLR
, SB
): /* shlr.b */
2977 if (fetch2 (sd
, &code
->dst
, &rd
))
2980 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
2981 ea
= 1; /* unary op */
2982 else /* binary op */
2983 fetch (sd
, &code
->src
, &ea
);
2985 if (code
->opcode
== O (O_SHLL
, SB
))
2988 c
= rd
& (0x80 >> (ea
- 1));
2994 c
= rd
& (1 << (ea
- 1));
2995 rd
= (unsigned char) rd
>> ea
;
2999 case O (O_SHLL
, SW
): /* shll.w */
3000 case O (O_SHLR
, SW
): /* shlr.w */
3001 if (fetch2 (sd
, &code
->dst
, &rd
))
3004 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3005 ea
= 1; /* unary op */
3007 fetch (sd
, &code
->src
, &ea
);
3009 if (code
->opcode
== O (O_SHLL
, SW
))
3012 c
= rd
& (0x8000 >> (ea
- 1));
3018 c
= rd
& (1 << (ea
- 1));
3019 rd
= (unsigned short) rd
>> ea
;
3023 case O (O_SHLL
, SL
): /* shll.l */
3024 case O (O_SHLR
, SL
): /* shlr.l */
3025 if (fetch2 (sd
, &code
->dst
, &rd
))
3028 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3029 ea
= 1; /* unary op */
3031 fetch (sd
, &code
->src
, &ea
);
3033 if (code
->opcode
== O (O_SHLL
, SL
))
3036 c
= rd
& (0x80000000 >> (ea
- 1));
3042 c
= rd
& (1 << (ea
- 1));
3043 rd
= (unsigned int) rd
>> ea
;
3047 case O (O_SHAL
, SB
):
3048 case O (O_SHAR
, SB
):
3049 if (fetch2 (sd
, &code
->dst
, &rd
))
3052 if (code
->src
.type
== X (OP_IMM
, SB
))
3053 fetch (sd
, &code
->src
, &ea
);
3057 if (code
->opcode
== O (O_SHAL
, SB
))
3059 c
= rd
& (0x80 >> (ea
- 1));
3060 res
= rd
>> (7 - ea
);
3061 v
= ((res
& 1) && !(res
& 2))
3062 || (!(res
& 1) && (res
& 2));
3067 c
= rd
& (1 << (ea
- 1));
3069 rd
= ((signed char) rd
) >> ea
;
3073 case O (O_SHAL
, SW
):
3074 case O (O_SHAR
, SW
):
3075 if (fetch2 (sd
, &code
->dst
, &rd
))
3078 if (code
->src
.type
== X (OP_IMM
, SW
))
3079 fetch (sd
, &code
->src
, &ea
);
3083 if (code
->opcode
== O (O_SHAL
, SW
))
3085 c
= rd
& (0x8000 >> (ea
- 1));
3086 res
= rd
>> (15 - ea
);
3087 v
= ((res
& 1) && !(res
& 2))
3088 || (!(res
& 1) && (res
& 2));
3093 c
= rd
& (1 << (ea
- 1));
3095 rd
= ((signed short) rd
) >> ea
;
3099 case O (O_SHAL
, SL
):
3100 case O (O_SHAR
, SL
):
3101 if (fetch2 (sd
, &code
->dst
, &rd
))
3104 if (code
->src
.type
== X (OP_IMM
, SL
))
3105 fetch (sd
, &code
->src
, &ea
);
3109 if (code
->opcode
== O (O_SHAL
, SL
))
3111 c
= rd
& (0x80000000 >> (ea
- 1));
3112 res
= rd
>> (31 - ea
);
3113 v
= ((res
& 1) && !(res
& 2))
3114 || (!(res
& 1) && (res
& 2));
3119 c
= rd
& (1 << (ea
- 1));
3121 rd
= ((signed int) rd
) >> ea
;
3125 case O (O_ROTL
, SB
):
3126 case O (O_ROTR
, SB
):
3127 if (fetch2 (sd
, &code
->dst
, &rd
))
3130 if (code
->src
.type
== X (OP_IMM
, SB
))
3131 fetch (sd
, &code
->src
, &ea
);
3136 if (code
->opcode
== O (O_ROTL
, SB
))
3146 rd
= ((unsigned char) rd
) >> 1;
3154 case O (O_ROTL
, SW
):
3155 case O (O_ROTR
, SW
):
3156 if (fetch2 (sd
, &code
->dst
, &rd
))
3159 if (code
->src
.type
== X (OP_IMM
, SW
))
3160 fetch (sd
, &code
->src
, &ea
);
3165 if (code
->opcode
== O (O_ROTL
, SW
))
3175 rd
= ((unsigned short) rd
) >> 1;
3183 case O (O_ROTL
, SL
):
3184 case O (O_ROTR
, SL
):
3185 if (fetch2 (sd
, &code
->dst
, &rd
))
3188 if (code
->src
.type
== X (OP_IMM
, SL
))
3189 fetch (sd
, &code
->src
, &ea
);
3194 if (code
->opcode
== O (O_ROTL
, SL
))
3196 c
= rd
& 0x80000000;
3204 rd
= ((unsigned int) rd
) >> 1;
3212 case O (O_ROTXL
, SB
):
3213 case O (O_ROTXR
, SB
):
3214 if (fetch2 (sd
, &code
->dst
, &rd
))
3217 if (code
->src
.type
== X (OP_IMM
, SB
))
3218 fetch (sd
, &code
->src
, &ea
);
3223 if (code
->opcode
== O (O_ROTXL
, SB
))
3234 rd
= ((unsigned char) rd
) >> 1;
3243 case O (O_ROTXL
, SW
):
3244 case O (O_ROTXR
, SW
):
3245 if (fetch2 (sd
, &code
->dst
, &rd
))
3248 if (code
->src
.type
== X (OP_IMM
, SW
))
3249 fetch (sd
, &code
->src
, &ea
);
3254 if (code
->opcode
== O (O_ROTXL
, SW
))
3265 rd
= ((unsigned short) rd
) >> 1;
3274 case O (O_ROTXL
, SL
):
3275 case O (O_ROTXR
, SL
):
3276 if (fetch2 (sd
, &code
->dst
, &rd
))
3279 if (code
->src
.type
== X (OP_IMM
, SL
))
3280 fetch (sd
, &code
->src
, &ea
);
3285 if (code
->opcode
== O (O_ROTXL
, SL
))
3287 res
= rd
& 0x80000000;
3296 rd
= ((unsigned int) rd
) >> 1;
3307 case O (O_JMP
, SB
): /* jmp */
3309 fetch (sd
, &code
->src
, &pc
);
3314 case O (O_JSR
, SB
): /* jsr, jump to subroutine */
3316 if (fetch (sd
, &code
->src
, &pc
))
3319 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3321 if (h8300hmode
&& !h8300_normal_mode
)
3324 SET_MEMORY_L (tmp
, code
->next_pc
);
3329 SET_MEMORY_W (tmp
, code
->next_pc
);
3331 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3337 case O (O_BSR
, SB
): /* bsr, branch to subroutine */
3338 if (fetch (sd
, &code
->src
, &res
))
3340 pc
= code
->next_pc
+ res
;
3343 case O (O_RTE
, SN
): /* rte, return from exception */
3345 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3346 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3348 if (h8300smode
) /* pop exr */
3350 h8_set_exr (sd
, GET_MEMORY_L (tmp
));
3353 if (h8300hmode
&& !h8300_normal_mode
)
3355 h8_set_ccr (sd
, GET_MEMORY_L (tmp
));
3357 pc
= GET_MEMORY_L (tmp
);
3362 h8_set_ccr (sd
, GET_MEMORY_W (tmp
));
3364 pc
= GET_MEMORY_W (tmp
);
3369 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3372 case O (O_RTS
, SN
): /* rts, return from subroutine */
3374 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3376 if (h8300hmode
&& !h8300_normal_mode
)
3378 pc
= GET_MEMORY_L (tmp
);
3383 pc
= GET_MEMORY_W (tmp
);
3387 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3390 case O (O_ILL
, SB
): /* illegal */
3391 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
3394 case O (O_SLEEP
, SN
): /* sleep */
3395 /* Check for magic numbers in r1 and r2. */
3396 if ((h8_get_reg (sd
, R1_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC1
&&
3397 (h8_get_reg (sd
, R2_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC2
&&
3398 SIM_WIFEXITED (h8_get_reg (sd
, 0)))
3400 /* This trap comes from _exit, not from gdb. */
3401 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_exited
,
3402 SIM_WEXITSTATUS (h8_get_reg (sd
, 0)));
3405 /* Unfortunately this won't really work, because
3406 when we take a breakpoint trap, R0 has a "random",
3407 user-defined value. Don't see any immediate solution. */
3408 else if (SIM_WIFSTOPPED (h8_get_reg (sd
, 0)))
3410 /* Pass the stop signal up to gdb. */
3411 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
,
3412 SIM_WSTOPSIG (h8_get_reg (sd
, 0)));
3417 /* Treat it as a sigtrap. */
3418 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3422 case O (O_TRAPA
, SB
): /* trapa */
3423 if (fetch (sd
, &code
->src
, &res
))
3424 goto end
; /* res is vector number. */
3426 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3427 if(h8300_normal_mode
)
3430 SET_MEMORY_W (tmp
, code
->next_pc
);
3432 SET_MEMORY_W (tmp
, h8_get_ccr (sd
));
3437 SET_MEMORY_L (tmp
, code
->next_pc
);
3439 SET_MEMORY_L (tmp
, h8_get_ccr (sd
));
3447 SET_MEMORY_L (tmp
, h8_get_exr (sd
));
3450 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3452 if(h8300_normal_mode
)
3453 pc
= GET_MEMORY_L (0x10 + res
* 2); /* Vector addresses are 0x10,0x12,0x14 and 0x16 */
3455 pc
= GET_MEMORY_L (0x20 + res
* 4);
3459 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3462 case O (O_BSETEQ
, SB
):
3467 case O (O_BSETNE
, SB
):
3472 case O (O_BCLREQ
, SB
):
3477 case O (O_BCLRNE
, SB
):
3482 OBITOP (O_BNOT
, 1, 1, ea
^= m
); /* bnot */
3483 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
); /* btst */
3485 OBITOP (O_BSET
, 1, 1, ea
|= m
); /* bset */
3487 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
); /* bclr */
3488 OBITOP (O_BLD
, 1, 0, c
= ea
& m
); /* bld */
3489 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
)); /* bild */
3490 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
3491 if (C
) ea
|= m
); /* bst */
3492 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
3493 if (!C
) ea
|= m
); /* bist */
3494 OBITOP (O_BSTZ
, 1, 1, ea
&= ~m
;
3495 if (Z
) ea
|= m
); /* bstz */
3496 OBITOP (O_BISTZ
, 1, 1, ea
&= ~m
;
3497 if (!Z
) ea
|= m
); /* bistz */
3498 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
); /* band */
3499 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
); /* biand */
3500 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
); /* bor */
3501 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
); /* bior */
3502 OBITOP (O_BXOR
, 1, 0, c
= ((ea
& m
) != 0)!= C
); /* bxor */
3503 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
); /* bixor */
3505 case O (O_BFLD
, SB
): /* bfld */
3508 if (fetch (sd
, &code
->src
, &bit
))
3513 if (fetch (sd
, &code
->dst
, &ea
))
3523 if (store (sd
, &code
->op3
, ea
))
3528 case O(O_BFST
, SB
): /* bfst */
3529 /* bitfield store */
3530 /* NOTE: the imm8 value is in dst, and the ea value
3531 (which is actually the destination) is in op3.
3532 It has to be that way, to avoid breaking the assembler. */
3534 if (fetch (sd
, &code
->dst
, &bit
)) /* imm8 */
3536 if (bit
== 0) /* noop -- nothing to do. */
3539 if (fetch (sd
, &code
->src
, &rd
)) /* reg8 src */
3542 if (fetch2 (sd
, &code
->op3
, &ea
)) /* ea dst */
3545 /* Left-shift the register data into position. */
3546 for (tmp
= bit
; !(tmp
& 1); tmp
>>= 1)
3549 /* Combine it with the neighboring bits. */
3550 ea
= (ea
& ~bit
) | (rd
& bit
);
3553 if (store2 (sd
, &code
->op3
, ea
))
3557 case O (O_CLRMAC
, SN
): /* clrmac */
3558 h8_set_mach (sd
, 0);
3559 h8_set_macl (sd
, 0);
3560 h8_set_macZ (sd
, 1);
3561 h8_set_macV (sd
, 0);
3562 h8_set_macN (sd
, 0);
3565 case O (O_STMAC
, SL
): /* stmac, 260 */
3566 switch (code
->src
.type
) {
3567 case X (OP_MACH
, SL
):
3568 res
= h8_get_mach (sd
);
3569 if (res
& 0x200) /* sign extend */
3572 case X (OP_MACL
, SL
):
3573 res
= h8_get_macl (sd
);
3575 default: goto illegal
;
3577 nz
= !h8_get_macZ (sd
);
3578 n
= h8_get_macN (sd
);
3579 v
= h8_get_macV (sd
);
3581 if (store (sd
, &code
->dst
, res
))
3586 case O (O_LDMAC
, SL
): /* ldmac, 179 */
3587 if (fetch (sd
, &code
->src
, &rd
))
3590 switch (code
->dst
.type
) {
3591 case X (OP_MACH
, SL
):
3592 rd
&= 0x3ff; /* Truncate to 10 bits */
3593 h8_set_mach (sd
, rd
);
3595 case X (OP_MACL
, SL
):
3596 h8_set_macl (sd
, rd
);
3598 default: goto illegal
;
3600 h8_set_macV (sd
, 0);
3604 if (fetch (sd
, &code
->src
, &rd
) ||
3605 fetch (sd
, &code
->dst
, &res
))
3608 /* Ye gods, this is non-portable!
3609 However, the existing mul/div code is similar. */
3610 res
= SEXTSHORT (res
) * SEXTSHORT (rd
);
3612 if (h8_get_macS (sd
)) /* Saturating mode */
3614 long long mac
= h8_get_macl (sd
);
3616 if (mac
& 0x80000000) /* sign extend */
3617 mac
|= 0xffffffff00000000LL
;
3620 if (mac
> 0x7fffffff || mac
< 0xffffffff80000000LL
)
3621 h8_set_macV (sd
, 1);
3622 h8_set_macZ (sd
, (mac
== 0));
3623 h8_set_macN (sd
, (mac
< 0));
3624 h8_set_macl (sd
, (int) mac
);
3626 else /* "Less Saturating" mode */
3628 long long mac
= h8_get_mach (sd
);
3630 mac
+= h8_get_macl (sd
);
3632 if (mac
& 0x20000000000LL
) /* sign extend */
3633 mac
|= 0xfffffc0000000000LL
;
3636 if (mac
> 0x1ffffffffffLL
||
3637 mac
< (long long) 0xfffffe0000000000LL
)
3638 h8_set_macV (sd
, 1);
3639 h8_set_macZ (sd
, (mac
== 0));
3640 h8_set_macN (sd
, (mac
< 0));
3641 h8_set_macl (sd
, (int) mac
);
3643 h8_set_mach (sd
, (int) (mac
& 0x3ff));
3647 case O (O_MULS
, SW
): /* muls.w */
3648 if (fetch (sd
, &code
->src
, &ea
) ||
3649 fetch (sd
, &code
->dst
, &rd
))
3652 ea
= SEXTSHORT (ea
);
3653 res
= SEXTSHORT (ea
* SEXTSHORT (rd
));
3657 if (store (sd
, &code
->dst
, res
))
3662 case O (O_MULS
, SL
): /* muls.l */
3663 if (fetch (sd
, &code
->src
, &ea
) ||
3664 fetch (sd
, &code
->dst
, &rd
))
3669 n
= res
& 0x80000000;
3670 nz
= res
& 0xffffffff;
3671 if (store (sd
, &code
->dst
, res
))
3675 case O (O_MULSU
, SL
): /* muls/u.l */
3676 if (fetch (sd
, &code
->src
, &ea
) ||
3677 fetch (sd
, &code
->dst
, &rd
))
3680 /* Compute upper 32 bits of the 64-bit result. */
3681 res
= (((long long) ea
) * ((long long) rd
)) >> 32;
3683 n
= res
& 0x80000000;
3684 nz
= res
& 0xffffffff;
3685 if (store (sd
, &code
->dst
, res
))
3689 case O (O_MULU
, SW
): /* mulu.w */
3690 if (fetch (sd
, &code
->src
, &ea
) ||
3691 fetch (sd
, &code
->dst
, &rd
))
3694 res
= UEXTSHORT ((UEXTSHORT (ea
) * UEXTSHORT (rd
)));
3696 /* Don't set Z or N. */
3697 if (store (sd
, &code
->dst
, res
))
3702 case O (O_MULU
, SL
): /* mulu.l */
3703 if (fetch (sd
, &code
->src
, &ea
) ||
3704 fetch (sd
, &code
->dst
, &rd
))
3709 /* Don't set Z or N. */
3710 if (store (sd
, &code
->dst
, res
))
3715 case O (O_MULUU
, SL
): /* mulu/u.l */
3716 if (fetch (sd
, &code
->src
, &ea
) ||
3717 fetch (sd
, &code
->dst
, &rd
))
3720 /* Compute upper 32 bits of the 64-bit result. */
3721 res
= (((unsigned long long) (unsigned) ea
) *
3722 ((unsigned long long) (unsigned) rd
)) >> 32;
3724 /* Don't set Z or N. */
3725 if (store (sd
, &code
->dst
, res
))
3730 case O (O_MULXS
, SB
): /* mulxs.b */
3731 if (fetch (sd
, &code
->src
, &ea
) ||
3732 fetch (sd
, &code
->dst
, &rd
))
3736 res
= ea
* SEXTCHAR (rd
);
3740 if (store (sd
, &code
->dst
, res
))
3745 case O (O_MULXS
, SW
): /* mulxs.w */
3746 if (fetch (sd
, &code
->src
, &ea
) ||
3747 fetch (sd
, &code
->dst
, &rd
))
3750 ea
= SEXTSHORT (ea
);
3751 res
= ea
* SEXTSHORT (rd
& 0xffff);
3753 n
= res
& 0x80000000;
3754 nz
= res
& 0xffffffff;
3755 if (store (sd
, &code
->dst
, res
))
3760 case O (O_MULXU
, SB
): /* mulxu.b */
3761 if (fetch (sd
, &code
->src
, &ea
) ||
3762 fetch (sd
, &code
->dst
, &rd
))
3765 res
= UEXTCHAR (ea
) * UEXTCHAR (rd
);
3767 if (store (sd
, &code
->dst
, res
))
3772 case O (O_MULXU
, SW
): /* mulxu.w */
3773 if (fetch (sd
, &code
->src
, &ea
) ||
3774 fetch (sd
, &code
->dst
, &rd
))
3777 res
= UEXTSHORT (ea
) * UEXTSHORT (rd
);
3779 if (store (sd
, &code
->dst
, res
))
3784 case O (O_TAS
, SB
): /* tas (test and set) */
3785 if (!h8300sxmode
) /* h8sx can use any register. */
3786 switch (code
->src
.reg
)
3797 if (fetch (sd
, &code
->src
, &res
))
3799 if (store (sd
, &code
->src
, res
| 0x80))
3802 goto just_flags_log8
;
3804 case O (O_DIVU
, SW
): /* divu.w */
3805 if (fetch (sd
, &code
->src
, &ea
) ||
3806 fetch (sd
, &code
->dst
, &rd
))
3812 res
= (unsigned) (UEXTSHORT (rd
) / UEXTSHORT (ea
));
3816 if (store (sd
, &code
->dst
, res
))
3820 case O (O_DIVU
, SL
): /* divu.l */
3821 if (fetch (sd
, &code
->src
, &ea
) ||
3822 fetch (sd
, &code
->dst
, &rd
))
3825 n
= ea
& 0x80000000;
3826 nz
= ea
& 0xffffffff;
3828 res
= (unsigned) rd
/ ea
;
3832 if (store (sd
, &code
->dst
, res
))
3836 case O (O_DIVS
, SW
): /* divs.w */
3837 if (fetch (sd
, &code
->src
, &ea
) ||
3838 fetch (sd
, &code
->dst
, &rd
))
3843 res
= SEXTSHORT (rd
) / SEXTSHORT (ea
);
3853 if (store (sd
, &code
->dst
, res
))
3857 case O (O_DIVS
, SL
): /* divs.l */
3858 if (fetch (sd
, &code
->src
, &ea
) ||
3859 fetch (sd
, &code
->dst
, &rd
))
3873 n
= res
& 0x80000000;
3874 if (store (sd
, &code
->dst
, res
))
3878 case O (O_DIVXU
, SB
): /* divxu.b */
3879 if (fetch (sd
, &code
->src
, &ea
) ||
3880 fetch (sd
, &code
->dst
, &rd
))
3883 rd
= UEXTSHORT (rd
);
3890 tmp
= (unsigned) rd
% ea
;
3891 res
= (unsigned) rd
/ ea
;
3899 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
3903 case O (O_DIVXU
, SW
): /* divxu.w */
3904 if (fetch (sd
, &code
->src
, &ea
) ||
3905 fetch (sd
, &code
->dst
, &rd
))
3908 ea
= UEXTSHORT (ea
);
3914 tmp
= (unsigned) rd
% ea
;
3915 res
= (unsigned) rd
/ ea
;
3923 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
3927 case O (O_DIVXS
, SB
): /* divxs.b */
3928 if (fetch (sd
, &code
->src
, &ea
) ||
3929 fetch (sd
, &code
->dst
, &rd
))
3932 rd
= SEXTSHORT (rd
);
3937 tmp
= (int) rd
% (int) ea
;
3938 res
= (int) rd
/ (int) ea
;
3949 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
3953 case O (O_DIVXS
, SW
): /* divxs.w */
3954 if (fetch (sd
, &code
->src
, &ea
) ||
3955 fetch (sd
, &code
->dst
, &rd
))
3958 ea
= SEXTSHORT (ea
);
3962 tmp
= (int) rd
% (int) ea
;
3963 res
= (int) rd
/ (int) ea
;
3973 n
= res
& 0x80000000;
3974 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
3978 case O (O_EXTS
, SW
): /* exts.w, signed extend */
3979 if (fetch2 (sd
, &code
->dst
, &rd
))
3981 ea
= rd
& 0x80 ? -256 : 0;
3982 res
= (rd
& 0xff) + ea
;
3985 case O (O_EXTS
, SL
): /* exts.l, signed extend */
3986 if (fetch2 (sd
, &code
->dst
, &rd
))
3988 if (code
->src
.type
== X (OP_IMM
, SL
))
3990 if (fetch (sd
, &code
->src
, &ea
))
3993 if (ea
== 2) /* exts.l #2, nn */
3995 /* Sign-extend from 8-bit to 32-bit. */
3996 ea
= rd
& 0x80 ? -256 : 0;
3997 res
= (rd
& 0xff) + ea
;
4001 /* Sign-extend from 16-bit to 32-bit. */
4002 ea
= rd
& 0x8000 ? -65536 : 0;
4003 res
= (rd
& 0xffff) + ea
;
4006 case O (O_EXTU
, SW
): /* extu.w, unsigned extend */
4007 if (fetch2 (sd
, &code
->dst
, &rd
))
4010 res
= (rd
& 0xff) + ea
;
4013 case O (O_EXTU
, SL
): /* extu.l, unsigned extend */
4014 if (fetch2 (sd
, &code
->dst
, &rd
))
4016 if (code
->src
.type
== X (OP_IMM
, SL
))
4018 if (fetch (sd
, &code
->src
, &ea
))
4021 if (ea
== 2) /* extu.l #2, nn */
4023 /* Zero-extend from 8-bit to 32-bit. */
4025 res
= (rd
& 0xff) + ea
;
4029 /* Zero-extend from 16-bit to 32-bit. */
4031 res
= (rd
& 0xffff) + ea
;
4034 case O (O_NOP
, SN
): /* nop */
4037 case O (O_STM
, SL
): /* stm, store to memory */
4039 int nregs
, firstreg
, i
;
4041 nregs
= GET_MEMORY_B (pc
+ 1);
4044 firstreg
= code
->src
.reg
;
4046 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
4048 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) - 4);
4049 SET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
), h8_get_reg (sd
, i
));
4054 case O (O_LDM
, SL
): /* ldm, load from memory */
4055 case O (O_RTEL
, SN
): /* rte/l, ldm plus rte */
4056 case O (O_RTSL
, SN
): /* rts/l, ldm plus rts */
4058 int nregs
, firstreg
, i
;
4060 nregs
= ((GET_MEMORY_B (pc
+ 1) >> 4) & 0xf);
4061 firstreg
= code
->dst
.reg
& 0xf;
4062 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
4064 h8_set_reg (sd
, i
, GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
)));
4065 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) + 4);
4068 switch (code
->opcode
) {
4069 case O (O_RTEL
, SN
):
4071 case O (O_RTSL
, SN
):
4080 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4081 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch? */
4082 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4083 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4084 res
= res
; /* Value added == 0. */
4085 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4086 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4087 res
= res
+ 0x6; /* Value added == 6. */
4088 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4089 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4090 res
= res
+ 0x6; /* Value added == 6. */
4091 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4092 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4093 res
= res
+ 0x60; /* Value added == 60. */
4094 else if (!c
&& (9 <= (res
>> 4) && (res
>> 4) <= 15) &&
4095 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4096 res
= res
+ 0x66; /* Value added == 66. */
4097 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4098 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4099 res
= res
+ 0x66; /* Value added == 66. */
4100 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4101 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4102 res
= res
+ 0x60; /* Value added == 60. */
4103 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4104 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4105 res
= res
+ 0x66; /* Value added == 66. */
4106 else if (c
&& (1 <= (res
>> 4) && (res
>> 4) <= 3) &&
4107 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4108 res
= res
+ 0x66; /* Value added == 66. */
4113 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4114 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch, fetch2... */
4115 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4116 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4117 res
= res
; /* Value added == 0. */
4118 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4119 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4120 res
= res
+ 0xfa; /* Value added == 0xfa. */
4121 else if ( c
&& (7 <= (res
>> 4) && (res
>> 4) <= 15) &&
4122 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4123 res
= res
+ 0xa0; /* Value added == 0xa0. */
4124 else if (c
&& (6 <= (res
>> 4) && (res
>> 4) <= 15) &&
4125 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4126 res
= res
+ 0x9a; /* Value added == 0x9a. */
4132 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4137 sim_io_printf (sd
, "sim_resume: internal error.\n");
4138 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4142 if (code
->dst
.type
== X (OP_CCR
, SB
) ||
4143 code
->dst
.type
== X (OP_CCR
, SW
))
4145 h8_set_ccr (sd
, res
);
4148 else if (h8300smode
&&
4149 (code
->dst
.type
== X (OP_EXR
, SB
) ||
4150 code
->dst
.type
== X (OP_EXR
, SW
)))
4152 h8_set_exr (sd
, res
);
4153 if (h8300smode
) /* Get exr. */
4155 trace
= (h8_get_exr (sd
) >> 7) & 1;
4156 intMask
= h8_get_exr (sd
) & 7;
4165 /* When a branch works */
4166 if (fetch (sd
, &code
->src
, &res
))
4168 if (res
& 1) /* bad address */
4170 pc
= code
->next_pc
+ res
;
4173 /* Set the cond codes from res */
4176 /* Set the flags after an 8 bit inc/dec operation */
4180 v
= (rd
& 0x7f) == 0x7f;
4183 /* Set the flags after an 16 bit inc/dec operation */
4187 v
= (rd
& 0x7fff) == 0x7fff;
4190 /* Set the flags after an 32 bit inc/dec operation */
4192 n
= res
& 0x80000000;
4193 nz
= res
& 0xffffffff;
4194 v
= (rd
& 0x7fffffff) == 0x7fffffff;
4198 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4201 if (store2 (sd
, &code
->dst
, rd
))
4206 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4209 if (store2 (sd
, &code
->dst
, rd
))
4214 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4215 n
= (rd
& 0x80000000);
4216 nz
= rd
& 0xffffffff;
4217 if (store2 (sd
, &code
->dst
, rd
))
4222 if (store2 (sd
, &code
->dst
, res
))
4226 /* flags after a 32bit logical operation */
4227 n
= res
& 0x80000000;
4228 nz
= res
& 0xffffffff;
4233 if (store2 (sd
, &code
->dst
, res
))
4237 /* flags after a 16bit logical operation */
4244 if (store2 (sd
, &code
->dst
, res
))
4254 if (store2 (sd
, &code
->dst
, res
))
4261 switch (code
->opcode
/ 4)
4265 v
= ((rd
& 0x80) == (ea
& 0x80)
4266 && (rd
& 0x80) != (res
& 0x80));
4271 v
= ((rd
& 0x80) != (-ea
& 0x80)
4272 && (rd
& 0x80) != (res
& 0x80));
4279 break; /* No effect on v flag. */
4284 if (store2 (sd
, &code
->dst
, res
))
4290 c
= (res
& 0x10000);
4291 switch (code
->opcode
/ 4)
4295 v
= ((rd
& 0x8000) == (ea
& 0x8000)
4296 && (rd
& 0x8000) != (res
& 0x8000));
4301 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
4302 && (rd
& 0x8000) != (res
& 0x8000));
4311 if (store2 (sd
, &code
->dst
, res
))
4315 n
= res
& 0x80000000;
4316 nz
= res
& 0xffffffff;
4317 switch (code
->opcode
/ 4)
4321 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
4322 && (rd
& 0x80000000) != (res
& 0x80000000));
4323 c
= ((unsigned) res
< (unsigned) rd
) ||
4324 ((unsigned) res
< (unsigned) ea
);
4329 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
4330 && (rd
& 0x80000000) != (res
& 0x80000000));
4331 c
= (unsigned) rd
< (unsigned) -ea
;
4334 v
= (rd
== 0x80000000);
4341 if ((res
= h8_get_delayed_branch (sd
)) != 0)
4344 h8_set_delayed_branch (sd
, 0);
4352 h8_set_ticks (sd
, h8_get_ticks (sd
) + get_now () - tick_start
);
4353 h8_set_cycles (sd
, h8_get_cycles (sd
) + cycles
);
4354 h8_set_insts (sd
, h8_get_insts (sd
) + insts
);
4359 h8_set_exr (sd
, (trace
<<7) | intMask
);
4361 h8_set_mask (sd
, oldmask
);
4365 sim_engine_run (SIM_DESC sd
,
4366 int next_cpu_nr
, /* ignore */
4367 int nr_cpus
, /* ignore */
4372 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4374 cpu
= STATE_CPU (sd
, 0);
4378 step_once (sd
, cpu
);
4379 if (sim_events_tick (sd
))
4380 sim_events_process (sd
);
4385 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
4392 for (i
= 0; i
< size
; i
++)
4394 if (addr
< memory_size
)
4396 h8_set_memory (sd
, addr
+ i
, buffer
[i
]);
4405 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
4410 if (addr
+ size
< memory_size
)
4411 memcpy (buffer
, h8_get_memory_buf (sd
) + addr
, size
);
4418 h8300_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *value
, int length
)
4423 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
4424 shortval
= (value
[0] << 8) | (value
[1]);
4425 intval
= h8300hmode
? longval
: shortval
;
4427 init_pointers (CPU_STATE (cpu
));
4431 if(h8300_normal_mode
)
4432 cpu
->pc
= shortval
; /* PC for Normal mode is 2 bytes */
4452 cpu
->regs
[rn
] = intval
;
4457 cpu
->regs
[rn
] = longval
;
4464 h8300_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *buf
, int length
)
4469 init_pointers (CPU_STATE (cpu
));
4471 if (!h8300smode
&& rn
>= EXR_REGNUM
)
4506 /* In Normal mode PC is 2 byte, but other registers are 4 byte */
4507 if ((h8300hmode
|| longreg
) && !(rn
== PC_REGNUM
&& h8300_normal_mode
))
4524 sim_info (SIM_DESC sd
, int verbose
)
4526 double timetaken
= (double) h8_get_ticks (sd
) / (double) now_persec ();
4527 double virttime
= h8_get_cycles (sd
) / 10.0e6
;
4529 sim_io_printf (sd
, "\n\n#instructions executed %10d\n", h8_get_insts (sd
));
4530 sim_io_printf (sd
, "#cycles (v approximate) %10d\n", h8_get_cycles (sd
));
4531 sim_io_printf (sd
, "#real time taken %10.4f\n", timetaken
);
4532 sim_io_printf (sd
, "#virtual time taken %10.4f\n", virttime
);
4533 if (timetaken
!= 0.0)
4534 sim_io_printf (sd
, "#simulation ratio %10.4f\n", virttime
/ timetaken
);
4537 /* This to be conditional on `what' (aka `verbose'),
4538 however it was never passed as non-zero. */
4542 for (i
= 0; i
< O_LAST
; i
++)
4544 if (h8_get_stats (sd
, i
))
4545 sim_io_printf (sd
, "%d: %d\n", i
, h8_get_stats (sd
, i
));
4551 /* Indicate whether the cpu is an H8/300 or H8/300H.
4552 FLAG is non-zero for the H8/300H. */
4555 set_h8300h (unsigned long machine
)
4557 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4558 This function being replaced by a sim_open:ARGV configuration
4561 h8300hmode
= h8300smode
= h8300sxmode
= h8300_normal_mode
= 0;
4563 if (machine
== bfd_mach_h8300sx
|| machine
== bfd_mach_h8300sxn
)
4566 if (machine
== bfd_mach_h8300s
|| machine
== bfd_mach_h8300sn
|| h8300sxmode
)
4569 if (machine
== bfd_mach_h8300h
|| machine
== bfd_mach_h8300hn
|| h8300smode
)
4572 if(machine
== bfd_mach_h8300hn
|| machine
== bfd_mach_h8300sn
|| machine
== bfd_mach_h8300sxn
)
4573 h8300_normal_mode
= 1;
4576 /* H8300-specific options.
4577 TODO: These really should be merged into the common model modules. */
4585 h8300_option_handler (SIM_DESC sd
, sim_cpu
*cpu ATTRIBUTE_UNUSED
, int opt
,
4586 char *arg
, int is_command ATTRIBUTE_UNUSED
)
4588 switch ((H8300_OPTIONS
) opt
)
4591 set_h8300h (bfd_mach_h8300h
);
4594 set_h8300h (bfd_mach_h8300s
);
4596 case OPTION_H8300SX
:
4597 set_h8300h (bfd_mach_h8300sx
);
4601 /* We'll actually never get here; the caller handles the error
4603 sim_io_eprintf (sd
, "Unknown option `%s'\n", arg
);
4610 static const OPTION h8300_options
[] =
4612 { {"h8300h", no_argument
, NULL
, OPTION_H8300H
},
4613 'h', NULL
, "Indicate the CPU is H8/300H",
4614 h8300_option_handler
},
4615 { {"h8300s", no_argument
, NULL
, OPTION_H8300S
},
4616 'S', NULL
, "Indicate the CPU is H8S",
4617 h8300_option_handler
},
4618 { {"h8300sx", no_argument
, NULL
, OPTION_H8300SX
},
4619 'x', NULL
, "Indicate the CPU is H8SX",
4620 h8300_option_handler
},
4621 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
, NULL
}
4625 h8300_pc_get (sim_cpu
*cpu
)
4631 h8300_pc_set (sim_cpu
*cpu
, sim_cia pc
)
4636 /* Cover function of sim_state_free to free the cpu buffers as well. */
4639 free_state (SIM_DESC sd
)
4641 if (STATE_MODULES (sd
) != NULL
)
4642 sim_module_uninstall (sd
);
4644 /* Fixme: free buffers in _sim_cpu. */
4645 sim_state_free (sd
);
4649 sim_open (SIM_OPEN_KIND kind
,
4650 struct host_callback_struct
*callback
,
4658 sd
= sim_state_alloc (kind
, callback
);
4660 /* The cpu data is kept in a separately allocated chunk of memory. */
4661 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
4667 cpu
= STATE_CPU (sd
, 0);
4668 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4669 cpu
->regs
[SBR_REGNUM
] = 0xFFFFFF00;
4670 /* sim_cpu object is new, so some initialization is needed. */
4671 init_pointers_needed
= 1;
4673 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
4679 if (sim_add_option_table (sd
, NULL
, h8300_options
) != SIM_RC_OK
)
4685 /* The parser will print an error message for us, so we silently return. */
4686 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
4688 /* Uninstall the modules to avoid memory leaks,
4689 file descriptor leaks, etc. */
4694 /* Check for/establish the a reference program image. */
4695 if (sim_analyze_program (sd
,
4696 (STATE_PROG_ARGV (sd
) != NULL
4697 ? *STATE_PROG_ARGV (sd
)
4698 : NULL
), abfd
) != SIM_RC_OK
)
4704 /* Establish any remaining configuration options. */
4705 if (sim_config (sd
) != SIM_RC_OK
)
4711 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
4713 /* Uninstall the modules to avoid memory leaks,
4714 file descriptor leaks, etc. */
4719 /* CPU specific initialization. */
4720 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
4722 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
4724 CPU_REG_FETCH (cpu
) = h8300_reg_fetch
;
4725 CPU_REG_STORE (cpu
) = h8300_reg_store
;
4726 CPU_PC_FETCH (cpu
) = h8300_pc_get
;
4727 CPU_PC_STORE (cpu
) = h8300_pc_set
;
4730 /* sim_hw_configure (sd); */
4732 /* FIXME: Much of the code in sim_load can be moved here. */
4737 /* Called by gdb to load a program into memory. */
4740 sim_load (SIM_DESC sd
, const char *prog
, bfd
*abfd
, int from_tty
)
4744 /* FIXME: The code below that sets a specific variant of the H8/300
4745 being simulated should be moved to sim_open(). */
4747 /* See if the file is for the H8/300 or H8/300H. */
4748 /* ??? This may not be the most efficient way. The z8k simulator
4749 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
4753 prog_bfd
= bfd_openr (prog
, NULL
);
4754 if (prog_bfd
!= NULL
)
4756 /* Set the cpu type. We ignore failure from bfd_check_format
4757 and bfd_openr as sim_load_file checks too. */
4758 if (bfd_check_format (prog_bfd
, bfd_object
))
4760 set_h8300h (bfd_get_mach (prog_bfd
));
4764 /* If we're using gdb attached to the simulator, then we have to
4765 reallocate memory for the simulator.
4767 When gdb first starts, it calls fetch_registers (among other
4768 functions), which in turn calls init_pointers, which allocates
4771 The problem is when we do that, we don't know whether we're
4772 debugging an H8/300 or H8/300H program.
4774 This is the first point at which we can make that determination,
4775 so we just reallocate memory now; this will also allow us to handle
4776 switching between H8/300 and H8/300H programs without exiting
4779 if (h8300smode
&& !h8300_normal_mode
)
4780 memory_size
= H8300S_MSIZE
;
4781 else if (h8300hmode
&& !h8300_normal_mode
)
4782 memory_size
= H8300H_MSIZE
;
4784 memory_size
= H8300_MSIZE
;
4786 if (h8_get_memory_buf (sd
))
4787 free (h8_get_memory_buf (sd
));
4789 h8_set_memory_buf (sd
, (unsigned char *)
4790 calloc (sizeof (char), memory_size
));
4791 sd
->memory_size
= memory_size
;
4793 /* `msize' must be a power of two. */
4794 if ((memory_size
& (memory_size
- 1)) != 0)
4796 sim_io_printf (sd
, "sim_load: bad memory size.\n");
4799 h8_set_mask (sd
, memory_size
- 1);
4801 if (sim_load_file (sd
, STATE_MY_NAME (sd
), STATE_CALLBACK (sd
), prog
,
4802 prog_bfd
, STATE_OPEN_KIND (sd
) == SIM_OPEN_DEBUG
,
4806 /* Close the bfd if we opened it. */
4807 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4808 bfd_close (prog_bfd
);
4812 /* Close the bfd if we opened it. */
4813 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4814 bfd_close (prog_bfd
);
4819 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
4820 char * const *argv
, char * const *env
)
4827 h8_set_pc (sd
, bfd_get_start_address (abfd
));
4831 /* Command Line support. */
4834 /* Counting the no. of commandline arguments. */
4835 for (no_of_args
= 0; argv
[no_of_args
] != NULL
; no_of_args
++)
4838 /* Allocating memory for the argv pointers. */
4839 h8_set_command_line (sd
, (char **) malloc ((sizeof (char *))
4840 * (no_of_args
+ 1)));
4842 for (i
= 0; i
< no_of_args
; i
++)
4844 /* Copying the argument string. */
4845 h8_set_cmdline_arg (sd
, i
, (char *) strdup (argv
[i
]));
4847 h8_set_cmdline_arg (sd
, i
, NULL
);