sim/igen/igen.h

   1 /*  This file is part of the program psim.
   2
   3     Copyright (C) 1994-1998, Andrew Cagney <cagney@highland.com.au>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18
  19     */
  20
  21 /* code-generation options: */
  22
  23 typedef enum {
  24
  25   /* Transfer control to an instructions semantic code using the the
  26      standard call/return mechanism */
  27
  28   generate_calls,
  29
  30   /* Transfer control to an instructions semantic code using
  31      (computed) goto's instead of the more conventional call/return
  32      mechanism */
  33
  34   generate_jumps,
  35
  36 } igen_code;
  37
  38 typedef enum {
  39   nia_is_cia_plus_one,
  40   nia_is_void,
  41   nia_is_invalid,
  42 } igen_nia;
  43
  44
  45
  46 typedef struct _igen_gen_options igen_gen_options;
  47 struct _igen_gen_options {
  48   int direct_access;
  49   int semantic_icache;
  50   int insn_in_icache;
  51   int conditional_issue;
  52   int slot_verification;
  53   int delayed_branch;
  54
  55   /* If zeroing a register, which one? */
  56   int zero_reg;
  57   int zero_reg_nr;
  58
  59   /* should multiple simulators be generated? */
  60   int multi_sim;
  61
  62   /* name of the default multi-sim model */
  63   char *default_model;
  64
  65   /* should the simulator support multi word instructions and if so,
  66      what is the max nr of words. */
  67   int multi_word;
  68
  69   /* SMP?  Should the generated code include SMP support (>0) and if
  70      so, for how many processors? */
  71   int smp;
  72
  73   /* how should the next instruction address be computed? */
  74   igen_nia nia;
  75
  76   /* nr of instructions in the decoded instruction cache */
  77   int icache;
  78   int icache_size;
  79
  80   /* see above */
  81   igen_code code;
  82 };
  83
  84
  85 typedef struct _igen_trace_options igen_trace_options;
  86 struct _igen_trace_options {
  87   int rule_selection;
  88   int rule_rejection;
  89   int insn_insertion;
  90   int insn_expansion;
  91   int entries;
  92   int combine;
  93 };
  94
  95 typedef struct _igen_name {
  96   char *u;
  97   char *l;
  98 } igen_name;
  99 typedef struct _igen_module {
 100   igen_name prefix;
 101   igen_name suffix;
 102 } igen_module;
 103
 104 typedef struct _igen_module_options {
 105   igen_module global;
 106   igen_module engine;
 107   igen_module icache;
 108   igen_module idecode;
 109   igen_module itable;
 110   igen_module semantics;
 111   igen_module support;
 112 } igen_module_options;
 113
 114 typedef struct _igen_decode_options igen_decode_options ;
 115 struct _igen_decode_options {
 116
 117   /* Combine tables?  Should the generator make a second pass through
 118      each generated table looking for any sub-entries that contain the
 119      same instructions.  Those entries being merged into a single
 120      table */
 121   int combine;
 122
 123   /* Instruction expansion? Should the semantic code for each
 124      instruction, when the oportunity arrises, be expanded according
 125      to the variable opcode files that the instruction decode process
 126      renders constant */
 127   int duplicate;
 128
 129   /* Treat reserved fields as constant (zero) instead of ignoring
 130      their value when determining decode tables */
 131   int zero_reserved;
 132
 133   /* Convert any padded switch rules into goto_switch */
 134   int switch_as_goto;
 135
 136   /* Force all tables to be generated with this lookup mechanism */
 137   char *overriding_gen;
 138 };
 139
 140
 141 typedef struct _igen_warn_options igen_warn_options;
 142 struct _igen_warn_options {
 143
 144   /* Issue warning about discarded instructions */
 145   int discard;
 146
 147   /* Issue warning about invalid instruction widths */
 148   int width;
 149
 150   /* Issue warning about unimplemented instructions */
 151   int unimplemented;
 152
 153 };
 154
 155
 156
 157 typedef struct _igen_options igen_options;
 158 struct _igen_options {
 159
 160   /* What does the instruction look like - bit ordering, size, widths or
 161      offesets */
 162   int hi_bit_nr;
 163   int insn_bit_size;
 164   int insn_specifying_widths;
 165
 166   /* what should global names be prefixed with? */
 167   igen_module_options module;
 168
 169   /* See above for options and flags */
 170   igen_gen_options gen;
 171
 172   /* See above for trace options */
 173   igen_trace_options trace;
 174
 175   /* See above for include options */
 176   table_include *include;
 177
 178   /* See above for decode options */
 179   igen_decode_options decode;
 180
 181   /* Filter set to be used on the flag field of the instruction table */
 182   filter *flags_filter;
 183
 184   /* See above for warn options */
 185   igen_warn_options warn;
 186
 187   /* Be more picky about the input */
 188   error_func (*warning);
 189
 190   /* Model (processor) set - like flags_filter. Used to select the
 191      specific ISA within a processor family. */
 192   filter *model_filter;
 193
 194   /* Format name set */
 195   filter *format_name_filter;
 196 };
 197
 198 extern igen_options options;
 199
 200 /* default options - hopefully backward compatible */ \
 201 #define INIT_OPTIONS() \
 202 do { \
 203   memset (&options, 0, sizeof options); \
 204   memset (&options.warn, -1, sizeof (options.warn)); \
 205   options.hi_bit_nr = 0; \
 206   options.insn_bit_size = default_insn_bit_size; \
 207   options.insn_specifying_widths = 0; \
 208   options.module.global.prefix.u = ""; \
 209   options.module.global.prefix.l = ""; \
 210   /* the prefixes */ \
 211   options.module.engine = options.module.global; \
 212   options.module.icache = options.module.global; \
 213   options.module.idecode = options.module.global; \
 214   options.module.itable = options.module.global; \
 215   options.module.semantics = options.module.global; \
 216   options.module.support = options.module.global; \
 217   /* the suffixes */ \
 218   options.module.engine.suffix.l = "engine"; \
 219   options.module.engine.suffix.u = "ENGINE"; \
 220   options.module.icache.suffix.l = "icache"; \
 221   options.module.icache.suffix.u = "ICACHE"; \
 222   options.module.idecode.suffix.l = "idecode"; \
 223   options.module.idecode.suffix.u = "IDECODE"; \
 224   options.module.itable.suffix.l = "itable"; \
 225   options.module.itable.suffix.u = "ITABLE"; \
 226   options.module.semantics.suffix.l = "semantics"; \
 227   options.module.semantics.suffix.u = "SEMANTICS"; \
 228   options.module.support.suffix.l = "support"; \
 229   options.module.support.suffix.u = "SUPPORT"; \
 230   /* misc stuff */ \
 231   options.gen.code = generate_calls; \
 232   options.gen.icache_size = 1024; \
 233   options.warning = warning; \
 234 } while (0)