sim/iq2000/mloop.in

   1 # Simulator main loop for IQ2000. -*- C -*-
   2 # Copyright (C) 1998, 1999, 2007 Free Software Foundation, Inc.
   3 # Contributed by Cygnus Solutions.
   4 #
   5 # This file is part of the GNU Simulators.
   6 #
   7 # This program is free software; you can redistribute it and/or modify
   8 # it under the terms of the GNU General Public License as published by
   9 # the Free Software Foundation; either version 2, or (at your option)
  10 # any later version.
  11 #
  12 # This program is distributed in the hope that it will be useful,
  13 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 # GNU General Public License for more details.
  16 #
  17 # You should have received a copy of the GNU General Public License along
  18 # with this program; if not, write to the Free Software Foundation, Inc.,
  19 # 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20
  21 # Syntax:
  22 # /bin/sh mainloop.in command
  23 #
  24 # Command is one of:
  25 #
  26 # init
  27 # support
  28 # extract-{simple,scache,pbb}
  29 # {full,fast}-exec-{simple,scache,pbb}
  30 #
  31 # A target need only provide a "full" version of one of simple,scache,pbb.
  32 # If the target wants it can also provide a fast version of same.
  33 # It can't provide more than this, however for illustration's sake the IQ2000
  34 # port provides examples of all.
  35
  36 # ??? After a few more ports are done, revisit.
  37 # Will eventually need to machine generate a lot of this.
  38
  39 case "x$1" in
  40
  41 xsupport)
  42
  43 cat <<EOF
  44
  45 static INLINE const IDESC *
  46 extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
  47          int fast_p)
  48 {
  49   const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf);
  50   @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
  51   if (! fast_p)
  52     {
  53       int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
  54       int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
  55       @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
  56     }
  57   return id;
  58 }
  59
  60 static INLINE SEM_PC
  61 execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
  62 {
  63   SEM_PC vpc;
  64
  65   /* Force R0 to zero before every insn.  */
  66   @cpu@_h_gr_set (current_cpu, 0, 0);
  67
  68   if (fast_p)
  69     {
  70 #if ! WITH_SEM_SWITCH_FAST
  71 #if WITH_SCACHE
  72       vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
  73 #else
  74       vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
  75 #endif
  76 #else
  77       abort ();
  78 #endif /* WITH_SEM_SWITCH_FAST */
  79     }
  80   else
  81     {
  82 #if ! WITH_SEM_SWITCH_FULL
  83       ARGBUF *abuf = &sc->argbuf;
  84       const IDESC *idesc = abuf->idesc;
  85 #if WITH_SCACHE_PBB
  86       int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL);
  87 #else
  88       int virtual_p = 0;
  89 #endif
  90
  91       if (! virtual_p)
  92         {
  93           /* FIXME: call x-before */
  94           if (ARGBUF_PROFILE_P (abuf))
  95             PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
  96           /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}.  */
  97           if (PROFILE_MODEL_P (current_cpu)
  98               && ARGBUF_PROFILE_P (abuf))
  99             @cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
 100           TRACE_INSN_INIT (current_cpu, abuf, 1);
 101           TRACE_INSN (current_cpu, idesc->idata,
 102                       (const struct argbuf *) abuf, abuf->addr);
 103         }
 104 #if WITH_SCACHE
 105       vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
 106 #else
 107       vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
 108 #endif
 109       if (! virtual_p)
 110         {
 111           /* FIXME: call x-after */
 112           if (PROFILE_MODEL_P (current_cpu)
 113               && ARGBUF_PROFILE_P (abuf))
 114             {
 115               int cycles;
 116
 117               cycles = (*idesc->timing->model_fn) (current_cpu, sc);
 118               @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
 119             }
 120           TRACE_INSN_FINI (current_cpu, abuf, 1);
 121         }
 122 #else
 123       abort ();
 124 #endif /* WITH_SEM_SWITCH_FULL */
 125     }
 126
 127   return vpc;
 128 }
 129
 130 EOF
 131 ;;
 132
 133 xinit)
 134 ;;
 135
 136 xextract-simple | xextract-scache)
 137
 138 # Inputs:  current_cpu, vpc, sc, FAST_P
 139 # Outputs: sc filled in
 140
 141 cat <<EOF
 142 {
 143   CGEN_INSN_INT insn = GETIMEMUSI (current_cpu, CPU2INSN(vpc));
 144   extract (current_cpu, vpc, insn, SEM_ARGBUF (sc), FAST_P);
 145   SEM_SKIP_COMPILE (current_cpu, sc, 1);
 146 }
 147 EOF
 148
 149 ;;
 150
 151 xextract-pbb)
 152
 153 # Inputs:  current_cpu, pc, sc, max_insns, FAST_P
 154 # Outputs: sc, pc
 155 # sc must be left pointing past the last created entry.
 156 # pc must be left pointing past the last created entry.
 157 # If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
 158 # to record the vpc of the cti insn.
 159 # SET_INSN_COUNT(n) must be called to record number of real insns.
 160
 161 cat <<EOF
 162 {
 163   const IDESC *idesc;
 164   int icount = 0;
 165
 166   /* Is the CTI instruction at the end of the PBB a likely branch?  */
 167   int likely_cti;
 168
 169   while (max_insns > 0)
 170     {
 171       USI insn = GETIMEMUSI (current_cpu, CPU2INSN(pc));
 172
 173       idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
 174       SEM_SKIP_COMPILE (current_cpu, sc, 1);
 175       ++sc;
 176       --max_insns;
 177       ++icount;
 178       pc += idesc->length;
 179
 180       if (IDESC_CTI_P (idesc))
 181         {
 182           /* Likely branches annul their delay slot if the branch is
 183              not taken by using the (skip ..) rtx.  We'll rely on
 184              that.  */
 185           likely_cti = (IDESC_SKIP_P (idesc));
 186
 187           SET_CTI_VPC (sc - 1);
 188
 189           if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
 190             {
 191               USI insn = GETIMEMUSI (current_cpu, CPU2INSN(pc));
 192               idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
 193
 194               if (likely_cti && IDESC_CTI_P (idesc))
 195                 {
 196                   /* malformed program */
 197                   sim_io_eprintf (CPU_STATE (current_cpu),
 198                     "malformed program, \`%s' insn in branch likely delay slot\n",
 199                     CGEN_INSN_NAME (idesc->idata));
 200                 }
 201               else
 202                 {
 203                   ++sc;
 204                   --max_insns;
 205                   ++icount;
 206                   pc += idesc->length;
 207                 }
 208             }
 209           break;
 210         }
 211     }
 212
 213  Finish:
 214   SET_INSN_COUNT (icount);
 215 }
 216 EOF
 217
 218 ;;
 219
 220 xfull-exec-* | xfast-exec-*)
 221
 222 # Inputs: current_cpu, sc, FAST_P
 223 # Outputs: vpc
 224 # vpc contains the address of the next insn to execute
 225
 226 cat <<EOF
 227 {
 228 #if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
 229 #define DEFINE_SWITCH
 230 #include "sem-switch.c"
 231 #else
 232   vpc = execute (current_cpu, vpc, FAST_P);
 233 #endif
 234 }
 235 EOF
 236
 237 ;;
 238
 239 *)
 240   echo "Invalid argument to mainloop.in: $1" >&2
 241   exit 1
 242   ;;
 243
 244 esac