sim/m32c/gdb-if.c

   1 /* gdb.c --- sim interface to GDB.
   2
   3 Copyright (C) 2005-2021 Free Software Foundation, Inc.
   4 Contributed by Red Hat, Inc.
   5
   6 This file is part of the GNU simulators.
   7
   8 This program is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3 of the License, or
  11 (at your option) any later version.
  12
  13 This program is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "config.h"
  22 #include <stdio.h>
  23 #include <assert.h>
  24 #include <signal.h>
  25 #include <stdlib.h>
  26 #include <string.h>
  27 #include <ctype.h>
  28
  29 #include "ansidecl.h"
  30 #include "libiberty.h"
  31 #include "sim/callback.h"
  32 #include "sim/sim.h"
  33 #include "gdb/signals.h"
  34 #include "gdb/sim-m32c.h"
  35
  36 #include "cpu.h"
  37 #include "mem.h"
  38 #include "load.h"
  39 #include "syscalls.h"
  40 #ifdef TIMER_A
  41 #include "timer_a.h"
  42 #endif
  43
  44 /* I don't want to wrap up all the minisim's data structures in an
  45    object and pass that around.  That'd be a big change, and neither
  46    GDB nor run needs that ability.
  47
  48    So we just have one instance, that lives in global variables, and
  49    each time we open it, we re-initialize it.  */
  50 struct sim_state
  51 {
  52   const char *message;
  53 };
  54
  55 static struct sim_state the_minisim = {
  56   "This is the sole m32c minisim instance.  See libsim.a's global variables."
  57 };
  58
  59 static int open;
  60
  61 SIM_DESC
  62 sim_open (SIM_OPEN_KIND kind,
  63           struct host_callback_struct *callback,
  64           struct bfd *abfd, char * const *argv)
  65 {
  66   setbuf (stdout, 0);
  67   if (open)
  68     fprintf (stderr, "m32c minisim: re-opened sim\n");
  69
  70   /* The 'run' interface doesn't use this function, so we don't care
  71      about KIND; it's always SIM_OPEN_DEBUG.  */
  72   if (kind != SIM_OPEN_DEBUG)
  73     fprintf (stderr, "m32c minisim: sim_open KIND != SIM_OPEN_DEBUG: %d\n",
  74              kind);
  75
  76   if (abfd)
  77     m32c_set_mach (bfd_get_mach (abfd));
  78
  79   /* We can use ABFD, if non-NULL to select the appropriate
  80      architecture.  But we only support the r8c right now.  */
  81
  82   set_callbacks (callback);
  83
  84   /* We don't expect any command-line arguments.  */
  85
  86   init_mem ();
  87   init_regs ();
  88
  89   open = 1;
  90   return &the_minisim;
  91 }
  92
  93 static void
  94 check_desc (SIM_DESC sd)
  95 {
  96   if (sd != &the_minisim)
  97     fprintf (stderr, "m32c minisim: desc != &the_minisim\n");
  98 }
  99
 100 void
 101 sim_close (SIM_DESC sd, int quitting)
 102 {
 103   check_desc (sd);
 104
 105   /* Not much to do.  At least free up our memory.  */
 106   init_mem ();
 107
 108   open = 0;
 109 }
 110
 111 static bfd *
 112 open_objfile (const char *filename)
 113 {
 114   bfd *prog = bfd_openr (filename, 0);
 115
 116   if (!prog)
 117     {
 118       fprintf (stderr, "Can't read %s\n", filename);
 119       return 0;
 120     }
 121
 122   if (!bfd_check_format (prog, bfd_object))
 123     {
 124       fprintf (stderr, "%s not a m32c program\n", filename);
 125       return 0;
 126     }
 127
 128   return prog;
 129 }
 130
 131
 132 SIM_RC
 133 sim_load (SIM_DESC sd, const char *prog, struct bfd * abfd, int from_tty)
 134 {
 135   check_desc (sd);
 136
 137   if (!abfd)
 138     abfd = open_objfile (prog);
 139   if (!abfd)
 140     return SIM_RC_FAIL;
 141
 142   m32c_load (abfd);
 143
 144   return SIM_RC_OK;
 145 }
 146
 147 SIM_RC
 148 sim_create_inferior (SIM_DESC sd, struct bfd * abfd,
 149                      char * const *argv, char * const *env)
 150 {
 151   check_desc (sd);
 152
 153   if (abfd)
 154     m32c_load (abfd);
 155
 156   return SIM_RC_OK;
 157 }
 158
 159 int
 160 sim_read (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
 161 {
 162   check_desc (sd);
 163
 164   if (mem == 0)
 165     return 0;
 166
 167   mem_get_blk ((int) mem, buf, length);
 168
 169   return length;
 170 }
 171
 172 int
 173 sim_write (SIM_DESC sd, SIM_ADDR mem, const unsigned char *buf, int length)
 174 {
 175   check_desc (sd);
 176
 177   mem_put_blk ((int) mem, buf, length);
 178
 179   return length;
 180 }
 181
 182
 183 /* Read the LENGTH bytes at BUF as an little-endian value.  */
 184 static DI
 185 get_le (unsigned char *buf, int length)
 186 {
 187   DI acc = 0;
 188   while (--length >= 0)
 189     acc = (acc << 8) + buf[length];
 190
 191   return acc;
 192 }
 193
 194 /* Store VAL as a little-endian value in the LENGTH bytes at BUF.  */
 195 static void
 196 put_le (unsigned char *buf, int length, DI val)
 197 {
 198   int i;
 199
 200   for (i = 0; i < length; i++)
 201     {
 202       buf[i] = val & 0xff;
 203       val >>= 8;
 204     }
 205 }
 206
 207 static int
 208 check_regno (enum m32c_sim_reg regno)
 209 {
 210   return 0 <= regno && regno < m32c_sim_reg_num_regs;
 211 }
 212
 213 static size_t
 214 mask_size (int addr_mask)
 215 {
 216   switch (addr_mask)
 217     {
 218     case 0xffff:
 219       return 2;
 220     case 0xfffff:
 221     case 0xffffff:
 222       return 3;
 223     default:
 224       fprintf (stderr,
 225                "m32c minisim: addr_mask_size: unexpected mask 0x%x\n",
 226                addr_mask);
 227       return sizeof (addr_mask);
 228     }
 229 }
 230
 231 static size_t
 232 reg_size (enum m32c_sim_reg regno)
 233 {
 234   switch (regno)
 235     {
 236     case m32c_sim_reg_r0_bank0:
 237     case m32c_sim_reg_r1_bank0:
 238     case m32c_sim_reg_r2_bank0:
 239     case m32c_sim_reg_r3_bank0:
 240     case m32c_sim_reg_r0_bank1:
 241     case m32c_sim_reg_r1_bank1:
 242     case m32c_sim_reg_r2_bank1:
 243     case m32c_sim_reg_r3_bank1:
 244     case m32c_sim_reg_flg:
 245     case m32c_sim_reg_svf:
 246       return 2;
 247
 248     case m32c_sim_reg_a0_bank0:
 249     case m32c_sim_reg_a1_bank0:
 250     case m32c_sim_reg_fb_bank0:
 251     case m32c_sim_reg_sb_bank0:
 252     case m32c_sim_reg_a0_bank1:
 253     case m32c_sim_reg_a1_bank1:
 254     case m32c_sim_reg_fb_bank1:
 255     case m32c_sim_reg_sb_bank1:
 256     case m32c_sim_reg_usp:
 257     case m32c_sim_reg_isp:
 258       return mask_size (addr_mask);
 259
 260     case m32c_sim_reg_pc:
 261     case m32c_sim_reg_intb:
 262     case m32c_sim_reg_svp:
 263     case m32c_sim_reg_vct:
 264       return mask_size (membus_mask);
 265
 266     case m32c_sim_reg_dmd0:
 267     case m32c_sim_reg_dmd1:
 268       return 1;
 269
 270     case m32c_sim_reg_dct0:
 271     case m32c_sim_reg_dct1:
 272     case m32c_sim_reg_drc0:
 273     case m32c_sim_reg_drc1:
 274       return 2;
 275
 276     case m32c_sim_reg_dma0:
 277     case m32c_sim_reg_dma1:
 278     case m32c_sim_reg_dsa0:
 279     case m32c_sim_reg_dsa1:
 280     case m32c_sim_reg_dra0:
 281     case m32c_sim_reg_dra1:
 282       return 3;
 283
 284     default:
 285       fprintf (stderr, "m32c minisim: unrecognized register number: %d\n",
 286                regno);
 287       return -1;
 288     }
 289 }
 290
 291 int
 292 sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
 293 {
 294   size_t size;
 295
 296   check_desc (sd);
 297
 298   if (!check_regno (regno))
 299     return 0;
 300
 301   size = reg_size (regno);
 302   if (length == size)
 303     {
 304       DI val;
 305
 306       switch (regno)
 307         {
 308         case m32c_sim_reg_r0_bank0:
 309           val = regs.r[0].r_r0;
 310           break;
 311         case m32c_sim_reg_r1_bank0:
 312           val = regs.r[0].r_r1;
 313           break;
 314         case m32c_sim_reg_r2_bank0:
 315           val = regs.r[0].r_r2;
 316           break;
 317         case m32c_sim_reg_r3_bank0:
 318           val = regs.r[0].r_r3;
 319           break;
 320         case m32c_sim_reg_a0_bank0:
 321           val = regs.r[0].r_a0;
 322           break;
 323         case m32c_sim_reg_a1_bank0:
 324           val = regs.r[0].r_a1;
 325           break;
 326         case m32c_sim_reg_fb_bank0:
 327           val = regs.r[0].r_fb;
 328           break;
 329         case m32c_sim_reg_sb_bank0:
 330           val = regs.r[0].r_sb;
 331           break;
 332         case m32c_sim_reg_r0_bank1:
 333           val = regs.r[1].r_r0;
 334           break;
 335         case m32c_sim_reg_r1_bank1:
 336           val = regs.r[1].r_r1;
 337           break;
 338         case m32c_sim_reg_r2_bank1:
 339           val = regs.r[1].r_r2;
 340           break;
 341         case m32c_sim_reg_r3_bank1:
 342           val = regs.r[1].r_r3;
 343           break;
 344         case m32c_sim_reg_a0_bank1:
 345           val = regs.r[1].r_a0;
 346           break;
 347         case m32c_sim_reg_a1_bank1:
 348           val = regs.r[1].r_a1;
 349           break;
 350         case m32c_sim_reg_fb_bank1:
 351           val = regs.r[1].r_fb;
 352           break;
 353         case m32c_sim_reg_sb_bank1:
 354           val = regs.r[1].r_sb;
 355           break;
 356
 357         case m32c_sim_reg_usp:
 358           val = regs.r_usp;
 359           break;
 360         case m32c_sim_reg_isp:
 361           val = regs.r_isp;
 362           break;
 363         case m32c_sim_reg_pc:
 364           val = regs.r_pc;
 365           break;
 366         case m32c_sim_reg_intb:
 367           val = regs.r_intbl * 65536 + regs.r_intbl;
 368           break;
 369         case m32c_sim_reg_flg:
 370           val = regs.r_flags;
 371           break;
 372
 373           /* These registers aren't implemented by the minisim.  */
 374         case m32c_sim_reg_svf:
 375         case m32c_sim_reg_svp:
 376         case m32c_sim_reg_vct:
 377         case m32c_sim_reg_dmd0:
 378         case m32c_sim_reg_dmd1:
 379         case m32c_sim_reg_dct0:
 380         case m32c_sim_reg_dct1:
 381         case m32c_sim_reg_drc0:
 382         case m32c_sim_reg_drc1:
 383         case m32c_sim_reg_dma0:
 384         case m32c_sim_reg_dma1:
 385         case m32c_sim_reg_dsa0:
 386         case m32c_sim_reg_dsa1:
 387         case m32c_sim_reg_dra0:
 388         case m32c_sim_reg_dra1:
 389           return 0;
 390
 391         default:
 392           fprintf (stderr, "m32c minisim: unrecognized register number: %d\n",
 393                    regno);
 394           return -1;
 395         }
 396
 397       put_le (buf, length, val);
 398     }
 399
 400   return size;
 401 }
 402
 403 int
 404 sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
 405 {
 406   size_t size;
 407
 408   check_desc (sd);
 409
 410   if (!check_regno (regno))
 411     return -1;
 412
 413   size = reg_size (regno);
 414
 415   if (length == size)
 416     {
 417       DI val = get_le (buf, length);
 418
 419       switch (regno)
 420         {
 421         case m32c_sim_reg_r0_bank0:
 422           regs.r[0].r_r0 = val & 0xffff;
 423           break;
 424         case m32c_sim_reg_r1_bank0:
 425           regs.r[0].r_r1 = val & 0xffff;
 426           break;
 427         case m32c_sim_reg_r2_bank0:
 428           regs.r[0].r_r2 = val & 0xffff;
 429           break;
 430         case m32c_sim_reg_r3_bank0:
 431           regs.r[0].r_r3 = val & 0xffff;
 432           break;
 433         case m32c_sim_reg_a0_bank0:
 434           regs.r[0].r_a0 = val & addr_mask;
 435           break;
 436         case m32c_sim_reg_a1_bank0:
 437           regs.r[0].r_a1 = val & addr_mask;
 438           break;
 439         case m32c_sim_reg_fb_bank0:
 440           regs.r[0].r_fb = val & addr_mask;
 441           break;
 442         case m32c_sim_reg_sb_bank0:
 443           regs.r[0].r_sb = val & addr_mask;
 444           break;
 445         case m32c_sim_reg_r0_bank1:
 446           regs.r[1].r_r0 = val & 0xffff;
 447           break;
 448         case m32c_sim_reg_r1_bank1:
 449           regs.r[1].r_r1 = val & 0xffff;
 450           break;
 451         case m32c_sim_reg_r2_bank1:
 452           regs.r[1].r_r2 = val & 0xffff;
 453           break;
 454         case m32c_sim_reg_r3_bank1:
 455           regs.r[1].r_r3 = val & 0xffff;
 456           break;
 457         case m32c_sim_reg_a0_bank1:
 458           regs.r[1].r_a0 = val & addr_mask;
 459           break;
 460         case m32c_sim_reg_a1_bank1:
 461           regs.r[1].r_a1 = val & addr_mask;
 462           break;
 463         case m32c_sim_reg_fb_bank1:
 464           regs.r[1].r_fb = val & addr_mask;
 465           break;
 466         case m32c_sim_reg_sb_bank1:
 467           regs.r[1].r_sb = val & addr_mask;
 468           break;
 469
 470         case m32c_sim_reg_usp:
 471           regs.r_usp = val & addr_mask;
 472           break;
 473         case m32c_sim_reg_isp:
 474           regs.r_isp = val & addr_mask;
 475           break;
 476         case m32c_sim_reg_pc:
 477           regs.r_pc = val & membus_mask;
 478           break;
 479         case m32c_sim_reg_intb:
 480           regs.r_intbl = (val & membus_mask) & 0xffff;
 481           regs.r_intbh = (val & membus_mask) >> 16;
 482           break;
 483         case m32c_sim_reg_flg:
 484           regs.r_flags = val & 0xffff;
 485           break;
 486
 487           /* These registers aren't implemented by the minisim.  */
 488         case m32c_sim_reg_svf:
 489         case m32c_sim_reg_svp:
 490         case m32c_sim_reg_vct:
 491         case m32c_sim_reg_dmd0:
 492         case m32c_sim_reg_dmd1:
 493         case m32c_sim_reg_dct0:
 494         case m32c_sim_reg_dct1:
 495         case m32c_sim_reg_drc0:
 496         case m32c_sim_reg_drc1:
 497         case m32c_sim_reg_dma0:
 498         case m32c_sim_reg_dma1:
 499         case m32c_sim_reg_dsa0:
 500         case m32c_sim_reg_dsa1:
 501         case m32c_sim_reg_dra0:
 502         case m32c_sim_reg_dra1:
 503           return 0;
 504
 505         default:
 506           fprintf (stderr, "m32c minisim: unrecognized register number: %d\n",
 507                    regno);
 508           return 0;
 509         }
 510     }
 511
 512   return size;
 513 }
 514
 515 static volatile int stop;
 516 static enum sim_stop reason;
 517 static int siggnal;
 518
 519
 520 /* Given a signal number used by the M32C bsp (that is, newlib),
 521    return a target signal number used by GDB.  */
 522 static int
 523 m32c_signal_to_target (int m32c)
 524 {
 525   switch (m32c)
 526     {
 527     case 4:
 528       return GDB_SIGNAL_ILL;
 529
 530     case 5:
 531       return GDB_SIGNAL_TRAP;
 532
 533     case 10:
 534       return GDB_SIGNAL_BUS;
 535
 536     case 11:
 537       return GDB_SIGNAL_SEGV;
 538
 539     case 24:
 540       return GDB_SIGNAL_XCPU;
 541
 542     case 2:
 543       return GDB_SIGNAL_INT;
 544
 545     case 8:
 546       return GDB_SIGNAL_FPE;
 547
 548     case 6:
 549       return GDB_SIGNAL_ABRT;
 550     }
 551
 552   return 0;
 553 }
 554
 555
 556 /* Take a step return code RC and set up the variables consulted by
 557    sim_stop_reason appropriately.  */
 558 static void
 559 handle_step (int rc)
 560 {
 561   if (M32C_STEPPED (rc) || M32C_HIT_BREAK (rc))
 562     {
 563       reason = sim_stopped;
 564       siggnal = GDB_SIGNAL_TRAP;
 565     }
 566   else if (M32C_STOPPED (rc))
 567     {
 568       reason = sim_stopped;
 569       siggnal = m32c_signal_to_target (M32C_STOP_SIG (rc));
 570     }
 571   else
 572     {
 573       assert (M32C_EXITED (rc));
 574       reason = sim_exited;
 575       siggnal = M32C_EXIT_STATUS (rc);
 576     }
 577 }
 578
 579
 580 void
 581 sim_resume (SIM_DESC sd, int step, int sig_to_deliver)
 582 {
 583   check_desc (sd);
 584
 585   if (sig_to_deliver != 0)
 586     {
 587       fprintf (stderr,
 588                "Warning: the m32c minisim does not implement "
 589                "signal delivery yet.\n" "Resuming with no signal.\n");
 590     }
 591
 592   if (step)
 593     {
 594       handle_step (decode_opcode ());
 595 #ifdef TIMER_A
 596       update_timer_a ();
 597 #endif
 598     }
 599   else
 600     {
 601       /* We don't clear 'stop' here, because then we would miss
 602          interrupts that arrived on the way here.  Instead, we clear
 603          the flag in sim_stop_reason, after GDB has disabled the
 604          interrupt signal handler.  */
 605       for (;;)
 606         {
 607           int rc;
 608
 609           if (stop)
 610             {
 611               stop = 0;
 612               reason = sim_stopped;
 613               siggnal = GDB_SIGNAL_INT;
 614               break;
 615             }
 616
 617           rc = decode_opcode ();
 618 #ifdef TIMER_A
 619           update_timer_a ();
 620 #endif
 621
 622           if (!M32C_STEPPED (rc))
 623             {
 624               handle_step (rc);
 625               break;
 626             }
 627         }
 628     }
 629   m32c_sim_restore_console ();
 630 }
 631
 632 int
 633 sim_stop (SIM_DESC sd)
 634 {
 635   stop = 1;
 636
 637   return 1;
 638 }
 639
 640 void
 641 sim_stop_reason (SIM_DESC sd, enum sim_stop *reason_p, int *sigrc_p)
 642 {
 643   check_desc (sd);
 644
 645   *reason_p = reason;
 646   *sigrc_p = siggnal;
 647 }
 648
 649 void
 650 sim_do_command (SIM_DESC sd, const char *cmd)
 651 {
 652   const char *arg;
 653   char **argv = buildargv (cmd);
 654
 655   check_desc (sd);
 656
 657   cmd = arg = "";
 658   if (argv != NULL)
 659     {
 660       if (argv[0] != NULL)
 661         cmd = argv[0];
 662       if (argv[1] != NULL)
 663         arg = argv[1];
 664     }
 665
 666   if (strcmp (cmd, "trace") == 0)
 667     {
 668       if (strcmp (arg, "on") == 0)
 669         trace = 1;
 670       else if (strcmp (arg, "off") == 0)
 671         trace = 0;
 672       else
 673         printf ("The 'sim trace' command expects 'on' or 'off' "
 674                 "as an argument.\n");
 675     }
 676   else if (strcmp (cmd, "verbose") == 0)
 677     {
 678       if (strcmp (arg, "on") == 0)
 679         verbose = 1;
 680       else if (strcmp (arg, "off") == 0)
 681         verbose = 0;
 682       else
 683         printf ("The 'sim verbose' command expects 'on' or 'off'"
 684                 " as an argument.\n");
 685     }
 686   else
 687     printf ("The 'sim' command expects either 'trace' or 'verbose'"
 688             " as a subcommand.\n");
 689
 690   freeargv (argv);
 691 }
 692
 693 char **
 694 sim_complete_command (SIM_DESC sd, const char *text, const char *word)
 695 {
 696   return NULL;
 697 }
 698
 699 char *
 700 sim_memory_map (SIM_DESC sd)
 701 {
 702   return NULL;
 703 }
 704
 705 void
 706 sim_info (SIM_DESC sd, int verbose)
 707 {
 708   printf ("The m32c minisim doesn't collect any statistics.\n");
 709 }