sim/m32r/cpu.h

   1 /* CPU family header for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_M32RBF_H
  26 #define CPU_M32RBF_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 2
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 1
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[16];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* control registers */
  48   USI h_cr[16];
  49 #define GET_H_CR(index) m32rbf_h_cr_get_handler (current_cpu, index)
  50 #define SET_H_CR(index, x) \
  51 do { \
  52 m32rbf_h_cr_set_handler (current_cpu, (index), (x));\
  53 } while (0)
  54   /* accumulator */
  55   DI h_accum;
  56 #define GET_H_ACCUM() m32rbf_h_accum_get_handler (current_cpu)
  57 #define SET_H_ACCUM(x) \
  58 do { \
  59 m32rbf_h_accum_set_handler (current_cpu, (x));\
  60 } while (0)
  61   /* condition bit */
  62   BI h_cond;
  63 #define GET_H_COND() CPU (h_cond)
  64 #define SET_H_COND(x) (CPU (h_cond) = (x))
  65   /* psw part of psw */
  66   UQI h_psw;
  67 #define GET_H_PSW() m32rbf_h_psw_get_handler (current_cpu)
  68 #define SET_H_PSW(x) \
  69 do { \
  70 m32rbf_h_psw_set_handler (current_cpu, (x));\
  71 } while (0)
  72   /* backup psw */
  73   UQI h_bpsw;
  74 #define GET_H_BPSW() CPU (h_bpsw)
  75 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
  76   /* backup bpsw */
  77   UQI h_bbpsw;
  78 #define GET_H_BBPSW() CPU (h_bbpsw)
  79 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
  80   /* lock */
  81   BI h_lock;
  82 #define GET_H_LOCK() CPU (h_lock)
  83 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
  84   } hardware;
  85 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  86 } M32RBF_CPU_DATA;
  87
  88 /* Cover fns for register access.  */
  89 USI m32rbf_h_pc_get (SIM_CPU *);
  90 void m32rbf_h_pc_set (SIM_CPU *, USI);
  91 SI m32rbf_h_gr_get (SIM_CPU *, UINT);
  92 void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
  93 USI m32rbf_h_cr_get (SIM_CPU *, UINT);
  94 void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
  95 DI m32rbf_h_accum_get (SIM_CPU *);
  96 void m32rbf_h_accum_set (SIM_CPU *, DI);
  97 BI m32rbf_h_cond_get (SIM_CPU *);
  98 void m32rbf_h_cond_set (SIM_CPU *, BI);
  99 UQI m32rbf_h_psw_get (SIM_CPU *);
 100 void m32rbf_h_psw_set (SIM_CPU *, UQI);
 101 UQI m32rbf_h_bpsw_get (SIM_CPU *);
 102 void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
 103 UQI m32rbf_h_bbpsw_get (SIM_CPU *);
 104 void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
 105 BI m32rbf_h_lock_get (SIM_CPU *);
 106 void m32rbf_h_lock_set (SIM_CPU *, BI);
 107
 108 /* These must be hand-written.  */
 109 extern CPUREG_FETCH_FN m32rbf_fetch_register;
 110 extern CPUREG_STORE_FN m32rbf_store_register;
 111
 112 typedef struct {
 113   UINT h_gr;
 114 } MODEL_M32R_D_DATA;
 115
 116 typedef struct {
 117   int empty;
 118 } MODEL_TEST_DATA;
 119
 120 /* Instruction argument buffer.  */
 121
 122 union sem_fields {
 123   struct { /* no operands */
 124     int empty;
 125   } fmt_empty;
 126   struct { /*  */
 127     UINT f_uimm4;
 128   } sfmt_trap;
 129   struct { /*  */
 130     IADDR i_disp24;
 131     unsigned char out_h_gr_14;
 132   } sfmt_bl24;
 133   struct { /*  */
 134     IADDR i_disp8;
 135     unsigned char out_h_gr_14;
 136   } sfmt_bl8;
 137   struct { /*  */
 138     SI* i_dr;
 139     UINT f_hi16;
 140     unsigned char out_dr;
 141   } sfmt_seth;
 142   struct { /*  */
 143     SI* i_sr;
 144     UINT f_r1;
 145     unsigned char in_sr;
 146   } sfmt_mvtc;
 147   struct { /*  */
 148     SI* i_dr;
 149     UINT f_r2;
 150     unsigned char out_dr;
 151   } sfmt_mvfc;
 152   struct { /*  */
 153     ADDR i_uimm24;
 154     SI* i_dr;
 155     unsigned char out_dr;
 156   } sfmt_ld24;
 157   struct { /*  */
 158     SI* i_sr;
 159     unsigned char in_sr;
 160     unsigned char out_h_gr_14;
 161   } sfmt_jl;
 162   struct { /*  */
 163     SI* i_dr;
 164     UINT f_uimm5;
 165     unsigned char in_dr;
 166     unsigned char out_dr;
 167   } sfmt_slli;
 168   struct { /*  */
 169     SI* i_dr;
 170     INT f_simm8;
 171     unsigned char in_dr;
 172     unsigned char out_dr;
 173   } sfmt_addi;
 174   struct { /*  */
 175     SI* i_src1;
 176     SI* i_src2;
 177     unsigned char in_src1;
 178     unsigned char in_src2;
 179     unsigned char out_src2;
 180   } sfmt_st_plus;
 181   struct { /*  */
 182     SI* i_src1;
 183     SI* i_src2;
 184     INT f_simm16;
 185     unsigned char in_src1;
 186     unsigned char in_src2;
 187   } sfmt_st_d;
 188   struct { /*  */
 189     SI* i_dr;
 190     SI* i_sr;
 191     unsigned char in_sr;
 192     unsigned char out_dr;
 193     unsigned char out_sr;
 194   } sfmt_ld_plus;
 195   struct { /*  */
 196     IADDR i_disp16;
 197     SI* i_src1;
 198     SI* i_src2;
 199     unsigned char in_src1;
 200     unsigned char in_src2;
 201   } sfmt_beq;
 202   struct { /*  */
 203     SI* i_dr;
 204     SI* i_sr;
 205     UINT f_uimm16;
 206     unsigned char in_sr;
 207     unsigned char out_dr;
 208   } sfmt_and3;
 209   struct { /*  */
 210     SI* i_dr;
 211     SI* i_sr;
 212     INT f_simm16;
 213     unsigned char in_sr;
 214     unsigned char out_dr;
 215   } sfmt_add3;
 216   struct { /*  */
 217     SI* i_dr;
 218     SI* i_sr;
 219     unsigned char in_dr;
 220     unsigned char in_sr;
 221     unsigned char out_dr;
 222   } sfmt_add;
 223 #if WITH_SCACHE_PBB
 224   /* Writeback handler.  */
 225   struct {
 226     /* Pointer to argbuf entry for insn whose results need writing back.  */
 227     const struct argbuf *abuf;
 228   } write;
 229   /* x-before handler */
 230   struct {
 231     /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 232     int first_p;
 233   } before;
 234   /* x-after handler */
 235   struct {
 236     int empty;
 237   } after;
 238   /* This entry is used to terminate each pbb.  */
 239   struct {
 240     /* Number of insns in pbb.  */
 241     int insn_count;
 242     /* Next pbb to execute.  */
 243     SCACHE *next;
 244     SCACHE *branch_target;
 245   } chain;
 246 #endif
 247 };
 248
 249 /* The ARGBUF struct.  */
 250 struct argbuf {
 251   /* These are the baseclass definitions.  */
 252   IADDR addr;
 253   const IDESC *idesc;
 254   char trace_p;
 255   char profile_p;
 256   /* ??? Temporary hack for skip insns.  */
 257   char skip_count;
 258   char unused;
 259   /* cpu specific data follows */
 260   union sem semantic;
 261   int written;
 262   union sem_fields fields;
 263 };
 264
 265 /* A cached insn.
 266
 267    ??? SCACHE used to contain more than just argbuf.  We could delete the
 268    type entirely and always just use ARGBUF, but for future concerns and as
 269    a level of abstraction it is left in.  */
 270
 271 struct scache {
 272   struct argbuf argbuf;
 273 };
 274
 275 /* Macros to simplify extraction, reading and semantic code.
 276    These define and assign the local vars that contain the insn's fields.  */
 277
 278 #define EXTRACT_IFMT_EMPTY_VARS \
 279   unsigned int length;
 280 #define EXTRACT_IFMT_EMPTY_CODE \
 281   length = 0; \
 282
 283 #define EXTRACT_IFMT_ADD_VARS \
 284   UINT f_op1; \
 285   UINT f_r1; \
 286   UINT f_op2; \
 287   UINT f_r2; \
 288   unsigned int length;
 289 #define EXTRACT_IFMT_ADD_CODE \
 290   length = 2; \
 291   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 292   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 293   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 294   f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 295
 296 #define EXTRACT_IFMT_ADD3_VARS \
 297   UINT f_op1; \
 298   UINT f_r1; \
 299   UINT f_op2; \
 300   UINT f_r2; \
 301   INT f_simm16; \
 302   unsigned int length;
 303 #define EXTRACT_IFMT_ADD3_CODE \
 304   length = 4; \
 305   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 306   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 307   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 308   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 309   f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 310
 311 #define EXTRACT_IFMT_AND3_VARS \
 312   UINT f_op1; \
 313   UINT f_r1; \
 314   UINT f_op2; \
 315   UINT f_r2; \
 316   UINT f_uimm16; \
 317   unsigned int length;
 318 #define EXTRACT_IFMT_AND3_CODE \
 319   length = 4; \
 320   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 321   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 322   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 323   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 324   f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
 325
 326 #define EXTRACT_IFMT_OR3_VARS \
 327   UINT f_op1; \
 328   UINT f_r1; \
 329   UINT f_op2; \
 330   UINT f_r2; \
 331   UINT f_uimm16; \
 332   unsigned int length;
 333 #define EXTRACT_IFMT_OR3_CODE \
 334   length = 4; \
 335   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 336   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 337   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 338   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 339   f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
 340
 341 #define EXTRACT_IFMT_ADDI_VARS \
 342   UINT f_op1; \
 343   UINT f_r1; \
 344   INT f_simm8; \
 345   unsigned int length;
 346 #define EXTRACT_IFMT_ADDI_CODE \
 347   length = 2; \
 348   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 349   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 350   f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
 351
 352 #define EXTRACT_IFMT_ADDV3_VARS \
 353   UINT f_op1; \
 354   UINT f_r1; \
 355   UINT f_op2; \
 356   UINT f_r2; \
 357   INT f_simm16; \
 358   unsigned int length;
 359 #define EXTRACT_IFMT_ADDV3_CODE \
 360   length = 4; \
 361   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 362   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 363   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 364   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 365   f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 366
 367 #define EXTRACT_IFMT_BC8_VARS \
 368   UINT f_op1; \
 369   UINT f_r1; \
 370   SI f_disp8; \
 371   unsigned int length;
 372 #define EXTRACT_IFMT_BC8_CODE \
 373   length = 2; \
 374   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 375   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 376   f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 377
 378 #define EXTRACT_IFMT_BC24_VARS \
 379   UINT f_op1; \
 380   UINT f_r1; \
 381   SI f_disp24; \
 382   unsigned int length;
 383 #define EXTRACT_IFMT_BC24_CODE \
 384   length = 4; \
 385   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 386   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 387   f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 388
 389 #define EXTRACT_IFMT_BEQ_VARS \
 390   UINT f_op1; \
 391   UINT f_r1; \
 392   UINT f_op2; \
 393   UINT f_r2; \
 394   SI f_disp16; \
 395   unsigned int length;
 396 #define EXTRACT_IFMT_BEQ_CODE \
 397   length = 4; \
 398   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 399   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 400   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 401   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 402   f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 403
 404 #define EXTRACT_IFMT_BEQZ_VARS \
 405   UINT f_op1; \
 406   UINT f_r1; \
 407   UINT f_op2; \
 408   UINT f_r2; \
 409   SI f_disp16; \
 410   unsigned int length;
 411 #define EXTRACT_IFMT_BEQZ_CODE \
 412   length = 4; \
 413   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 414   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 415   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 416   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 417   f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 418
 419 #define EXTRACT_IFMT_CMP_VARS \
 420   UINT f_op1; \
 421   UINT f_r1; \
 422   UINT f_op2; \
 423   UINT f_r2; \
 424   unsigned int length;
 425 #define EXTRACT_IFMT_CMP_CODE \
 426   length = 2; \
 427   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 428   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 429   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 430   f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 431
 432 #define EXTRACT_IFMT_CMPI_VARS \
 433   UINT f_op1; \
 434   UINT f_r1; \
 435   UINT f_op2; \
 436   UINT f_r2; \
 437   INT f_simm16; \
 438   unsigned int length;
 439 #define EXTRACT_IFMT_CMPI_CODE \
 440   length = 4; \
 441   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 442   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 443   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 444   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 445   f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 446
 447 #define EXTRACT_IFMT_DIV_VARS \
 448   UINT f_op1; \
 449   UINT f_r1; \
 450   UINT f_op2; \
 451   UINT f_r2; \
 452   INT f_simm16; \
 453   unsigned int length;
 454 #define EXTRACT_IFMT_DIV_CODE \
 455   length = 4; \
 456   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 457   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 458   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 459   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 460   f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 461
 462 #define EXTRACT_IFMT_JL_VARS \
 463   UINT f_op1; \
 464   UINT f_r1; \
 465   UINT f_op2; \
 466   UINT f_r2; \
 467   unsigned int length;
 468 #define EXTRACT_IFMT_JL_CODE \
 469   length = 2; \
 470   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 471   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 472   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 473   f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 474
 475 #define EXTRACT_IFMT_LD24_VARS \
 476   UINT f_op1; \
 477   UINT f_r1; \
 478   UINT f_uimm24; \
 479   unsigned int length;
 480 #define EXTRACT_IFMT_LD24_CODE \
 481   length = 4; \
 482   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 483   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 484   f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
 485
 486 #define EXTRACT_IFMT_LDI16_VARS \
 487   UINT f_op1; \
 488   UINT f_r1; \
 489   UINT f_op2; \
 490   UINT f_r2; \
 491   INT f_simm16; \
 492   unsigned int length;
 493 #define EXTRACT_IFMT_LDI16_CODE \
 494   length = 4; \
 495   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 496   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 497   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 498   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 499   f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 500
 501 #define EXTRACT_IFMT_MVFACHI_VARS \
 502   UINT f_op1; \
 503   UINT f_r1; \
 504   UINT f_op2; \
 505   UINT f_r2; \
 506   unsigned int length;
 507 #define EXTRACT_IFMT_MVFACHI_CODE \
 508   length = 2; \
 509   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 510   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 511   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 512   f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 513
 514 #define EXTRACT_IFMT_MVFC_VARS \
 515   UINT f_op1; \
 516   UINT f_r1; \
 517   UINT f_op2; \
 518   UINT f_r2; \
 519   unsigned int length;
 520 #define EXTRACT_IFMT_MVFC_CODE \
 521   length = 2; \
 522   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 523   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 524   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 525   f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 526
 527 #define EXTRACT_IFMT_MVTACHI_VARS \
 528   UINT f_op1; \
 529   UINT f_r1; \
 530   UINT f_op2; \
 531   UINT f_r2; \
 532   unsigned int length;
 533 #define EXTRACT_IFMT_MVTACHI_CODE \
 534   length = 2; \
 535   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 536   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 537   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 538   f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 539
 540 #define EXTRACT_IFMT_MVTC_VARS \
 541   UINT f_op1; \
 542   UINT f_r1; \
 543   UINT f_op2; \
 544   UINT f_r2; \
 545   unsigned int length;
 546 #define EXTRACT_IFMT_MVTC_CODE \
 547   length = 2; \
 548   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 549   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 550   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 551   f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 552
 553 #define EXTRACT_IFMT_NOP_VARS \
 554   UINT f_op1; \
 555   UINT f_r1; \
 556   UINT f_op2; \
 557   UINT f_r2; \
 558   unsigned int length;
 559 #define EXTRACT_IFMT_NOP_CODE \
 560   length = 2; \
 561   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 562   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 563   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 564   f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 565
 566 #define EXTRACT_IFMT_SETH_VARS \
 567   UINT f_op1; \
 568   UINT f_r1; \
 569   UINT f_op2; \
 570   UINT f_r2; \
 571   UINT f_hi16; \
 572   unsigned int length;
 573 #define EXTRACT_IFMT_SETH_CODE \
 574   length = 4; \
 575   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 576   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 577   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 578   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 579   f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
 580
 581 #define EXTRACT_IFMT_SLLI_VARS \
 582   UINT f_op1; \
 583   UINT f_r1; \
 584   UINT f_shift_op2; \
 585   UINT f_uimm5; \
 586   unsigned int length;
 587 #define EXTRACT_IFMT_SLLI_CODE \
 588   length = 2; \
 589   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 590   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 591   f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
 592   f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
 593
 594 #define EXTRACT_IFMT_ST_D_VARS \
 595   UINT f_op1; \
 596   UINT f_r1; \
 597   UINT f_op2; \
 598   UINT f_r2; \
 599   INT f_simm16; \
 600   unsigned int length;
 601 #define EXTRACT_IFMT_ST_D_CODE \
 602   length = 4; \
 603   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 604   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 605   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 606   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 607   f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 608
 609 #define EXTRACT_IFMT_TRAP_VARS \
 610   UINT f_op1; \
 611   UINT f_r1; \
 612   UINT f_op2; \
 613   UINT f_uimm4; \
 614   unsigned int length;
 615 #define EXTRACT_IFMT_TRAP_CODE \
 616   length = 2; \
 617   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 618   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 619   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 620   f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 621
 622 /* Collection of various things for the trace handler to use.  */
 623
 624 typedef struct trace_record {
 625   IADDR pc;
 626   /* FIXME:wip */
 627 } TRACE_RECORD;
 628
 629 #endif /* CPU_M32RBF_H */