sim/m32r/cpu.h

   1 /* CPU family header for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_M32RBF_H
  26 #define CPU_M32RBF_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 2
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 1
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[16];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* control registers */
  48   USI h_cr[16];
  49 /* GET_H_CR macro user-written */
  50 /* SET_H_CR macro user-written */
  51   /* accumulator */
  52   DI h_accum;
  53 /* GET_H_ACCUM macro user-written */
  54 /* SET_H_ACCUM macro user-written */
  55 /* start-sanitize-m32rx */
  56   /* accumulators */
  57   DI h_accums[2];
  58 /* end-sanitize-m32rx */
  59 /* start-sanitize-m32rx */
  60 /* GET_H_ACCUMS macro user-written */
  61 /* SET_H_ACCUMS macro user-written */
  62 /* end-sanitize-m32rx */
  63   /* condition bit */
  64   BI h_cond;
  65 #define GET_H_COND() CPU (h_cond)
  66 #define SET_H_COND(x) (CPU (h_cond) = (x))
  67   /* psw part of psw */
  68   UQI h_psw;
  69 /* GET_H_PSW macro user-written */
  70 /* SET_H_PSW macro user-written */
  71   /* backup psw */
  72   UQI h_bpsw;
  73 #define GET_H_BPSW() CPU (h_bpsw)
  74 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
  75   /* backup bpsw */
  76   UQI h_bbpsw;
  77 #define GET_H_BBPSW() CPU (h_bbpsw)
  78 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
  79   /* lock */
  80   BI h_lock;
  81 #define GET_H_LOCK() CPU (h_lock)
  82 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
  83   } hardware;
  84 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  85 } M32RBF_CPU_DATA;
  86
  87 /* Cover fns for register access.  */
  88 USI m32rbf_h_pc_get (SIM_CPU *);
  89 void m32rbf_h_pc_set (SIM_CPU *, USI);
  90 SI m32rbf_h_gr_get (SIM_CPU *, UINT);
  91 void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
  92 USI m32rbf_h_cr_get (SIM_CPU *, UINT);
  93 void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
  94 DI m32rbf_h_accum_get (SIM_CPU *);
  95 void m32rbf_h_accum_set (SIM_CPU *, DI);
  96 DI m32rbf_h_accums_get (SIM_CPU *, UINT);
  97 void m32rbf_h_accums_set (SIM_CPU *, UINT, DI);
  98 BI m32rbf_h_cond_get (SIM_CPU *);
  99 void m32rbf_h_cond_set (SIM_CPU *, BI);
 100 UQI m32rbf_h_psw_get (SIM_CPU *);
 101 void m32rbf_h_psw_set (SIM_CPU *, UQI);
 102 UQI m32rbf_h_bpsw_get (SIM_CPU *);
 103 void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
 104 UQI m32rbf_h_bbpsw_get (SIM_CPU *);
 105 void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
 106 BI m32rbf_h_lock_get (SIM_CPU *);
 107 void m32rbf_h_lock_set (SIM_CPU *, BI);
 108
 109 /* These must be hand-written.  */
 110 extern CPUREG_FETCH_FN m32rbf_fetch_register;
 111 extern CPUREG_STORE_FN m32rbf_store_register;
 112
 113 typedef struct {
 114   UINT h_gr;
 115 } MODEL_M32R_D_DATA;
 116
 117 typedef struct {
 118   int empty;
 119 } MODEL_TEST_DATA;
 120
 121 /* The ARGBUF struct.  */
 122 struct argbuf {
 123   /* These are the baseclass definitions.  */
 124   PCADDR addr;
 125   const IDESC *idesc;
 126   char trace_p;
 127   char profile_p;
 128   /* cpu specific data follows */
 129   union sem semantic;
 130   int written;
 131   union {
 132     struct { /* empty format for unspecified field list */
 133       int empty;
 134     } fmt_empty;
 135     struct { /* e.g. add $dr,$sr */
 136       SI * i_dr;
 137       SI * i_sr;
 138       unsigned char in_dr;
 139       unsigned char in_sr;
 140       unsigned char out_dr;
 141     } fmt_add;
 142     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
 143       INT f_simm16;
 144       SI * i_sr;
 145       SI * i_dr;
 146       unsigned char in_sr;
 147       unsigned char out_dr;
 148     } fmt_add3;
 149     struct { /* e.g. and3 $dr,$sr,$uimm16 */
 150       UINT f_uimm16;
 151       SI * i_sr;
 152       SI * i_dr;
 153       unsigned char in_sr;
 154       unsigned char out_dr;
 155     } fmt_and3;
 156     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
 157       UINT f_uimm16;
 158       SI * i_sr;
 159       SI * i_dr;
 160       unsigned char in_sr;
 161       unsigned char out_dr;
 162     } fmt_or3;
 163     struct { /* e.g. addi $dr,$simm8 */
 164       INT f_simm8;
 165       SI * i_dr;
 166       unsigned char in_dr;
 167       unsigned char out_dr;
 168     } fmt_addi;
 169     struct { /* e.g. addv $dr,$sr */
 170       SI * i_dr;
 171       SI * i_sr;
 172       unsigned char in_dr;
 173       unsigned char in_sr;
 174       unsigned char out_dr;
 175     } fmt_addv;
 176     struct { /* e.g. addv3 $dr,$sr,$simm16 */
 177       INT f_simm16;
 178       SI * i_sr;
 179       SI * i_dr;
 180       unsigned char in_sr;
 181       unsigned char out_dr;
 182     } fmt_addv3;
 183     struct { /* e.g. addx $dr,$sr */
 184       SI * i_dr;
 185       SI * i_sr;
 186       unsigned char in_dr;
 187       unsigned char in_sr;
 188       unsigned char out_dr;
 189     } fmt_addx;
 190     struct { /* e.g. cmp $src1,$src2 */
 191       SI * i_src1;
 192       SI * i_src2;
 193       unsigned char in_src1;
 194       unsigned char in_src2;
 195     } fmt_cmp;
 196     struct { /* e.g. cmpi $src2,$simm16 */
 197       INT f_simm16;
 198       SI * i_src2;
 199       unsigned char in_src2;
 200     } fmt_cmpi;
 201     struct { /* e.g. div $dr,$sr */
 202       SI * i_sr;
 203       SI * i_dr;
 204       unsigned char in_sr;
 205       unsigned char in_dr;
 206       unsigned char out_dr;
 207     } fmt_div;
 208     struct { /* e.g. ld $dr,@$sr */
 209       SI * i_sr;
 210       SI * i_dr;
 211       unsigned char in_sr;
 212       unsigned char out_dr;
 213     } fmt_ld;
 214     struct { /* e.g. ld $dr,@($slo16,$sr) */
 215       INT f_simm16;
 216       SI * i_sr;
 217       SI * i_dr;
 218       unsigned char in_sr;
 219       unsigned char out_dr;
 220     } fmt_ld_d;
 221     struct { /* e.g. ldb $dr,@$sr */
 222       SI * i_sr;
 223       SI * i_dr;
 224       unsigned char in_sr;
 225       unsigned char out_dr;
 226     } fmt_ldb;
 227     struct { /* e.g. ldb $dr,@($slo16,$sr) */
 228       INT f_simm16;
 229       SI * i_sr;
 230       SI * i_dr;
 231       unsigned char in_sr;
 232       unsigned char out_dr;
 233     } fmt_ldb_d;
 234     struct { /* e.g. ldh $dr,@$sr */
 235       SI * i_sr;
 236       SI * i_dr;
 237       unsigned char in_sr;
 238       unsigned char out_dr;
 239     } fmt_ldh;
 240     struct { /* e.g. ldh $dr,@($slo16,$sr) */
 241       INT f_simm16;
 242       SI * i_sr;
 243       SI * i_dr;
 244       unsigned char in_sr;
 245       unsigned char out_dr;
 246     } fmt_ldh_d;
 247     struct { /* e.g. ld $dr,@$sr+ */
 248       SI * i_sr;
 249       SI * i_dr;
 250       unsigned char in_sr;
 251       unsigned char out_dr;
 252       unsigned char out_sr;
 253     } fmt_ld_plus;
 254     struct { /* e.g. ld24 $dr,$uimm24 */
 255       ADDR i_uimm24;
 256       SI * i_dr;
 257       unsigned char out_dr;
 258     } fmt_ld24;
 259     struct { /* e.g. ldi8 $dr,$simm8 */
 260       INT f_simm8;
 261       SI * i_dr;
 262       unsigned char out_dr;
 263     } fmt_ldi8;
 264     struct { /* e.g. ldi16 $dr,$hash$slo16 */
 265       INT f_simm16;
 266       SI * i_dr;
 267       unsigned char out_dr;
 268     } fmt_ldi16;
 269     struct { /* e.g. lock $dr,@$sr */
 270       SI * i_sr;
 271       SI * i_dr;
 272       unsigned char in_sr;
 273       unsigned char out_dr;
 274     } fmt_lock;
 275     struct { /* e.g. machi $src1,$src2 */
 276       SI * i_src1;
 277       SI * i_src2;
 278       unsigned char in_src1;
 279       unsigned char in_src2;
 280     } fmt_machi;
 281     struct { /* e.g. mulhi $src1,$src2 */
 282       SI * i_src1;
 283       SI * i_src2;
 284       unsigned char in_src1;
 285       unsigned char in_src2;
 286     } fmt_mulhi;
 287     struct { /* e.g. mv $dr,$sr */
 288       SI * i_sr;
 289       SI * i_dr;
 290       unsigned char in_sr;
 291       unsigned char out_dr;
 292     } fmt_mv;
 293     struct { /* e.g. mvfachi $dr */
 294       SI * i_dr;
 295       unsigned char out_dr;
 296     } fmt_mvfachi;
 297     struct { /* e.g. mvfc $dr,$scr */
 298       UINT f_r2;
 299       SI * i_dr;
 300       unsigned char out_dr;
 301     } fmt_mvfc;
 302     struct { /* e.g. mvtachi $src1 */
 303       SI * i_src1;
 304       unsigned char in_src1;
 305     } fmt_mvtachi;
 306     struct { /* e.g. mvtc $sr,$dcr */
 307       UINT f_r1;
 308       SI * i_sr;
 309       unsigned char in_sr;
 310     } fmt_mvtc;
 311     struct { /* e.g. nop */
 312       int empty;
 313     } fmt_nop;
 314     struct { /* e.g. rac */
 315       int empty;
 316     } fmt_rac;
 317     struct { /* e.g. seth $dr,$hash$hi16 */
 318       UINT f_hi16;
 319       SI * i_dr;
 320       unsigned char out_dr;
 321     } fmt_seth;
 322     struct { /* e.g. sll3 $dr,$sr,$simm16 */
 323       INT f_simm16;
 324       SI * i_sr;
 325       SI * i_dr;
 326       unsigned char in_sr;
 327       unsigned char out_dr;
 328     } fmt_sll3;
 329     struct { /* e.g. slli $dr,$uimm5 */
 330       UINT f_uimm5;
 331       SI * i_dr;
 332       unsigned char in_dr;
 333       unsigned char out_dr;
 334     } fmt_slli;
 335     struct { /* e.g. st $src1,@$src2 */
 336       SI * i_src2;
 337       SI * i_src1;
 338       unsigned char in_src2;
 339       unsigned char in_src1;
 340     } fmt_st;
 341     struct { /* e.g. st $src1,@($slo16,$src2) */
 342       INT f_simm16;
 343       SI * i_src2;
 344       SI * i_src1;
 345       unsigned char in_src2;
 346       unsigned char in_src1;
 347     } fmt_st_d;
 348     struct { /* e.g. stb $src1,@$src2 */
 349       SI * i_src2;
 350       SI * i_src1;
 351       unsigned char in_src2;
 352       unsigned char in_src1;
 353     } fmt_stb;
 354     struct { /* e.g. stb $src1,@($slo16,$src2) */
 355       INT f_simm16;
 356       SI * i_src2;
 357       SI * i_src1;
 358       unsigned char in_src2;
 359       unsigned char in_src1;
 360     } fmt_stb_d;
 361     struct { /* e.g. sth $src1,@$src2 */
 362       SI * i_src2;
 363       SI * i_src1;
 364       unsigned char in_src2;
 365       unsigned char in_src1;
 366     } fmt_sth;
 367     struct { /* e.g. sth $src1,@($slo16,$src2) */
 368       INT f_simm16;
 369       SI * i_src2;
 370       SI * i_src1;
 371       unsigned char in_src2;
 372       unsigned char in_src1;
 373     } fmt_sth_d;
 374     struct { /* e.g. st $src1,@+$src2 */
 375       SI * i_src2;
 376       SI * i_src1;
 377       unsigned char in_src2;
 378       unsigned char in_src1;
 379       unsigned char out_src2;
 380     } fmt_st_plus;
 381     struct { /* e.g. unlock $src1,@$src2 */
 382       SI * i_src2;
 383       SI * i_src1;
 384       unsigned char in_src2;
 385       unsigned char in_src1;
 386     } fmt_unlock;
 387   /* cti insns, kept separately so addr_cache is in fixed place */
 388   struct {
 389     union {
 390     struct { /* e.g. bc.s $disp8 */
 391       IADDR i_disp8;
 392     } fmt_bc8;
 393     struct { /* e.g. bc.l $disp24 */
 394       IADDR i_disp24;
 395     } fmt_bc24;
 396     struct { /* e.g. beq $src1,$src2,$disp16 */
 397       SI * i_src1;
 398       SI * i_src2;
 399       IADDR i_disp16;
 400       unsigned char in_src1;
 401       unsigned char in_src2;
 402     } fmt_beq;
 403     struct { /* e.g. beqz $src2,$disp16 */
 404       SI * i_src2;
 405       IADDR i_disp16;
 406       unsigned char in_src2;
 407     } fmt_beqz;
 408     struct { /* e.g. bl.s $disp8 */
 409       IADDR i_disp8;
 410       unsigned char out_h_gr_14;
 411     } fmt_bl8;
 412     struct { /* e.g. bl.l $disp24 */
 413       IADDR i_disp24;
 414       unsigned char out_h_gr_14;
 415     } fmt_bl24;
 416     struct { /* e.g. bra.s $disp8 */
 417       IADDR i_disp8;
 418     } fmt_bra8;
 419     struct { /* e.g. bra.l $disp24 */
 420       IADDR i_disp24;
 421     } fmt_bra24;
 422     struct { /* e.g. jl $sr */
 423       SI * i_sr;
 424       unsigned char in_sr;
 425       unsigned char out_h_gr_14;
 426     } fmt_jl;
 427     struct { /* e.g. jmp $sr */
 428       SI * i_sr;
 429       unsigned char in_sr;
 430     } fmt_jmp;
 431     struct { /* e.g. rte */
 432       int empty;
 433     } fmt_rte;
 434     struct { /* e.g. trap $uimm4 */
 435       UINT f_uimm4;
 436     } fmt_trap;
 437     } fields;
 438 #if WITH_SCACHE_PBB
 439     SEM_PC addr_cache;
 440 #endif
 441   } cti;
 442 #if WITH_SCACHE_PBB
 443     /* Writeback handler.  */
 444     struct {
 445       /* Pointer to argbuf entry for insn whose results need writing back.  */
 446       const struct argbuf *abuf;
 447     } write;
 448     /* x-before handler */
 449     struct {
 450       /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 451       int first_p;
 452     } before;
 453     /* x-after handler */
 454     struct {
 455       int empty;
 456     } after;
 457     /* This entry is used to terminate each pbb.  */
 458     struct {
 459       /* Number of insns in pbb.  */
 460       int insn_count;
 461       /* Next pbb to execute.  */
 462       SCACHE *next;
 463     } chain;
 464 #endif
 465   } fields;
 466 };
 467
 468 /* A cached insn.
 469
 470    ??? SCACHE used to contain more than just argbuf.  We could delete the
 471    type entirely and always just use ARGBUF, but for future concerns and as
 472    a level of abstraction it is left in.  */
 473
 474 struct scache {
 475   struct argbuf argbuf;
 476 };
 477
 478 /* Macros to simplify extraction, reading and semantic code.
 479    These define and assign the local vars that contain the insn's fields.  */
 480
 481 #define EXTRACT_FMT_EMPTY_VARS \
 482   /* Instruction fields.  */ \
 483   unsigned int length;
 484 #define EXTRACT_FMT_EMPTY_CODE \
 485   length = 0; \
 486
 487 #define EXTRACT_FMT_ADD_VARS \
 488   /* Instruction fields.  */ \
 489   UINT f_op1; \
 490   UINT f_r1; \
 491   UINT f_op2; \
 492   UINT f_r2; \
 493   unsigned int length;
 494 #define EXTRACT_FMT_ADD_CODE \
 495   length = 2; \
 496   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 497   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 498   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 499   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 500
 501 #define EXTRACT_FMT_ADD3_VARS \
 502   /* Instruction fields.  */ \
 503   UINT f_op1; \
 504   UINT f_r1; \
 505   UINT f_op2; \
 506   UINT f_r2; \
 507   INT f_simm16; \
 508   unsigned int length;
 509 #define EXTRACT_FMT_ADD3_CODE \
 510   length = 4; \
 511   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 512   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 513   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 514   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 515   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 516
 517 #define EXTRACT_FMT_AND3_VARS \
 518   /* Instruction fields.  */ \
 519   UINT f_op1; \
 520   UINT f_r1; \
 521   UINT f_op2; \
 522   UINT f_r2; \
 523   UINT f_uimm16; \
 524   unsigned int length;
 525 #define EXTRACT_FMT_AND3_CODE \
 526   length = 4; \
 527   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 528   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 529   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 530   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 531   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 532
 533 #define EXTRACT_FMT_OR3_VARS \
 534   /* Instruction fields.  */ \
 535   UINT f_op1; \
 536   UINT f_r1; \
 537   UINT f_op2; \
 538   UINT f_r2; \
 539   UINT f_uimm16; \
 540   unsigned int length;
 541 #define EXTRACT_FMT_OR3_CODE \
 542   length = 4; \
 543   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 544   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 545   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 546   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 547   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 548
 549 #define EXTRACT_FMT_ADDI_VARS \
 550   /* Instruction fields.  */ \
 551   UINT f_op1; \
 552   UINT f_r1; \
 553   INT f_simm8; \
 554   unsigned int length;
 555 #define EXTRACT_FMT_ADDI_CODE \
 556   length = 2; \
 557   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 558   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 559   f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 560
 561 #define EXTRACT_FMT_ADDV_VARS \
 562   /* Instruction fields.  */ \
 563   UINT f_op1; \
 564   UINT f_r1; \
 565   UINT f_op2; \
 566   UINT f_r2; \
 567   unsigned int length;
 568 #define EXTRACT_FMT_ADDV_CODE \
 569   length = 2; \
 570   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 571   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 572   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 573   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 574
 575 #define EXTRACT_FMT_ADDV3_VARS \
 576   /* Instruction fields.  */ \
 577   UINT f_op1; \
 578   UINT f_r1; \
 579   UINT f_op2; \
 580   UINT f_r2; \
 581   INT f_simm16; \
 582   unsigned int length;
 583 #define EXTRACT_FMT_ADDV3_CODE \
 584   length = 4; \
 585   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 586   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 587   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 588   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 589   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 590
 591 #define EXTRACT_FMT_ADDX_VARS \
 592   /* Instruction fields.  */ \
 593   UINT f_op1; \
 594   UINT f_r1; \
 595   UINT f_op2; \
 596   UINT f_r2; \
 597   unsigned int length;
 598 #define EXTRACT_FMT_ADDX_CODE \
 599   length = 2; \
 600   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 601   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 602   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 603   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 604
 605 #define EXTRACT_FMT_BC8_VARS \
 606   /* Instruction fields.  */ \
 607   UINT f_op1; \
 608   UINT f_r1; \
 609   SI f_disp8; \
 610   unsigned int length;
 611 #define EXTRACT_FMT_BC8_CODE \
 612   length = 2; \
 613   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 614   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 615   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 616
 617 #define EXTRACT_FMT_BC24_VARS \
 618   /* Instruction fields.  */ \
 619   UINT f_op1; \
 620   UINT f_r1; \
 621   SI f_disp24; \
 622   unsigned int length;
 623 #define EXTRACT_FMT_BC24_CODE \
 624   length = 4; \
 625   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 626   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 627   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 628
 629 #define EXTRACT_FMT_BEQ_VARS \
 630   /* Instruction fields.  */ \
 631   UINT f_op1; \
 632   UINT f_r1; \
 633   UINT f_op2; \
 634   UINT f_r2; \
 635   SI f_disp16; \
 636   unsigned int length;
 637 #define EXTRACT_FMT_BEQ_CODE \
 638   length = 4; \
 639   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 640   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 641   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 642   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 643   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 644
 645 #define EXTRACT_FMT_BEQZ_VARS \
 646   /* Instruction fields.  */ \
 647   UINT f_op1; \
 648   UINT f_r1; \
 649   UINT f_op2; \
 650   UINT f_r2; \
 651   SI f_disp16; \
 652   unsigned int length;
 653 #define EXTRACT_FMT_BEQZ_CODE \
 654   length = 4; \
 655   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 656   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 657   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 658   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 659   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 660
 661 #define EXTRACT_FMT_BL8_VARS \
 662   /* Instruction fields.  */ \
 663   UINT f_op1; \
 664   UINT f_r1; \
 665   SI f_disp8; \
 666   unsigned int length;
 667 #define EXTRACT_FMT_BL8_CODE \
 668   length = 2; \
 669   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 670   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 671   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 672
 673 #define EXTRACT_FMT_BL24_VARS \
 674   /* Instruction fields.  */ \
 675   UINT f_op1; \
 676   UINT f_r1; \
 677   SI f_disp24; \
 678   unsigned int length;
 679 #define EXTRACT_FMT_BL24_CODE \
 680   length = 4; \
 681   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 682   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 683   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 684
 685 #define EXTRACT_FMT_BRA8_VARS \
 686   /* Instruction fields.  */ \
 687   UINT f_op1; \
 688   UINT f_r1; \
 689   SI f_disp8; \
 690   unsigned int length;
 691 #define EXTRACT_FMT_BRA8_CODE \
 692   length = 2; \
 693   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 694   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 695   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 696
 697 #define EXTRACT_FMT_BRA24_VARS \
 698   /* Instruction fields.  */ \
 699   UINT f_op1; \
 700   UINT f_r1; \
 701   SI f_disp24; \
 702   unsigned int length;
 703 #define EXTRACT_FMT_BRA24_CODE \
 704   length = 4; \
 705   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 706   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 707   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 708
 709 #define EXTRACT_FMT_CMP_VARS \
 710   /* Instruction fields.  */ \
 711   UINT f_op1; \
 712   UINT f_r1; \
 713   UINT f_op2; \
 714   UINT f_r2; \
 715   unsigned int length;
 716 #define EXTRACT_FMT_CMP_CODE \
 717   length = 2; \
 718   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 719   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 720   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 721   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 722
 723 #define EXTRACT_FMT_CMPI_VARS \
 724   /* Instruction fields.  */ \
 725   UINT f_op1; \
 726   UINT f_r1; \
 727   UINT f_op2; \
 728   UINT f_r2; \
 729   INT f_simm16; \
 730   unsigned int length;
 731 #define EXTRACT_FMT_CMPI_CODE \
 732   length = 4; \
 733   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 734   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 735   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 736   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 737   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 738
 739 #define EXTRACT_FMT_DIV_VARS \
 740   /* Instruction fields.  */ \
 741   UINT f_op1; \
 742   UINT f_r1; \
 743   UINT f_op2; \
 744   UINT f_r2; \
 745   INT f_simm16; \
 746   unsigned int length;
 747 #define EXTRACT_FMT_DIV_CODE \
 748   length = 4; \
 749   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 750   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 751   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 752   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 753   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 754
 755 #define EXTRACT_FMT_JL_VARS \
 756   /* Instruction fields.  */ \
 757   UINT f_op1; \
 758   UINT f_r1; \
 759   UINT f_op2; \
 760   UINT f_r2; \
 761   unsigned int length;
 762 #define EXTRACT_FMT_JL_CODE \
 763   length = 2; \
 764   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 765   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 766   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 767   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 768
 769 #define EXTRACT_FMT_JMP_VARS \
 770   /* Instruction fields.  */ \
 771   UINT f_op1; \
 772   UINT f_r1; \
 773   UINT f_op2; \
 774   UINT f_r2; \
 775   unsigned int length;
 776 #define EXTRACT_FMT_JMP_CODE \
 777   length = 2; \
 778   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 779   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 780   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 781   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 782
 783 #define EXTRACT_FMT_LD_VARS \
 784   /* Instruction fields.  */ \
 785   UINT f_op1; \
 786   UINT f_r1; \
 787   UINT f_op2; \
 788   UINT f_r2; \
 789   unsigned int length;
 790 #define EXTRACT_FMT_LD_CODE \
 791   length = 2; \
 792   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 793   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 794   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 795   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 796
 797 #define EXTRACT_FMT_LD_D_VARS \
 798   /* Instruction fields.  */ \
 799   UINT f_op1; \
 800   UINT f_r1; \
 801   UINT f_op2; \
 802   UINT f_r2; \
 803   INT f_simm16; \
 804   unsigned int length;
 805 #define EXTRACT_FMT_LD_D_CODE \
 806   length = 4; \
 807   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 808   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 809   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 810   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 811   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 812
 813 #define EXTRACT_FMT_LDB_VARS \
 814   /* Instruction fields.  */ \
 815   UINT f_op1; \
 816   UINT f_r1; \
 817   UINT f_op2; \
 818   UINT f_r2; \
 819   unsigned int length;
 820 #define EXTRACT_FMT_LDB_CODE \
 821   length = 2; \
 822   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 823   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 824   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 825   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 826
 827 #define EXTRACT_FMT_LDB_D_VARS \
 828   /* Instruction fields.  */ \
 829   UINT f_op1; \
 830   UINT f_r1; \
 831   UINT f_op2; \
 832   UINT f_r2; \
 833   INT f_simm16; \
 834   unsigned int length;
 835 #define EXTRACT_FMT_LDB_D_CODE \
 836   length = 4; \
 837   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 838   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 839   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 840   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 841   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 842
 843 #define EXTRACT_FMT_LDH_VARS \
 844   /* Instruction fields.  */ \
 845   UINT f_op1; \
 846   UINT f_r1; \
 847   UINT f_op2; \
 848   UINT f_r2; \
 849   unsigned int length;
 850 #define EXTRACT_FMT_LDH_CODE \
 851   length = 2; \
 852   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 853   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 854   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 855   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 856
 857 #define EXTRACT_FMT_LDH_D_VARS \
 858   /* Instruction fields.  */ \
 859   UINT f_op1; \
 860   UINT f_r1; \
 861   UINT f_op2; \
 862   UINT f_r2; \
 863   INT f_simm16; \
 864   unsigned int length;
 865 #define EXTRACT_FMT_LDH_D_CODE \
 866   length = 4; \
 867   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 868   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 869   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 870   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 871   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 872
 873 #define EXTRACT_FMT_LD_PLUS_VARS \
 874   /* Instruction fields.  */ \
 875   UINT f_op1; \
 876   UINT f_r1; \
 877   UINT f_op2; \
 878   UINT f_r2; \
 879   unsigned int length;
 880 #define EXTRACT_FMT_LD_PLUS_CODE \
 881   length = 2; \
 882   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 883   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 884   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 885   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 886
 887 #define EXTRACT_FMT_LD24_VARS \
 888   /* Instruction fields.  */ \
 889   UINT f_op1; \
 890   UINT f_r1; \
 891   UINT f_uimm24; \
 892   unsigned int length;
 893 #define EXTRACT_FMT_LD24_CODE \
 894   length = 4; \
 895   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 896   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 897   f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
 898
 899 #define EXTRACT_FMT_LDI8_VARS \
 900   /* Instruction fields.  */ \
 901   UINT f_op1; \
 902   UINT f_r1; \
 903   INT f_simm8; \
 904   unsigned int length;
 905 #define EXTRACT_FMT_LDI8_CODE \
 906   length = 2; \
 907   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 908   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 909   f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 910
 911 #define EXTRACT_FMT_LDI16_VARS \
 912   /* Instruction fields.  */ \
 913   UINT f_op1; \
 914   UINT f_r1; \
 915   UINT f_op2; \
 916   UINT f_r2; \
 917   INT f_simm16; \
 918   unsigned int length;
 919 #define EXTRACT_FMT_LDI16_CODE \
 920   length = 4; \
 921   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 922   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 923   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 924   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 925   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 926
 927 #define EXTRACT_FMT_LOCK_VARS \
 928   /* Instruction fields.  */ \
 929   UINT f_op1; \
 930   UINT f_r1; \
 931   UINT f_op2; \
 932   UINT f_r2; \
 933   unsigned int length;
 934 #define EXTRACT_FMT_LOCK_CODE \
 935   length = 2; \
 936   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 937   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 938   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 939   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 940
 941 #define EXTRACT_FMT_MACHI_VARS \
 942   /* Instruction fields.  */ \
 943   UINT f_op1; \
 944   UINT f_r1; \
 945   UINT f_op2; \
 946   UINT f_r2; \
 947   unsigned int length;
 948 #define EXTRACT_FMT_MACHI_CODE \
 949   length = 2; \
 950   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 951   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 952   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 953   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 954
 955 #define EXTRACT_FMT_MULHI_VARS \
 956   /* Instruction fields.  */ \
 957   UINT f_op1; \
 958   UINT f_r1; \
 959   UINT f_op2; \
 960   UINT f_r2; \
 961   unsigned int length;
 962 #define EXTRACT_FMT_MULHI_CODE \
 963   length = 2; \
 964   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 965   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 966   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 967   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 968
 969 #define EXTRACT_FMT_MV_VARS \
 970   /* Instruction fields.  */ \
 971   UINT f_op1; \
 972   UINT f_r1; \
 973   UINT f_op2; \
 974   UINT f_r2; \
 975   unsigned int length;
 976 #define EXTRACT_FMT_MV_CODE \
 977   length = 2; \
 978   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 979   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 980   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 981   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 982
 983 #define EXTRACT_FMT_MVFACHI_VARS \
 984   /* Instruction fields.  */ \
 985   UINT f_op1; \
 986   UINT f_r1; \
 987   UINT f_op2; \
 988   UINT f_r2; \
 989   unsigned int length;
 990 #define EXTRACT_FMT_MVFACHI_CODE \
 991   length = 2; \
 992   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 993   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 994   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 995   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 996
 997 #define EXTRACT_FMT_MVFC_VARS \
 998   /* Instruction fields.  */ \
 999   UINT f_op1; \
1000   UINT f_r1; \
1001   UINT f_op2; \
1002   UINT f_r2; \
1003   unsigned int length;
1004 #define EXTRACT_FMT_MVFC_CODE \
1005   length = 2; \
1006   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1007   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1008   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1009   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1010
1011 #define EXTRACT_FMT_MVTACHI_VARS \
1012   /* Instruction fields.  */ \
1013   UINT f_op1; \
1014   UINT f_r1; \
1015   UINT f_op2; \
1016   UINT f_r2; \
1017   unsigned int length;
1018 #define EXTRACT_FMT_MVTACHI_CODE \
1019   length = 2; \
1020   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1021   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1022   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1023   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1024
1025 #define EXTRACT_FMT_MVTC_VARS \
1026   /* Instruction fields.  */ \
1027   UINT f_op1; \
1028   UINT f_r1; \
1029   UINT f_op2; \
1030   UINT f_r2; \
1031   unsigned int length;
1032 #define EXTRACT_FMT_MVTC_CODE \
1033   length = 2; \
1034   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1035   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1036   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1037   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1038
1039 #define EXTRACT_FMT_NOP_VARS \
1040   /* Instruction fields.  */ \
1041   UINT f_op1; \
1042   UINT f_r1; \
1043   UINT f_op2; \
1044   UINT f_r2; \
1045   unsigned int length;
1046 #define EXTRACT_FMT_NOP_CODE \
1047   length = 2; \
1048   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1049   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1050   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1051   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1052
1053 #define EXTRACT_FMT_RAC_VARS \
1054   /* Instruction fields.  */ \
1055   UINT f_op1; \
1056   UINT f_r1; \
1057   UINT f_op2; \
1058   UINT f_r2; \
1059   unsigned int length;
1060 #define EXTRACT_FMT_RAC_CODE \
1061   length = 2; \
1062   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1063   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1064   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1065   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1066
1067 #define EXTRACT_FMT_RTE_VARS \
1068   /* Instruction fields.  */ \
1069   UINT f_op1; \
1070   UINT f_r1; \
1071   UINT f_op2; \
1072   UINT f_r2; \
1073   unsigned int length;
1074 #define EXTRACT_FMT_RTE_CODE \
1075   length = 2; \
1076   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1077   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1078   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1079   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1080
1081 #define EXTRACT_FMT_SETH_VARS \
1082   /* Instruction fields.  */ \
1083   UINT f_op1; \
1084   UINT f_r1; \
1085   UINT f_op2; \
1086   UINT f_r2; \
1087   UINT f_hi16; \
1088   unsigned int length;
1089 #define EXTRACT_FMT_SETH_CODE \
1090   length = 4; \
1091   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1092   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1093   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1094   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1095   f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
1096
1097 #define EXTRACT_FMT_SLL3_VARS \
1098   /* Instruction fields.  */ \
1099   UINT f_op1; \
1100   UINT f_r1; \
1101   UINT f_op2; \
1102   UINT f_r2; \
1103   INT f_simm16; \
1104   unsigned int length;
1105 #define EXTRACT_FMT_SLL3_CODE \
1106   length = 4; \
1107   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1108   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1109   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1110   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1111   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1112
1113 #define EXTRACT_FMT_SLLI_VARS \
1114   /* Instruction fields.  */ \
1115   UINT f_op1; \
1116   UINT f_r1; \
1117   UINT f_shift_op2; \
1118   UINT f_uimm5; \
1119   unsigned int length;
1120 #define EXTRACT_FMT_SLLI_CODE \
1121   length = 2; \
1122   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1123   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1124   f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
1125   f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
1126
1127 #define EXTRACT_FMT_ST_VARS \
1128   /* Instruction fields.  */ \
1129   UINT f_op1; \
1130   UINT f_r1; \
1131   UINT f_op2; \
1132   UINT f_r2; \
1133   unsigned int length;
1134 #define EXTRACT_FMT_ST_CODE \
1135   length = 2; \
1136   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1137   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1138   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1139   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1140
1141 #define EXTRACT_FMT_ST_D_VARS \
1142   /* Instruction fields.  */ \
1143   UINT f_op1; \
1144   UINT f_r1; \
1145   UINT f_op2; \
1146   UINT f_r2; \
1147   INT f_simm16; \
1148   unsigned int length;
1149 #define EXTRACT_FMT_ST_D_CODE \
1150   length = 4; \
1151   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1152   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1153   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1154   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1155   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1156
1157 #define EXTRACT_FMT_STB_VARS \
1158   /* Instruction fields.  */ \
1159   UINT f_op1; \
1160   UINT f_r1; \
1161   UINT f_op2; \
1162   UINT f_r2; \
1163   unsigned int length;
1164 #define EXTRACT_FMT_STB_CODE \
1165   length = 2; \
1166   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1167   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1168   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1169   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1170
1171 #define EXTRACT_FMT_STB_D_VARS \
1172   /* Instruction fields.  */ \
1173   UINT f_op1; \
1174   UINT f_r1; \
1175   UINT f_op2; \
1176   UINT f_r2; \
1177   INT f_simm16; \
1178   unsigned int length;
1179 #define EXTRACT_FMT_STB_D_CODE \
1180   length = 4; \
1181   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1182   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1183   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1184   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1185   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1186
1187 #define EXTRACT_FMT_STH_VARS \
1188   /* Instruction fields.  */ \
1189   UINT f_op1; \
1190   UINT f_r1; \
1191   UINT f_op2; \
1192   UINT f_r2; \
1193   unsigned int length;
1194 #define EXTRACT_FMT_STH_CODE \
1195   length = 2; \
1196   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1197   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1198   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1199   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1200
1201 #define EXTRACT_FMT_STH_D_VARS \
1202   /* Instruction fields.  */ \
1203   UINT f_op1; \
1204   UINT f_r1; \
1205   UINT f_op2; \
1206   UINT f_r2; \
1207   INT f_simm16; \
1208   unsigned int length;
1209 #define EXTRACT_FMT_STH_D_CODE \
1210   length = 4; \
1211   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1212   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1213   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1214   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1215   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1216
1217 #define EXTRACT_FMT_ST_PLUS_VARS \
1218   /* Instruction fields.  */ \
1219   UINT f_op1; \
1220   UINT f_r1; \
1221   UINT f_op2; \
1222   UINT f_r2; \
1223   unsigned int length;
1224 #define EXTRACT_FMT_ST_PLUS_CODE \
1225   length = 2; \
1226   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1227   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1228   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1229   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1230
1231 #define EXTRACT_FMT_TRAP_VARS \
1232   /* Instruction fields.  */ \
1233   UINT f_op1; \
1234   UINT f_r1; \
1235   UINT f_op2; \
1236   UINT f_uimm4; \
1237   unsigned int length;
1238 #define EXTRACT_FMT_TRAP_CODE \
1239   length = 2; \
1240   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1241   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1242   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1243   f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
1244
1245 #define EXTRACT_FMT_UNLOCK_VARS \
1246   /* Instruction fields.  */ \
1247   UINT f_op1; \
1248   UINT f_r1; \
1249   UINT f_op2; \
1250   UINT f_r2; \
1251   unsigned int length;
1252 #define EXTRACT_FMT_UNLOCK_CODE \
1253   length = 2; \
1254   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1255   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1256   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1257   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1258
1259 /* Collection of various things for the trace handler to use.  */
1260
1261 typedef struct trace_record {
1262   PCADDR pc;
1263   /* FIXME:wip */
1264 } TRACE_RECORD;
1265
1266 #endif /* CPU_M32RBF_H */