sim/m32r/cpux.h

   1 /* CPU family header for m32rx.
   2
   3 This file is machine generated with CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_M32RX_H
  26 #define CPU_M32RX_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 2
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 2
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[16];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* control registers */
  48   USI h_cr[7];
  49 #define GET_H_CR(a1) CPU (h_cr)[a1]
  50 #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
  51   /* accumulator */
  52   DI h_accum;
  53 #define GET_H_ACCUM() CPU (h_accum)
  54 #define SET_H_ACCUM(x) (CPU (h_accum) = (x))
  55 /* start-sanitize-m32rx */
  56   /* accumulators */
  57   DI h_accums[2];
  58 /* end-sanitize-m32rx */
  59 #define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
  60 #define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
  61 /* start-sanitize-m32rx */
  62   /* abort flag */
  63   UBI h_abort;
  64 /* end-sanitize-m32rx */
  65 #define GET_H_ABORT() CPU (h_abort)
  66 #define SET_H_ABORT(x) (CPU (h_abort) = (x))
  67   /* condition bit */
  68   UBI h_cond;
  69 #define GET_H_COND() CPU (h_cond)
  70 #define SET_H_COND(x) (CPU (h_cond) = (x))
  71   /* sm */
  72   UBI h_sm;
  73 #define GET_H_SM() CPU (h_sm)
  74 #define SET_H_SM(x) (CPU (h_sm) = (x))
  75   /* bsm */
  76   UBI h_bsm;
  77 #define GET_H_BSM() CPU (h_bsm)
  78 #define SET_H_BSM(x) (CPU (h_bsm) = (x))
  79   /* ie */
  80   UBI h_ie;
  81 #define GET_H_IE() CPU (h_ie)
  82 #define SET_H_IE(x) (CPU (h_ie) = (x))
  83   /* bie */
  84   UBI h_bie;
  85 #define GET_H_BIE() CPU (h_bie)
  86 #define SET_H_BIE(x) (CPU (h_bie) = (x))
  87   /* bcond */
  88   UBI h_bcond;
  89 #define GET_H_BCOND() CPU (h_bcond)
  90 #define SET_H_BCOND(x) (CPU (h_bcond) = (x))
  91   /* bpc */
  92   SI h_bpc;
  93 #define GET_H_BPC() CPU (h_bpc)
  94 #define SET_H_BPC(x) (CPU (h_bpc) = (x))
  95   /* lock */
  96   UBI h_lock;
  97 #define GET_H_LOCK() CPU (h_lock)
  98 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
  99   } hardware;
 100 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
 101   /* CPU profiling state information.  */
 102   struct {
 103   /* general registers */
 104   unsigned long h_gr;
 105   } profile;
 106 #define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
 107 } M32RX_CPU_DATA;
 108
 109 USI m32rx_h_pc_get (SIM_CPU *);
 110 void m32rx_h_pc_set (SIM_CPU *, USI);
 111 SI m32rx_h_gr_get (SIM_CPU *, UINT);
 112 void m32rx_h_gr_set (SIM_CPU *, UINT, SI);
 113 USI m32rx_h_cr_get (SIM_CPU *, UINT);
 114 void m32rx_h_cr_set (SIM_CPU *, UINT, USI);
 115 DI m32rx_h_accum_get (SIM_CPU *);
 116 void m32rx_h_accum_set (SIM_CPU *, DI);
 117 DI m32rx_h_accums_get (SIM_CPU *, UINT);
 118 void m32rx_h_accums_set (SIM_CPU *, UINT, DI);
 119 UBI m32rx_h_abort_get (SIM_CPU *);
 120 void m32rx_h_abort_set (SIM_CPU *, UBI);
 121 UBI m32rx_h_cond_get (SIM_CPU *);
 122 void m32rx_h_cond_set (SIM_CPU *, UBI);
 123 UBI m32rx_h_sm_get (SIM_CPU *);
 124 void m32rx_h_sm_set (SIM_CPU *, UBI);
 125 UBI m32rx_h_bsm_get (SIM_CPU *);
 126 void m32rx_h_bsm_set (SIM_CPU *, UBI);
 127 UBI m32rx_h_ie_get (SIM_CPU *);
 128 void m32rx_h_ie_set (SIM_CPU *, UBI);
 129 UBI m32rx_h_bie_get (SIM_CPU *);
 130 void m32rx_h_bie_set (SIM_CPU *, UBI);
 131 UBI m32rx_h_bcond_get (SIM_CPU *);
 132 void m32rx_h_bcond_set (SIM_CPU *, UBI);
 133 SI m32rx_h_bpc_get (SIM_CPU *);
 134 void m32rx_h_bpc_set (SIM_CPU *, SI);
 135 UBI m32rx_h_lock_get (SIM_CPU *);
 136 void m32rx_h_lock_set (SIM_CPU *, UBI);
 137 extern DECODE *m32rx_decode (SIM_CPU *, PCADDR, insn_t);
 138
 139 /* The ARGBUF struct.  */
 140 struct argbuf {
 141   /* These are the baseclass definitions.  */
 142   unsigned int length;
 143   PCADDR addr;
 144   const struct cgen_insn *opcode;
 145 #if ! defined (SCACHE_P)
 146   insn_t insn;
 147 #endif
 148   /* cpu specific data follows */
 149   union {
 150     struct { /* e.g. add $dr,$sr */
 151       UINT f_r1;
 152       UINT f_r2;
 153     } fmt_0_add;
 154     struct { /* e.g. add3 $dr,$sr,#$slo16 */
 155       UINT f_r1;
 156       UINT f_r2;
 157       HI f_simm16;
 158     } fmt_1_add3;
 159     struct { /* e.g. and3 $dr,$sr,#$uimm16 */
 160       UINT f_r1;
 161       UINT f_r2;
 162       USI f_uimm16;
 163     } fmt_2_and3;
 164     struct { /* e.g. or3 $dr,$sr,#$ulo16 */
 165       UINT f_r1;
 166       UINT f_r2;
 167       UHI f_uimm16;
 168     } fmt_3_or3;
 169     struct { /* e.g. addi $dr,#$simm8 */
 170       UINT f_r1;
 171       SI f_simm8;
 172     } fmt_4_addi;
 173     struct { /* e.g. addv $dr,$sr */
 174       UINT f_r1;
 175       UINT f_r2;
 176     } fmt_5_addv;
 177     struct { /* e.g. addv3 $dr,$sr,#$simm16 */
 178       UINT f_r1;
 179       UINT f_r2;
 180       SI f_simm16;
 181     } fmt_6_addv3;
 182     struct { /* e.g. addx $dr,$sr */
 183       UINT f_r1;
 184       UINT f_r2;
 185     } fmt_7_addx;
 186     struct { /* e.g. bc $disp8 */
 187       IADDR f_disp8;
 188     } fmt_8_bc8;
 189     struct { /* e.g. bc $disp24 */
 190       IADDR f_disp24;
 191     } fmt_9_bc24;
 192     struct { /* e.g. beq $src1,$src2,$disp16 */
 193       UINT f_r1;
 194       UINT f_r2;
 195       IADDR f_disp16;
 196     } fmt_10_beq;
 197     struct { /* e.g. beqz $src2,$disp16 */
 198       UINT f_r2;
 199       IADDR f_disp16;
 200     } fmt_11_beqz;
 201     struct { /* e.g. bl $disp8 */
 202       IADDR f_disp8;
 203     } fmt_12_bl8;
 204     struct { /* e.g. bl $disp24 */
 205       IADDR f_disp24;
 206     } fmt_13_bl24;
 207     struct { /* e.g. bcl $disp8 */
 208       IADDR f_disp8;
 209     } fmt_14_bcl8;
 210     struct { /* e.g. bcl $disp24 */
 211       IADDR f_disp24;
 212     } fmt_15_bcl24;
 213     struct { /* e.g. bra $disp8 */
 214       IADDR f_disp8;
 215     } fmt_16_bra8;
 216     struct { /* e.g. bra $disp24 */
 217       IADDR f_disp24;
 218     } fmt_17_bra24;
 219     struct { /* e.g. cmp $src1,$src2 */
 220       UINT f_r1;
 221       UINT f_r2;
 222     } fmt_18_cmp;
 223     struct { /* e.g. cmpi $src2,#$simm16 */
 224       UINT f_r2;
 225       SI f_simm16;
 226     } fmt_19_cmpi;
 227     struct { /* e.g. cmpui $src2,#$uimm16 */
 228       UINT f_r2;
 229       USI f_uimm16;
 230     } fmt_20_cmpui;
 231     struct { /* e.g. cmpz $src2 */
 232       UINT f_r2;
 233     } fmt_21_cmpz;
 234     struct { /* e.g. div $dr,$sr */
 235       UINT f_r1;
 236       UINT f_r2;
 237     } fmt_22_div;
 238     struct { /* e.g. jc $sr */
 239       UINT f_r2;
 240     } fmt_23_jc;
 241     struct { /* e.g. jl $sr */
 242       UINT f_r2;
 243     } fmt_24_jl;
 244     struct { /* e.g. jmp $sr */
 245       UINT f_r2;
 246     } fmt_25_jmp;
 247     struct { /* e.g. ld $dr,@$sr */
 248       UINT f_r1;
 249       UINT f_r2;
 250     } fmt_26_ld;
 251     struct { /* e.g. ld $dr,@($slo16,$sr) */
 252       UINT f_r1;
 253       UINT f_r2;
 254       HI f_simm16;
 255     } fmt_27_ld_d;
 256     struct { /* e.g. ldb $dr,@$sr */
 257       UINT f_r1;
 258       UINT f_r2;
 259     } fmt_28_ldb;
 260     struct { /* e.g. ldb $dr,@($slo16,$sr) */
 261       UINT f_r1;
 262       UINT f_r2;
 263       HI f_simm16;
 264     } fmt_29_ldb_d;
 265     struct { /* e.g. ldh $dr,@$sr */
 266       UINT f_r1;
 267       UINT f_r2;
 268     } fmt_30_ldh;
 269     struct { /* e.g. ldh $dr,@($slo16,$sr) */
 270       UINT f_r1;
 271       UINT f_r2;
 272       HI f_simm16;
 273     } fmt_31_ldh_d;
 274     struct { /* e.g. ld $dr,@$sr+ */
 275       UINT f_r1;
 276       UINT f_r2;
 277     } fmt_32_ld_plus;
 278     struct { /* e.g. ld24 $dr,#$uimm24 */
 279       UINT f_r1;
 280       ADDR f_uimm24;
 281     } fmt_33_ld24;
 282     struct { /* e.g. ldi $dr,#$simm8 */
 283       UINT f_r1;
 284       SI f_simm8;
 285     } fmt_34_ldi8;
 286     struct { /* e.g. ldi $dr,$slo16 */
 287       UINT f_r1;
 288       HI f_simm16;
 289     } fmt_35_ldi16;
 290     struct { /* e.g. lock $dr,@$sr */
 291       UINT f_r1;
 292       UINT f_r2;
 293     } fmt_36_lock;
 294     struct { /* e.g. machi $src1,$src2,$acc */
 295       UINT f_r1;
 296       UINT f_acc;
 297       UINT f_r2;
 298     } fmt_37_machi_a;
 299     struct { /* e.g. mulhi $src1,$src2,$acc */
 300       UINT f_r1;
 301       UINT f_acc;
 302       UINT f_r2;
 303     } fmt_38_mulhi_a;
 304     struct { /* e.g. mv $dr,$sr */
 305       UINT f_r1;
 306       UINT f_r2;
 307     } fmt_39_mv;
 308     struct { /* e.g. mvfachi $dr,$accs */
 309       UINT f_r1;
 310       UINT f_accs;
 311     } fmt_40_mvfachi_a;
 312     struct { /* e.g. mvfc $dr,$scr */
 313       UINT f_r1;
 314       UINT f_r2;
 315     } fmt_41_mvfc;
 316     struct { /* e.g. mvtachi $src1,$accs */
 317       UINT f_r1;
 318       UINT f_accs;
 319     } fmt_42_mvtachi_a;
 320     struct { /* e.g. mvtc $sr,$dcr */
 321       UINT f_r1;
 322       UINT f_r2;
 323     } fmt_43_mvtc;
 324     struct { /* e.g. nop */
 325       int empty;
 326     } fmt_44_nop;
 327     struct { /* e.g. rac $accd,$accs,#$imm1 */
 328       UINT f_accd;
 329       UINT f_accs;
 330       USI f_imm1;
 331     } fmt_45_rac_dsi;
 332     struct { /* e.g. rte */
 333       int empty;
 334     } fmt_46_rte;
 335     struct { /* e.g. seth $dr,#$hi16 */
 336       UINT f_r1;
 337       UHI f_hi16;
 338     } fmt_47_seth;
 339     struct { /* e.g. sll3 $dr,$sr,#$simm16 */
 340       UINT f_r1;
 341       UINT f_r2;
 342       SI f_simm16;
 343     } fmt_48_sll3;
 344     struct { /* e.g. slli $dr,#$uimm5 */
 345       UINT f_r1;
 346       USI f_uimm5;
 347     } fmt_49_slli;
 348     struct { /* e.g. st $src1,@$src2 */
 349       UINT f_r1;
 350       UINT f_r2;
 351     } fmt_50_st;
 352     struct { /* e.g. st $src1,@($slo16,$src2) */
 353       UINT f_r1;
 354       UINT f_r2;
 355       HI f_simm16;
 356     } fmt_51_st_d;
 357     struct { /* e.g. stb $src1,@$src2 */
 358       UINT f_r1;
 359       UINT f_r2;
 360     } fmt_52_stb;
 361     struct { /* e.g. stb $src1,@($slo16,$src2) */
 362       UINT f_r1;
 363       UINT f_r2;
 364       HI f_simm16;
 365     } fmt_53_stb_d;
 366     struct { /* e.g. sth $src1,@$src2 */
 367       UINT f_r1;
 368       UINT f_r2;
 369     } fmt_54_sth;
 370     struct { /* e.g. sth $src1,@($slo16,$src2) */
 371       UINT f_r1;
 372       UINT f_r2;
 373       HI f_simm16;
 374     } fmt_55_sth_d;
 375     struct { /* e.g. st $src1,@+$src2 */
 376       UINT f_r1;
 377       UINT f_r2;
 378     } fmt_56_st_plus;
 379     struct { /* e.g. trap #$uimm4 */
 380       USI f_uimm4;
 381     } fmt_57_trap;
 382     struct { /* e.g. unlock $src1,@$src2 */
 383       UINT f_r1;
 384       UINT f_r2;
 385     } fmt_58_unlock;
 386     struct { /* e.g. satb $dr,$sr */
 387       UINT f_r1;
 388       UINT f_r2;
 389     } fmt_59_satb;
 390     struct { /* e.g. sat $dr,$sr */
 391       UINT f_r1;
 392       UINT f_r2;
 393     } fmt_60_sat;
 394     struct { /* e.g. sadd */
 395       int empty;
 396     } fmt_61_sadd;
 397     struct { /* e.g. macwu1 $src1,$src2 */
 398       UINT f_r1;
 399       UINT f_r2;
 400     } fmt_62_macwu1;
 401     struct { /* e.g. msblo $src1,$src2 */
 402       UINT f_r1;
 403       UINT f_r2;
 404     } fmt_63_msblo;
 405     struct { /* e.g. mulwu1 $src1,$src2 */
 406       UINT f_r1;
 407       UINT f_r2;
 408     } fmt_64_mulwu1;
 409     struct { /* e.g. sc */
 410       int empty;
 411     } fmt_65_sc;
 412   } fields;
 413 #if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
 414   unsigned long h_gr_get;
 415   unsigned long h_gr_set;
 416 #endif
 417 };
 418
 419 /* A cached insn.
 420    This is currently also used in the non-scache case.  In this situation we
 421    assume the cache size is 1, and do a few things a little differently.  */
 422 /* FIXME: non-scache version to be redone.  */
 423
 424 struct scache {
 425   IADDR next;
 426   union {
 427 #if ! WITH_SEM_SWITCH_FULL
 428     SEMANTIC_FN *sem_fn;
 429 #endif
 430 #if ! WITH_SEM_SWITCH_FAST
 431     SEMANTIC_FN *sem_fast_fn;
 432 #endif
 433 #if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
 434 #ifdef __GNUC__
 435     void *sem_case;
 436 #else
 437     int sem_case;
 438 #endif
 439 #endif
 440   } semantic;
 441   struct argbuf argbuf;
 442 };
 443
 444 /* Macros to simplify extraction, reading and semantic code.
 445    These define and assign the local vars that contain the insn's fields.  */
 446
 447 #define EXTRACT_FMT_0_ADD_VARS \
 448   /* Instruction fields.  */ \
 449   UINT f_op1; \
 450   UINT f_r1; \
 451   UINT f_op2; \
 452   UINT f_r2; \
 453   unsigned int length;
 454 #define EXTRACT_FMT_0_ADD_CODE \
 455   length = 2; \
 456   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 457   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 458   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 459   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 460
 461 #define EXTRACT_FMT_1_ADD3_VARS \
 462   /* Instruction fields.  */ \
 463   UINT f_op1; \
 464   UINT f_r1; \
 465   UINT f_op2; \
 466   UINT f_r2; \
 467   int f_simm16; \
 468   unsigned int length;
 469 #define EXTRACT_FMT_1_ADD3_CODE \
 470   length = 4; \
 471   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 472   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 473   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 474   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 475   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 476
 477 #define EXTRACT_FMT_2_AND3_VARS \
 478   /* Instruction fields.  */ \
 479   UINT f_op1; \
 480   UINT f_r1; \
 481   UINT f_op2; \
 482   UINT f_r2; \
 483   UINT f_uimm16; \
 484   unsigned int length;
 485 #define EXTRACT_FMT_2_AND3_CODE \
 486   length = 4; \
 487   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 488   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 489   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 490   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 491   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 492
 493 #define EXTRACT_FMT_3_OR3_VARS \
 494   /* Instruction fields.  */ \
 495   UINT f_op1; \
 496   UINT f_r1; \
 497   UINT f_op2; \
 498   UINT f_r2; \
 499   UINT f_uimm16; \
 500   unsigned int length;
 501 #define EXTRACT_FMT_3_OR3_CODE \
 502   length = 4; \
 503   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 504   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 505   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 506   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 507   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 508
 509 #define EXTRACT_FMT_4_ADDI_VARS \
 510   /* Instruction fields.  */ \
 511   UINT f_op1; \
 512   UINT f_r1; \
 513   int f_simm8; \
 514   unsigned int length;
 515 #define EXTRACT_FMT_4_ADDI_CODE \
 516   length = 2; \
 517   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 518   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 519   f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
 520
 521 #define EXTRACT_FMT_5_ADDV_VARS \
 522   /* Instruction fields.  */ \
 523   UINT f_op1; \
 524   UINT f_r1; \
 525   UINT f_op2; \
 526   UINT f_r2; \
 527   unsigned int length;
 528 #define EXTRACT_FMT_5_ADDV_CODE \
 529   length = 2; \
 530   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 531   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 532   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 533   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 534
 535 #define EXTRACT_FMT_6_ADDV3_VARS \
 536   /* Instruction fields.  */ \
 537   UINT f_op1; \
 538   UINT f_r1; \
 539   UINT f_op2; \
 540   UINT f_r2; \
 541   int f_simm16; \
 542   unsigned int length;
 543 #define EXTRACT_FMT_6_ADDV3_CODE \
 544   length = 4; \
 545   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 546   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 547   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 548   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 549   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 550
 551 #define EXTRACT_FMT_7_ADDX_VARS \
 552   /* Instruction fields.  */ \
 553   UINT f_op1; \
 554   UINT f_r1; \
 555   UINT f_op2; \
 556   UINT f_r2; \
 557   unsigned int length;
 558 #define EXTRACT_FMT_7_ADDX_CODE \
 559   length = 2; \
 560   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 561   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 562   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 563   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 564
 565 #define EXTRACT_FMT_8_BC8_VARS \
 566   /* Instruction fields.  */ \
 567   UINT f_op1; \
 568   UINT f_r1; \
 569   int f_disp8; \
 570   unsigned int length;
 571 #define EXTRACT_FMT_8_BC8_CODE \
 572   length = 2; \
 573   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 574   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 575   f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \
 576
 577 #define EXTRACT_FMT_9_BC24_VARS \
 578   /* Instruction fields.  */ \
 579   UINT f_op1; \
 580   UINT f_r1; \
 581   int f_disp24; \
 582   unsigned int length;
 583 #define EXTRACT_FMT_9_BC24_CODE \
 584   length = 4; \
 585   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 586   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 587   f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \
 588
 589 #define EXTRACT_FMT_10_BEQ_VARS \
 590   /* Instruction fields.  */ \
 591   UINT f_op1; \
 592   UINT f_r1; \
 593   UINT f_op2; \
 594   UINT f_r2; \
 595   int f_disp16; \
 596   unsigned int length;
 597 #define EXTRACT_FMT_10_BEQ_CODE \
 598   length = 4; \
 599   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 600   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 601   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 602   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 603   f_disp16 = ((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2)); \
 604
 605 #define EXTRACT_FMT_11_BEQZ_VARS \
 606   /* Instruction fields.  */ \
 607   UINT f_op1; \
 608   UINT f_r1; \
 609   UINT f_op2; \
 610   UINT f_r2; \
 611   int f_disp16; \
 612   unsigned int length;
 613 #define EXTRACT_FMT_11_BEQZ_CODE \
 614   length = 4; \
 615   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 616   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 617   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 618   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 619   f_disp16 = ((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2)); \
 620
 621 #define EXTRACT_FMT_12_BL8_VARS \
 622   /* Instruction fields.  */ \
 623   UINT f_op1; \
 624   UINT f_r1; \
 625   int f_disp8; \
 626   unsigned int length;
 627 #define EXTRACT_FMT_12_BL8_CODE \
 628   length = 2; \
 629   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 630   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 631   f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \
 632
 633 #define EXTRACT_FMT_13_BL24_VARS \
 634   /* Instruction fields.  */ \
 635   UINT f_op1; \
 636   UINT f_r1; \
 637   int f_disp24; \
 638   unsigned int length;
 639 #define EXTRACT_FMT_13_BL24_CODE \
 640   length = 4; \
 641   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 642   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 643   f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \
 644
 645 #define EXTRACT_FMT_14_BCL8_VARS \
 646   /* Instruction fields.  */ \
 647   UINT f_op1; \
 648   UINT f_r1; \
 649   int f_disp8; \
 650   unsigned int length;
 651 #define EXTRACT_FMT_14_BCL8_CODE \
 652   length = 2; \
 653   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 654   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 655   f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \
 656
 657 #define EXTRACT_FMT_15_BCL24_VARS \
 658   /* Instruction fields.  */ \
 659   UINT f_op1; \
 660   UINT f_r1; \
 661   int f_disp24; \
 662   unsigned int length;
 663 #define EXTRACT_FMT_15_BCL24_CODE \
 664   length = 4; \
 665   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 666   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 667   f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \
 668
 669 #define EXTRACT_FMT_16_BRA8_VARS \
 670   /* Instruction fields.  */ \
 671   UINT f_op1; \
 672   UINT f_r1; \
 673   int f_disp8; \
 674   unsigned int length;
 675 #define EXTRACT_FMT_16_BRA8_CODE \
 676   length = 2; \
 677   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 678   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 679   f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \
 680
 681 #define EXTRACT_FMT_17_BRA24_VARS \
 682   /* Instruction fields.  */ \
 683   UINT f_op1; \
 684   UINT f_r1; \
 685   int f_disp24; \
 686   unsigned int length;
 687 #define EXTRACT_FMT_17_BRA24_CODE \
 688   length = 4; \
 689   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 690   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 691   f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \
 692
 693 #define EXTRACT_FMT_18_CMP_VARS \
 694   /* Instruction fields.  */ \
 695   UINT f_op1; \
 696   UINT f_r1; \
 697   UINT f_op2; \
 698   UINT f_r2; \
 699   unsigned int length;
 700 #define EXTRACT_FMT_18_CMP_CODE \
 701   length = 2; \
 702   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 703   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 704   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 705   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 706
 707 #define EXTRACT_FMT_19_CMPI_VARS \
 708   /* Instruction fields.  */ \
 709   UINT f_op1; \
 710   UINT f_r1; \
 711   UINT f_op2; \
 712   UINT f_r2; \
 713   int f_simm16; \
 714   unsigned int length;
 715 #define EXTRACT_FMT_19_CMPI_CODE \
 716   length = 4; \
 717   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 718   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 719   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 720   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 721   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 722
 723 #define EXTRACT_FMT_20_CMPUI_VARS \
 724   /* Instruction fields.  */ \
 725   UINT f_op1; \
 726   UINT f_r1; \
 727   UINT f_op2; \
 728   UINT f_r2; \
 729   UINT f_uimm16; \
 730   unsigned int length;
 731 #define EXTRACT_FMT_20_CMPUI_CODE \
 732   length = 4; \
 733   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 734   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 735   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 736   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 737   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 738
 739 #define EXTRACT_FMT_21_CMPZ_VARS \
 740   /* Instruction fields.  */ \
 741   UINT f_op1; \
 742   UINT f_r1; \
 743   UINT f_op2; \
 744   UINT f_r2; \
 745   unsigned int length;
 746 #define EXTRACT_FMT_21_CMPZ_CODE \
 747   length = 2; \
 748   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 749   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 750   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 751   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 752
 753 #define EXTRACT_FMT_22_DIV_VARS \
 754   /* Instruction fields.  */ \
 755   UINT f_op1; \
 756   UINT f_r1; \
 757   UINT f_op2; \
 758   UINT f_r2; \
 759   int f_simm16; \
 760   unsigned int length;
 761 #define EXTRACT_FMT_22_DIV_CODE \
 762   length = 4; \
 763   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 764   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 765   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 766   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 767   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 768
 769 #define EXTRACT_FMT_23_JC_VARS \
 770   /* Instruction fields.  */ \
 771   UINT f_op1; \
 772   UINT f_r1; \
 773   UINT f_op2; \
 774   UINT f_r2; \
 775   unsigned int length;
 776 #define EXTRACT_FMT_23_JC_CODE \
 777   length = 2; \
 778   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 779   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 780   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 781   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 782
 783 #define EXTRACT_FMT_24_JL_VARS \
 784   /* Instruction fields.  */ \
 785   UINT f_op1; \
 786   UINT f_r1; \
 787   UINT f_op2; \
 788   UINT f_r2; \
 789   unsigned int length;
 790 #define EXTRACT_FMT_24_JL_CODE \
 791   length = 2; \
 792   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 793   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 794   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 795   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 796
 797 #define EXTRACT_FMT_25_JMP_VARS \
 798   /* Instruction fields.  */ \
 799   UINT f_op1; \
 800   UINT f_r1; \
 801   UINT f_op2; \
 802   UINT f_r2; \
 803   unsigned int length;
 804 #define EXTRACT_FMT_25_JMP_CODE \
 805   length = 2; \
 806   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 807   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 808   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 809   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 810
 811 #define EXTRACT_FMT_26_LD_VARS \
 812   /* Instruction fields.  */ \
 813   UINT f_op1; \
 814   UINT f_r1; \
 815   UINT f_op2; \
 816   UINT f_r2; \
 817   unsigned int length;
 818 #define EXTRACT_FMT_26_LD_CODE \
 819   length = 2; \
 820   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 821   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 822   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 823   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 824
 825 #define EXTRACT_FMT_27_LD_D_VARS \
 826   /* Instruction fields.  */ \
 827   UINT f_op1; \
 828   UINT f_r1; \
 829   UINT f_op2; \
 830   UINT f_r2; \
 831   int f_simm16; \
 832   unsigned int length;
 833 #define EXTRACT_FMT_27_LD_D_CODE \
 834   length = 4; \
 835   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 836   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 837   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 838   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 839   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 840
 841 #define EXTRACT_FMT_28_LDB_VARS \
 842   /* Instruction fields.  */ \
 843   UINT f_op1; \
 844   UINT f_r1; \
 845   UINT f_op2; \
 846   UINT f_r2; \
 847   unsigned int length;
 848 #define EXTRACT_FMT_28_LDB_CODE \
 849   length = 2; \
 850   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 851   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 852   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 853   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 854
 855 #define EXTRACT_FMT_29_LDB_D_VARS \
 856   /* Instruction fields.  */ \
 857   UINT f_op1; \
 858   UINT f_r1; \
 859   UINT f_op2; \
 860   UINT f_r2; \
 861   int f_simm16; \
 862   unsigned int length;
 863 #define EXTRACT_FMT_29_LDB_D_CODE \
 864   length = 4; \
 865   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 866   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 867   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 868   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 869   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 870
 871 #define EXTRACT_FMT_30_LDH_VARS \
 872   /* Instruction fields.  */ \
 873   UINT f_op1; \
 874   UINT f_r1; \
 875   UINT f_op2; \
 876   UINT f_r2; \
 877   unsigned int length;
 878 #define EXTRACT_FMT_30_LDH_CODE \
 879   length = 2; \
 880   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 881   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 882   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 883   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 884
 885 #define EXTRACT_FMT_31_LDH_D_VARS \
 886   /* Instruction fields.  */ \
 887   UINT f_op1; \
 888   UINT f_r1; \
 889   UINT f_op2; \
 890   UINT f_r2; \
 891   int f_simm16; \
 892   unsigned int length;
 893 #define EXTRACT_FMT_31_LDH_D_CODE \
 894   length = 4; \
 895   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 896   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 897   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 898   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 899   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 900
 901 #define EXTRACT_FMT_32_LD_PLUS_VARS \
 902   /* Instruction fields.  */ \
 903   UINT f_op1; \
 904   UINT f_r1; \
 905   UINT f_op2; \
 906   UINT f_r2; \
 907   unsigned int length;
 908 #define EXTRACT_FMT_32_LD_PLUS_CODE \
 909   length = 2; \
 910   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 911   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 912   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 913   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 914
 915 #define EXTRACT_FMT_33_LD24_VARS \
 916   /* Instruction fields.  */ \
 917   UINT f_op1; \
 918   UINT f_r1; \
 919   UINT f_uimm24; \
 920   unsigned int length;
 921 #define EXTRACT_FMT_33_LD24_CODE \
 922   length = 4; \
 923   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 924   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 925   f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
 926
 927 #define EXTRACT_FMT_34_LDI8_VARS \
 928   /* Instruction fields.  */ \
 929   UINT f_op1; \
 930   UINT f_r1; \
 931   int f_simm8; \
 932   unsigned int length;
 933 #define EXTRACT_FMT_34_LDI8_CODE \
 934   length = 2; \
 935   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 936   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 937   f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
 938
 939 #define EXTRACT_FMT_35_LDI16_VARS \
 940   /* Instruction fields.  */ \
 941   UINT f_op1; \
 942   UINT f_r1; \
 943   UINT f_op2; \
 944   UINT f_r2; \
 945   int f_simm16; \
 946   unsigned int length;
 947 #define EXTRACT_FMT_35_LDI16_CODE \
 948   length = 4; \
 949   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 950   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 951   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 952   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 953   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 954
 955 #define EXTRACT_FMT_36_LOCK_VARS \
 956   /* Instruction fields.  */ \
 957   UINT f_op1; \
 958   UINT f_r1; \
 959   UINT f_op2; \
 960   UINT f_r2; \
 961   unsigned int length;
 962 #define EXTRACT_FMT_36_LOCK_CODE \
 963   length = 2; \
 964   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 965   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 966   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 967   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 968
 969 #define EXTRACT_FMT_37_MACHI_A_VARS \
 970   /* Instruction fields.  */ \
 971   UINT f_op1; \
 972   UINT f_r1; \
 973   UINT f_acc; \
 974   UINT f_op23; \
 975   UINT f_r2; \
 976   unsigned int length;
 977 #define EXTRACT_FMT_37_MACHI_A_CODE \
 978   length = 2; \
 979   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 980   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 981   f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
 982   f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
 983   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 984
 985 #define EXTRACT_FMT_38_MULHI_A_VARS \
 986   /* Instruction fields.  */ \
 987   UINT f_op1; \
 988   UINT f_r1; \
 989   UINT f_acc; \
 990   UINT f_op23; \
 991   UINT f_r2; \
 992   unsigned int length;
 993 #define EXTRACT_FMT_38_MULHI_A_CODE \
 994   length = 2; \
 995   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 996   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 997   f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
 998   f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
 999   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1000
1001 #define EXTRACT_FMT_39_MV_VARS \
1002   /* Instruction fields.  */ \
1003   UINT f_op1; \
1004   UINT f_r1; \
1005   UINT f_op2; \
1006   UINT f_r2; \
1007   unsigned int length;
1008 #define EXTRACT_FMT_39_MV_CODE \
1009   length = 2; \
1010   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1011   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1012   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1013   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1014
1015 #define EXTRACT_FMT_40_MVFACHI_A_VARS \
1016   /* Instruction fields.  */ \
1017   UINT f_op1; \
1018   UINT f_r1; \
1019   UINT f_op2; \
1020   UINT f_accs; \
1021   UINT f_op3; \
1022   unsigned int length;
1023 #define EXTRACT_FMT_40_MVFACHI_A_CODE \
1024   length = 2; \
1025   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1026   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1027   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1028   f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1029   f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
1030
1031 #define EXTRACT_FMT_41_MVFC_VARS \
1032   /* Instruction fields.  */ \
1033   UINT f_op1; \
1034   UINT f_r1; \
1035   UINT f_op2; \
1036   UINT f_r2; \
1037   unsigned int length;
1038 #define EXTRACT_FMT_41_MVFC_CODE \
1039   length = 2; \
1040   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1041   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1042   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1043   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1044
1045 #define EXTRACT_FMT_42_MVTACHI_A_VARS \
1046   /* Instruction fields.  */ \
1047   UINT f_op1; \
1048   UINT f_r1; \
1049   UINT f_op2; \
1050   UINT f_accs; \
1051   UINT f_op3; \
1052   unsigned int length;
1053 #define EXTRACT_FMT_42_MVTACHI_A_CODE \
1054   length = 2; \
1055   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1056   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1057   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1058   f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1059   f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
1060
1061 #define EXTRACT_FMT_43_MVTC_VARS \
1062   /* Instruction fields.  */ \
1063   UINT f_op1; \
1064   UINT f_r1; \
1065   UINT f_op2; \
1066   UINT f_r2; \
1067   unsigned int length;
1068 #define EXTRACT_FMT_43_MVTC_CODE \
1069   length = 2; \
1070   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1071   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1072   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1073   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1074
1075 #define EXTRACT_FMT_44_NOP_VARS \
1076   /* Instruction fields.  */ \
1077   UINT f_op1; \
1078   UINT f_r1; \
1079   UINT f_op2; \
1080   UINT f_r2; \
1081   unsigned int length;
1082 #define EXTRACT_FMT_44_NOP_CODE \
1083   length = 2; \
1084   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1085   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1086   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1087   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1088
1089 #define EXTRACT_FMT_45_RAC_DSI_VARS \
1090   /* Instruction fields.  */ \
1091   UINT f_op1; \
1092   UINT f_accd; \
1093   UINT f_bits67; \
1094   UINT f_op2; \
1095   UINT f_accs; \
1096   UINT f_bit14; \
1097   UINT f_imm1; \
1098   unsigned int length;
1099 #define EXTRACT_FMT_45_RAC_DSI_CODE \
1100   length = 2; \
1101   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1102   f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \
1103   f_bits67 = EXTRACT_UNSIGNED (insn, 16, 6, 2); \
1104   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1105   f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1106   f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \
1107   f_imm1 = ((EXTRACT_UNSIGNED (insn, 16, 15, 1)) + (1)); \
1108
1109 #define EXTRACT_FMT_46_RTE_VARS \
1110   /* Instruction fields.  */ \
1111   UINT f_op1; \
1112   UINT f_r1; \
1113   UINT f_op2; \
1114   UINT f_r2; \
1115   unsigned int length;
1116 #define EXTRACT_FMT_46_RTE_CODE \
1117   length = 2; \
1118   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1119   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1120   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1121   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1122
1123 #define EXTRACT_FMT_47_SETH_VARS \
1124   /* Instruction fields.  */ \
1125   UINT f_op1; \
1126   UINT f_r1; \
1127   UINT f_op2; \
1128   UINT f_r2; \
1129   UINT f_hi16; \
1130   unsigned int length;
1131 #define EXTRACT_FMT_47_SETH_CODE \
1132   length = 4; \
1133   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1134   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1135   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1136   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1137   f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1138
1139 #define EXTRACT_FMT_48_SLL3_VARS \
1140   /* Instruction fields.  */ \
1141   UINT f_op1; \
1142   UINT f_r1; \
1143   UINT f_op2; \
1144   UINT f_r2; \
1145   int f_simm16; \
1146   unsigned int length;
1147 #define EXTRACT_FMT_48_SLL3_CODE \
1148   length = 4; \
1149   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1150   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1151   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1152   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1153   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1154
1155 #define EXTRACT_FMT_49_SLLI_VARS \
1156   /* Instruction fields.  */ \
1157   UINT f_op1; \
1158   UINT f_r1; \
1159   UINT f_shift_op2; \
1160   UINT f_uimm5; \
1161   unsigned int length;
1162 #define EXTRACT_FMT_49_SLLI_CODE \
1163   length = 2; \
1164   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1165   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1166   f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
1167   f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
1168
1169 #define EXTRACT_FMT_50_ST_VARS \
1170   /* Instruction fields.  */ \
1171   UINT f_op1; \
1172   UINT f_r1; \
1173   UINT f_op2; \
1174   UINT f_r2; \
1175   unsigned int length;
1176 #define EXTRACT_FMT_50_ST_CODE \
1177   length = 2; \
1178   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1179   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1180   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1181   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1182
1183 #define EXTRACT_FMT_51_ST_D_VARS \
1184   /* Instruction fields.  */ \
1185   UINT f_op1; \
1186   UINT f_r1; \
1187   UINT f_op2; \
1188   UINT f_r2; \
1189   int f_simm16; \
1190   unsigned int length;
1191 #define EXTRACT_FMT_51_ST_D_CODE \
1192   length = 4; \
1193   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1194   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1195   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1196   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1197   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1198
1199 #define EXTRACT_FMT_52_STB_VARS \
1200   /* Instruction fields.  */ \
1201   UINT f_op1; \
1202   UINT f_r1; \
1203   UINT f_op2; \
1204   UINT f_r2; \
1205   unsigned int length;
1206 #define EXTRACT_FMT_52_STB_CODE \
1207   length = 2; \
1208   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1209   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1210   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1211   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1212
1213 #define EXTRACT_FMT_53_STB_D_VARS \
1214   /* Instruction fields.  */ \
1215   UINT f_op1; \
1216   UINT f_r1; \
1217   UINT f_op2; \
1218   UINT f_r2; \
1219   int f_simm16; \
1220   unsigned int length;
1221 #define EXTRACT_FMT_53_STB_D_CODE \
1222   length = 4; \
1223   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1224   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1225   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1226   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1227   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1228
1229 #define EXTRACT_FMT_54_STH_VARS \
1230   /* Instruction fields.  */ \
1231   UINT f_op1; \
1232   UINT f_r1; \
1233   UINT f_op2; \
1234   UINT f_r2; \
1235   unsigned int length;
1236 #define EXTRACT_FMT_54_STH_CODE \
1237   length = 2; \
1238   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1239   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1240   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1241   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1242
1243 #define EXTRACT_FMT_55_STH_D_VARS \
1244   /* Instruction fields.  */ \
1245   UINT f_op1; \
1246   UINT f_r1; \
1247   UINT f_op2; \
1248   UINT f_r2; \
1249   int f_simm16; \
1250   unsigned int length;
1251 #define EXTRACT_FMT_55_STH_D_CODE \
1252   length = 4; \
1253   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1254   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1255   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1256   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1257   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1258
1259 #define EXTRACT_FMT_56_ST_PLUS_VARS \
1260   /* Instruction fields.  */ \
1261   UINT f_op1; \
1262   UINT f_r1; \
1263   UINT f_op2; \
1264   UINT f_r2; \
1265   unsigned int length;
1266 #define EXTRACT_FMT_56_ST_PLUS_CODE \
1267   length = 2; \
1268   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1269   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1270   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1271   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1272
1273 #define EXTRACT_FMT_57_TRAP_VARS \
1274   /* Instruction fields.  */ \
1275   UINT f_op1; \
1276   UINT f_r1; \
1277   UINT f_op2; \
1278   UINT f_uimm4; \
1279   unsigned int length;
1280 #define EXTRACT_FMT_57_TRAP_CODE \
1281   length = 2; \
1282   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1283   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1284   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1285   f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1286
1287 #define EXTRACT_FMT_58_UNLOCK_VARS \
1288   /* Instruction fields.  */ \
1289   UINT f_op1; \
1290   UINT f_r1; \
1291   UINT f_op2; \
1292   UINT f_r2; \
1293   unsigned int length;
1294 #define EXTRACT_FMT_58_UNLOCK_CODE \
1295   length = 2; \
1296   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1297   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1298   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1299   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1300
1301 #define EXTRACT_FMT_59_SATB_VARS \
1302   /* Instruction fields.  */ \
1303   UINT f_op1; \
1304   UINT f_r1; \
1305   UINT f_op2; \
1306   UINT f_r2; \
1307   UINT f_uimm16; \
1308   unsigned int length;
1309 #define EXTRACT_FMT_59_SATB_CODE \
1310   length = 4; \
1311   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1312   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1313   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1314   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1315   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1316
1317 #define EXTRACT_FMT_60_SAT_VARS \
1318   /* Instruction fields.  */ \
1319   UINT f_op1; \
1320   UINT f_r1; \
1321   UINT f_op2; \
1322   UINT f_r2; \
1323   UINT f_uimm16; \
1324   unsigned int length;
1325 #define EXTRACT_FMT_60_SAT_CODE \
1326   length = 4; \
1327   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1328   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1329   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1330   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1331   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1332
1333 #define EXTRACT_FMT_61_SADD_VARS \
1334   /* Instruction fields.  */ \
1335   UINT f_op1; \
1336   UINT f_r1; \
1337   UINT f_op2; \
1338   UINT f_r2; \
1339   unsigned int length;
1340 #define EXTRACT_FMT_61_SADD_CODE \
1341   length = 2; \
1342   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1343   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1344   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1345   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1346
1347 #define EXTRACT_FMT_62_MACWU1_VARS \
1348   /* Instruction fields.  */ \
1349   UINT f_op1; \
1350   UINT f_r1; \
1351   UINT f_op2; \
1352   UINT f_r2; \
1353   unsigned int length;
1354 #define EXTRACT_FMT_62_MACWU1_CODE \
1355   length = 2; \
1356   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1357   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1358   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1359   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1360
1361 #define EXTRACT_FMT_63_MSBLO_VARS \
1362   /* Instruction fields.  */ \
1363   UINT f_op1; \
1364   UINT f_r1; \
1365   UINT f_op2; \
1366   UINT f_r2; \
1367   unsigned int length;
1368 #define EXTRACT_FMT_63_MSBLO_CODE \
1369   length = 2; \
1370   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1371   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1372   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1373   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1374
1375 #define EXTRACT_FMT_64_MULWU1_VARS \
1376   /* Instruction fields.  */ \
1377   UINT f_op1; \
1378   UINT f_r1; \
1379   UINT f_op2; \
1380   UINT f_r2; \
1381   unsigned int length;
1382 #define EXTRACT_FMT_64_MULWU1_CODE \
1383   length = 2; \
1384   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1385   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1386   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1387   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1388
1389 #define EXTRACT_FMT_65_SC_VARS \
1390   /* Instruction fields.  */ \
1391   UINT f_op1; \
1392   UINT f_r1; \
1393   UINT f_op2; \
1394   UINT f_r2; \
1395   unsigned int length;
1396 #define EXTRACT_FMT_65_SC_CODE \
1397   length = 2; \
1398   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1399   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1400   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1401   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1402
1403 /* Fetched input values of an instruction.  */
1404
1405 struct parexec {
1406   union {
1407     struct { /* e.g. add $dr,$sr */
1408       SI dr;
1409       SI sr;
1410     } fmt_0_add;
1411     struct { /* e.g. add3 $dr,$sr,#$slo16 */
1412       HI slo16;
1413       SI sr;
1414     } fmt_1_add3;
1415     struct { /* e.g. and3 $dr,$sr,#$uimm16 */
1416       SI sr;
1417       USI uimm16;
1418     } fmt_2_and3;
1419     struct { /* e.g. or3 $dr,$sr,#$ulo16 */
1420       SI sr;
1421       UHI ulo16;
1422     } fmt_3_or3;
1423     struct { /* e.g. addi $dr,#$simm8 */
1424       SI dr;
1425       SI simm8;
1426     } fmt_4_addi;
1427     struct { /* e.g. addv $dr,$sr */
1428       SI dr;
1429       SI sr;
1430     } fmt_5_addv;
1431     struct { /* e.g. addv3 $dr,$sr,#$simm16 */
1432       SI simm16;
1433       SI sr;
1434     } fmt_6_addv3;
1435     struct { /* e.g. addx $dr,$sr */
1436       UBI condbit;
1437       SI dr;
1438       SI sr;
1439     } fmt_7_addx;
1440     struct { /* e.g. bc $disp8 */
1441       UBI condbit;
1442       IADDR disp8;
1443     } fmt_8_bc8;
1444     struct { /* e.g. bc $disp24 */
1445       UBI condbit;
1446       IADDR disp24;
1447     } fmt_9_bc24;
1448     struct { /* e.g. beq $src1,$src2,$disp16 */
1449       IADDR disp16;
1450       SI src1;
1451       SI src2;
1452     } fmt_10_beq;
1453     struct { /* e.g. beqz $src2,$disp16 */
1454       IADDR disp16;
1455       SI src2;
1456     } fmt_11_beqz;
1457     struct { /* e.g. bl $disp8 */
1458       IADDR disp8;
1459       USI pc;
1460     } fmt_12_bl8;
1461     struct { /* e.g. bl $disp24 */
1462       IADDR disp24;
1463       USI pc;
1464     } fmt_13_bl24;
1465     struct { /* e.g. bcl $disp8 */
1466       UBI condbit;
1467       IADDR disp8;
1468       USI pc;
1469     } fmt_14_bcl8;
1470     struct { /* e.g. bcl $disp24 */
1471       UBI condbit;
1472       IADDR disp24;
1473       USI pc;
1474     } fmt_15_bcl24;
1475     struct { /* e.g. bra $disp8 */
1476       IADDR disp8;
1477     } fmt_16_bra8;
1478     struct { /* e.g. bra $disp24 */
1479       IADDR disp24;
1480     } fmt_17_bra24;
1481     struct { /* e.g. cmp $src1,$src2 */
1482       SI src1;
1483       SI src2;
1484     } fmt_18_cmp;
1485     struct { /* e.g. cmpi $src2,#$simm16 */
1486       SI simm16;
1487       SI src2;
1488     } fmt_19_cmpi;
1489     struct { /* e.g. cmpui $src2,#$uimm16 */
1490       SI src2;
1491       USI uimm16;
1492     } fmt_20_cmpui;
1493     struct { /* e.g. cmpz $src2 */
1494       SI src2;
1495     } fmt_21_cmpz;
1496     struct { /* e.g. div $dr,$sr */
1497       SI dr;
1498       SI sr;
1499     } fmt_22_div;
1500     struct { /* e.g. jc $sr */
1501       UBI condbit;
1502       SI sr;
1503     } fmt_23_jc;
1504     struct { /* e.g. jl $sr */
1505       USI pc;
1506       SI sr;
1507     } fmt_24_jl;
1508     struct { /* e.g. jmp $sr */
1509       SI sr;
1510     } fmt_25_jmp;
1511     struct { /* e.g. ld $dr,@$sr */
1512       SI h_memory_sr;
1513       SI sr;
1514     } fmt_26_ld;
1515     struct { /* e.g. ld $dr,@($slo16,$sr) */
1516       SI h_memory_add_WI_sr_slo16;
1517       HI slo16;
1518       SI sr;
1519     } fmt_27_ld_d;
1520     struct { /* e.g. ldb $dr,@$sr */
1521       QI h_memory_sr;
1522       SI sr;
1523     } fmt_28_ldb;
1524     struct { /* e.g. ldb $dr,@($slo16,$sr) */
1525       QI h_memory_add_WI_sr_slo16;
1526       HI slo16;
1527       SI sr;
1528     } fmt_29_ldb_d;
1529     struct { /* e.g. ldh $dr,@$sr */
1530       HI h_memory_sr;
1531       SI sr;
1532     } fmt_30_ldh;
1533     struct { /* e.g. ldh $dr,@($slo16,$sr) */
1534       HI h_memory_add_WI_sr_slo16;
1535       HI slo16;
1536       SI sr;
1537     } fmt_31_ldh_d;
1538     struct { /* e.g. ld $dr,@$sr+ */
1539       SI h_memory_sr;
1540       SI sr;
1541     } fmt_32_ld_plus;
1542     struct { /* e.g. ld24 $dr,#$uimm24 */
1543       ADDR uimm24;
1544     } fmt_33_ld24;
1545     struct { /* e.g. ldi $dr,#$simm8 */
1546       SI simm8;
1547     } fmt_34_ldi8;
1548     struct { /* e.g. ldi $dr,$slo16 */
1549       HI slo16;
1550     } fmt_35_ldi16;
1551     struct { /* e.g. lock $dr,@$sr */
1552       SI h_memory_sr;
1553       SI sr;
1554     } fmt_36_lock;
1555     struct { /* e.g. machi $src1,$src2,$acc */
1556       DI acc;
1557       SI src1;
1558       SI src2;
1559     } fmt_37_machi_a;
1560     struct { /* e.g. mulhi $src1,$src2,$acc */
1561       SI src1;
1562       SI src2;
1563     } fmt_38_mulhi_a;
1564     struct { /* e.g. mv $dr,$sr */
1565       SI sr;
1566     } fmt_39_mv;
1567     struct { /* e.g. mvfachi $dr,$accs */
1568       DI accs;
1569     } fmt_40_mvfachi_a;
1570     struct { /* e.g. mvfc $dr,$scr */
1571       USI scr;
1572     } fmt_41_mvfc;
1573     struct { /* e.g. mvtachi $src1,$accs */
1574       DI accs;
1575       SI src1;
1576     } fmt_42_mvtachi_a;
1577     struct { /* e.g. mvtc $sr,$dcr */
1578       SI sr;
1579     } fmt_43_mvtc;
1580     struct { /* e.g. nop */
1581       int empty;
1582     } fmt_44_nop;
1583     struct { /* e.g. rac $accd,$accs,#$imm1 */
1584       DI accs;
1585       USI imm1;
1586     } fmt_45_rac_dsi;
1587     struct { /* e.g. rte */
1588       UBI h_bcond_0;
1589       UBI h_bie_0;
1590       SI h_bpc_0;
1591       UBI h_bsm_0;
1592     } fmt_46_rte;
1593     struct { /* e.g. seth $dr,#$hi16 */
1594       UHI hi16;
1595     } fmt_47_seth;
1596     struct { /* e.g. sll3 $dr,$sr,#$simm16 */
1597       SI simm16;
1598       SI sr;
1599     } fmt_48_sll3;
1600     struct { /* e.g. slli $dr,#$uimm5 */
1601       SI dr;
1602       USI uimm5;
1603     } fmt_49_slli;
1604     struct { /* e.g. st $src1,@$src2 */
1605       SI src1;
1606       SI src2;
1607     } fmt_50_st;
1608     struct { /* e.g. st $src1,@($slo16,$src2) */
1609       HI slo16;
1610       SI src1;
1611       SI src2;
1612     } fmt_51_st_d;
1613     struct { /* e.g. stb $src1,@$src2 */
1614       SI src1;
1615       SI src2;
1616     } fmt_52_stb;
1617     struct { /* e.g. stb $src1,@($slo16,$src2) */
1618       HI slo16;
1619       SI src1;
1620       SI src2;
1621     } fmt_53_stb_d;
1622     struct { /* e.g. sth $src1,@$src2 */
1623       SI src1;
1624       SI src2;
1625     } fmt_54_sth;
1626     struct { /* e.g. sth $src1,@($slo16,$src2) */
1627       HI slo16;
1628       SI src1;
1629       SI src2;
1630     } fmt_55_sth_d;
1631     struct { /* e.g. st $src1,@+$src2 */
1632       SI src1;
1633       SI src2;
1634     } fmt_56_st_plus;
1635     struct { /* e.g. trap #$uimm4 */
1636       USI pc;
1637       SI h_cr_0;
1638       USI uimm4;
1639     } fmt_57_trap;
1640     struct { /* e.g. unlock $src1,@$src2 */
1641       UBI h_lock_0;
1642       SI src1;
1643       SI src2;
1644     } fmt_58_unlock;
1645     struct { /* e.g. satb $dr,$sr */
1646       SI sr;
1647     } fmt_59_satb;
1648     struct { /* e.g. sat $dr,$sr */
1649       UBI condbit;
1650       SI sr;
1651     } fmt_60_sat;
1652     struct { /* e.g. sadd */
1653       DI h_accums_0;
1654       DI h_accums_1;
1655     } fmt_61_sadd;
1656     struct { /* e.g. macwu1 $src1,$src2 */
1657       DI h_accums_1;
1658       SI src1;
1659       SI src2;
1660     } fmt_62_macwu1;
1661     struct { /* e.g. msblo $src1,$src2 */
1662       DI accum;
1663       SI src1;
1664       SI src2;
1665     } fmt_63_msblo;
1666     struct { /* e.g. mulwu1 $src1,$src2 */
1667       SI src1;
1668       SI src2;
1669     } fmt_64_mulwu1;
1670     struct { /* e.g. sc */
1671       UBI condbit;
1672     } fmt_65_sc;
1673   } operands;
1674 };
1675
1676 #endif /* CPU_M32RX_H */