sim/m32r/cpux.h

   1 /* CPU family header for m32rxf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_M32RXF_H
  26 #define CPU_M32RXF_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 2
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 2
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[16];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* control registers */
  48   USI h_cr[16];
  49 #define GET_H_CR(a1) CPU (h_cr)[a1]
  50 #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
  51   /* accumulator */
  52   DI h_accum;
  53 #define GET_H_ACCUM() CPU (h_accum)
  54 #define SET_H_ACCUM(x) (CPU (h_accum) = (x))
  55 /* start-sanitize-m32rx */
  56   /* accumulators */
  57   DI h_accums[2];
  58 /* end-sanitize-m32rx */
  59 #define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
  60 #define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
  61   /* condition bit */
  62   BI h_cond;
  63 #define GET_H_COND() CPU (h_cond)
  64 #define SET_H_COND(x) (CPU (h_cond) = (x))
  65   /* psw part of psw */
  66   UQI h_psw;
  67 #define GET_H_PSW() CPU (h_psw)
  68 #define SET_H_PSW(x) (CPU (h_psw) = (x))
  69   /* backup psw */
  70   UQI h_bpsw;
  71 #define GET_H_BPSW() CPU (h_bpsw)
  72 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
  73   /* backup bpsw */
  74   UQI h_bbpsw;
  75 #define GET_H_BBPSW() CPU (h_bbpsw)
  76 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
  77   /* lock */
  78   BI h_lock;
  79 #define GET_H_LOCK() CPU (h_lock)
  80 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
  81   } hardware;
  82 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  83 } M32RXF_CPU_DATA;
  84
  85 /* Cover fns for register access.  */
  86 USI m32rxf_h_pc_get (SIM_CPU *);
  87 void m32rxf_h_pc_set (SIM_CPU *, USI);
  88 SI m32rxf_h_gr_get (SIM_CPU *, UINT);
  89 void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
  90 USI m32rxf_h_cr_get (SIM_CPU *, UINT);
  91 void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
  92 DI m32rxf_h_accum_get (SIM_CPU *);
  93 void m32rxf_h_accum_set (SIM_CPU *, DI);
  94 DI m32rxf_h_accums_get (SIM_CPU *, UINT);
  95 void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
  96 BI m32rxf_h_cond_get (SIM_CPU *);
  97 void m32rxf_h_cond_set (SIM_CPU *, BI);
  98 UQI m32rxf_h_psw_get (SIM_CPU *);
  99 void m32rxf_h_psw_set (SIM_CPU *, UQI);
 100 UQI m32rxf_h_bpsw_get (SIM_CPU *);
 101 void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
 102 UQI m32rxf_h_bbpsw_get (SIM_CPU *);
 103 void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
 104 BI m32rxf_h_lock_get (SIM_CPU *);
 105 void m32rxf_h_lock_set (SIM_CPU *, BI);
 106
 107 /* These must be hand-written.  */
 108 extern CPUREG_FETCH_FN m32rxf_fetch_register;
 109 extern CPUREG_STORE_FN m32rxf_store_register;
 110
 111 typedef struct {
 112   int empty;
 113 } MODEL_M32RX_DATA;
 114
 115 /* The ARGBUF struct.  */
 116 struct argbuf {
 117   /* These are the baseclass definitions.  */
 118   PCADDR addr;
 119   const IDESC *idesc;
 120   /* cpu specific data follows */
 121   union sem semantic;
 122   int written;
 123   union {
 124     struct { /* e.g. add $dr,$sr */
 125       SI * f_r1;
 126       SI * f_r2;
 127       unsigned char in_dr;
 128       unsigned char in_sr;
 129       unsigned char out_dr;
 130     } fmt_add;
 131     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
 132       SI * f_r1;
 133       SI * f_r2;
 134       HI f_simm16;
 135       unsigned char in_sr;
 136       unsigned char out_dr;
 137     } fmt_add3;
 138     struct { /* e.g. and3 $dr,$sr,$uimm16 */
 139       SI * f_r1;
 140       SI * f_r2;
 141       USI f_uimm16;
 142       unsigned char in_sr;
 143       unsigned char out_dr;
 144     } fmt_and3;
 145     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
 146       SI * f_r1;
 147       SI * f_r2;
 148       UHI f_uimm16;
 149       unsigned char in_sr;
 150       unsigned char out_dr;
 151     } fmt_or3;
 152     struct { /* e.g. addi $dr,$simm8 */
 153       SI * f_r1;
 154       SI f_simm8;
 155       unsigned char in_dr;
 156       unsigned char out_dr;
 157     } fmt_addi;
 158     struct { /* e.g. addv $dr,$sr */
 159       SI * f_r1;
 160       SI * f_r2;
 161       unsigned char in_dr;
 162       unsigned char in_sr;
 163       unsigned char out_dr;
 164     } fmt_addv;
 165     struct { /* e.g. addv3 $dr,$sr,$simm16 */
 166       SI * f_r1;
 167       SI * f_r2;
 168       SI f_simm16;
 169       unsigned char in_sr;
 170       unsigned char out_dr;
 171     } fmt_addv3;
 172     struct { /* e.g. addx $dr,$sr */
 173       SI * f_r1;
 174       SI * f_r2;
 175       unsigned char in_dr;
 176       unsigned char in_sr;
 177       unsigned char out_dr;
 178     } fmt_addx;
 179     struct { /* e.g. cmp $src1,$src2 */
 180       SI * f_r1;
 181       SI * f_r2;
 182       unsigned char in_src1;
 183       unsigned char in_src2;
 184     } fmt_cmp;
 185     struct { /* e.g. cmpi $src2,$simm16 */
 186       SI * f_r2;
 187       SI f_simm16;
 188       unsigned char in_src2;
 189     } fmt_cmpi;
 190     struct { /* e.g. cmpz $src2 */
 191       SI * f_r2;
 192       unsigned char in_src2;
 193     } fmt_cmpz;
 194     struct { /* e.g. div $dr,$sr */
 195       SI * f_r1;
 196       SI * f_r2;
 197       unsigned char in_sr;
 198       unsigned char in_dr;
 199       unsigned char out_dr;
 200     } fmt_div;
 201     struct { /* e.g. ld $dr,@$sr */
 202       SI * f_r1;
 203       SI * f_r2;
 204       unsigned char in_sr;
 205       unsigned char out_dr;
 206     } fmt_ld;
 207     struct { /* e.g. ld $dr,@($slo16,$sr) */
 208       SI * f_r1;
 209       SI * f_r2;
 210       HI f_simm16;
 211       unsigned char in_sr;
 212       unsigned char out_dr;
 213     } fmt_ld_d;
 214     struct { /* e.g. ldb $dr,@$sr */
 215       SI * f_r1;
 216       SI * f_r2;
 217       unsigned char in_sr;
 218       unsigned char out_dr;
 219     } fmt_ldb;
 220     struct { /* e.g. ldb $dr,@($slo16,$sr) */
 221       SI * f_r1;
 222       SI * f_r2;
 223       HI f_simm16;
 224       unsigned char in_sr;
 225       unsigned char out_dr;
 226     } fmt_ldb_d;
 227     struct { /* e.g. ldh $dr,@$sr */
 228       SI * f_r1;
 229       SI * f_r2;
 230       unsigned char in_sr;
 231       unsigned char out_dr;
 232     } fmt_ldh;
 233     struct { /* e.g. ldh $dr,@($slo16,$sr) */
 234       SI * f_r1;
 235       SI * f_r2;
 236       HI f_simm16;
 237       unsigned char in_sr;
 238       unsigned char out_dr;
 239     } fmt_ldh_d;
 240     struct { /* e.g. ld $dr,@$sr+ */
 241       SI * f_r1;
 242       SI * f_r2;
 243       unsigned char in_sr;
 244       unsigned char out_dr;
 245       unsigned char out_sr;
 246     } fmt_ld_plus;
 247     struct { /* e.g. ld24 $dr,$uimm24 */
 248       SI * f_r1;
 249       ADDR f_uimm24;
 250       unsigned char out_dr;
 251     } fmt_ld24;
 252     struct { /* e.g. ldi8 $dr,$simm8 */
 253       SI * f_r1;
 254       SI f_simm8;
 255       unsigned char out_dr;
 256     } fmt_ldi8;
 257     struct { /* e.g. ldi16 $dr,$hash$slo16 */
 258       SI * f_r1;
 259       HI f_simm16;
 260       unsigned char out_dr;
 261     } fmt_ldi16;
 262     struct { /* e.g. lock $dr,@$sr */
 263       SI * f_r1;
 264       SI * f_r2;
 265       unsigned char in_sr;
 266       unsigned char out_dr;
 267     } fmt_lock;
 268     struct { /* e.g. machi $src1,$src2,$acc */
 269       SI * f_r1;
 270       UINT f_acc;
 271       SI * f_r2;
 272       unsigned char in_src1;
 273       unsigned char in_src2;
 274     } fmt_machi_a;
 275     struct { /* e.g. mulhi $src1,$src2,$acc */
 276       SI * f_r1;
 277       UINT f_acc;
 278       SI * f_r2;
 279       unsigned char in_src1;
 280       unsigned char in_src2;
 281     } fmt_mulhi_a;
 282     struct { /* e.g. mv $dr,$sr */
 283       SI * f_r1;
 284       SI * f_r2;
 285       unsigned char in_sr;
 286       unsigned char out_dr;
 287     } fmt_mv;
 288     struct { /* e.g. mvfachi $dr,$accs */
 289       SI * f_r1;
 290       UINT f_accs;
 291       unsigned char out_dr;
 292     } fmt_mvfachi_a;
 293     struct { /* e.g. mvfc $dr,$scr */
 294       SI * f_r1;
 295       UINT f_r2;
 296       unsigned char out_dr;
 297     } fmt_mvfc;
 298     struct { /* e.g. mvtachi $src1,$accs */
 299       SI * f_r1;
 300       UINT f_accs;
 301       unsigned char in_src1;
 302     } fmt_mvtachi_a;
 303     struct { /* e.g. mvtc $sr,$dcr */
 304       UINT f_r1;
 305       SI * f_r2;
 306       unsigned char in_sr;
 307     } fmt_mvtc;
 308     struct { /* e.g. nop */
 309       int empty;
 310     } fmt_nop;
 311     struct { /* e.g. rac $accd,$accs,$imm1 */
 312       UINT f_accd;
 313       UINT f_accs;
 314       USI f_imm1;
 315     } fmt_rac_dsi;
 316     struct { /* e.g. seth $dr,$hash$hi16 */
 317       SI * f_r1;
 318       UHI f_hi16;
 319       unsigned char out_dr;
 320     } fmt_seth;
 321     struct { /* e.g. sll3 $dr,$sr,$simm16 */
 322       SI * f_r1;
 323       SI * f_r2;
 324       SI f_simm16;
 325       unsigned char in_sr;
 326       unsigned char out_dr;
 327     } fmt_sll3;
 328     struct { /* e.g. slli $dr,$uimm5 */
 329       SI * f_r1;
 330       USI f_uimm5;
 331       unsigned char in_dr;
 332       unsigned char out_dr;
 333     } fmt_slli;
 334     struct { /* e.g. st $src1,@$src2 */
 335       SI * f_r1;
 336       SI * f_r2;
 337       unsigned char in_src2;
 338       unsigned char in_src1;
 339     } fmt_st;
 340     struct { /* e.g. st $src1,@($slo16,$src2) */
 341       SI * f_r1;
 342       SI * f_r2;
 343       HI f_simm16;
 344       unsigned char in_src2;
 345       unsigned char in_src1;
 346     } fmt_st_d;
 347     struct { /* e.g. stb $src1,@$src2 */
 348       SI * f_r1;
 349       SI * f_r2;
 350       unsigned char in_src2;
 351       unsigned char in_src1;
 352     } fmt_stb;
 353     struct { /* e.g. stb $src1,@($slo16,$src2) */
 354       SI * f_r1;
 355       SI * f_r2;
 356       HI f_simm16;
 357       unsigned char in_src2;
 358       unsigned char in_src1;
 359     } fmt_stb_d;
 360     struct { /* e.g. sth $src1,@$src2 */
 361       SI * f_r1;
 362       SI * f_r2;
 363       unsigned char in_src2;
 364       unsigned char in_src1;
 365     } fmt_sth;
 366     struct { /* e.g. sth $src1,@($slo16,$src2) */
 367       SI * f_r1;
 368       SI * f_r2;
 369       HI f_simm16;
 370       unsigned char in_src2;
 371       unsigned char in_src1;
 372     } fmt_sth_d;
 373     struct { /* e.g. st $src1,@+$src2 */
 374       SI * f_r1;
 375       SI * f_r2;
 376       unsigned char in_src2;
 377       unsigned char in_src1;
 378       unsigned char out_src2;
 379     } fmt_st_plus;
 380     struct { /* e.g. unlock $src1,@$src2 */
 381       SI * f_r1;
 382       SI * f_r2;
 383       unsigned char in_src2;
 384       unsigned char in_src1;
 385     } fmt_unlock;
 386     struct { /* e.g. satb $dr,$sr */
 387       SI * f_r1;
 388       SI * f_r2;
 389       unsigned char in_sr;
 390       unsigned char out_dr;
 391     } fmt_satb;
 392     struct { /* e.g. sat $dr,$sr */
 393       SI * f_r1;
 394       SI * f_r2;
 395       unsigned char in_sr;
 396       unsigned char out_dr;
 397     } fmt_sat;
 398     struct { /* e.g. sadd */
 399       int empty;
 400     } fmt_sadd;
 401     struct { /* e.g. macwu1 $src1,$src2 */
 402       SI * f_r1;
 403       SI * f_r2;
 404       unsigned char in_src1;
 405       unsigned char in_src2;
 406     } fmt_macwu1;
 407     struct { /* e.g. msblo $src1,$src2 */
 408       SI * f_r1;
 409       SI * f_r2;
 410       unsigned char in_src1;
 411       unsigned char in_src2;
 412     } fmt_msblo;
 413     struct { /* e.g. mulwu1 $src1,$src2 */
 414       SI * f_r1;
 415       SI * f_r2;
 416       unsigned char in_src1;
 417       unsigned char in_src2;
 418     } fmt_mulwu1;
 419     struct { /* e.g. sc */
 420       int empty;
 421     } fmt_sc;
 422   /* cti insns, kept separately so addr_cache is in fixed place */
 423   struct {
 424     union {
 425     struct { /* e.g. bc.s $disp8 */
 426       IADDR f_disp8;
 427     } fmt_bc8;
 428     struct { /* e.g. bc.l $disp24 */
 429       IADDR f_disp24;
 430     } fmt_bc24;
 431     struct { /* e.g. beq $src1,$src2,$disp16 */
 432       SI * f_r1;
 433       SI * f_r2;
 434       IADDR f_disp16;
 435       unsigned char in_src1;
 436       unsigned char in_src2;
 437     } fmt_beq;
 438     struct { /* e.g. beqz $src2,$disp16 */
 439       SI * f_r2;
 440       IADDR f_disp16;
 441       unsigned char in_src2;
 442     } fmt_beqz;
 443     struct { /* e.g. bl.s $disp8 */
 444       IADDR f_disp8;
 445       unsigned char out_h_gr_14;
 446     } fmt_bl8;
 447     struct { /* e.g. bl.l $disp24 */
 448       IADDR f_disp24;
 449       unsigned char out_h_gr_14;
 450     } fmt_bl24;
 451     struct { /* e.g. bcl.s $disp8 */
 452       IADDR f_disp8;
 453       unsigned char out_h_gr_14;
 454     } fmt_bcl8;
 455     struct { /* e.g. bcl.l $disp24 */
 456       IADDR f_disp24;
 457       unsigned char out_h_gr_14;
 458     } fmt_bcl24;
 459     struct { /* e.g. bra.s $disp8 */
 460       IADDR f_disp8;
 461     } fmt_bra8;
 462     struct { /* e.g. bra.l $disp24 */
 463       IADDR f_disp24;
 464     } fmt_bra24;
 465     struct { /* e.g. jc $sr */
 466       SI * f_r2;
 467       unsigned char in_sr;
 468     } fmt_jc;
 469     struct { /* e.g. jl $sr */
 470       SI * f_r2;
 471       unsigned char in_sr;
 472       unsigned char out_h_gr_14;
 473     } fmt_jl;
 474     struct { /* e.g. jmp $sr */
 475       SI * f_r2;
 476       unsigned char in_sr;
 477     } fmt_jmp;
 478     struct { /* e.g. rte */
 479       int empty;
 480     } fmt_rte;
 481     struct { /* e.g. trap $uimm4 */
 482       USI f_uimm4;
 483     } fmt_trap;
 484     } fields;
 485 #if WITH_SCACHE_PBB_M32RXF
 486     SEM_PC addr_cache;
 487 #endif
 488   } cti;
 489 #if WITH_SCACHE_PBB_M32RXF
 490     /* Writeback handler.  */
 491     struct {
 492       /* Pointer to argbuf entry for insn whose results need writing back.  */
 493       const struct argbuf *abuf;
 494     } write;
 495     /* x-before handler */
 496     struct {
 497       /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 498       int first_p;
 499     } before;
 500     /* x-after handler */
 501     struct {
 502       int empty;
 503     } after;
 504     /* This entry is used to terminate each pbb.  */
 505     struct {
 506       /* Number of insns in pbb.  */
 507       int insn_count;
 508       /* Next pbb to execute.  */
 509       SCACHE *next;
 510     } chain;
 511 #endif
 512   } fields;
 513 };
 514
 515 /* A cached insn.
 516
 517    ??? SCACHE used to contain more than just argbuf.  We could delete the
 518    type entirely and always just use ARGBUF, but for future concerns and as
 519    a level of abstraction it is left in.  */
 520
 521 struct scache {
 522   struct argbuf argbuf;
 523 };
 524
 525 /* Macros to simplify extraction, reading and semantic code.
 526    These define and assign the local vars that contain the insn's fields.  */
 527
 528 #define EXTRACT_FMT_ADD_VARS \
 529   /* Instruction fields.  */ \
 530   UINT f_op1; \
 531   UINT f_r1; \
 532   UINT f_op2; \
 533   UINT f_r2; \
 534   unsigned int length;
 535 #define EXTRACT_FMT_ADD_CODE \
 536   length = 2; \
 537   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 538   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 539   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 540   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 541
 542 #define EXTRACT_FMT_ADD3_VARS \
 543   /* Instruction fields.  */ \
 544   UINT f_op1; \
 545   UINT f_r1; \
 546   UINT f_op2; \
 547   UINT f_r2; \
 548   int f_simm16; \
 549   unsigned int length;
 550 #define EXTRACT_FMT_ADD3_CODE \
 551   length = 4; \
 552   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 553   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 554   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 555   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 556   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 557
 558 #define EXTRACT_FMT_AND3_VARS \
 559   /* Instruction fields.  */ \
 560   UINT f_op1; \
 561   UINT f_r1; \
 562   UINT f_op2; \
 563   UINT f_r2; \
 564   UINT f_uimm16; \
 565   unsigned int length;
 566 #define EXTRACT_FMT_AND3_CODE \
 567   length = 4; \
 568   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 569   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 570   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 571   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 572   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 573
 574 #define EXTRACT_FMT_OR3_VARS \
 575   /* Instruction fields.  */ \
 576   UINT f_op1; \
 577   UINT f_r1; \
 578   UINT f_op2; \
 579   UINT f_r2; \
 580   UINT f_uimm16; \
 581   unsigned int length;
 582 #define EXTRACT_FMT_OR3_CODE \
 583   length = 4; \
 584   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 585   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 586   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 587   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 588   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 589
 590 #define EXTRACT_FMT_ADDI_VARS \
 591   /* Instruction fields.  */ \
 592   UINT f_op1; \
 593   UINT f_r1; \
 594   int f_simm8; \
 595   unsigned int length;
 596 #define EXTRACT_FMT_ADDI_CODE \
 597   length = 2; \
 598   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 599   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 600   f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
 601
 602 #define EXTRACT_FMT_ADDV_VARS \
 603   /* Instruction fields.  */ \
 604   UINT f_op1; \
 605   UINT f_r1; \
 606   UINT f_op2; \
 607   UINT f_r2; \
 608   unsigned int length;
 609 #define EXTRACT_FMT_ADDV_CODE \
 610   length = 2; \
 611   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 612   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 613   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 614   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 615
 616 #define EXTRACT_FMT_ADDV3_VARS \
 617   /* Instruction fields.  */ \
 618   UINT f_op1; \
 619   UINT f_r1; \
 620   UINT f_op2; \
 621   UINT f_r2; \
 622   int f_simm16; \
 623   unsigned int length;
 624 #define EXTRACT_FMT_ADDV3_CODE \
 625   length = 4; \
 626   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 627   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 628   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 629   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 630   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 631
 632 #define EXTRACT_FMT_ADDX_VARS \
 633   /* Instruction fields.  */ \
 634   UINT f_op1; \
 635   UINT f_r1; \
 636   UINT f_op2; \
 637   UINT f_r2; \
 638   unsigned int length;
 639 #define EXTRACT_FMT_ADDX_CODE \
 640   length = 2; \
 641   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 642   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 643   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 644   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 645
 646 #define EXTRACT_FMT_BC8_VARS \
 647   /* Instruction fields.  */ \
 648   UINT f_op1; \
 649   UINT f_r1; \
 650   int f_disp8; \
 651   unsigned int length;
 652 #define EXTRACT_FMT_BC8_CODE \
 653   length = 2; \
 654   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 655   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 656   f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 657
 658 #define EXTRACT_FMT_BC24_VARS \
 659   /* Instruction fields.  */ \
 660   UINT f_op1; \
 661   UINT f_r1; \
 662   int f_disp24; \
 663   unsigned int length;
 664 #define EXTRACT_FMT_BC24_CODE \
 665   length = 4; \
 666   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 667   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 668   f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
 669
 670 #define EXTRACT_FMT_BEQ_VARS \
 671   /* Instruction fields.  */ \
 672   UINT f_op1; \
 673   UINT f_r1; \
 674   UINT f_op2; \
 675   UINT f_r2; \
 676   int f_disp16; \
 677   unsigned int length;
 678 #define EXTRACT_FMT_BEQ_CODE \
 679   length = 4; \
 680   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 681   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 682   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 683   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 684   f_disp16 = ((((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2))) + (pc)); \
 685
 686 #define EXTRACT_FMT_BEQZ_VARS \
 687   /* Instruction fields.  */ \
 688   UINT f_op1; \
 689   UINT f_r1; \
 690   UINT f_op2; \
 691   UINT f_r2; \
 692   int f_disp16; \
 693   unsigned int length;
 694 #define EXTRACT_FMT_BEQZ_CODE \
 695   length = 4; \
 696   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 697   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 698   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 699   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 700   f_disp16 = ((((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2))) + (pc)); \
 701
 702 #define EXTRACT_FMT_BL8_VARS \
 703   /* Instruction fields.  */ \
 704   UINT f_op1; \
 705   UINT f_r1; \
 706   int f_disp8; \
 707   unsigned int length;
 708 #define EXTRACT_FMT_BL8_CODE \
 709   length = 2; \
 710   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 711   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 712   f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 713
 714 #define EXTRACT_FMT_BL24_VARS \
 715   /* Instruction fields.  */ \
 716   UINT f_op1; \
 717   UINT f_r1; \
 718   int f_disp24; \
 719   unsigned int length;
 720 #define EXTRACT_FMT_BL24_CODE \
 721   length = 4; \
 722   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 723   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 724   f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
 725
 726 #define EXTRACT_FMT_BCL8_VARS \
 727   /* Instruction fields.  */ \
 728   UINT f_op1; \
 729   UINT f_r1; \
 730   int f_disp8; \
 731   unsigned int length;
 732 #define EXTRACT_FMT_BCL8_CODE \
 733   length = 2; \
 734   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 735   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 736   f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 737
 738 #define EXTRACT_FMT_BCL24_VARS \
 739   /* Instruction fields.  */ \
 740   UINT f_op1; \
 741   UINT f_r1; \
 742   int f_disp24; \
 743   unsigned int length;
 744 #define EXTRACT_FMT_BCL24_CODE \
 745   length = 4; \
 746   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 747   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 748   f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
 749
 750 #define EXTRACT_FMT_BRA8_VARS \
 751   /* Instruction fields.  */ \
 752   UINT f_op1; \
 753   UINT f_r1; \
 754   int f_disp8; \
 755   unsigned int length;
 756 #define EXTRACT_FMT_BRA8_CODE \
 757   length = 2; \
 758   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 759   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 760   f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 761
 762 #define EXTRACT_FMT_BRA24_VARS \
 763   /* Instruction fields.  */ \
 764   UINT f_op1; \
 765   UINT f_r1; \
 766   int f_disp24; \
 767   unsigned int length;
 768 #define EXTRACT_FMT_BRA24_CODE \
 769   length = 4; \
 770   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 771   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 772   f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
 773
 774 #define EXTRACT_FMT_CMP_VARS \
 775   /* Instruction fields.  */ \
 776   UINT f_op1; \
 777   UINT f_r1; \
 778   UINT f_op2; \
 779   UINT f_r2; \
 780   unsigned int length;
 781 #define EXTRACT_FMT_CMP_CODE \
 782   length = 2; \
 783   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 784   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 785   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 786   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 787
 788 #define EXTRACT_FMT_CMPI_VARS \
 789   /* Instruction fields.  */ \
 790   UINT f_op1; \
 791   UINT f_r1; \
 792   UINT f_op2; \
 793   UINT f_r2; \
 794   int f_simm16; \
 795   unsigned int length;
 796 #define EXTRACT_FMT_CMPI_CODE \
 797   length = 4; \
 798   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 799   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 800   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 801   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 802   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 803
 804 #define EXTRACT_FMT_CMPZ_VARS \
 805   /* Instruction fields.  */ \
 806   UINT f_op1; \
 807   UINT f_r1; \
 808   UINT f_op2; \
 809   UINT f_r2; \
 810   unsigned int length;
 811 #define EXTRACT_FMT_CMPZ_CODE \
 812   length = 2; \
 813   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 814   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 815   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 816   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 817
 818 #define EXTRACT_FMT_DIV_VARS \
 819   /* Instruction fields.  */ \
 820   UINT f_op1; \
 821   UINT f_r1; \
 822   UINT f_op2; \
 823   UINT f_r2; \
 824   int f_simm16; \
 825   unsigned int length;
 826 #define EXTRACT_FMT_DIV_CODE \
 827   length = 4; \
 828   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 829   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 830   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 831   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 832   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 833
 834 #define EXTRACT_FMT_JC_VARS \
 835   /* Instruction fields.  */ \
 836   UINT f_op1; \
 837   UINT f_r1; \
 838   UINT f_op2; \
 839   UINT f_r2; \
 840   unsigned int length;
 841 #define EXTRACT_FMT_JC_CODE \
 842   length = 2; \
 843   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 844   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 845   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 846   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 847
 848 #define EXTRACT_FMT_JL_VARS \
 849   /* Instruction fields.  */ \
 850   UINT f_op1; \
 851   UINT f_r1; \
 852   UINT f_op2; \
 853   UINT f_r2; \
 854   unsigned int length;
 855 #define EXTRACT_FMT_JL_CODE \
 856   length = 2; \
 857   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 858   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 859   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 860   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 861
 862 #define EXTRACT_FMT_JMP_VARS \
 863   /* Instruction fields.  */ \
 864   UINT f_op1; \
 865   UINT f_r1; \
 866   UINT f_op2; \
 867   UINT f_r2; \
 868   unsigned int length;
 869 #define EXTRACT_FMT_JMP_CODE \
 870   length = 2; \
 871   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 872   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 873   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 874   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 875
 876 #define EXTRACT_FMT_LD_VARS \
 877   /* Instruction fields.  */ \
 878   UINT f_op1; \
 879   UINT f_r1; \
 880   UINT f_op2; \
 881   UINT f_r2; \
 882   unsigned int length;
 883 #define EXTRACT_FMT_LD_CODE \
 884   length = 2; \
 885   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 886   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 887   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 888   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 889
 890 #define EXTRACT_FMT_LD_D_VARS \
 891   /* Instruction fields.  */ \
 892   UINT f_op1; \
 893   UINT f_r1; \
 894   UINT f_op2; \
 895   UINT f_r2; \
 896   int f_simm16; \
 897   unsigned int length;
 898 #define EXTRACT_FMT_LD_D_CODE \
 899   length = 4; \
 900   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 901   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 902   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 903   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 904   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 905
 906 #define EXTRACT_FMT_LDB_VARS \
 907   /* Instruction fields.  */ \
 908   UINT f_op1; \
 909   UINT f_r1; \
 910   UINT f_op2; \
 911   UINT f_r2; \
 912   unsigned int length;
 913 #define EXTRACT_FMT_LDB_CODE \
 914   length = 2; \
 915   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 916   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 917   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 918   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 919
 920 #define EXTRACT_FMT_LDB_D_VARS \
 921   /* Instruction fields.  */ \
 922   UINT f_op1; \
 923   UINT f_r1; \
 924   UINT f_op2; \
 925   UINT f_r2; \
 926   int f_simm16; \
 927   unsigned int length;
 928 #define EXTRACT_FMT_LDB_D_CODE \
 929   length = 4; \
 930   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 931   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 932   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 933   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 934   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 935
 936 #define EXTRACT_FMT_LDH_VARS \
 937   /* Instruction fields.  */ \
 938   UINT f_op1; \
 939   UINT f_r1; \
 940   UINT f_op2; \
 941   UINT f_r2; \
 942   unsigned int length;
 943 #define EXTRACT_FMT_LDH_CODE \
 944   length = 2; \
 945   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 946   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 947   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 948   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 949
 950 #define EXTRACT_FMT_LDH_D_VARS \
 951   /* Instruction fields.  */ \
 952   UINT f_op1; \
 953   UINT f_r1; \
 954   UINT f_op2; \
 955   UINT f_r2; \
 956   int f_simm16; \
 957   unsigned int length;
 958 #define EXTRACT_FMT_LDH_D_CODE \
 959   length = 4; \
 960   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 961   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 962   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 963   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 964   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 965
 966 #define EXTRACT_FMT_LD_PLUS_VARS \
 967   /* Instruction fields.  */ \
 968   UINT f_op1; \
 969   UINT f_r1; \
 970   UINT f_op2; \
 971   UINT f_r2; \
 972   unsigned int length;
 973 #define EXTRACT_FMT_LD_PLUS_CODE \
 974   length = 2; \
 975   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 976   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 977   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 978   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 979
 980 #define EXTRACT_FMT_LD24_VARS \
 981   /* Instruction fields.  */ \
 982   UINT f_op1; \
 983   UINT f_r1; \
 984   UINT f_uimm24; \
 985   unsigned int length;
 986 #define EXTRACT_FMT_LD24_CODE \
 987   length = 4; \
 988   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 989   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 990   f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
 991
 992 #define EXTRACT_FMT_LDI8_VARS \
 993   /* Instruction fields.  */ \
 994   UINT f_op1; \
 995   UINT f_r1; \
 996   int f_simm8; \
 997   unsigned int length;
 998 #define EXTRACT_FMT_LDI8_CODE \
 999   length = 2; \
1000   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1001   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1002   f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
1003
1004 #define EXTRACT_FMT_LDI16_VARS \
1005   /* Instruction fields.  */ \
1006   UINT f_op1; \
1007   UINT f_r1; \
1008   UINT f_op2; \
1009   UINT f_r2; \
1010   int f_simm16; \
1011   unsigned int length;
1012 #define EXTRACT_FMT_LDI16_CODE \
1013   length = 4; \
1014   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1015   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1016   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1017   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1018   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1019
1020 #define EXTRACT_FMT_LOCK_VARS \
1021   /* Instruction fields.  */ \
1022   UINT f_op1; \
1023   UINT f_r1; \
1024   UINT f_op2; \
1025   UINT f_r2; \
1026   unsigned int length;
1027 #define EXTRACT_FMT_LOCK_CODE \
1028   length = 2; \
1029   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1030   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1031   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1032   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1033
1034 #define EXTRACT_FMT_MACHI_A_VARS \
1035   /* Instruction fields.  */ \
1036   UINT f_op1; \
1037   UINT f_r1; \
1038   UINT f_acc; \
1039   UINT f_op23; \
1040   UINT f_r2; \
1041   unsigned int length;
1042 #define EXTRACT_FMT_MACHI_A_CODE \
1043   length = 2; \
1044   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1045   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1046   f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
1047   f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
1048   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1049
1050 #define EXTRACT_FMT_MULHI_A_VARS \
1051   /* Instruction fields.  */ \
1052   UINT f_op1; \
1053   UINT f_r1; \
1054   UINT f_acc; \
1055   UINT f_op23; \
1056   UINT f_r2; \
1057   unsigned int length;
1058 #define EXTRACT_FMT_MULHI_A_CODE \
1059   length = 2; \
1060   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1061   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1062   f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
1063   f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
1064   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1065
1066 #define EXTRACT_FMT_MV_VARS \
1067   /* Instruction fields.  */ \
1068   UINT f_op1; \
1069   UINT f_r1; \
1070   UINT f_op2; \
1071   UINT f_r2; \
1072   unsigned int length;
1073 #define EXTRACT_FMT_MV_CODE \
1074   length = 2; \
1075   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1076   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1077   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1078   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1079
1080 #define EXTRACT_FMT_MVFACHI_A_VARS \
1081   /* Instruction fields.  */ \
1082   UINT f_op1; \
1083   UINT f_r1; \
1084   UINT f_op2; \
1085   UINT f_accs; \
1086   UINT f_op3; \
1087   unsigned int length;
1088 #define EXTRACT_FMT_MVFACHI_A_CODE \
1089   length = 2; \
1090   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1091   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1092   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1093   f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1094   f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
1095
1096 #define EXTRACT_FMT_MVFC_VARS \
1097   /* Instruction fields.  */ \
1098   UINT f_op1; \
1099   UINT f_r1; \
1100   UINT f_op2; \
1101   UINT f_r2; \
1102   unsigned int length;
1103 #define EXTRACT_FMT_MVFC_CODE \
1104   length = 2; \
1105   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1106   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1107   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1108   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1109
1110 #define EXTRACT_FMT_MVTACHI_A_VARS \
1111   /* Instruction fields.  */ \
1112   UINT f_op1; \
1113   UINT f_r1; \
1114   UINT f_op2; \
1115   UINT f_accs; \
1116   UINT f_op3; \
1117   unsigned int length;
1118 #define EXTRACT_FMT_MVTACHI_A_CODE \
1119   length = 2; \
1120   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1121   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1122   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1123   f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1124   f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
1125
1126 #define EXTRACT_FMT_MVTC_VARS \
1127   /* Instruction fields.  */ \
1128   UINT f_op1; \
1129   UINT f_r1; \
1130   UINT f_op2; \
1131   UINT f_r2; \
1132   unsigned int length;
1133 #define EXTRACT_FMT_MVTC_CODE \
1134   length = 2; \
1135   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1136   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1137   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1138   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1139
1140 #define EXTRACT_FMT_NOP_VARS \
1141   /* Instruction fields.  */ \
1142   UINT f_op1; \
1143   UINT f_r1; \
1144   UINT f_op2; \
1145   UINT f_r2; \
1146   unsigned int length;
1147 #define EXTRACT_FMT_NOP_CODE \
1148   length = 2; \
1149   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1150   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1151   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1152   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1153
1154 #define EXTRACT_FMT_RAC_DSI_VARS \
1155   /* Instruction fields.  */ \
1156   UINT f_op1; \
1157   UINT f_accd; \
1158   UINT f_bits67; \
1159   UINT f_op2; \
1160   UINT f_accs; \
1161   UINT f_bit14; \
1162   UINT f_imm1; \
1163   unsigned int length;
1164 #define EXTRACT_FMT_RAC_DSI_CODE \
1165   length = 2; \
1166   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1167   f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \
1168   f_bits67 = EXTRACT_UNSIGNED (insn, 16, 6, 2); \
1169   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1170   f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1171   f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \
1172   f_imm1 = ((EXTRACT_UNSIGNED (insn, 16, 15, 1)) + (1)); \
1173
1174 #define EXTRACT_FMT_RTE_VARS \
1175   /* Instruction fields.  */ \
1176   UINT f_op1; \
1177   UINT f_r1; \
1178   UINT f_op2; \
1179   UINT f_r2; \
1180   unsigned int length;
1181 #define EXTRACT_FMT_RTE_CODE \
1182   length = 2; \
1183   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1184   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1185   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1186   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1187
1188 #define EXTRACT_FMT_SETH_VARS \
1189   /* Instruction fields.  */ \
1190   UINT f_op1; \
1191   UINT f_r1; \
1192   UINT f_op2; \
1193   UINT f_r2; \
1194   UINT f_hi16; \
1195   unsigned int length;
1196 #define EXTRACT_FMT_SETH_CODE \
1197   length = 4; \
1198   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1199   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1200   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1201   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1202   f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1203
1204 #define EXTRACT_FMT_SLL3_VARS \
1205   /* Instruction fields.  */ \
1206   UINT f_op1; \
1207   UINT f_r1; \
1208   UINT f_op2; \
1209   UINT f_r2; \
1210   int f_simm16; \
1211   unsigned int length;
1212 #define EXTRACT_FMT_SLL3_CODE \
1213   length = 4; \
1214   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1215   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1216   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1217   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1218   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1219
1220 #define EXTRACT_FMT_SLLI_VARS \
1221   /* Instruction fields.  */ \
1222   UINT f_op1; \
1223   UINT f_r1; \
1224   UINT f_shift_op2; \
1225   UINT f_uimm5; \
1226   unsigned int length;
1227 #define EXTRACT_FMT_SLLI_CODE \
1228   length = 2; \
1229   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1230   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1231   f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
1232   f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
1233
1234 #define EXTRACT_FMT_ST_VARS \
1235   /* Instruction fields.  */ \
1236   UINT f_op1; \
1237   UINT f_r1; \
1238   UINT f_op2; \
1239   UINT f_r2; \
1240   unsigned int length;
1241 #define EXTRACT_FMT_ST_CODE \
1242   length = 2; \
1243   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1244   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1245   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1246   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1247
1248 #define EXTRACT_FMT_ST_D_VARS \
1249   /* Instruction fields.  */ \
1250   UINT f_op1; \
1251   UINT f_r1; \
1252   UINT f_op2; \
1253   UINT f_r2; \
1254   int f_simm16; \
1255   unsigned int length;
1256 #define EXTRACT_FMT_ST_D_CODE \
1257   length = 4; \
1258   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1259   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1260   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1261   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1262   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1263
1264 #define EXTRACT_FMT_STB_VARS \
1265   /* Instruction fields.  */ \
1266   UINT f_op1; \
1267   UINT f_r1; \
1268   UINT f_op2; \
1269   UINT f_r2; \
1270   unsigned int length;
1271 #define EXTRACT_FMT_STB_CODE \
1272   length = 2; \
1273   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1274   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1275   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1276   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1277
1278 #define EXTRACT_FMT_STB_D_VARS \
1279   /* Instruction fields.  */ \
1280   UINT f_op1; \
1281   UINT f_r1; \
1282   UINT f_op2; \
1283   UINT f_r2; \
1284   int f_simm16; \
1285   unsigned int length;
1286 #define EXTRACT_FMT_STB_D_CODE \
1287   length = 4; \
1288   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1289   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1290   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1291   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1292   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1293
1294 #define EXTRACT_FMT_STH_VARS \
1295   /* Instruction fields.  */ \
1296   UINT f_op1; \
1297   UINT f_r1; \
1298   UINT f_op2; \
1299   UINT f_r2; \
1300   unsigned int length;
1301 #define EXTRACT_FMT_STH_CODE \
1302   length = 2; \
1303   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1304   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1305   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1306   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1307
1308 #define EXTRACT_FMT_STH_D_VARS \
1309   /* Instruction fields.  */ \
1310   UINT f_op1; \
1311   UINT f_r1; \
1312   UINT f_op2; \
1313   UINT f_r2; \
1314   int f_simm16; \
1315   unsigned int length;
1316 #define EXTRACT_FMT_STH_D_CODE \
1317   length = 4; \
1318   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1319   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1320   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1321   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1322   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1323
1324 #define EXTRACT_FMT_ST_PLUS_VARS \
1325   /* Instruction fields.  */ \
1326   UINT f_op1; \
1327   UINT f_r1; \
1328   UINT f_op2; \
1329   UINT f_r2; \
1330   unsigned int length;
1331 #define EXTRACT_FMT_ST_PLUS_CODE \
1332   length = 2; \
1333   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1334   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1335   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1336   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1337
1338 #define EXTRACT_FMT_TRAP_VARS \
1339   /* Instruction fields.  */ \
1340   UINT f_op1; \
1341   UINT f_r1; \
1342   UINT f_op2; \
1343   UINT f_uimm4; \
1344   unsigned int length;
1345 #define EXTRACT_FMT_TRAP_CODE \
1346   length = 2; \
1347   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1348   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1349   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1350   f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1351
1352 #define EXTRACT_FMT_UNLOCK_VARS \
1353   /* Instruction fields.  */ \
1354   UINT f_op1; \
1355   UINT f_r1; \
1356   UINT f_op2; \
1357   UINT f_r2; \
1358   unsigned int length;
1359 #define EXTRACT_FMT_UNLOCK_CODE \
1360   length = 2; \
1361   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1362   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1363   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1364   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1365
1366 #define EXTRACT_FMT_SATB_VARS \
1367   /* Instruction fields.  */ \
1368   UINT f_op1; \
1369   UINT f_r1; \
1370   UINT f_op2; \
1371   UINT f_r2; \
1372   UINT f_uimm16; \
1373   unsigned int length;
1374 #define EXTRACT_FMT_SATB_CODE \
1375   length = 4; \
1376   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1377   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1378   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1379   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1380   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1381
1382 #define EXTRACT_FMT_SAT_VARS \
1383   /* Instruction fields.  */ \
1384   UINT f_op1; \
1385   UINT f_r1; \
1386   UINT f_op2; \
1387   UINT f_r2; \
1388   UINT f_uimm16; \
1389   unsigned int length;
1390 #define EXTRACT_FMT_SAT_CODE \
1391   length = 4; \
1392   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1393   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1394   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1395   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1396   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1397
1398 #define EXTRACT_FMT_SADD_VARS \
1399   /* Instruction fields.  */ \
1400   UINT f_op1; \
1401   UINT f_r1; \
1402   UINT f_op2; \
1403   UINT f_r2; \
1404   unsigned int length;
1405 #define EXTRACT_FMT_SADD_CODE \
1406   length = 2; \
1407   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1408   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1409   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1410   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1411
1412 #define EXTRACT_FMT_MACWU1_VARS \
1413   /* Instruction fields.  */ \
1414   UINT f_op1; \
1415   UINT f_r1; \
1416   UINT f_op2; \
1417   UINT f_r2; \
1418   unsigned int length;
1419 #define EXTRACT_FMT_MACWU1_CODE \
1420   length = 2; \
1421   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1422   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1423   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1424   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1425
1426 #define EXTRACT_FMT_MSBLO_VARS \
1427   /* Instruction fields.  */ \
1428   UINT f_op1; \
1429   UINT f_r1; \
1430   UINT f_op2; \
1431   UINT f_r2; \
1432   unsigned int length;
1433 #define EXTRACT_FMT_MSBLO_CODE \
1434   length = 2; \
1435   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1436   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1437   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1438   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1439
1440 #define EXTRACT_FMT_MULWU1_VARS \
1441   /* Instruction fields.  */ \
1442   UINT f_op1; \
1443   UINT f_r1; \
1444   UINT f_op2; \
1445   UINT f_r2; \
1446   unsigned int length;
1447 #define EXTRACT_FMT_MULWU1_CODE \
1448   length = 2; \
1449   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1450   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1451   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1452   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1453
1454 #define EXTRACT_FMT_SC_VARS \
1455   /* Instruction fields.  */ \
1456   UINT f_op1; \
1457   UINT f_r1; \
1458   UINT f_op2; \
1459   UINT f_r2; \
1460   unsigned int length;
1461 #define EXTRACT_FMT_SC_CODE \
1462   length = 2; \
1463   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1464   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1465   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1466   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1467
1468 /* Queued output values of an instruction.  */
1469
1470 struct parexec {
1471   union {
1472     struct { /* e.g. add $dr,$sr */
1473       SI dr;
1474     } fmt_add;
1475     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
1476       SI dr;
1477     } fmt_add3;
1478     struct { /* e.g. and3 $dr,$sr,$uimm16 */
1479       SI dr;
1480     } fmt_and3;
1481     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
1482       SI dr;
1483     } fmt_or3;
1484     struct { /* e.g. addi $dr,$simm8 */
1485       SI dr;
1486     } fmt_addi;
1487     struct { /* e.g. addv $dr,$sr */
1488       SI dr;
1489       BI condbit;
1490     } fmt_addv;
1491     struct { /* e.g. addv3 $dr,$sr,$simm16 */
1492       SI dr;
1493       BI condbit;
1494     } fmt_addv3;
1495     struct { /* e.g. addx $dr,$sr */
1496       SI dr;
1497       BI condbit;
1498     } fmt_addx;
1499     struct { /* e.g. bc.s $disp8 */
1500       USI pc;
1501     } fmt_bc8;
1502     struct { /* e.g. bc.l $disp24 */
1503       USI pc;
1504     } fmt_bc24;
1505     struct { /* e.g. beq $src1,$src2,$disp16 */
1506       USI pc;
1507     } fmt_beq;
1508     struct { /* e.g. beqz $src2,$disp16 */
1509       USI pc;
1510     } fmt_beqz;
1511     struct { /* e.g. bl.s $disp8 */
1512       SI h_gr_14;
1513       USI pc;
1514     } fmt_bl8;
1515     struct { /* e.g. bl.l $disp24 */
1516       SI h_gr_14;
1517       USI pc;
1518     } fmt_bl24;
1519     struct { /* e.g. bcl.s $disp8 */
1520       SI h_gr_14;
1521       USI pc;
1522     } fmt_bcl8;
1523     struct { /* e.g. bcl.l $disp24 */
1524       SI h_gr_14;
1525       USI pc;
1526     } fmt_bcl24;
1527     struct { /* e.g. bra.s $disp8 */
1528       USI pc;
1529     } fmt_bra8;
1530     struct { /* e.g. bra.l $disp24 */
1531       USI pc;
1532     } fmt_bra24;
1533     struct { /* e.g. cmp $src1,$src2 */
1534       BI condbit;
1535     } fmt_cmp;
1536     struct { /* e.g. cmpi $src2,$simm16 */
1537       BI condbit;
1538     } fmt_cmpi;
1539     struct { /* e.g. cmpz $src2 */
1540       BI condbit;
1541     } fmt_cmpz;
1542     struct { /* e.g. div $dr,$sr */
1543       SI dr;
1544     } fmt_div;
1545     struct { /* e.g. jc $sr */
1546       USI pc;
1547     } fmt_jc;
1548     struct { /* e.g. jl $sr */
1549       SI h_gr_14;
1550       USI pc;
1551     } fmt_jl;
1552     struct { /* e.g. jmp $sr */
1553       USI pc;
1554     } fmt_jmp;
1555     struct { /* e.g. ld $dr,@$sr */
1556       SI dr;
1557     } fmt_ld;
1558     struct { /* e.g. ld $dr,@($slo16,$sr) */
1559       SI dr;
1560     } fmt_ld_d;
1561     struct { /* e.g. ldb $dr,@$sr */
1562       SI dr;
1563     } fmt_ldb;
1564     struct { /* e.g. ldb $dr,@($slo16,$sr) */
1565       SI dr;
1566     } fmt_ldb_d;
1567     struct { /* e.g. ldh $dr,@$sr */
1568       SI dr;
1569     } fmt_ldh;
1570     struct { /* e.g. ldh $dr,@($slo16,$sr) */
1571       SI dr;
1572     } fmt_ldh_d;
1573     struct { /* e.g. ld $dr,@$sr+ */
1574       SI dr;
1575       SI sr;
1576     } fmt_ld_plus;
1577     struct { /* e.g. ld24 $dr,$uimm24 */
1578       SI dr;
1579     } fmt_ld24;
1580     struct { /* e.g. ldi8 $dr,$simm8 */
1581       SI dr;
1582     } fmt_ldi8;
1583     struct { /* e.g. ldi16 $dr,$hash$slo16 */
1584       SI dr;
1585     } fmt_ldi16;
1586     struct { /* e.g. lock $dr,@$sr */
1587       BI h_lock_0;
1588       SI dr;
1589     } fmt_lock;
1590     struct { /* e.g. machi $src1,$src2,$acc */
1591       DI acc;
1592     } fmt_machi_a;
1593     struct { /* e.g. mulhi $src1,$src2,$acc */
1594       DI acc;
1595     } fmt_mulhi_a;
1596     struct { /* e.g. mv $dr,$sr */
1597       SI dr;
1598     } fmt_mv;
1599     struct { /* e.g. mvfachi $dr,$accs */
1600       SI dr;
1601     } fmt_mvfachi_a;
1602     struct { /* e.g. mvfc $dr,$scr */
1603       SI dr;
1604     } fmt_mvfc;
1605     struct { /* e.g. mvtachi $src1,$accs */
1606       DI accs;
1607     } fmt_mvtachi_a;
1608     struct { /* e.g. mvtc $sr,$dcr */
1609       USI dcr;
1610     } fmt_mvtc;
1611     struct { /* e.g. nop */
1612       int empty;
1613     } fmt_nop;
1614     struct { /* e.g. rac $accd,$accs,$imm1 */
1615       DI accd;
1616     } fmt_rac_dsi;
1617     struct { /* e.g. rte */
1618       USI pc;
1619       USI h_cr_6;
1620       UQI h_psw_0;
1621       UQI h_bpsw_0;
1622     } fmt_rte;
1623     struct { /* e.g. seth $dr,$hash$hi16 */
1624       SI dr;
1625     } fmt_seth;
1626     struct { /* e.g. sll3 $dr,$sr,$simm16 */
1627       SI dr;
1628     } fmt_sll3;
1629     struct { /* e.g. slli $dr,$uimm5 */
1630       SI dr;
1631     } fmt_slli;
1632     struct { /* e.g. st $src1,@$src2 */
1633       SI h_memory_src2;
1634       USI h_memory_src2_idx;
1635     } fmt_st;
1636     struct { /* e.g. st $src1,@($slo16,$src2) */
1637       SI h_memory_add__VM_src2_slo16;
1638       USI h_memory_add__VM_src2_slo16_idx;
1639     } fmt_st_d;
1640     struct { /* e.g. stb $src1,@$src2 */
1641       QI h_memory_src2;
1642       USI h_memory_src2_idx;
1643     } fmt_stb;
1644     struct { /* e.g. stb $src1,@($slo16,$src2) */
1645       QI h_memory_add__VM_src2_slo16;
1646       USI h_memory_add__VM_src2_slo16_idx;
1647     } fmt_stb_d;
1648     struct { /* e.g. sth $src1,@$src2 */
1649       HI h_memory_src2;
1650       USI h_memory_src2_idx;
1651     } fmt_sth;
1652     struct { /* e.g. sth $src1,@($slo16,$src2) */
1653       HI h_memory_add__VM_src2_slo16;
1654       USI h_memory_add__VM_src2_slo16_idx;
1655     } fmt_sth_d;
1656     struct { /* e.g. st $src1,@+$src2 */
1657       SI h_memory_new_src2;
1658       USI h_memory_new_src2_idx;
1659       SI src2;
1660     } fmt_st_plus;
1661     struct { /* e.g. trap $uimm4 */
1662       USI h_cr_14;
1663       USI h_cr_6;
1664       UQI h_bbpsw_0;
1665       UQI h_bpsw_0;
1666       UQI h_psw_0;
1667       SI pc;
1668     } fmt_trap;
1669     struct { /* e.g. unlock $src1,@$src2 */
1670       SI h_memory_src2;
1671       USI h_memory_src2_idx;
1672       BI h_lock_0;
1673     } fmt_unlock;
1674     struct { /* e.g. satb $dr,$sr */
1675       SI dr;
1676     } fmt_satb;
1677     struct { /* e.g. sat $dr,$sr */
1678       SI dr;
1679     } fmt_sat;
1680     struct { /* e.g. sadd */
1681       DI h_accums_0;
1682     } fmt_sadd;
1683     struct { /* e.g. macwu1 $src1,$src2 */
1684       DI h_accums_1;
1685     } fmt_macwu1;
1686     struct { /* e.g. msblo $src1,$src2 */
1687       DI accum;
1688     } fmt_msblo;
1689     struct { /* e.g. mulwu1 $src1,$src2 */
1690       DI h_accums_1;
1691     } fmt_mulwu1;
1692     struct { /* e.g. sc */
1693       int empty;
1694     } fmt_sc;
1695   } operands;
1696   /* For conditionally written operands, bitmask of which ones were.  */
1697   int written;
1698 };
1699
1700 #endif /* CPU_M32RXF_H */