]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/m32r/decode2.c
projects / thirdparty / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Add support for the m32r2 processor
[thirdparty/binutils-gdb.git] / sim / m32r / decode2.c
1 /* Simulator instruction decoder for m32r2f.
2
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6
7 This file is part of the GNU simulators.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23 */
24
25 #define WANT_CPU m32r2f
26 #define WANT_CPU_M32R2F
27
28 #include "sim-main.h"
29 #include "sim-assert.h"
30
31 /* Insn can't be executed in parallel.
32 Or is that "do NOt Pass to Air defense Radar"? :-) */
33 #define NOPAR (-1)
34
35 /* The instruction descriptor array.
36 This is computed at runtime. Space for it is not malloc'd to save a
37 teensy bit of cpu in the decoder. Moving it to malloc space is trivial
38 but won't be done until necessary (we don't currently support the runtime
39 addition of instructions nor an SMP machine with different cpus). */
40 static IDESC m32r2f_insn_data[M32R2F_INSN__MAX];
41
42 /* Commas between elements are contained in the macros.
43 Some of these are conditionally compiled out. */
44
45 static const struct insn_sem m32r2f_insn_sem[] =
46 {
47 { VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR },
48 { VIRTUAL_INSN_X_AFTER, M32R2F_INSN_X_AFTER, M32R2F_SFMT_EMPTY, NOPAR, NOPAR },
49 { VIRTUAL_INSN_X_BEFORE, M32R2F_INSN_X_BEFORE, M32R2F_SFMT_EMPTY, NOPAR, NOPAR },
50 { VIRTUAL_INSN_X_CTI_CHAIN, M32R2F_INSN_X_CTI_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR },
51 { VIRTUAL_INSN_X_CHAIN, M32R2F_INSN_X_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR },
52 { VIRTUAL_INSN_X_BEGIN, M32R2F_INSN_X_BEGIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR },
53 { M32R_INSN_ADD, M32R2F_INSN_ADD, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_ADD, M32R2F_INSN_WRITE_ADD },
54 { M32R_INSN_ADD3, M32R2F_INSN_ADD3, M32R2F_SFMT_ADD3, NOPAR, NOPAR },
55 { M32R_INSN_AND, M32R2F_INSN_AND, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_AND, M32R2F_INSN_WRITE_AND },
56 { M32R_INSN_AND3, M32R2F_INSN_AND3, M32R2F_SFMT_AND3, NOPAR, NOPAR },
57 { M32R_INSN_OR, M32R2F_INSN_OR, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_OR, M32R2F_INSN_WRITE_OR },
58 { M32R_INSN_OR3, M32R2F_INSN_OR3, M32R2F_SFMT_OR3, NOPAR, NOPAR },
59 { M32R_INSN_XOR, M32R2F_INSN_XOR, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_XOR, M32R2F_INSN_WRITE_XOR },
60 { M32R_INSN_XOR3, M32R2F_INSN_XOR3, M32R2F_SFMT_AND3, NOPAR, NOPAR },
61 { M32R_INSN_ADDI, M32R2F_INSN_ADDI, M32R2F_SFMT_ADDI, M32R2F_INSN_PAR_ADDI, M32R2F_INSN_WRITE_ADDI },
62 { M32R_INSN_ADDV, M32R2F_INSN_ADDV, M32R2F_SFMT_ADDV, M32R2F_INSN_PAR_ADDV, M32R2F_INSN_WRITE_ADDV },
63 { M32R_INSN_ADDV3, M32R2F_INSN_ADDV3, M32R2F_SFMT_ADDV3, NOPAR, NOPAR },
64 { M32R_INSN_ADDX, M32R2F_INSN_ADDX, M32R2F_SFMT_ADDX, M32R2F_INSN_PAR_ADDX, M32R2F_INSN_WRITE_ADDX },
65 { M32R_INSN_BC8, M32R2F_INSN_BC8, M32R2F_SFMT_BC8, M32R2F_INSN_PAR_BC8, M32R2F_INSN_WRITE_BC8 },
66 { M32R_INSN_BC24, M32R2F_INSN_BC24, M32R2F_SFMT_BC24, NOPAR, NOPAR },
67 { M32R_INSN_BEQ, M32R2F_INSN_BEQ, M32R2F_SFMT_BEQ, NOPAR, NOPAR },
68 { M32R_INSN_BEQZ, M32R2F_INSN_BEQZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR },
69 { M32R_INSN_BGEZ, M32R2F_INSN_BGEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR },
70 { M32R_INSN_BGTZ, M32R2F_INSN_BGTZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR },
71 { M32R_INSN_BLEZ, M32R2F_INSN_BLEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR },
72 { M32R_INSN_BLTZ, M32R2F_INSN_BLTZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR },
73 { M32R_INSN_BNEZ, M32R2F_INSN_BNEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR },
74 { M32R_INSN_BL8, M32R2F_INSN_BL8, M32R2F_SFMT_BL8, M32R2F_INSN_PAR_BL8, M32R2F_INSN_WRITE_BL8 },
75 { M32R_INSN_BL24, M32R2F_INSN_BL24, M32R2F_SFMT_BL24, NOPAR, NOPAR },
76 { M32R_INSN_BCL8, M32R2F_INSN_BCL8, M32R2F_SFMT_BCL8, M32R2F_INSN_PAR_BCL8, M32R2F_INSN_WRITE_BCL8 },
77 { M32R_INSN_BCL24, M32R2F_INSN_BCL24, M32R2F_SFMT_BCL24, NOPAR, NOPAR },
78 { M32R_INSN_BNC8, M32R2F_INSN_BNC8, M32R2F_SFMT_BC8, M32R2F_INSN_PAR_BNC8, M32R2F_INSN_WRITE_BNC8 },
79 { M32R_INSN_BNC24, M32R2F_INSN_BNC24, M32R2F_SFMT_BC24, NOPAR, NOPAR },
80 { M32R_INSN_BNE, M32R2F_INSN_BNE, M32R2F_SFMT_BEQ, NOPAR, NOPAR },
81 { M32R_INSN_BRA8, M32R2F_INSN_BRA8, M32R2F_SFMT_BRA8, M32R2F_INSN_PAR_BRA8, M32R2F_INSN_WRITE_BRA8 },
82 { M32R_INSN_BRA24, M32R2F_INSN_BRA24, M32R2F_SFMT_BRA24, NOPAR, NOPAR },
83 { M32R_INSN_BNCL8, M32R2F_INSN_BNCL8, M32R2F_SFMT_BCL8, M32R2F_INSN_PAR_BNCL8, M32R2F_INSN_WRITE_BNCL8 },
84 { M32R_INSN_BNCL24, M32R2F_INSN_BNCL24, M32R2F_SFMT_BCL24, NOPAR, NOPAR },
85 { M32R_INSN_CMP, M32R2F_INSN_CMP, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMP, M32R2F_INSN_WRITE_CMP },
86 { M32R_INSN_CMPI, M32R2F_INSN_CMPI, M32R2F_SFMT_CMPI, NOPAR, NOPAR },
87 { M32R_INSN_CMPU, M32R2F_INSN_CMPU, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMPU, M32R2F_INSN_WRITE_CMPU },
88 { M32R_INSN_CMPUI, M32R2F_INSN_CMPUI, M32R2F_SFMT_CMPI, NOPAR, NOPAR },
89 { M32R_INSN_CMPEQ, M32R2F_INSN_CMPEQ, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMPEQ, M32R2F_INSN_WRITE_CMPEQ },
90 { M32R_INSN_CMPZ, M32R2F_INSN_CMPZ, M32R2F_SFMT_CMPZ, M32R2F_INSN_PAR_CMPZ, M32R2F_INSN_WRITE_CMPZ },
91 { M32R_INSN_DIV, M32R2F_INSN_DIV, M32R2F_SFMT_DIV, NOPAR, NOPAR },
92 { M32R_INSN_DIVU, M32R2F_INSN_DIVU, M32R2F_SFMT_DIV, NOPAR, NOPAR },
93 { M32R_INSN_REM, M32R2F_INSN_REM, M32R2F_SFMT_DIV, NOPAR, NOPAR },
94 { M32R_INSN_REMU, M32R2F_INSN_REMU, M32R2F_SFMT_DIV, NOPAR, NOPAR },
95 { M32R_INSN_REMH, M32R2F_INSN_REMH, M32R2F_SFMT_DIV, NOPAR, NOPAR },
96 { M32R_INSN_REMUH, M32R2F_INSN_REMUH, M32R2F_SFMT_DIV, NOPAR, NOPAR },
97 { M32R_INSN_REMB, M32R2F_INSN_REMB, M32R2F_SFMT_DIV, NOPAR, NOPAR },
98 { M32R_INSN_REMUB, M32R2F_INSN_REMUB, M32R2F_SFMT_DIV, NOPAR, NOPAR },
99 { M32R_INSN_DIVUH, M32R2F_INSN_DIVUH, M32R2F_SFMT_DIV, NOPAR, NOPAR },
100 { M32R_INSN_DIVB, M32R2F_INSN_DIVB, M32R2F_SFMT_DIV, NOPAR, NOPAR },
101 { M32R_INSN_DIVUB, M32R2F_INSN_DIVUB, M32R2F_SFMT_DIV, NOPAR, NOPAR },
102 { M32R_INSN_DIVH, M32R2F_INSN_DIVH, M32R2F_SFMT_DIV, NOPAR, NOPAR },
103 { M32R_INSN_JC, M32R2F_INSN_JC, M32R2F_SFMT_JC, M32R2F_INSN_PAR_JC, M32R2F_INSN_WRITE_JC },
104 { M32R_INSN_JNC, M32R2F_INSN_JNC, M32R2F_SFMT_JC, M32R2F_INSN_PAR_JNC, M32R2F_INSN_WRITE_JNC },
105 { M32R_INSN_JL, M32R2F_INSN_JL, M32R2F_SFMT_JL, M32R2F_INSN_PAR_JL, M32R2F_INSN_WRITE_JL },
106 { M32R_INSN_JMP, M32R2F_INSN_JMP, M32R2F_SFMT_JMP, M32R2F_INSN_PAR_JMP, M32R2F_INSN_WRITE_JMP },
107 { M32R_INSN_LD, M32R2F_INSN_LD, M32R2F_SFMT_LD, M32R2F_INSN_PAR_LD, M32R2F_INSN_WRITE_LD },
108 { M32R_INSN_LD_D, M32R2F_INSN_LD_D, M32R2F_SFMT_LD_D, NOPAR, NOPAR },
109 { M32R_INSN_LDB, M32R2F_INSN_LDB, M32R2F_SFMT_LDB, M32R2F_INSN_PAR_LDB, M32R2F_INSN_WRITE_LDB },
110 { M32R_INSN_LDB_D, M32R2F_INSN_LDB_D, M32R2F_SFMT_LDB_D, NOPAR, NOPAR },
111 { M32R_INSN_LDH, M32R2F_INSN_LDH, M32R2F_SFMT_LDH, M32R2F_INSN_PAR_LDH, M32R2F_INSN_WRITE_LDH },
112 { M32R_INSN_LDH_D, M32R2F_INSN_LDH_D, M32R2F_SFMT_LDH_D, NOPAR, NOPAR },
113 { M32R_INSN_LDUB, M32R2F_INSN_LDUB, M32R2F_SFMT_LDB, M32R2F_INSN_PAR_LDUB, M32R2F_INSN_WRITE_LDUB },
114 { M32R_INSN_LDUB_D, M32R2F_INSN_LDUB_D, M32R2F_SFMT_LDB_D, NOPAR, NOPAR },
115 { M32R_INSN_LDUH, M32R2F_INSN_LDUH, M32R2F_SFMT_LDH, M32R2F_INSN_PAR_LDUH, M32R2F_INSN_WRITE_LDUH },
116 { M32R_INSN_LDUH_D, M32R2F_INSN_LDUH_D, M32R2F_SFMT_LDH_D, NOPAR, NOPAR },
117 { M32R_INSN_LD_PLUS, M32R2F_INSN_LD_PLUS, M32R2F_SFMT_LD_PLUS, M32R2F_INSN_PAR_LD_PLUS, M32R2F_INSN_WRITE_LD_PLUS },
118 { M32R_INSN_LD24, M32R2F_INSN_LD24, M32R2F_SFMT_LD24, NOPAR, NOPAR },
119 { M32R_INSN_LDI8, M32R2F_INSN_LDI8, M32R2F_SFMT_LDI8, M32R2F_INSN_PAR_LDI8, M32R2F_INSN_WRITE_LDI8 },
120 { M32R_INSN_LDI16, M32R2F_INSN_LDI16, M32R2F_SFMT_LDI16, NOPAR, NOPAR },
121 { M32R_INSN_LOCK, M32R2F_INSN_LOCK, M32R2F_SFMT_LOCK, M32R2F_INSN_PAR_LOCK, M32R2F_INSN_WRITE_LOCK },
122 { M32R_INSN_MACHI_A, M32R2F_INSN_MACHI_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACHI_A, M32R2F_INSN_WRITE_MACHI_A },
123 { M32R_INSN_MACLO_A, M32R2F_INSN_MACLO_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACLO_A, M32R2F_INSN_WRITE_MACLO_A },
124 { M32R_INSN_MACWHI_A, M32R2F_INSN_MACWHI_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACWHI_A, M32R2F_INSN_WRITE_MACWHI_A },
125 { M32R_INSN_MACWLO_A, M32R2F_INSN_MACWLO_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACWLO_A, M32R2F_INSN_WRITE_MACWLO_A },
126 { M32R_INSN_MUL, M32R2F_INSN_MUL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_MUL, M32R2F_INSN_WRITE_MUL },
127 { M32R_INSN_MULHI_A, M32R2F_INSN_MULHI_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULHI_A, M32R2F_INSN_WRITE_MULHI_A },
128 { M32R_INSN_MULLO_A, M32R2F_INSN_MULLO_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULLO_A, M32R2F_INSN_WRITE_MULLO_A },
129 { M32R_INSN_MULWHI_A, M32R2F_INSN_MULWHI_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULWHI_A, M32R2F_INSN_WRITE_MULWHI_A },
130 { M32R_INSN_MULWLO_A, M32R2F_INSN_MULWLO_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULWLO_A, M32R2F_INSN_WRITE_MULWLO_A },
131 { M32R_INSN_MV, M32R2F_INSN_MV, M32R2F_SFMT_MV, M32R2F_INSN_PAR_MV, M32R2F_INSN_WRITE_MV },
132 { M32R_INSN_MVFACHI_A, M32R2F_INSN_MVFACHI_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACHI_A, M32R2F_INSN_WRITE_MVFACHI_A },
133 { M32R_INSN_MVFACLO_A, M32R2F_INSN_MVFACLO_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACLO_A, M32R2F_INSN_WRITE_MVFACLO_A },
134 { M32R_INSN_MVFACMI_A, M32R2F_INSN_MVFACMI_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACMI_A, M32R2F_INSN_WRITE_MVFACMI_A },
135 { M32R_INSN_MVFC, M32R2F_INSN_MVFC, M32R2F_SFMT_MVFC, M32R2F_INSN_PAR_MVFC, M32R2F_INSN_WRITE_MVFC },
136 { M32R_INSN_MVTACHI_A, M32R2F_INSN_MVTACHI_A, M32R2F_SFMT_MVTACHI_A, M32R2F_INSN_PAR_MVTACHI_A, M32R2F_INSN_WRITE_MVTACHI_A },
137 { M32R_INSN_MVTACLO_A, M32R2F_INSN_MVTACLO_A, M32R2F_SFMT_MVTACHI_A, M32R2F_INSN_PAR_MVTACLO_A, M32R2F_INSN_WRITE_MVTACLO_A },
138 { M32R_INSN_MVTC, M32R2F_INSN_MVTC, M32R2F_SFMT_MVTC, M32R2F_INSN_PAR_MVTC, M32R2F_INSN_WRITE_MVTC },
139 { M32R_INSN_NEG, M32R2F_INSN_NEG, M32R2F_SFMT_MV, M32R2F_INSN_PAR_NEG, M32R2F_INSN_WRITE_NEG },
140 { M32R_INSN_NOP, M32R2F_INSN_NOP, M32R2F_SFMT_NOP, M32R2F_INSN_PAR_NOP, M32R2F_INSN_WRITE_NOP },
141 { M32R_INSN_NOT, M32R2F_INSN_NOT, M32R2F_SFMT_MV, M32R2F_INSN_PAR_NOT, M32R2F_INSN_WRITE_NOT },
142 { M32R_INSN_RAC_DSI, M32R2F_INSN_RAC_DSI, M32R2F_SFMT_RAC_DSI, M32R2F_INSN_PAR_RAC_DSI, M32R2F_INSN_WRITE_RAC_DSI },
143 { M32R_INSN_RACH_DSI, M32R2F_INSN_RACH_DSI, M32R2F_SFMT_RAC_DSI, M32R2F_INSN_PAR_RACH_DSI, M32R2F_INSN_WRITE_RACH_DSI },
144 { M32R_INSN_RTE, M32R2F_INSN_RTE, M32R2F_SFMT_RTE, M32R2F_INSN_PAR_RTE, M32R2F_INSN_WRITE_RTE },
145 { M32R_INSN_SETH, M32R2F_INSN_SETH, M32R2F_SFMT_SETH, NOPAR, NOPAR },
146 { M32R_INSN_SLL, M32R2F_INSN_SLL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SLL, M32R2F_INSN_WRITE_SLL },
147 { M32R_INSN_SLL3, M32R2F_INSN_SLL3, M32R2F_SFMT_SLL3, NOPAR, NOPAR },
148 { M32R_INSN_SLLI, M32R2F_INSN_SLLI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SLLI, M32R2F_INSN_WRITE_SLLI },
149 { M32R_INSN_SRA, M32R2F_INSN_SRA, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SRA, M32R2F_INSN_WRITE_SRA },
150 { M32R_INSN_SRA3, M32R2F_INSN_SRA3, M32R2F_SFMT_SLL3, NOPAR, NOPAR },
151 { M32R_INSN_SRAI, M32R2F_INSN_SRAI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SRAI, M32R2F_INSN_WRITE_SRAI },
152 { M32R_INSN_SRL, M32R2F_INSN_SRL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SRL, M32R2F_INSN_WRITE_SRL },
153 { M32R_INSN_SRL3, M32R2F_INSN_SRL3, M32R2F_SFMT_SLL3, NOPAR, NOPAR },
154 { M32R_INSN_SRLI, M32R2F_INSN_SRLI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SRLI, M32R2F_INSN_WRITE_SRLI },
155 { M32R_INSN_ST, M32R2F_INSN_ST, M32R2F_SFMT_ST, M32R2F_INSN_PAR_ST, M32R2F_INSN_WRITE_ST },
156 { M32R_INSN_ST_D, M32R2F_INSN_ST_D, M32R2F_SFMT_ST_D, NOPAR, NOPAR },
157 { M32R_INSN_STB, M32R2F_INSN_STB, M32R2F_SFMT_STB, M32R2F_INSN_PAR_STB, M32R2F_INSN_WRITE_STB },
158 { M32R_INSN_STB_D, M32R2F_INSN_STB_D, M32R2F_SFMT_STB_D, NOPAR, NOPAR },
159 { M32R_INSN_STH, M32R2F_INSN_STH, M32R2F_SFMT_STH, M32R2F_INSN_PAR_STH, M32R2F_INSN_WRITE_STH },
160 { M32R_INSN_STH_D, M32R2F_INSN_STH_D, M32R2F_SFMT_STH_D, NOPAR, NOPAR },
161 { M32R_INSN_ST_PLUS, M32R2F_INSN_ST_PLUS, M32R2F_SFMT_ST_PLUS, M32R2F_INSN_PAR_ST_PLUS, M32R2F_INSN_WRITE_ST_PLUS },
162 { M32R_INSN_STH_PLUS, M32R2F_INSN_STH_PLUS, M32R2F_SFMT_STH_PLUS, M32R2F_INSN_PAR_STH_PLUS, M32R2F_INSN_WRITE_STH_PLUS },
163 { M32R_INSN_STB_PLUS, M32R2F_INSN_STB_PLUS, M32R2F_SFMT_STB_PLUS, M32R2F_INSN_PAR_STB_PLUS, M32R2F_INSN_WRITE_STB_PLUS },
164 { M32R_INSN_ST_MINUS, M32R2F_INSN_ST_MINUS, M32R2F_SFMT_ST_PLUS, M32R2F_INSN_PAR_ST_MINUS, M32R2F_INSN_WRITE_ST_MINUS },
165 { M32R_INSN_SUB, M32R2F_INSN_SUB, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SUB, M32R2F_INSN_WRITE_SUB },
166 { M32R_INSN_SUBV, M32R2F_INSN_SUBV, M32R2F_SFMT_ADDV, M32R2F_INSN_PAR_SUBV, M32R2F_INSN_WRITE_SUBV },
167 { M32R_INSN_SUBX, M32R2F_INSN_SUBX, M32R2F_SFMT_ADDX, M32R2F_INSN_PAR_SUBX, M32R2F_INSN_WRITE_SUBX },
168 { M32R_INSN_TRAP, M32R2F_INSN_TRAP, M32R2F_SFMT_TRAP, M32R2F_INSN_PAR_TRAP, M32R2F_INSN_WRITE_TRAP },
169 { M32R_INSN_UNLOCK, M32R2F_INSN_UNLOCK, M32R2F_SFMT_UNLOCK, M32R2F_INSN_PAR_UNLOCK, M32R2F_INSN_WRITE_UNLOCK },
170 { M32R_INSN_SATB, M32R2F_INSN_SATB, M32R2F_SFMT_SATB, NOPAR, NOPAR },
171 { M32R_INSN_SATH, M32R2F_INSN_SATH, M32R2F_SFMT_SATB, NOPAR, NOPAR },
172 { M32R_INSN_SAT, M32R2F_INSN_SAT, M32R2F_SFMT_SAT, NOPAR, NOPAR },
173 { M32R_INSN_PCMPBZ, M32R2F_INSN_PCMPBZ, M32R2F_SFMT_CMPZ, M32R2F_INSN_PAR_PCMPBZ, M32R2F_INSN_WRITE_PCMPBZ },
174 { M32R_INSN_SADD, M32R2F_INSN_SADD, M32R2F_SFMT_SADD, M32R2F_INSN_PAR_SADD, M32R2F_INSN_WRITE_SADD },
175 { M32R_INSN_MACWU1, M32R2F_INSN_MACWU1, M32R2F_SFMT_MACWU1, M32R2F_INSN_PAR_MACWU1, M32R2F_INSN_WRITE_MACWU1 },
176 { M32R_INSN_MSBLO, M32R2F_INSN_MSBLO, M32R2F_SFMT_MSBLO, M32R2F_INSN_PAR_MSBLO, M32R2F_INSN_WRITE_MSBLO },
177 { M32R_INSN_MULWU1, M32R2F_INSN_MULWU1, M32R2F_SFMT_MULWU1, M32R2F_INSN_PAR_MULWU1, M32R2F_INSN_WRITE_MULWU1 },
178 { M32R_INSN_MACLH1, M32R2F_INSN_MACLH1, M32R2F_SFMT_MACWU1, M32R2F_INSN_PAR_MACLH1, M32R2F_INSN_WRITE_MACLH1 },
179 { M32R_INSN_SC, M32R2F_INSN_SC, M32R2F_SFMT_SC, M32R2F_INSN_PAR_SC, M32R2F_INSN_WRITE_SC },
180 { M32R_INSN_SNC, M32R2F_INSN_SNC, M32R2F_SFMT_SC, M32R2F_INSN_PAR_SNC, M32R2F_INSN_WRITE_SNC },
181 { M32R_INSN_CLRPSW, M32R2F_INSN_CLRPSW, M32R2F_SFMT_CLRPSW, M32R2F_INSN_PAR_CLRPSW, M32R2F_INSN_WRITE_CLRPSW },
182 { M32R_INSN_SETPSW, M32R2F_INSN_SETPSW, M32R2F_SFMT_SETPSW, M32R2F_INSN_PAR_SETPSW, M32R2F_INSN_WRITE_SETPSW },
183 { M32R_INSN_BSET, M32R2F_INSN_BSET, M32R2F_SFMT_BSET, NOPAR, NOPAR },
184 { M32R_INSN_BCLR, M32R2F_INSN_BCLR, M32R2F_SFMT_BSET, NOPAR, NOPAR },
185 { M32R_INSN_BTST, M32R2F_INSN_BTST, M32R2F_SFMT_BTST, M32R2F_INSN_PAR_BTST, M32R2F_INSN_WRITE_BTST },
186 };
187
188 static const struct insn_sem m32r2f_insn_sem_invalid = {
189 VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR
190 };
191
192 /* Initialize an IDESC from the compile-time computable parts. */
193
194 static INLINE void
195 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
196 {
197 const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
198
199 id->num = t->index;
200 id->sfmt = t->sfmt;
201 if ((int) t->type <= 0)
202 id->idata = & cgen_virtual_insn_table[- (int) t->type];
203 else
204 id->idata = & insn_table[t->type];
205 id->attrs = CGEN_INSN_ATTRS (id->idata);
206 /* Oh my god, a magic number. */
207 id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
208
209 #if WITH_PROFILE_MODEL_P
210 id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
211 {
212 SIM_DESC sd = CPU_STATE (cpu);
213 SIM_ASSERT (t->index == id->timing->num);
214 }
215 #endif
216
217 /* Semantic pointers are initialized elsewhere. */
218 }
219
220 /* Initialize the instruction descriptor table. */
221
222 void
223 m32r2f_init_idesc_table (SIM_CPU *cpu)
224 {
225 IDESC *id,*tabend;
226 const struct insn_sem *t,*tend;
227 int tabsize = M32R2F_INSN__MAX;
228 IDESC *table = m32r2f_insn_data;
229
230 memset (table, 0, tabsize * sizeof (IDESC));
231
232 /* First set all entries to the `invalid insn'. */
233 t = & m32r2f_insn_sem_invalid;
234 for (id = table, tabend = table + tabsize; id < tabend; ++id)
235 init_idesc (cpu, id, t);
236
237 /* Now fill in the values for the chosen cpu. */
238 for (t = m32r2f_insn_sem, tend = t + sizeof (m32r2f_insn_sem) / sizeof (*t);
239 t != tend; ++t)
240 {
241 init_idesc (cpu, & table[t->index], t);
242 if (t->par_index != NOPAR)
243 {
244 init_idesc (cpu, &table[t->par_index], t);
245 table[t->index].par_idesc = &table[t->par_index];
246 }
247 if (t->par_index != NOPAR)
248 {
249 init_idesc (cpu, &table[t->write_index], t);
250 table[t->par_index].par_idesc = &table[t->write_index];
251 }
252 }
253
254 /* Link the IDESC table into the cpu. */
255 CPU_IDESC (cpu) = table;
256 }
257
258 /* Given an instruction, return a pointer to its IDESC entry. */
259
260 const IDESC *
261 m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
262 CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
263 ARGBUF *abuf)
264 {
265 /* Result of decoder. */
266 M32R2F_INSN_TYPE itype;
267
268 {
269 CGEN_INSN_INT insn = base_insn;
270
271 {
272 unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
273 switch (val)
274 {
275 case 0 : itype = M32R2F_INSN_SUBV; goto extract_sfmt_addv;
276 case 1 : itype = M32R2F_INSN_SUBX; goto extract_sfmt_addx;
277 case 2 : itype = M32R2F_INSN_SUB; goto extract_sfmt_add;
278 case 3 : itype = M32R2F_INSN_NEG; goto extract_sfmt_mv;
279 case 4 : itype = M32R2F_INSN_CMP; goto extract_sfmt_cmp;
280 case 5 : itype = M32R2F_INSN_CMPU; goto extract_sfmt_cmp;
281 case 6 : itype = M32R2F_INSN_CMPEQ; goto extract_sfmt_cmp;
282 case 7 :
283 {
284 unsigned int val = (((insn >> 8) & (3 << 0)));
285 switch (val)
286 {
287 case 0 : itype = M32R2F_INSN_CMPZ; goto extract_sfmt_cmpz;
288 case 3 : itype = M32R2F_INSN_PCMPBZ; goto extract_sfmt_cmpz;
289 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
290 }
291 }
292 case 8 : itype = M32R2F_INSN_ADDV; goto extract_sfmt_addv;
293 case 9 : itype = M32R2F_INSN_ADDX; goto extract_sfmt_addx;
294 case 10 : itype = M32R2F_INSN_ADD; goto extract_sfmt_add;
295 case 11 : itype = M32R2F_INSN_NOT; goto extract_sfmt_mv;
296 case 12 : itype = M32R2F_INSN_AND; goto extract_sfmt_add;
297 case 13 : itype = M32R2F_INSN_XOR; goto extract_sfmt_add;
298 case 14 : itype = M32R2F_INSN_OR; goto extract_sfmt_add;
299 case 15 : itype = M32R2F_INSN_BTST; goto extract_sfmt_btst;
300 case 16 : itype = M32R2F_INSN_SRL; goto extract_sfmt_add;
301 case 18 : itype = M32R2F_INSN_SRA; goto extract_sfmt_add;
302 case 20 : itype = M32R2F_INSN_SLL; goto extract_sfmt_add;
303 case 22 : itype = M32R2F_INSN_MUL; goto extract_sfmt_add;
304 case 24 : itype = M32R2F_INSN_MV; goto extract_sfmt_mv;
305 case 25 : itype = M32R2F_INSN_MVFC; goto extract_sfmt_mvfc;
306 case 26 : itype = M32R2F_INSN_MVTC; goto extract_sfmt_mvtc;
307 case 28 :
308 {
309 unsigned int val = (((insn >> 8) & (3 << 0)));
310 switch (val)
311 {
312 case 0 : itype = M32R2F_INSN_JC; goto extract_sfmt_jc;
313 case 1 : itype = M32R2F_INSN_JNC; goto extract_sfmt_jc;
314 case 2 : itype = M32R2F_INSN_JL; goto extract_sfmt_jl;
315 case 3 : itype = M32R2F_INSN_JMP; goto extract_sfmt_jmp;
316 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
317 }
318 }
319 case 29 : itype = M32R2F_INSN_RTE; goto extract_sfmt_rte;
320 case 31 : itype = M32R2F_INSN_TRAP; goto extract_sfmt_trap;
321 case 32 : itype = M32R2F_INSN_STB; goto extract_sfmt_stb;
322 case 33 : itype = M32R2F_INSN_STB_PLUS; goto extract_sfmt_stb_plus;
323 case 34 : itype = M32R2F_INSN_STH; goto extract_sfmt_sth;
324 case 35 : itype = M32R2F_INSN_STH_PLUS; goto extract_sfmt_sth_plus;
325 case 36 : itype = M32R2F_INSN_ST; goto extract_sfmt_st;
326 case 37 : itype = M32R2F_INSN_UNLOCK; goto extract_sfmt_unlock;
327 case 38 : itype = M32R2F_INSN_ST_PLUS; goto extract_sfmt_st_plus;
328 case 39 : itype = M32R2F_INSN_ST_MINUS; goto extract_sfmt_st_plus;
329 case 40 : itype = M32R2F_INSN_LDB; goto extract_sfmt_ldb;
330 case 41 : itype = M32R2F_INSN_LDUB; goto extract_sfmt_ldb;
331 case 42 : itype = M32R2F_INSN_LDH; goto extract_sfmt_ldh;
332 case 43 : itype = M32R2F_INSN_LDUH; goto extract_sfmt_ldh;
333 case 44 : itype = M32R2F_INSN_LD; goto extract_sfmt_ld;
334 case 45 : itype = M32R2F_INSN_LOCK; goto extract_sfmt_lock;
335 case 46 : itype = M32R2F_INSN_LD_PLUS; goto extract_sfmt_ld_plus;
336 case 48 : /* fall through */
337 case 56 : itype = M32R2F_INSN_MULHI_A; goto extract_sfmt_mulhi_a;
338 case 49 : /* fall through */
339 case 57 : itype = M32R2F_INSN_MULLO_A; goto extract_sfmt_mulhi_a;
340 case 50 : /* fall through */
341 case 58 : itype = M32R2F_INSN_MULWHI_A; goto extract_sfmt_mulhi_a;
342 case 51 : /* fall through */
343 case 59 : itype = M32R2F_INSN_MULWLO_A; goto extract_sfmt_mulhi_a;
344 case 52 : /* fall through */
345 case 60 : itype = M32R2F_INSN_MACHI_A; goto extract_sfmt_machi_a;
346 case 53 : /* fall through */
347 case 61 : itype = M32R2F_INSN_MACLO_A; goto extract_sfmt_machi_a;
348 case 54 : /* fall through */
349 case 62 : itype = M32R2F_INSN_MACWHI_A; goto extract_sfmt_machi_a;
350 case 55 : /* fall through */
351 case 63 : itype = M32R2F_INSN_MACWLO_A; goto extract_sfmt_machi_a;
352 case 64 : /* fall through */
353 case 65 : /* fall through */
354 case 66 : /* fall through */
355 case 67 : /* fall through */
356 case 68 : /* fall through */
357 case 69 : /* fall through */
358 case 70 : /* fall through */
359 case 71 : /* fall through */
360 case 72 : /* fall through */
361 case 73 : /* fall through */
362 case 74 : /* fall through */
363 case 75 : /* fall through */
364 case 76 : /* fall through */
365 case 77 : /* fall through */
366 case 78 : /* fall through */
367 case 79 : itype = M32R2F_INSN_ADDI; goto extract_sfmt_addi;
368 case 80 : /* fall through */
369 case 81 : itype = M32R2F_INSN_SRLI; goto extract_sfmt_slli;
370 case 82 : /* fall through */
371 case 83 : itype = M32R2F_INSN_SRAI; goto extract_sfmt_slli;
372 case 84 : /* fall through */
373 case 85 : itype = M32R2F_INSN_SLLI; goto extract_sfmt_slli;
374 case 87 :
375 {
376 unsigned int val = (((insn >> 0) & (1 << 0)));
377 switch (val)
378 {
379 case 0 : itype = M32R2F_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a;
380 case 1 : itype = M32R2F_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a;
381 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
382 }
383 }
384 case 88 : itype = M32R2F_INSN_RACH_DSI; goto extract_sfmt_rac_dsi;
385 case 89 : itype = M32R2F_INSN_RAC_DSI; goto extract_sfmt_rac_dsi;
386 case 90 : itype = M32R2F_INSN_MULWU1; goto extract_sfmt_mulwu1;
387 case 91 : itype = M32R2F_INSN_MACWU1; goto extract_sfmt_macwu1;
388 case 92 : itype = M32R2F_INSN_MACLH1; goto extract_sfmt_macwu1;
389 case 93 : itype = M32R2F_INSN_MSBLO; goto extract_sfmt_msblo;
390 case 94 : itype = M32R2F_INSN_SADD; goto extract_sfmt_sadd;
391 case 95 :
392 {
393 unsigned int val = (((insn >> 0) & (3 << 0)));
394 switch (val)
395 {
396 case 0 : itype = M32R2F_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a;
397 case 1 : itype = M32R2F_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a;
398 case 2 : itype = M32R2F_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a;
399 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
400 }
401 }
402 case 96 : /* fall through */
403 case 97 : /* fall through */
404 case 98 : /* fall through */
405 case 99 : /* fall through */
406 case 100 : /* fall through */
407 case 101 : /* fall through */
408 case 102 : /* fall through */
409 case 103 : /* fall through */
410 case 104 : /* fall through */
411 case 105 : /* fall through */
412 case 106 : /* fall through */
413 case 107 : /* fall through */
414 case 108 : /* fall through */
415 case 109 : /* fall through */
416 case 110 : /* fall through */
417 case 111 : itype = M32R2F_INSN_LDI8; goto extract_sfmt_ldi8;
418 case 112 :
419 {
420 unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0)));
421 switch (val)
422 {
423 case 0 : itype = M32R2F_INSN_NOP; goto extract_sfmt_nop;
424 case 2 : /* fall through */
425 case 3 : itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw;
426 case 4 : /* fall through */
427 case 5 : itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw;
428 case 9 : itype = M32R2F_INSN_SC; goto extract_sfmt_sc;
429 case 11 : itype = M32R2F_INSN_SNC; goto extract_sfmt_sc;
430 case 16 : /* fall through */
431 case 17 : itype = M32R2F_INSN_BCL8; goto extract_sfmt_bcl8;
432 case 18 : /* fall through */
433 case 19 : itype = M32R2F_INSN_BNCL8; goto extract_sfmt_bcl8;
434 case 24 : /* fall through */
435 case 25 : itype = M32R2F_INSN_BC8; goto extract_sfmt_bc8;
436 case 26 : /* fall through */
437 case 27 : itype = M32R2F_INSN_BNC8; goto extract_sfmt_bc8;
438 case 28 : /* fall through */
439 case 29 : itype = M32R2F_INSN_BL8; goto extract_sfmt_bl8;
440 case 30 : /* fall through */
441 case 31 : itype = M32R2F_INSN_BRA8; goto extract_sfmt_bra8;
442 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
443 }
444 }
445 case 113 : /* fall through */
446 case 114 : /* fall through */
447 case 115 : /* fall through */
448 case 116 : /* fall through */
449 case 117 : /* fall through */
450 case 118 : /* fall through */
451 case 119 : /* fall through */
452 case 120 : /* fall through */
453 case 121 : /* fall through */
454 case 122 : /* fall through */
455 case 123 : /* fall through */
456 case 124 : /* fall through */
457 case 125 : /* fall through */
458 case 126 : /* fall through */
459 case 127 :
460 {
461 unsigned int val = (((insn >> 8) & (15 << 0)));
462 switch (val)
463 {
464 case 1 : itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw;
465 case 2 : itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw;
466 case 8 : itype = M32R2F_INSN_BCL8; goto extract_sfmt_bcl8;
467 case 9 : itype = M32R2F_INSN_BNCL8; goto extract_sfmt_bcl8;
468 case 12 : itype = M32R2F_INSN_BC8; goto extract_sfmt_bc8;
469 case 13 : itype = M32R2F_INSN_BNC8; goto extract_sfmt_bc8;
470 case 14 : itype = M32R2F_INSN_BL8; goto extract_sfmt_bl8;
471 case 15 : itype = M32R2F_INSN_BRA8; goto extract_sfmt_bra8;
472 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
473 }
474 }
475 case 132 : itype = M32R2F_INSN_CMPI; goto extract_sfmt_cmpi;
476 case 133 : itype = M32R2F_INSN_CMPUI; goto extract_sfmt_cmpi;
477 case 134 :
478 {
479 unsigned int val = (((insn >> -8) & (3 << 0)));
480 switch (val)
481 {
482 case 0 : itype = M32R2F_INSN_SAT; goto extract_sfmt_sat;
483 case 2 : itype = M32R2F_INSN_SATH; goto extract_sfmt_satb;
484 case 3 : itype = M32R2F_INSN_SATB; goto extract_sfmt_satb;
485 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
486 }
487 }
488 case 136 : itype = M32R2F_INSN_ADDV3; goto extract_sfmt_addv3;
489 case 138 : itype = M32R2F_INSN_ADD3; goto extract_sfmt_add3;
490 case 140 : itype = M32R2F_INSN_AND3; goto extract_sfmt_and3;
491 case 141 : itype = M32R2F_INSN_XOR3; goto extract_sfmt_and3;
492 case 142 : itype = M32R2F_INSN_OR3; goto extract_sfmt_or3;
493 case 144 :
494 {
495 unsigned int val = (((insn >> -13) & (3 << 0)));
496 switch (val)
497 {
498 case 0 : itype = M32R2F_INSN_DIV; goto extract_sfmt_div;
499 case 2 : itype = M32R2F_INSN_DIVH; goto extract_sfmt_div;
500 case 3 : itype = M32R2F_INSN_DIVB; goto extract_sfmt_div;
501 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
502 }
503 }
504 case 145 :
505 {
506 unsigned int val = (((insn >> -13) & (3 << 0)));
507 switch (val)
508 {
509 case 0 : itype = M32R2F_INSN_DIVU; goto extract_sfmt_div;
510 case 2 : itype = M32R2F_INSN_DIVUH; goto extract_sfmt_div;
511 case 3 : itype = M32R2F_INSN_DIVUB; goto extract_sfmt_div;
512 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
513 }
514 }
515 case 146 :
516 {
517 unsigned int val = (((insn >> -13) & (3 << 0)));
518 switch (val)
519 {
520 case 0 : itype = M32R2F_INSN_REM; goto extract_sfmt_div;
521 case 2 : itype = M32R2F_INSN_REMH; goto extract_sfmt_div;
522 case 3 : itype = M32R2F_INSN_REMB; goto extract_sfmt_div;
523 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
524 }
525 }
526 case 147 :
527 {
528 unsigned int val = (((insn >> -13) & (3 << 0)));
529 switch (val)
530 {
531 case 0 : itype = M32R2F_INSN_REMU; goto extract_sfmt_div;
532 case 2 : itype = M32R2F_INSN_REMUH; goto extract_sfmt_div;
533 case 3 : itype = M32R2F_INSN_REMUB; goto extract_sfmt_div;
534 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
535 }
536 }
537 case 152 : itype = M32R2F_INSN_SRL3; goto extract_sfmt_sll3;
538 case 154 : itype = M32R2F_INSN_SRA3; goto extract_sfmt_sll3;
539 case 156 : itype = M32R2F_INSN_SLL3; goto extract_sfmt_sll3;
540 case 159 : itype = M32R2F_INSN_LDI16; goto extract_sfmt_ldi16;
541 case 160 : itype = M32R2F_INSN_STB_D; goto extract_sfmt_stb_d;
542 case 162 : itype = M32R2F_INSN_STH_D; goto extract_sfmt_sth_d;
543 case 164 : itype = M32R2F_INSN_ST_D; goto extract_sfmt_st_d;
544 case 166 : itype = M32R2F_INSN_BSET; goto extract_sfmt_bset;
545 case 167 : itype = M32R2F_INSN_BCLR; goto extract_sfmt_bset;
546 case 168 : itype = M32R2F_INSN_LDB_D; goto extract_sfmt_ldb_d;
547 case 169 : itype = M32R2F_INSN_LDUB_D; goto extract_sfmt_ldb_d;
548 case 170 : itype = M32R2F_INSN_LDH_D; goto extract_sfmt_ldh_d;
549 case 171 : itype = M32R2F_INSN_LDUH_D; goto extract_sfmt_ldh_d;
550 case 172 : itype = M32R2F_INSN_LD_D; goto extract_sfmt_ld_d;
551 case 176 : itype = M32R2F_INSN_BEQ; goto extract_sfmt_beq;
552 case 177 : itype = M32R2F_INSN_BNE; goto extract_sfmt_beq;
553 case 184 : itype = M32R2F_INSN_BEQZ; goto extract_sfmt_beqz;
554 case 185 : itype = M32R2F_INSN_BNEZ; goto extract_sfmt_beqz;
555 case 186 : itype = M32R2F_INSN_BLTZ; goto extract_sfmt_beqz;
556 case 187 : itype = M32R2F_INSN_BGEZ; goto extract_sfmt_beqz;
557 case 188 : itype = M32R2F_INSN_BLEZ; goto extract_sfmt_beqz;
558 case 189 : itype = M32R2F_INSN_BGTZ; goto extract_sfmt_beqz;
559 case 220 : itype = M32R2F_INSN_SETH; goto extract_sfmt_seth;
560 case 224 : /* fall through */
561 case 225 : /* fall through */
562 case 226 : /* fall through */
563 case 227 : /* fall through */
564 case 228 : /* fall through */
565 case 229 : /* fall through */
566 case 230 : /* fall through */
567 case 231 : /* fall through */
568 case 232 : /* fall through */
569 case 233 : /* fall through */
570 case 234 : /* fall through */
571 case 235 : /* fall through */
572 case 236 : /* fall through */
573 case 237 : /* fall through */
574 case 238 : /* fall through */
575 case 239 : itype = M32R2F_INSN_LD24; goto extract_sfmt_ld24;
576 case 240 : /* fall through */
577 case 241 : /* fall through */
578 case 242 : /* fall through */
579 case 243 : /* fall through */
580 case 244 : /* fall through */
581 case 245 : /* fall through */
582 case 246 : /* fall through */
583 case 247 : /* fall through */
584 case 248 : /* fall through */
585 case 249 : /* fall through */
586 case 250 : /* fall through */
587 case 251 : /* fall through */
588 case 252 : /* fall through */
589 case 253 : /* fall through */
590 case 254 : /* fall through */
591 case 255 :
592 {
593 unsigned int val = (((insn >> 8) & (7 << 0)));
594 switch (val)
595 {
596 case 0 : itype = M32R2F_INSN_BCL24; goto extract_sfmt_bcl24;
597 case 1 : itype = M32R2F_INSN_BNCL24; goto extract_sfmt_bcl24;
598 case 4 : itype = M32R2F_INSN_BC24; goto extract_sfmt_bc24;
599 case 5 : itype = M32R2F_INSN_BNC24; goto extract_sfmt_bc24;
600 case 6 : itype = M32R2F_INSN_BL24; goto extract_sfmt_bl24;
601 case 7 : itype = M32R2F_INSN_BRA24; goto extract_sfmt_bra24;
602 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
603 }
604 }
605 default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
606 }
607 }
608 }
609
610 /* The instruction has been decoded, now extract the fields. */
611
612 extract_sfmt_empty:
613 {
614 const IDESC *idesc = &m32r2f_insn_data[itype];
615 #define FLD(f) abuf->fields.fmt_empty.f
616
617
618 /* Record the fields for the semantic handler. */
619 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
620
621 #undef FLD
622 return idesc;
623 }
624
625 extract_sfmt_add:
626 {
627 const IDESC *idesc = &m32r2f_insn_data[itype];
628 CGEN_INSN_INT insn = entire_insn;
629 #define FLD(f) abuf->fields.sfmt_add.f
630 UINT f_r1;
631 UINT f_r2;
632
633 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
634 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
635
636 /* Record the fields for the semantic handler. */
637 FLD (f_r1) = f_r1;
638 FLD (f_r2) = f_r2;
639 FLD (i_dr) = & CPU (h_gr)[f_r1];
640 FLD (i_sr) = & CPU (h_gr)[f_r2];
641 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
642
643 #if WITH_PROFILE_MODEL_P
644 /* Record the fields for profiling. */
645 if (PROFILE_MODEL_P (current_cpu))
646 {
647 FLD (in_dr) = f_r1;
648 FLD (in_sr) = f_r2;
649 FLD (out_dr) = f_r1;
650 }
651 #endif
652 #undef FLD
653 return idesc;
654 }
655
656 extract_sfmt_add3:
657 {
658 const IDESC *idesc = &m32r2f_insn_data[itype];
659 CGEN_INSN_INT insn = entire_insn;
660 #define FLD(f) abuf->fields.sfmt_add3.f
661 UINT f_r1;
662 UINT f_r2;
663 INT f_simm16;
664
665 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
666 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
667 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
668
669 /* Record the fields for the semantic handler. */
670 FLD (f_simm16) = f_simm16;
671 FLD (f_r2) = f_r2;
672 FLD (f_r1) = f_r1;
673 FLD (i_sr) = & CPU (h_gr)[f_r2];
674 FLD (i_dr) = & CPU (h_gr)[f_r1];
675 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
676
677 #if WITH_PROFILE_MODEL_P
678 /* Record the fields for profiling. */
679 if (PROFILE_MODEL_P (current_cpu))
680 {
681 FLD (in_sr) = f_r2;
682 FLD (out_dr) = f_r1;
683 }
684 #endif
685 #undef FLD
686 return idesc;
687 }
688
689 extract_sfmt_and3:
690 {
691 const IDESC *idesc = &m32r2f_insn_data[itype];
692 CGEN_INSN_INT insn = entire_insn;
693 #define FLD(f) abuf->fields.sfmt_and3.f
694 UINT f_r1;
695 UINT f_r2;
696 UINT f_uimm16;
697
698 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
699 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
700 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
701
702 /* Record the fields for the semantic handler. */
703 FLD (f_r2) = f_r2;
704 FLD (f_uimm16) = f_uimm16;
705 FLD (f_r1) = f_r1;
706 FLD (i_sr) = & CPU (h_gr)[f_r2];
707 FLD (i_dr) = & CPU (h_gr)[f_r1];
708 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
709
710 #if WITH_PROFILE_MODEL_P
711 /* Record the fields for profiling. */
712 if (PROFILE_MODEL_P (current_cpu))
713 {
714 FLD (in_sr) = f_r2;
715 FLD (out_dr) = f_r1;
716 }
717 #endif
718 #undef FLD
719 return idesc;
720 }
721
722 extract_sfmt_or3:
723 {
724 const IDESC *idesc = &m32r2f_insn_data[itype];
725 CGEN_INSN_INT insn = entire_insn;
726 #define FLD(f) abuf->fields.sfmt_and3.f
727 UINT f_r1;
728 UINT f_r2;
729 UINT f_uimm16;
730
731 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
732 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
733 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
734
735 /* Record the fields for the semantic handler. */
736 FLD (f_r2) = f_r2;
737 FLD (f_uimm16) = f_uimm16;
738 FLD (f_r1) = f_r1;
739 FLD (i_sr) = & CPU (h_gr)[f_r2];
740 FLD (i_dr) = & CPU (h_gr)[f_r1];
741 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
742
743 #if WITH_PROFILE_MODEL_P
744 /* Record the fields for profiling. */
745 if (PROFILE_MODEL_P (current_cpu))
746 {
747 FLD (in_sr) = f_r2;
748 FLD (out_dr) = f_r1;
749 }
750 #endif
751 #undef FLD
752 return idesc;
753 }
754
755 extract_sfmt_addi:
756 {
757 const IDESC *idesc = &m32r2f_insn_data[itype];
758 CGEN_INSN_INT insn = entire_insn;
759 #define FLD(f) abuf->fields.sfmt_addi.f
760 UINT f_r1;
761 INT f_simm8;
762
763 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
764 f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
765
766 /* Record the fields for the semantic handler. */
767 FLD (f_r1) = f_r1;
768 FLD (f_simm8) = f_simm8;
769 FLD (i_dr) = & CPU (h_gr)[f_r1];
770 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
771
772 #if WITH_PROFILE_MODEL_P
773 /* Record the fields for profiling. */
774 if (PROFILE_MODEL_P (current_cpu))
775 {
776 FLD (in_dr) = f_r1;
777 FLD (out_dr) = f_r1;
778 }
779 #endif
780 #undef FLD
781 return idesc;
782 }
783
784 extract_sfmt_addv:
785 {
786 const IDESC *idesc = &m32r2f_insn_data[itype];
787 CGEN_INSN_INT insn = entire_insn;
788 #define FLD(f) abuf->fields.sfmt_add.f
789 UINT f_r1;
790 UINT f_r2;
791
792 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
793 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
794
795 /* Record the fields for the semantic handler. */
796 FLD (f_r1) = f_r1;
797 FLD (f_r2) = f_r2;
798 FLD (i_dr) = & CPU (h_gr)[f_r1];
799 FLD (i_sr) = & CPU (h_gr)[f_r2];
800 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
801
802 #if WITH_PROFILE_MODEL_P
803 /* Record the fields for profiling. */
804 if (PROFILE_MODEL_P (current_cpu))
805 {
806 FLD (in_dr) = f_r1;
807 FLD (in_sr) = f_r2;
808 FLD (out_dr) = f_r1;
809 }
810 #endif
811 #undef FLD
812 return idesc;
813 }
814
815 extract_sfmt_addv3:
816 {
817 const IDESC *idesc = &m32r2f_insn_data[itype];
818 CGEN_INSN_INT insn = entire_insn;
819 #define FLD(f) abuf->fields.sfmt_add3.f
820 UINT f_r1;
821 UINT f_r2;
822 INT f_simm16;
823
824 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
825 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
826 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
827
828 /* Record the fields for the semantic handler. */
829 FLD (f_simm16) = f_simm16;
830 FLD (f_r2) = f_r2;
831 FLD (f_r1) = f_r1;
832 FLD (i_sr) = & CPU (h_gr)[f_r2];
833 FLD (i_dr) = & CPU (h_gr)[f_r1];
834 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
835
836 #if WITH_PROFILE_MODEL_P
837 /* Record the fields for profiling. */
838 if (PROFILE_MODEL_P (current_cpu))
839 {
840 FLD (in_sr) = f_r2;
841 FLD (out_dr) = f_r1;
842 }
843 #endif
844 #undef FLD
845 return idesc;
846 }
847
848 extract_sfmt_addx:
849 {
850 const IDESC *idesc = &m32r2f_insn_data[itype];
851 CGEN_INSN_INT insn = entire_insn;
852 #define FLD(f) abuf->fields.sfmt_add.f
853 UINT f_r1;
854 UINT f_r2;
855
856 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
857 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
858
859 /* Record the fields for the semantic handler. */
860 FLD (f_r1) = f_r1;
861 FLD (f_r2) = f_r2;
862 FLD (i_dr) = & CPU (h_gr)[f_r1];
863 FLD (i_sr) = & CPU (h_gr)[f_r2];
864 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
865
866 #if WITH_PROFILE_MODEL_P
867 /* Record the fields for profiling. */
868 if (PROFILE_MODEL_P (current_cpu))
869 {
870 FLD (in_dr) = f_r1;
871 FLD (in_sr) = f_r2;
872 FLD (out_dr) = f_r1;
873 }
874 #endif
875 #undef FLD
876 return idesc;
877 }
878
879 extract_sfmt_bc8:
880 {
881 const IDESC *idesc = &m32r2f_insn_data[itype];
882 CGEN_INSN_INT insn = entire_insn;
883 #define FLD(f) abuf->fields.sfmt_bl8.f
884 SI f_disp8;
885
886 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
887
888 /* Record the fields for the semantic handler. */
889 FLD (i_disp8) = f_disp8;
890 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
891
892 #if WITH_PROFILE_MODEL_P
893 /* Record the fields for profiling. */
894 if (PROFILE_MODEL_P (current_cpu))
895 {
896 }
897 #endif
898 #undef FLD
899 return idesc;
900 }
901
902 extract_sfmt_bc24:
903 {
904 const IDESC *idesc = &m32r2f_insn_data[itype];
905 CGEN_INSN_INT insn = entire_insn;
906 #define FLD(f) abuf->fields.sfmt_bl24.f
907 SI f_disp24;
908
909 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
910
911 /* Record the fields for the semantic handler. */
912 FLD (i_disp24) = f_disp24;
913 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
914
915 #if WITH_PROFILE_MODEL_P
916 /* Record the fields for profiling. */
917 if (PROFILE_MODEL_P (current_cpu))
918 {
919 }
920 #endif
921 #undef FLD
922 return idesc;
923 }
924
925 extract_sfmt_beq:
926 {
927 const IDESC *idesc = &m32r2f_insn_data[itype];
928 CGEN_INSN_INT insn = entire_insn;
929 #define FLD(f) abuf->fields.sfmt_beq.f
930 UINT f_r1;
931 UINT f_r2;
932 SI f_disp16;
933
934 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
935 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
936 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
937
938 /* Record the fields for the semantic handler. */
939 FLD (f_r1) = f_r1;
940 FLD (f_r2) = f_r2;
941 FLD (i_disp16) = f_disp16;
942 FLD (i_src1) = & CPU (h_gr)[f_r1];
943 FLD (i_src2) = & CPU (h_gr)[f_r2];
944 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
945
946 #if WITH_PROFILE_MODEL_P
947 /* Record the fields for profiling. */
948 if (PROFILE_MODEL_P (current_cpu))
949 {
950 FLD (in_src1) = f_r1;
951 FLD (in_src2) = f_r2;
952 }
953 #endif
954 #undef FLD
955 return idesc;
956 }
957
958 extract_sfmt_beqz:
959 {
960 const IDESC *idesc = &m32r2f_insn_data[itype];
961 CGEN_INSN_INT insn = entire_insn;
962 #define FLD(f) abuf->fields.sfmt_beq.f
963 UINT f_r2;
964 SI f_disp16;
965
966 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
967 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
968
969 /* Record the fields for the semantic handler. */
970 FLD (f_r2) = f_r2;
971 FLD (i_disp16) = f_disp16;
972 FLD (i_src2) = & CPU (h_gr)[f_r2];
973 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
974
975 #if WITH_PROFILE_MODEL_P
976 /* Record the fields for profiling. */
977 if (PROFILE_MODEL_P (current_cpu))
978 {
979 FLD (in_src2) = f_r2;
980 }
981 #endif
982 #undef FLD
983 return idesc;
984 }
985
986 extract_sfmt_bl8:
987 {
988 const IDESC *idesc = &m32r2f_insn_data[itype];
989 CGEN_INSN_INT insn = entire_insn;
990 #define FLD(f) abuf->fields.sfmt_bl8.f
991 SI f_disp8;
992
993 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
994
995 /* Record the fields for the semantic handler. */
996 FLD (i_disp8) = f_disp8;
997 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
998
999 #if WITH_PROFILE_MODEL_P
1000 /* Record the fields for profiling. */
1001 if (PROFILE_MODEL_P (current_cpu))
1002 {
1003 FLD (out_h_gr_SI_14) = 14;
1004 }
1005 #endif
1006 #undef FLD
1007 return idesc;
1008 }
1009
1010 extract_sfmt_bl24:
1011 {
1012 const IDESC *idesc = &m32r2f_insn_data[itype];
1013 CGEN_INSN_INT insn = entire_insn;
1014 #define FLD(f) abuf->fields.sfmt_bl24.f
1015 SI f_disp24;
1016
1017 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
1018
1019 /* Record the fields for the semantic handler. */
1020 FLD (i_disp24) = f_disp24;
1021 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1022
1023 #if WITH_PROFILE_MODEL_P
1024 /* Record the fields for profiling. */
1025 if (PROFILE_MODEL_P (current_cpu))
1026 {
1027 FLD (out_h_gr_SI_14) = 14;
1028 }
1029 #endif
1030 #undef FLD
1031 return idesc;
1032 }
1033
1034 extract_sfmt_bcl8:
1035 {
1036 const IDESC *idesc = &m32r2f_insn_data[itype];
1037 CGEN_INSN_INT insn = entire_insn;
1038 #define FLD(f) abuf->fields.sfmt_bl8.f
1039 SI f_disp8;
1040
1041 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
1042
1043 /* Record the fields for the semantic handler. */
1044 FLD (i_disp8) = f_disp8;
1045 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1046
1047 #if WITH_PROFILE_MODEL_P
1048 /* Record the fields for profiling. */
1049 if (PROFILE_MODEL_P (current_cpu))
1050 {
1051 FLD (out_h_gr_SI_14) = 14;
1052 }
1053 #endif
1054 #undef FLD
1055 return idesc;
1056 }
1057
1058 extract_sfmt_bcl24:
1059 {
1060 const IDESC *idesc = &m32r2f_insn_data[itype];
1061 CGEN_INSN_INT insn = entire_insn;
1062 #define FLD(f) abuf->fields.sfmt_bl24.f
1063 SI f_disp24;
1064
1065 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
1066
1067 /* Record the fields for the semantic handler. */
1068 FLD (i_disp24) = f_disp24;
1069 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1070
1071 #if WITH_PROFILE_MODEL_P
1072 /* Record the fields for profiling. */
1073 if (PROFILE_MODEL_P (current_cpu))
1074 {
1075 FLD (out_h_gr_SI_14) = 14;
1076 }
1077 #endif
1078 #undef FLD
1079 return idesc;
1080 }
1081
1082 extract_sfmt_bra8:
1083 {
1084 const IDESC *idesc = &m32r2f_insn_data[itype];
1085 CGEN_INSN_INT insn = entire_insn;
1086 #define FLD(f) abuf->fields.sfmt_bl8.f
1087 SI f_disp8;
1088
1089 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
1090
1091 /* Record the fields for the semantic handler. */
1092 FLD (i_disp8) = f_disp8;
1093 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1094
1095 #if WITH_PROFILE_MODEL_P
1096 /* Record the fields for profiling. */
1097 if (PROFILE_MODEL_P (current_cpu))
1098 {
1099 }
1100 #endif
1101 #undef FLD
1102 return idesc;
1103 }
1104
1105 extract_sfmt_bra24:
1106 {
1107 const IDESC *idesc = &m32r2f_insn_data[itype];
1108 CGEN_INSN_INT insn = entire_insn;
1109 #define FLD(f) abuf->fields.sfmt_bl24.f
1110 SI f_disp24;
1111
1112 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
1113
1114 /* Record the fields for the semantic handler. */
1115 FLD (i_disp24) = f_disp24;
1116 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1117
1118 #if WITH_PROFILE_MODEL_P
1119 /* Record the fields for profiling. */
1120 if (PROFILE_MODEL_P (current_cpu))
1121 {
1122 }
1123 #endif
1124 #undef FLD
1125 return idesc;
1126 }
1127
1128 extract_sfmt_cmp:
1129 {
1130 const IDESC *idesc = &m32r2f_insn_data[itype];
1131 CGEN_INSN_INT insn = entire_insn;
1132 #define FLD(f) abuf->fields.sfmt_st_plus.f
1133 UINT f_r1;
1134 UINT f_r2;
1135
1136 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1137 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1138
1139 /* Record the fields for the semantic handler. */
1140 FLD (f_r1) = f_r1;
1141 FLD (f_r2) = f_r2;
1142 FLD (i_src1) = & CPU (h_gr)[f_r1];
1143 FLD (i_src2) = & CPU (h_gr)[f_r2];
1144 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1145
1146 #if WITH_PROFILE_MODEL_P
1147 /* Record the fields for profiling. */
1148 if (PROFILE_MODEL_P (current_cpu))
1149 {
1150 FLD (in_src1) = f_r1;
1151 FLD (in_src2) = f_r2;
1152 }
1153 #endif
1154 #undef FLD
1155 return idesc;
1156 }
1157
1158 extract_sfmt_cmpi:
1159 {
1160 const IDESC *idesc = &m32r2f_insn_data[itype];
1161 CGEN_INSN_INT insn = entire_insn;
1162 #define FLD(f) abuf->fields.sfmt_st_d.f
1163 UINT f_r2;
1164 INT f_simm16;
1165
1166 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1167 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1168
1169 /* Record the fields for the semantic handler. */
1170 FLD (f_simm16) = f_simm16;
1171 FLD (f_r2) = f_r2;
1172 FLD (i_src2) = & CPU (h_gr)[f_r2];
1173 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
1174
1175 #if WITH_PROFILE_MODEL_P
1176 /* Record the fields for profiling. */
1177 if (PROFILE_MODEL_P (current_cpu))
1178 {
1179 FLD (in_src2) = f_r2;
1180 }
1181 #endif
1182 #undef FLD
1183 return idesc;
1184 }
1185
1186 extract_sfmt_cmpz:
1187 {
1188 const IDESC *idesc = &m32r2f_insn_data[itype];
1189 CGEN_INSN_INT insn = entire_insn;
1190 #define FLD(f) abuf->fields.sfmt_st_plus.f
1191 UINT f_r2;
1192
1193 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1194
1195 /* Record the fields for the semantic handler. */
1196 FLD (f_r2) = f_r2;
1197 FLD (i_src2) = & CPU (h_gr)[f_r2];
1198 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
1199
1200 #if WITH_PROFILE_MODEL_P
1201 /* Record the fields for profiling. */
1202 if (PROFILE_MODEL_P (current_cpu))
1203 {
1204 FLD (in_src2) = f_r2;
1205 }
1206 #endif
1207 #undef FLD
1208 return idesc;
1209 }
1210
1211 extract_sfmt_div:
1212 {
1213 const IDESC *idesc = &m32r2f_insn_data[itype];
1214 CGEN_INSN_INT insn = entire_insn;
1215 #define FLD(f) abuf->fields.sfmt_add.f
1216 UINT f_r1;
1217 UINT f_r2;
1218
1219 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1220 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1221
1222 /* Record the fields for the semantic handler. */
1223 FLD (f_r1) = f_r1;
1224 FLD (f_r2) = f_r2;
1225 FLD (i_dr) = & CPU (h_gr)[f_r1];
1226 FLD (i_sr) = & CPU (h_gr)[f_r2];
1227 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1228
1229 #if WITH_PROFILE_MODEL_P
1230 /* Record the fields for profiling. */
1231 if (PROFILE_MODEL_P (current_cpu))
1232 {
1233 FLD (in_dr) = f_r1;
1234 FLD (in_sr) = f_r2;
1235 FLD (out_dr) = f_r1;
1236 }
1237 #endif
1238 #undef FLD
1239 return idesc;
1240 }
1241
1242 extract_sfmt_jc:
1243 {
1244 const IDESC *idesc = &m32r2f_insn_data[itype];
1245 CGEN_INSN_INT insn = entire_insn;
1246 #define FLD(f) abuf->fields.sfmt_jl.f
1247 UINT f_r2;
1248
1249 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1250
1251 /* Record the fields for the semantic handler. */
1252 FLD (f_r2) = f_r2;
1253 FLD (i_sr) = & CPU (h_gr)[f_r2];
1254 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1255
1256 #if WITH_PROFILE_MODEL_P
1257 /* Record the fields for profiling. */
1258 if (PROFILE_MODEL_P (current_cpu))
1259 {
1260 FLD (in_sr) = f_r2;
1261 }
1262 #endif
1263 #undef FLD
1264 return idesc;
1265 }
1266
1267 extract_sfmt_jl:
1268 {
1269 const IDESC *idesc = &m32r2f_insn_data[itype];
1270 CGEN_INSN_INT insn = entire_insn;
1271 #define FLD(f) abuf->fields.sfmt_jl.f
1272 UINT f_r2;
1273
1274 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1275
1276 /* Record the fields for the semantic handler. */
1277 FLD (f_r2) = f_r2;
1278 FLD (i_sr) = & CPU (h_gr)[f_r2];
1279 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1280
1281 #if WITH_PROFILE_MODEL_P
1282 /* Record the fields for profiling. */
1283 if (PROFILE_MODEL_P (current_cpu))
1284 {
1285 FLD (in_sr) = f_r2;
1286 FLD (out_h_gr_SI_14) = 14;
1287 }
1288 #endif
1289 #undef FLD
1290 return idesc;
1291 }
1292
1293 extract_sfmt_jmp:
1294 {
1295 const IDESC *idesc = &m32r2f_insn_data[itype];
1296 CGEN_INSN_INT insn = entire_insn;
1297 #define FLD(f) abuf->fields.sfmt_jl.f
1298 UINT f_r2;
1299
1300 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1301
1302 /* Record the fields for the semantic handler. */
1303 FLD (f_r2) = f_r2;
1304 FLD (i_sr) = & CPU (h_gr)[f_r2];
1305 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1306
1307 #if WITH_PROFILE_MODEL_P
1308 /* Record the fields for profiling. */
1309 if (PROFILE_MODEL_P (current_cpu))
1310 {
1311 FLD (in_sr) = f_r2;
1312 }
1313 #endif
1314 #undef FLD
1315 return idesc;
1316 }
1317
1318 extract_sfmt_ld:
1319 {
1320 const IDESC *idesc = &m32r2f_insn_data[itype];
1321 CGEN_INSN_INT insn = entire_insn;
1322 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1323 UINT f_r1;
1324 UINT f_r2;
1325
1326 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1327 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1328
1329 /* Record the fields for the semantic handler. */
1330 FLD (f_r2) = f_r2;
1331 FLD (f_r1) = f_r1;
1332 FLD (i_sr) = & CPU (h_gr)[f_r2];
1333 FLD (i_dr) = & CPU (h_gr)[f_r1];
1334 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1335
1336 #if WITH_PROFILE_MODEL_P
1337 /* Record the fields for profiling. */
1338 if (PROFILE_MODEL_P (current_cpu))
1339 {
1340 FLD (in_sr) = f_r2;
1341 FLD (out_dr) = f_r1;
1342 }
1343 #endif
1344 #undef FLD
1345 return idesc;
1346 }
1347
1348 extract_sfmt_ld_d:
1349 {
1350 const IDESC *idesc = &m32r2f_insn_data[itype];
1351 CGEN_INSN_INT insn = entire_insn;
1352 #define FLD(f) abuf->fields.sfmt_add3.f
1353 UINT f_r1;
1354 UINT f_r2;
1355 INT f_simm16;
1356
1357 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1358 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1359 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1360
1361 /* Record the fields for the semantic handler. */
1362 FLD (f_simm16) = f_simm16;
1363 FLD (f_r2) = f_r2;
1364 FLD (f_r1) = f_r1;
1365 FLD (i_sr) = & CPU (h_gr)[f_r2];
1366 FLD (i_dr) = & CPU (h_gr)[f_r1];
1367 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1368
1369 #if WITH_PROFILE_MODEL_P
1370 /* Record the fields for profiling. */
1371 if (PROFILE_MODEL_P (current_cpu))
1372 {
1373 FLD (in_sr) = f_r2;
1374 FLD (out_dr) = f_r1;
1375 }
1376 #endif
1377 #undef FLD
1378 return idesc;
1379 }
1380
1381 extract_sfmt_ldb:
1382 {
1383 const IDESC *idesc = &m32r2f_insn_data[itype];
1384 CGEN_INSN_INT insn = entire_insn;
1385 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1386 UINT f_r1;
1387 UINT f_r2;
1388
1389 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1390 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1391
1392 /* Record the fields for the semantic handler. */
1393 FLD (f_r2) = f_r2;
1394 FLD (f_r1) = f_r1;
1395 FLD (i_sr) = & CPU (h_gr)[f_r2];
1396 FLD (i_dr) = & CPU (h_gr)[f_r1];
1397 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1398
1399 #if WITH_PROFILE_MODEL_P
1400 /* Record the fields for profiling. */
1401 if (PROFILE_MODEL_P (current_cpu))
1402 {
1403 FLD (in_sr) = f_r2;
1404 FLD (out_dr) = f_r1;
1405 }
1406 #endif
1407 #undef FLD
1408 return idesc;
1409 }
1410
1411 extract_sfmt_ldb_d:
1412 {
1413 const IDESC *idesc = &m32r2f_insn_data[itype];
1414 CGEN_INSN_INT insn = entire_insn;
1415 #define FLD(f) abuf->fields.sfmt_add3.f
1416 UINT f_r1;
1417 UINT f_r2;
1418 INT f_simm16;
1419
1420 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1421 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1422 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1423
1424 /* Record the fields for the semantic handler. */
1425 FLD (f_simm16) = f_simm16;
1426 FLD (f_r2) = f_r2;
1427 FLD (f_r1) = f_r1;
1428 FLD (i_sr) = & CPU (h_gr)[f_r2];
1429 FLD (i_dr) = & CPU (h_gr)[f_r1];
1430 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1431
1432 #if WITH_PROFILE_MODEL_P
1433 /* Record the fields for profiling. */
1434 if (PROFILE_MODEL_P (current_cpu))
1435 {
1436 FLD (in_sr) = f_r2;
1437 FLD (out_dr) = f_r1;
1438 }
1439 #endif
1440 #undef FLD
1441 return idesc;
1442 }
1443
1444 extract_sfmt_ldh:
1445 {
1446 const IDESC *idesc = &m32r2f_insn_data[itype];
1447 CGEN_INSN_INT insn = entire_insn;
1448 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1449 UINT f_r1;
1450 UINT f_r2;
1451
1452 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1453 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1454
1455 /* Record the fields for the semantic handler. */
1456 FLD (f_r2) = f_r2;
1457 FLD (f_r1) = f_r1;
1458 FLD (i_sr) = & CPU (h_gr)[f_r2];
1459 FLD (i_dr) = & CPU (h_gr)[f_r1];
1460 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1461
1462 #if WITH_PROFILE_MODEL_P
1463 /* Record the fields for profiling. */
1464 if (PROFILE_MODEL_P (current_cpu))
1465 {
1466 FLD (in_sr) = f_r2;
1467 FLD (out_dr) = f_r1;
1468 }
1469 #endif
1470 #undef FLD
1471 return idesc;
1472 }
1473
1474 extract_sfmt_ldh_d:
1475 {
1476 const IDESC *idesc = &m32r2f_insn_data[itype];
1477 CGEN_INSN_INT insn = entire_insn;
1478 #define FLD(f) abuf->fields.sfmt_add3.f
1479 UINT f_r1;
1480 UINT f_r2;
1481 INT f_simm16;
1482
1483 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1484 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1485 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1486
1487 /* Record the fields for the semantic handler. */
1488 FLD (f_simm16) = f_simm16;
1489 FLD (f_r2) = f_r2;
1490 FLD (f_r1) = f_r1;
1491 FLD (i_sr) = & CPU (h_gr)[f_r2];
1492 FLD (i_dr) = & CPU (h_gr)[f_r1];
1493 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1494
1495 #if WITH_PROFILE_MODEL_P
1496 /* Record the fields for profiling. */
1497 if (PROFILE_MODEL_P (current_cpu))
1498 {
1499 FLD (in_sr) = f_r2;
1500 FLD (out_dr) = f_r1;
1501 }
1502 #endif
1503 #undef FLD
1504 return idesc;
1505 }
1506
1507 extract_sfmt_ld_plus:
1508 {
1509 const IDESC *idesc = &m32r2f_insn_data[itype];
1510 CGEN_INSN_INT insn = entire_insn;
1511 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1512 UINT f_r1;
1513 UINT f_r2;
1514
1515 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1516 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1517
1518 /* Record the fields for the semantic handler. */
1519 FLD (f_r2) = f_r2;
1520 FLD (f_r1) = f_r1;
1521 FLD (i_sr) = & CPU (h_gr)[f_r2];
1522 FLD (i_dr) = & CPU (h_gr)[f_r1];
1523 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1524
1525 #if WITH_PROFILE_MODEL_P
1526 /* Record the fields for profiling. */
1527 if (PROFILE_MODEL_P (current_cpu))
1528 {
1529 FLD (in_sr) = f_r2;
1530 FLD (out_dr) = f_r1;
1531 FLD (out_sr) = f_r2;
1532 }
1533 #endif
1534 #undef FLD
1535 return idesc;
1536 }
1537
1538 extract_sfmt_ld24:
1539 {
1540 const IDESC *idesc = &m32r2f_insn_data[itype];
1541 CGEN_INSN_INT insn = entire_insn;
1542 #define FLD(f) abuf->fields.sfmt_ld24.f
1543 UINT f_r1;
1544 UINT f_uimm24;
1545
1546 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1547 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24);
1548
1549 /* Record the fields for the semantic handler. */
1550 FLD (f_r1) = f_r1;
1551 FLD (i_uimm24) = f_uimm24;
1552 FLD (i_dr) = & CPU (h_gr)[f_r1];
1553 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
1554
1555 #if WITH_PROFILE_MODEL_P
1556 /* Record the fields for profiling. */
1557 if (PROFILE_MODEL_P (current_cpu))
1558 {
1559 FLD (out_dr) = f_r1;
1560 }
1561 #endif
1562 #undef FLD
1563 return idesc;
1564 }
1565
1566 extract_sfmt_ldi8:
1567 {
1568 const IDESC *idesc = &m32r2f_insn_data[itype];
1569 CGEN_INSN_INT insn = entire_insn;
1570 #define FLD(f) abuf->fields.sfmt_addi.f
1571 UINT f_r1;
1572 INT f_simm8;
1573
1574 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1575 f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
1576
1577 /* Record the fields for the semantic handler. */
1578 FLD (f_simm8) = f_simm8;
1579 FLD (f_r1) = f_r1;
1580 FLD (i_dr) = & CPU (h_gr)[f_r1];
1581 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1582
1583 #if WITH_PROFILE_MODEL_P
1584 /* Record the fields for profiling. */
1585 if (PROFILE_MODEL_P (current_cpu))
1586 {
1587 FLD (out_dr) = f_r1;
1588 }
1589 #endif
1590 #undef FLD
1591 return idesc;
1592 }
1593
1594 extract_sfmt_ldi16:
1595 {
1596 const IDESC *idesc = &m32r2f_insn_data[itype];
1597 CGEN_INSN_INT insn = entire_insn;
1598 #define FLD(f) abuf->fields.sfmt_add3.f
1599 UINT f_r1;
1600 INT f_simm16;
1601
1602 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1603 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1604
1605 /* Record the fields for the semantic handler. */
1606 FLD (f_simm16) = f_simm16;
1607 FLD (f_r1) = f_r1;
1608 FLD (i_dr) = & CPU (h_gr)[f_r1];
1609 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1610
1611 #if WITH_PROFILE_MODEL_P
1612 /* Record the fields for profiling. */
1613 if (PROFILE_MODEL_P (current_cpu))
1614 {
1615 FLD (out_dr) = f_r1;
1616 }
1617 #endif
1618 #undef FLD
1619 return idesc;
1620 }
1621
1622 extract_sfmt_lock:
1623 {
1624 const IDESC *idesc = &m32r2f_insn_data[itype];
1625 CGEN_INSN_INT insn = entire_insn;
1626 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1627 UINT f_r1;
1628 UINT f_r2;
1629
1630 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1631 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1632
1633 /* Record the fields for the semantic handler. */
1634 FLD (f_r2) = f_r2;
1635 FLD (f_r1) = f_r1;
1636 FLD (i_sr) = & CPU (h_gr)[f_r2];
1637 FLD (i_dr) = & CPU (h_gr)[f_r1];
1638 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1639
1640 #if WITH_PROFILE_MODEL_P
1641 /* Record the fields for profiling. */
1642 if (PROFILE_MODEL_P (current_cpu))
1643 {
1644 FLD (in_sr) = f_r2;
1645 FLD (out_dr) = f_r1;
1646 }
1647 #endif
1648 #undef FLD
1649 return idesc;
1650 }
1651
1652 extract_sfmt_machi_a:
1653 {
1654 const IDESC *idesc = &m32r2f_insn_data[itype];
1655 CGEN_INSN_INT insn = entire_insn;
1656 #define FLD(f) abuf->fields.sfmt_machi_a.f
1657 UINT f_r1;
1658 UINT f_acc;
1659 UINT f_r2;
1660
1661 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1662 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
1663 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1664
1665 /* Record the fields for the semantic handler. */
1666 FLD (f_acc) = f_acc;
1667 FLD (f_r1) = f_r1;
1668 FLD (f_r2) = f_r2;
1669 FLD (i_src1) = & CPU (h_gr)[f_r1];
1670 FLD (i_src2) = & CPU (h_gr)[f_r2];
1671 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1672
1673 #if WITH_PROFILE_MODEL_P
1674 /* Record the fields for profiling. */
1675 if (PROFILE_MODEL_P (current_cpu))
1676 {
1677 FLD (in_src1) = f_r1;
1678 FLD (in_src2) = f_r2;
1679 }
1680 #endif
1681 #undef FLD
1682 return idesc;
1683 }
1684
1685 extract_sfmt_mulhi_a:
1686 {
1687 const IDESC *idesc = &m32r2f_insn_data[itype];
1688 CGEN_INSN_INT insn = entire_insn;
1689 #define FLD(f) abuf->fields.sfmt_machi_a.f
1690 UINT f_r1;
1691 UINT f_acc;
1692 UINT f_r2;
1693
1694 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1695 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
1696 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1697
1698 /* Record the fields for the semantic handler. */
1699 FLD (f_r1) = f_r1;
1700 FLD (f_r2) = f_r2;
1701 FLD (f_acc) = f_acc;
1702 FLD (i_src1) = & CPU (h_gr)[f_r1];
1703 FLD (i_src2) = & CPU (h_gr)[f_r2];
1704 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1705
1706 #if WITH_PROFILE_MODEL_P
1707 /* Record the fields for profiling. */
1708 if (PROFILE_MODEL_P (current_cpu))
1709 {
1710 FLD (in_src1) = f_r1;
1711 FLD (in_src2) = f_r2;
1712 }
1713 #endif
1714 #undef FLD
1715 return idesc;
1716 }
1717
1718 extract_sfmt_mv:
1719 {
1720 const IDESC *idesc = &m32r2f_insn_data[itype];
1721 CGEN_INSN_INT insn = entire_insn;
1722 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1723 UINT f_r1;
1724 UINT f_r2;
1725
1726 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1727 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1728
1729 /* Record the fields for the semantic handler. */
1730 FLD (f_r2) = f_r2;
1731 FLD (f_r1) = f_r1;
1732 FLD (i_sr) = & CPU (h_gr)[f_r2];
1733 FLD (i_dr) = & CPU (h_gr)[f_r1];
1734 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1735
1736 #if WITH_PROFILE_MODEL_P
1737 /* Record the fields for profiling. */
1738 if (PROFILE_MODEL_P (current_cpu))
1739 {
1740 FLD (in_sr) = f_r2;
1741 FLD (out_dr) = f_r1;
1742 }
1743 #endif
1744 #undef FLD
1745 return idesc;
1746 }
1747
1748 extract_sfmt_mvfachi_a:
1749 {
1750 const IDESC *idesc = &m32r2f_insn_data[itype];
1751 CGEN_INSN_INT insn = entire_insn;
1752 #define FLD(f) abuf->fields.sfmt_mvfachi_a.f
1753 UINT f_r1;
1754 UINT f_accs;
1755
1756 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1757 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1758
1759 /* Record the fields for the semantic handler. */
1760 FLD (f_accs) = f_accs;
1761 FLD (f_r1) = f_r1;
1762 FLD (i_dr) = & CPU (h_gr)[f_r1];
1763 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1764
1765 #if WITH_PROFILE_MODEL_P
1766 /* Record the fields for profiling. */
1767 if (PROFILE_MODEL_P (current_cpu))
1768 {
1769 FLD (out_dr) = f_r1;
1770 }
1771 #endif
1772 #undef FLD
1773 return idesc;
1774 }
1775
1776 extract_sfmt_mvfc:
1777 {
1778 const IDESC *idesc = &m32r2f_insn_data[itype];
1779 CGEN_INSN_INT insn = entire_insn;
1780 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1781 UINT f_r1;
1782 UINT f_r2;
1783
1784 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1785 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1786
1787 /* Record the fields for the semantic handler. */
1788 FLD (f_r2) = f_r2;
1789 FLD (f_r1) = f_r1;
1790 FLD (i_dr) = & CPU (h_gr)[f_r1];
1791 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1792
1793 #if WITH_PROFILE_MODEL_P
1794 /* Record the fields for profiling. */
1795 if (PROFILE_MODEL_P (current_cpu))
1796 {
1797 FLD (out_dr) = f_r1;
1798 }
1799 #endif
1800 #undef FLD
1801 return idesc;
1802 }
1803
1804 extract_sfmt_mvtachi_a:
1805 {
1806 const IDESC *idesc = &m32r2f_insn_data[itype];
1807 CGEN_INSN_INT insn = entire_insn;
1808 #define FLD(f) abuf->fields.sfmt_mvtachi_a.f
1809 UINT f_r1;
1810 UINT f_accs;
1811
1812 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1813 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1814
1815 /* Record the fields for the semantic handler. */
1816 FLD (f_accs) = f_accs;
1817 FLD (f_r1) = f_r1;
1818 FLD (i_src1) = & CPU (h_gr)[f_r1];
1819 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0));
1820
1821 #if WITH_PROFILE_MODEL_P
1822 /* Record the fields for profiling. */
1823 if (PROFILE_MODEL_P (current_cpu))
1824 {
1825 FLD (in_src1) = f_r1;
1826 }
1827 #endif
1828 #undef FLD
1829 return idesc;
1830 }
1831
1832 extract_sfmt_mvtc:
1833 {
1834 const IDESC *idesc = &m32r2f_insn_data[itype];
1835 CGEN_INSN_INT insn = entire_insn;
1836 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1837 UINT f_r1;
1838 UINT f_r2;
1839
1840 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1841 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1842
1843 /* Record the fields for the semantic handler. */
1844 FLD (f_r2) = f_r2;
1845 FLD (f_r1) = f_r1;
1846 FLD (i_sr) = & CPU (h_gr)[f_r2];
1847 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1848
1849 #if WITH_PROFILE_MODEL_P
1850 /* Record the fields for profiling. */
1851 if (PROFILE_MODEL_P (current_cpu))
1852 {
1853 FLD (in_sr) = f_r2;
1854 }
1855 #endif
1856 #undef FLD
1857 return idesc;
1858 }
1859
1860 extract_sfmt_nop:
1861 {
1862 const IDESC *idesc = &m32r2f_insn_data[itype];
1863 #define FLD(f) abuf->fields.fmt_empty.f
1864
1865
1866 /* Record the fields for the semantic handler. */
1867 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0));
1868
1869 #undef FLD
1870 return idesc;
1871 }
1872
1873 extract_sfmt_rac_dsi:
1874 {
1875 const IDESC *idesc = &m32r2f_insn_data[itype];
1876 CGEN_INSN_INT insn = entire_insn;
1877 #define FLD(f) abuf->fields.sfmt_rac_dsi.f
1878 UINT f_accd;
1879 UINT f_accs;
1880 SI f_imm1;
1881
1882 f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2);
1883 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1884 f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1));
1885
1886 /* Record the fields for the semantic handler. */
1887 FLD (f_accs) = f_accs;
1888 FLD (f_imm1) = f_imm1;
1889 FLD (f_accd) = f_accd;
1890 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0));
1891
1892 #undef FLD
1893 return idesc;
1894 }
1895
1896 extract_sfmt_rte:
1897 {
1898 const IDESC *idesc = &m32r2f_insn_data[itype];
1899 #define FLD(f) abuf->fields.fmt_empty.f
1900
1901
1902 /* Record the fields for the semantic handler. */
1903 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0));
1904
1905 #if WITH_PROFILE_MODEL_P
1906 /* Record the fields for profiling. */
1907 if (PROFILE_MODEL_P (current_cpu))
1908 {
1909 }
1910 #endif
1911 #undef FLD
1912 return idesc;
1913 }
1914
1915 extract_sfmt_seth:
1916 {
1917 const IDESC *idesc = &m32r2f_insn_data[itype];
1918 CGEN_INSN_INT insn = entire_insn;
1919 #define FLD(f) abuf->fields.sfmt_seth.f
1920 UINT f_r1;
1921 UINT f_hi16;
1922
1923 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1924 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
1925
1926 /* Record the fields for the semantic handler. */
1927 FLD (f_hi16) = f_hi16;
1928 FLD (f_r1) = f_r1;
1929 FLD (i_dr) = & CPU (h_gr)[f_r1];
1930 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1931
1932 #if WITH_PROFILE_MODEL_P
1933 /* Record the fields for profiling. */
1934 if (PROFILE_MODEL_P (current_cpu))
1935 {
1936 FLD (out_dr) = f_r1;
1937 }
1938 #endif
1939 #undef FLD
1940 return idesc;
1941 }
1942
1943 extract_sfmt_sll3:
1944 {
1945 const IDESC *idesc = &m32r2f_insn_data[itype];
1946 CGEN_INSN_INT insn = entire_insn;
1947 #define FLD(f) abuf->fields.sfmt_add3.f
1948 UINT f_r1;
1949 UINT f_r2;
1950 INT f_simm16;
1951
1952 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1953 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1954 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1955
1956 /* Record the fields for the semantic handler. */
1957 FLD (f_simm16) = f_simm16;
1958 FLD (f_r2) = f_r2;
1959 FLD (f_r1) = f_r1;
1960 FLD (i_sr) = & CPU (h_gr)[f_r2];
1961 FLD (i_dr) = & CPU (h_gr)[f_r1];
1962 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1963
1964 #if WITH_PROFILE_MODEL_P
1965 /* Record the fields for profiling. */
1966 if (PROFILE_MODEL_P (current_cpu))
1967 {
1968 FLD (in_sr) = f_r2;
1969 FLD (out_dr) = f_r1;
1970 }
1971 #endif
1972 #undef FLD
1973 return idesc;
1974 }
1975
1976 extract_sfmt_slli:
1977 {
1978 const IDESC *idesc = &m32r2f_insn_data[itype];
1979 CGEN_INSN_INT insn = entire_insn;
1980 #define FLD(f) abuf->fields.sfmt_slli.f
1981 UINT f_r1;
1982 UINT f_uimm5;
1983
1984 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1985 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5);
1986
1987 /* Record the fields for the semantic handler. */
1988 FLD (f_r1) = f_r1;
1989 FLD (f_uimm5) = f_uimm5;
1990 FLD (i_dr) = & CPU (h_gr)[f_r1];
1991 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
1992
1993 #if WITH_PROFILE_MODEL_P
1994 /* Record the fields for profiling. */
1995 if (PROFILE_MODEL_P (current_cpu))
1996 {
1997 FLD (in_dr) = f_r1;
1998 FLD (out_dr) = f_r1;
1999 }
2000 #endif
2001 #undef FLD
2002 return idesc;
2003 }
2004
2005 extract_sfmt_st:
2006 {
2007 const IDESC *idesc = &m32r2f_insn_data[itype];
2008 CGEN_INSN_INT insn = entire_insn;
2009 #define FLD(f) abuf->fields.sfmt_st_plus.f
2010 UINT f_r1;
2011 UINT f_r2;
2012
2013 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2014 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2015
2016 /* Record the fields for the semantic handler. */
2017 FLD (f_r1) = f_r1;
2018 FLD (f_r2) = f_r2;
2019 FLD (i_src1) = & CPU (h_gr)[f_r1];
2020 FLD (i_src2) = & CPU (h_gr)[f_r2];
2021 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2022
2023 #if WITH_PROFILE_MODEL_P
2024 /* Record the fields for profiling. */
2025 if (PROFILE_MODEL_P (current_cpu))
2026 {
2027 FLD (in_src1) = f_r1;
2028 FLD (in_src2) = f_r2;
2029 }
2030 #endif
2031 #undef FLD
2032 return idesc;
2033 }
2034
2035 extract_sfmt_st_d:
2036 {
2037 const IDESC *idesc = &m32r2f_insn_data[itype];
2038 CGEN_INSN_INT insn = entire_insn;
2039 #define FLD(f) abuf->fields.sfmt_st_d.f
2040 UINT f_r1;
2041 UINT f_r2;
2042 INT f_simm16;
2043
2044 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2045 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2046 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
2047
2048 /* Record the fields for the semantic handler. */
2049 FLD (f_simm16) = f_simm16;
2050 FLD (f_r1) = f_r1;
2051 FLD (f_r2) = f_r2;
2052 FLD (i_src1) = & CPU (h_gr)[f_r1];
2053 FLD (i_src2) = & CPU (h_gr)[f_r2];
2054 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2055
2056 #if WITH_PROFILE_MODEL_P
2057 /* Record the fields for profiling. */
2058 if (PROFILE_MODEL_P (current_cpu))
2059 {
2060 FLD (in_src1) = f_r1;
2061 FLD (in_src2) = f_r2;
2062 }
2063 #endif
2064 #undef FLD
2065 return idesc;
2066 }
2067
2068 extract_sfmt_stb:
2069 {
2070 const IDESC *idesc = &m32r2f_insn_data[itype];
2071 CGEN_INSN_INT insn = entire_insn;
2072 #define FLD(f) abuf->fields.sfmt_st_plus.f
2073 UINT f_r1;
2074 UINT f_r2;
2075
2076 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2077 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2078
2079 /* Record the fields for the semantic handler. */
2080 FLD (f_r1) = f_r1;
2081 FLD (f_r2) = f_r2;
2082 FLD (i_src1) = & CPU (h_gr)[f_r1];
2083 FLD (i_src2) = & CPU (h_gr)[f_r2];
2084 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2085
2086 #if WITH_PROFILE_MODEL_P
2087 /* Record the fields for profiling. */
2088 if (PROFILE_MODEL_P (current_cpu))
2089 {
2090 FLD (in_src1) = f_r1;
2091 FLD (in_src2) = f_r2;
2092 }
2093 #endif
2094 #undef FLD
2095 return idesc;
2096 }
2097
2098 extract_sfmt_stb_d:
2099 {
2100 const IDESC *idesc = &m32r2f_insn_data[itype];
2101 CGEN_INSN_INT insn = entire_insn;
2102 #define FLD(f) abuf->fields.sfmt_st_d.f
2103 UINT f_r1;
2104 UINT f_r2;
2105 INT f_simm16;
2106
2107 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2108 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2109 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
2110
2111 /* Record the fields for the semantic handler. */
2112 FLD (f_simm16) = f_simm16;
2113 FLD (f_r1) = f_r1;
2114 FLD (f_r2) = f_r2;
2115 FLD (i_src1) = & CPU (h_gr)[f_r1];
2116 FLD (i_src2) = & CPU (h_gr)[f_r2];
2117 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2118
2119 #if WITH_PROFILE_MODEL_P
2120 /* Record the fields for profiling. */
2121 if (PROFILE_MODEL_P (current_cpu))
2122 {
2123 FLD (in_src1) = f_r1;
2124 FLD (in_src2) = f_r2;
2125 }
2126 #endif
2127 #undef FLD
2128 return idesc;
2129 }
2130
2131 extract_sfmt_sth:
2132 {
2133 const IDESC *idesc = &m32r2f_insn_data[itype];
2134 CGEN_INSN_INT insn = entire_insn;
2135 #define FLD(f) abuf->fields.sfmt_st_plus.f
2136 UINT f_r1;
2137 UINT f_r2;
2138
2139 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2140 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2141
2142 /* Record the fields for the semantic handler. */
2143 FLD (f_r1) = f_r1;
2144 FLD (f_r2) = f_r2;
2145 FLD (i_src1) = & CPU (h_gr)[f_r1];
2146 FLD (i_src2) = & CPU (h_gr)[f_r2];
2147 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2148
2149 #if WITH_PROFILE_MODEL_P
2150 /* Record the fields for profiling. */
2151 if (PROFILE_MODEL_P (current_cpu))
2152 {
2153 FLD (in_src1) = f_r1;
2154 FLD (in_src2) = f_r2;
2155 }
2156 #endif
2157 #undef FLD
2158 return idesc;
2159 }
2160
2161 extract_sfmt_sth_d:
2162 {
2163 const IDESC *idesc = &m32r2f_insn_data[itype];
2164 CGEN_INSN_INT insn = entire_insn;
2165 #define FLD(f) abuf->fields.sfmt_st_d.f
2166 UINT f_r1;
2167 UINT f_r2;
2168 INT f_simm16;
2169
2170 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2171 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2172 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
2173
2174 /* Record the fields for the semantic handler. */
2175 FLD (f_simm16) = f_simm16;
2176 FLD (f_r1) = f_r1;
2177 FLD (f_r2) = f_r2;
2178 FLD (i_src1) = & CPU (h_gr)[f_r1];
2179 FLD (i_src2) = & CPU (h_gr)[f_r2];
2180 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2181
2182 #if WITH_PROFILE_MODEL_P
2183 /* Record the fields for profiling. */
2184 if (PROFILE_MODEL_P (current_cpu))
2185 {
2186 FLD (in_src1) = f_r1;
2187 FLD (in_src2) = f_r2;
2188 }
2189 #endif
2190 #undef FLD
2191 return idesc;
2192 }
2193
2194 extract_sfmt_st_plus:
2195 {
2196 const IDESC *idesc = &m32r2f_insn_data[itype];
2197 CGEN_INSN_INT insn = entire_insn;
2198 #define FLD(f) abuf->fields.sfmt_st_plus.f
2199 UINT f_r1;
2200 UINT f_r2;
2201
2202 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2203 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2204
2205 /* Record the fields for the semantic handler. */
2206 FLD (f_r1) = f_r1;
2207 FLD (f_r2) = f_r2;
2208 FLD (i_src1) = & CPU (h_gr)[f_r1];
2209 FLD (i_src2) = & CPU (h_gr)[f_r2];
2210 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2211
2212 #if WITH_PROFILE_MODEL_P
2213 /* Record the fields for profiling. */
2214 if (PROFILE_MODEL_P (current_cpu))
2215 {
2216 FLD (in_src1) = f_r1;
2217 FLD (in_src2) = f_r2;
2218 FLD (out_src2) = f_r2;
2219 }
2220 #endif
2221 #undef FLD
2222 return idesc;
2223 }
2224
2225 extract_sfmt_sth_plus:
2226 {
2227 const IDESC *idesc = &m32r2f_insn_data[itype];
2228 CGEN_INSN_INT insn = entire_insn;
2229 #define FLD(f) abuf->fields.sfmt_st_plus.f
2230 UINT f_r1;
2231 UINT f_r2;
2232
2233 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2234 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2235
2236 /* Record the fields for the semantic handler. */
2237 FLD (f_r1) = f_r1;
2238 FLD (f_r2) = f_r2;
2239 FLD (i_src1) = & CPU (h_gr)[f_r1];
2240 FLD (i_src2) = & CPU (h_gr)[f_r2];
2241 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2242
2243 #if WITH_PROFILE_MODEL_P
2244 /* Record the fields for profiling. */
2245 if (PROFILE_MODEL_P (current_cpu))
2246 {
2247 FLD (in_src1) = f_r1;
2248 FLD (in_src2) = f_r2;
2249 FLD (out_src2) = f_r2;
2250 }
2251 #endif
2252 #undef FLD
2253 return idesc;
2254 }
2255
2256 extract_sfmt_stb_plus:
2257 {
2258 const IDESC *idesc = &m32r2f_insn_data[itype];
2259 CGEN_INSN_INT insn = entire_insn;
2260 #define FLD(f) abuf->fields.sfmt_st_plus.f
2261 UINT f_r1;
2262 UINT f_r2;
2263
2264 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2265 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2266
2267 /* Record the fields for the semantic handler. */
2268 FLD (f_r1) = f_r1;
2269 FLD (f_r2) = f_r2;
2270 FLD (i_src1) = & CPU (h_gr)[f_r1];
2271 FLD (i_src2) = & CPU (h_gr)[f_r2];
2272 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2273
2274 #if WITH_PROFILE_MODEL_P
2275 /* Record the fields for profiling. */
2276 if (PROFILE_MODEL_P (current_cpu))
2277 {
2278 FLD (in_src1) = f_r1;
2279 FLD (in_src2) = f_r2;
2280 FLD (out_src2) = f_r2;
2281 }
2282 #endif
2283 #undef FLD
2284 return idesc;
2285 }
2286
2287 extract_sfmt_trap:
2288 {
2289 const IDESC *idesc = &m32r2f_insn_data[itype];
2290 CGEN_INSN_INT insn = entire_insn;
2291 #define FLD(f) abuf->fields.sfmt_trap.f
2292 UINT f_uimm4;
2293
2294 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2295
2296 /* Record the fields for the semantic handler. */
2297 FLD (f_uimm4) = f_uimm4;
2298 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
2299
2300 #if WITH_PROFILE_MODEL_P
2301 /* Record the fields for profiling. */
2302 if (PROFILE_MODEL_P (current_cpu))
2303 {
2304 }
2305 #endif
2306 #undef FLD
2307 return idesc;
2308 }
2309
2310 extract_sfmt_unlock:
2311 {
2312 const IDESC *idesc = &m32r2f_insn_data[itype];
2313 CGEN_INSN_INT insn = entire_insn;
2314 #define FLD(f) abuf->fields.sfmt_st_plus.f
2315 UINT f_r1;
2316 UINT f_r2;
2317
2318 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2319 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2320
2321 /* Record the fields for the semantic handler. */
2322 FLD (f_r1) = f_r1;
2323 FLD (f_r2) = f_r2;
2324 FLD (i_src1) = & CPU (h_gr)[f_r1];
2325 FLD (i_src2) = & CPU (h_gr)[f_r2];
2326 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2327
2328 #if WITH_PROFILE_MODEL_P
2329 /* Record the fields for profiling. */
2330 if (PROFILE_MODEL_P (current_cpu))
2331 {
2332 FLD (in_src1) = f_r1;
2333 FLD (in_src2) = f_r2;
2334 }
2335 #endif
2336 #undef FLD
2337 return idesc;
2338 }
2339
2340 extract_sfmt_satb:
2341 {
2342 const IDESC *idesc = &m32r2f_insn_data[itype];
2343 CGEN_INSN_INT insn = entire_insn;
2344 #define FLD(f) abuf->fields.sfmt_ld_plus.f
2345 UINT f_r1;
2346 UINT f_r2;
2347
2348 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2349 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2350
2351 /* Record the fields for the semantic handler. */
2352 FLD (f_r2) = f_r2;
2353 FLD (f_r1) = f_r1;
2354 FLD (i_sr) = & CPU (h_gr)[f_r2];
2355 FLD (i_dr) = & CPU (h_gr)[f_r1];
2356 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2357
2358 #if WITH_PROFILE_MODEL_P
2359 /* Record the fields for profiling. */
2360 if (PROFILE_MODEL_P (current_cpu))
2361 {
2362 FLD (in_sr) = f_r2;
2363 FLD (out_dr) = f_r1;
2364 }
2365 #endif
2366 #undef FLD
2367 return idesc;
2368 }
2369
2370 extract_sfmt_sat:
2371 {
2372 const IDESC *idesc = &m32r2f_insn_data[itype];
2373 CGEN_INSN_INT insn = entire_insn;
2374 #define FLD(f) abuf->fields.sfmt_ld_plus.f
2375 UINT f_r1;
2376 UINT f_r2;
2377
2378 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2379 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2380
2381 /* Record the fields for the semantic handler. */
2382 FLD (f_r2) = f_r2;
2383 FLD (f_r1) = f_r1;
2384 FLD (i_sr) = & CPU (h_gr)[f_r2];
2385 FLD (i_dr) = & CPU (h_gr)[f_r1];
2386 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2387
2388 #if WITH_PROFILE_MODEL_P
2389 /* Record the fields for profiling. */
2390 if (PROFILE_MODEL_P (current_cpu))
2391 {
2392 FLD (in_sr) = f_r2;
2393 FLD (out_dr) = f_r1;
2394 }
2395 #endif
2396 #undef FLD
2397 return idesc;
2398 }
2399
2400 extract_sfmt_sadd:
2401 {
2402 const IDESC *idesc = &m32r2f_insn_data[itype];
2403 #define FLD(f) abuf->fields.fmt_empty.f
2404
2405
2406 /* Record the fields for the semantic handler. */
2407 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0));
2408
2409 #undef FLD
2410 return idesc;
2411 }
2412
2413 extract_sfmt_macwu1:
2414 {
2415 const IDESC *idesc = &m32r2f_insn_data[itype];
2416 CGEN_INSN_INT insn = entire_insn;
2417 #define FLD(f) abuf->fields.sfmt_st_plus.f
2418 UINT f_r1;
2419 UINT f_r2;
2420
2421 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2422 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2423
2424 /* Record the fields for the semantic handler. */
2425 FLD (f_r1) = f_r1;
2426 FLD (f_r2) = f_r2;
2427 FLD (i_src1) = & CPU (h_gr)[f_r1];
2428 FLD (i_src2) = & CPU (h_gr)[f_r2];
2429 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2430
2431 #if WITH_PROFILE_MODEL_P
2432 /* Record the fields for profiling. */
2433 if (PROFILE_MODEL_P (current_cpu))
2434 {
2435 FLD (in_src1) = f_r1;
2436 FLD (in_src2) = f_r2;
2437 }
2438 #endif
2439 #undef FLD
2440 return idesc;
2441 }
2442
2443 extract_sfmt_msblo:
2444 {
2445 const IDESC *idesc = &m32r2f_insn_data[itype];
2446 CGEN_INSN_INT insn = entire_insn;
2447 #define FLD(f) abuf->fields.sfmt_st_plus.f
2448 UINT f_r1;
2449 UINT f_r2;
2450
2451 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2452 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2453
2454 /* Record the fields for the semantic handler. */
2455 FLD (f_r1) = f_r1;
2456 FLD (f_r2) = f_r2;
2457 FLD (i_src1) = & CPU (h_gr)[f_r1];
2458 FLD (i_src2) = & CPU (h_gr)[f_r2];
2459 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2460
2461 #if WITH_PROFILE_MODEL_P
2462 /* Record the fields for profiling. */
2463 if (PROFILE_MODEL_P (current_cpu))
2464 {
2465 FLD (in_src1) = f_r1;
2466 FLD (in_src2) = f_r2;
2467 }
2468 #endif
2469 #undef FLD
2470 return idesc;
2471 }
2472
2473 extract_sfmt_mulwu1:
2474 {
2475 const IDESC *idesc = &m32r2f_insn_data[itype];
2476 CGEN_INSN_INT insn = entire_insn;
2477 #define FLD(f) abuf->fields.sfmt_st_plus.f
2478 UINT f_r1;
2479 UINT f_r2;
2480
2481 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2482 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2483
2484 /* Record the fields for the semantic handler. */
2485 FLD (f_r1) = f_r1;
2486 FLD (f_r2) = f_r2;
2487 FLD (i_src1) = & CPU (h_gr)[f_r1];
2488 FLD (i_src2) = & CPU (h_gr)[f_r2];
2489 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2490
2491 #if WITH_PROFILE_MODEL_P
2492 /* Record the fields for profiling. */
2493 if (PROFILE_MODEL_P (current_cpu))
2494 {
2495 FLD (in_src1) = f_r1;
2496 FLD (in_src2) = f_r2;
2497 }
2498 #endif
2499 #undef FLD
2500 return idesc;
2501 }
2502
2503 extract_sfmt_sc:
2504 {
2505 const IDESC *idesc = &m32r2f_insn_data[itype];
2506 #define FLD(f) abuf->fields.fmt_empty.f
2507
2508
2509 /* Record the fields for the semantic handler. */
2510 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0));
2511
2512 #undef FLD
2513 return idesc;
2514 }
2515
2516 extract_sfmt_clrpsw:
2517 {
2518 const IDESC *idesc = &m32r2f_insn_data[itype];
2519 CGEN_INSN_INT insn = entire_insn;
2520 #define FLD(f) abuf->fields.sfmt_clrpsw.f
2521 UINT f_uimm8;
2522
2523 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
2524
2525 /* Record the fields for the semantic handler. */
2526 FLD (f_uimm8) = f_uimm8;
2527 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
2528
2529 #undef FLD
2530 return idesc;
2531 }
2532
2533 extract_sfmt_setpsw:
2534 {
2535 const IDESC *idesc = &m32r2f_insn_data[itype];
2536 CGEN_INSN_INT insn = entire_insn;
2537 #define FLD(f) abuf->fields.sfmt_clrpsw.f
2538 UINT f_uimm8;
2539
2540 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
2541
2542 /* Record the fields for the semantic handler. */
2543 FLD (f_uimm8) = f_uimm8;
2544 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
2545
2546 #undef FLD
2547 return idesc;
2548 }
2549
2550 extract_sfmt_bset:
2551 {
2552 const IDESC *idesc = &m32r2f_insn_data[itype];
2553 CGEN_INSN_INT insn = entire_insn;
2554 #define FLD(f) abuf->fields.sfmt_bset.f
2555 UINT f_uimm3;
2556 UINT f_r2;
2557 INT f_simm16;
2558
2559 f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
2560 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2561 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
2562
2563 /* Record the fields for the semantic handler. */
2564 FLD (f_simm16) = f_simm16;
2565 FLD (f_r2) = f_r2;
2566 FLD (f_uimm3) = f_uimm3;
2567 FLD (i_sr) = & CPU (h_gr)[f_r2];
2568 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
2569
2570 #if WITH_PROFILE_MODEL_P
2571 /* Record the fields for profiling. */
2572 if (PROFILE_MODEL_P (current_cpu))
2573 {
2574 FLD (in_sr) = f_r2;
2575 }
2576 #endif
2577 #undef FLD
2578 return idesc;
2579 }
2580
2581 extract_sfmt_btst:
2582 {
2583 const IDESC *idesc = &m32r2f_insn_data[itype];
2584 CGEN_INSN_INT insn = entire_insn;
2585 #define FLD(f) abuf->fields.sfmt_bset.f
2586 UINT f_uimm3;
2587 UINT f_r2;
2588
2589 f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3);
2590 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2591
2592 /* Record the fields for the semantic handler. */
2593 FLD (f_r2) = f_r2;
2594 FLD (f_uimm3) = f_uimm3;
2595 FLD (i_sr) = & CPU (h_gr)[f_r2];
2596 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
2597
2598 #if WITH_PROFILE_MODEL_P
2599 /* Record the fields for profiling. */
2600 if (PROFILE_MODEL_P (current_cpu))
2601 {
2602 FLD (in_sr) = f_r2;
2603 }
2604 #endif
2605 #undef FLD
2606 return idesc;
2607 }
2608
2609 }
A mirror of the official binutils-gdb repository