sim/m32r/m32r-sim.h

   1 /* collection of junk waiting time to sort out
   2    Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of the GNU Simulators.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef M32R_SIM_H
  22 #define M32R_SIM_H
  23
  24 /* gdb register numbers */
  25 #define PSW_REGNUM      16
  26 #define CBR_REGNUM      17
  27 #define SPI_REGNUM      18
  28 #define SPU_REGNUM      19
  29 #define BPC_REGNUM      20
  30 #define PC_REGNUM       21
  31 #define ACCL_REGNUM     22
  32 #define ACCH_REGNUM     23
  33 #define ACC1L_REGNUM    24
  34 #define ACC1H_REGNUM    25
  35 #define BBPSW_REGNUM    26
  36 #define BBPC_REGNUM     27
  37
  38 extern int m32r_decode_gdb_ctrl_regnum (int);
  39
  40 /* Cover macros for hardware accesses.
  41    FIXME: Eventually move to cgen.  */
  42 #define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
  43
  44 extern SI a_m32r_h_gr_get (SIM_CPU *, UINT);
  45 extern void a_m32r_h_gr_set (SIM_CPU *, UINT, SI);
  46 extern USI a_m32r_h_cr_get (SIM_CPU *, UINT);
  47 extern void a_m32r_h_cr_set (SIM_CPU *, UINT, USI);
  48
  49 extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
  50 extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
  51
  52 extern UQI m32rbf_h_psw_get_handler (SIM_CPU *);
  53 extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
  54
  55 extern DI m32rbf_h_accum_get_handler (SIM_CPU *);
  56 extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
  57
  58 extern USI m32rxf_h_cr_get_handler (SIM_CPU *, UINT);
  59 extern void m32rxf_h_cr_set_handler (SIM_CPU *, UINT, USI);
  60 extern UQI m32rxf_h_psw_get_handler (SIM_CPU *);
  61 extern void m32rxf_h_psw_set_handler (SIM_CPU *, UQI);
  62 extern DI m32rxf_h_accum_get_handler (SIM_CPU *);
  63 extern void m32rxf_h_accum_set_handler (SIM_CPU *, DI);
  64
  65 extern DI m32rxf_h_accums_get_handler (SIM_CPU *, UINT);
  66 extern void m32rxf_h_accums_set_handler (SIM_CPU *, UINT, DI);
  67 \f
  68 /* Misc. profile data.  */
  69
  70 typedef struct {
  71   /* nop insn slot filler count */
  72   unsigned int fillnop_count;
  73   /* number of parallel insns */
  74   unsigned int parallel_count;
  75
  76   /* FIXME: generalize this to handle all insn lengths, move to common.  */
  77   /* number of short insns, not including parallel ones */
  78   unsigned int short_count;
  79   /* number of long insns */
  80   unsigned int long_count;
  81
  82   /* Working area for computing cycle counts.  */
  83   unsigned long insn_cycles; /* FIXME: delete */
  84   unsigned long cti_stall;
  85   unsigned long load_stall;
  86   unsigned long biggest_cycles;
  87
  88   /* Bitmask of registers loaded by previous insn.  */
  89   unsigned int load_regs;
  90   /* Bitmask of registers loaded by current insn.  */
  91   unsigned int load_regs_pending;
  92 } M32R_MISC_PROFILE;
  93
  94 /* Initialize the working area.  */
  95 void m32r_init_insn_cycles (SIM_CPU *, int);
  96 /* Update the totals for the insn.  */
  97 void m32r_record_insn_cycles (SIM_CPU *, int);
  98
  99 /* This is invoked by the nop pattern in the .cpu file.  */
 100 #define PROFILE_COUNT_FILLNOPS(cpu, addr) \
 101 do { \
 102   if (PROFILE_INSN_P (cpu) \
 103       && (addr & 3) != 0) \
 104     ++ CPU_M32R_MISC_PROFILE (cpu)->fillnop_count; \
 105 } while (0)
 106
 107 /* This is invoked by the execute section of mloop{,x}.in.  */
 108 #define PROFILE_COUNT_PARINSNS(cpu) \
 109 do { \
 110   if (PROFILE_INSN_P (cpu)) \
 111     ++ CPU_M32R_MISC_PROFILE (cpu)->parallel_count; \
 112 } while (0)
 113
 114 /* This is invoked by the execute section of mloop{,x}.in.  */
 115 #define PROFILE_COUNT_SHORTINSNS(cpu) \
 116 do { \
 117   if (PROFILE_INSN_P (cpu)) \
 118     ++ CPU_M32R_MISC_PROFILE (cpu)->short_count; \
 119 } while (0)
 120
 121 /* This is invoked by the execute section of mloop{,x}.in.  */
 122 #define PROFILE_COUNT_LONGINSNS(cpu) \
 123 do { \
 124   if (PROFILE_INSN_P (cpu)) \
 125     ++ CPU_M32R_MISC_PROFILE (cpu)->long_count; \
 126 } while (0)
 127 \f
 128 #define GETTWI GETTSI
 129 #define SETTWI SETTSI
 130 \f
 131 /* Additional execution support.  */
 132
 133 /* Result of semantic function is one of
 134    - next address, branch only
 135    - NEW_PC_SKIP, sc/snc insn
 136    - NEW_PC_2, 2 byte non-branch non-sc/snc insn
 137    - NEW_PC_4, 4 byte non-branch insn
 138    The special values have bit 1 set so it's cheap to distinguish them.
 139    This works because all cti's are defined to zero the bottom two bits
 140    Note that the m32rx no longer doesn't implement its semantics with
 141    functions, so this isn't used.  It's kept around should it be needed
 142    again.  */
 143 /* FIXME: replace 0xffff0001 with 1?  */
 144 #define NEW_PC_BASE 0xffff0001
 145 #define NEW_PC_SKIP NEW_PC_BASE
 146 #define NEW_PC_2 (NEW_PC_BASE + 2)
 147 #define NEW_PC_4 (NEW_PC_BASE + 4)
 148 #define NEW_PC_BRANCH_P(addr) (((addr) & 1) == 0)
 149
 150 /* Modify "next pc" support to handle parallel execution.
 151    This is for the non-pbb case.  The m32rx no longer implements this.
 152    It's kept around should it be needed again.  */
 153 #if defined (WANT_CPU_M32RXF) && ! WITH_SCACHE_PBB_M32RXF
 154 #undef SEM_NEXT_VPC
 155 #define SEM_NEXT_VPC(abuf, len) (NEW_PC_BASE + (len))
 156 #undef SEM_SKIP_INSN
 157 #define SEM_SKIP_INSN(cpu, sc, vpcvar, yes) FIXME
 158 #endif
 159 \f
 160 /* Hardware/device support.
 161    ??? Will eventually want to move device stuff to config files.  */
 162
 163 /* Exception, Interrupt, and Trap addresses */
 164 #define EIT_SYSBREAK_ADDR       0x10
 165 #define EIT_RSVD_INSN_ADDR      0x20
 166 #define EIT_ADDR_EXCP_ADDR      0x30
 167 #define EIT_TRAP_BASE_ADDR      0x40
 168 #define EIT_EXTERN_ADDR         0x80
 169 #define EIT_RESET_ADDR          0x7ffffff0
 170 #define EIT_WAKEUP_ADDR         0x7ffffff0
 171
 172 /* Special purpose traps.  */
 173 #define TRAP_SYSCALL    0
 174 #define TRAP_BREAKPOINT 1
 175
 176 /* Support for the MSPR register (Cache Purge Control Register)
 177    and the MCCR register (Cache Control Register) are needed in order for
 178    overlays to work correctly with the scache.
 179    MSPR no longer exists but is supported for upward compatibility with
 180    early overlay support.  */
 181
 182 /* Cache Purge Control (only exists on early versions of chips) */
 183 #define MSPR_ADDR 0xfffffff7
 184 #define MSPR_PURGE 1
 185
 186 /* Lock Control Register (not supported) */
 187 #define MLCR_ADDR 0xfffffff7
 188 #define MLCR_LM 1
 189
 190 /* Power Management Control Register (not supported) */
 191 #define MPMR_ADDR 0xfffffffb
 192
 193 /* Cache Control Register */
 194 #define MCCR_ADDR 0xffffffff
 195 #define MCCR_CP 0x80
 196 /* not supported */
 197 #define MCCR_CM0 2
 198 #define MCCR_CM1 1
 199
 200 /* Serial device addresses.  */
 201 #ifdef M32R_EVA /* orig eva board, no longer supported */
 202 #define UART_INCHAR_ADDR        0xff102013
 203 #define UART_OUTCHAR_ADDR       0xff10200f
 204 #define UART_STATUS_ADDR        0xff102006
 205 /* Indicate ready bit is inverted.  */
 206 #define UART_INPUT_READY0
 207 #else
 208 /* These are the values for the MSA2000 board.
 209    ??? Will eventually need to move this to a config file.  */
 210 #define UART_INCHAR_ADDR        0xff004009
 211 #define UART_OUTCHAR_ADDR       0xff004007
 212 #define UART_STATUS_ADDR        0xff004002
 213 #endif
 214
 215 #define UART_INPUT_READY        0x4
 216 #define UART_OUTPUT_READY       0x1
 217
 218 /* Start address and length of all device support.  */
 219 #define M32R_DEVICE_ADDR        0xff000000
 220 #define M32R_DEVICE_LEN         0x01000000
 221
 222 /* sim_core_attach device argument.  */
 223 extern device m32r_devices;
 224
 225 /* FIXME: Temporary, until device support ready.  */
 226 struct _device { int foo; };
 227
 228 /* Handle the trap insn.  */
 229 USI m32r_trap (SIM_CPU *, PCADDR, int);
 230
 231 #endif /* M32R_SIM_H */