sim/m32r/m32r.c

   1 /* m32r simulator support code
   2    Copyright (C) 1996-2021 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5    This file is part of GDB, the GNU debugger.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #define WANT_CPU m32rbf
  21 #define WANT_CPU_M32RBF
  22
  23 #include "sim-main.h"
  24 #include "cgen-mem.h"
  25 #include "cgen-ops.h"
  26
  27 /* Return the size of REGNO in bytes.  */
  28
  29 static int
  30 m32rbf_register_size (int regno)
  31 {
  32   return 4;
  33 }
  34
  35 /* Decode gdb ctrl register number.  */
  36
  37 int
  38 m32r_decode_gdb_ctrl_regnum (int gdb_regnum)
  39 {
  40   switch (gdb_regnum)
  41     {
  42       case PSW_REGNUM : return H_CR_PSW;
  43       case CBR_REGNUM : return H_CR_CBR;
  44       case SPI_REGNUM : return H_CR_SPI;
  45       case SPU_REGNUM : return H_CR_SPU;
  46       case BPC_REGNUM : return H_CR_BPC;
  47       case BBPSW_REGNUM : return H_CR_BBPSW;
  48       case BBPC_REGNUM : return H_CR_BBPC;
  49       case EVB_REGNUM : return H_CR_CR5;
  50     }
  51   abort ();
  52 }
  53
  54 /* The contents of BUF are in target byte order.  */
  55
  56 int
  57 m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
  58 {
  59   int size = m32rbf_register_size (rn);
  60   if (len != size)
  61     return -1;
  62
  63   if (rn < 16)
  64     SETTWI (buf, m32rbf_h_gr_get (current_cpu, rn));
  65   else
  66     switch (rn)
  67       {
  68       case PSW_REGNUM :
  69       case CBR_REGNUM :
  70       case SPI_REGNUM :
  71       case SPU_REGNUM :
  72       case BPC_REGNUM :
  73       case BBPSW_REGNUM :
  74       case BBPC_REGNUM :
  75         SETTWI (buf, m32rbf_h_cr_get (current_cpu,
  76                                       m32r_decode_gdb_ctrl_regnum (rn)));
  77         break;
  78       case PC_REGNUM :
  79         SETTWI (buf, m32rbf_h_pc_get (current_cpu));
  80         break;
  81       case ACCL_REGNUM :
  82         SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu)));
  83         break;
  84       case ACCH_REGNUM :
  85         SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu)));
  86         break;
  87       default :
  88         return 0;
  89       }
  90
  91   return size;
  92 }
  93
  94 /* The contents of BUF are in target byte order.  */
  95
  96 int
  97 m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
  98 {
  99   int size = m32rbf_register_size (rn);
 100   if (len != size)
 101     return -1;
 102
 103   if (rn < 16)
 104     m32rbf_h_gr_set (current_cpu, rn, GETTWI (buf));
 105   else
 106     switch (rn)
 107       {
 108       case PSW_REGNUM :
 109       case CBR_REGNUM :
 110       case SPI_REGNUM :
 111       case SPU_REGNUM :
 112       case BPC_REGNUM :
 113       case BBPSW_REGNUM :
 114       case BBPC_REGNUM :
 115         m32rbf_h_cr_set (current_cpu,
 116                          m32r_decode_gdb_ctrl_regnum (rn),
 117                          GETTWI (buf));
 118         break;
 119       case PC_REGNUM :
 120         m32rbf_h_pc_set (current_cpu, GETTWI (buf));
 121         break;
 122       case ACCL_REGNUM :
 123         {
 124           DI val = m32rbf_h_accum_get (current_cpu);
 125           SETLODI (val, GETTWI (buf));
 126           m32rbf_h_accum_set (current_cpu, val);
 127           break;
 128         }
 129       case ACCH_REGNUM :
 130         {
 131           DI val = m32rbf_h_accum_get (current_cpu);
 132           SETHIDI (val, GETTWI (buf));
 133           m32rbf_h_accum_set (current_cpu, val);
 134           break;
 135         }
 136       default :
 137         return 0;
 138       }
 139
 140   return size;
 141 }
 142 \f
 143 USI
 144 m32rbf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
 145 {
 146   switch (cr)
 147     {
 148     case H_CR_PSW : /* psw */
 149       return (((CPU (h_bpsw) & 0xc1) << 8)
 150               | ((CPU (h_psw) & 0xc0) << 0)
 151               | GET_H_COND ());
 152     case H_CR_BBPSW : /* backup backup psw */
 153       return CPU (h_bbpsw) & 0xc1;
 154     case H_CR_CBR : /* condition bit */
 155       return GET_H_COND ();
 156     case H_CR_SPI : /* interrupt stack pointer */
 157       if (! GET_H_SM ())
 158         return CPU (h_gr[H_GR_SP]);
 159       else
 160         return CPU (h_cr[H_CR_SPI]);
 161     case H_CR_SPU : /* user stack pointer */
 162       if (GET_H_SM ())
 163         return CPU (h_gr[H_GR_SP]);
 164       else
 165         return CPU (h_cr[H_CR_SPU]);
 166     case H_CR_BPC : /* backup pc */
 167       return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
 168     case H_CR_BBPC : /* backup backup pc */
 169       return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
 170     case 4 : /* ??? unspecified, but apparently available */
 171     case 5 : /* ??? unspecified, but apparently available */
 172       return CPU (h_cr[cr]);
 173     default :
 174       return 0;
 175     }
 176 }
 177
 178 void
 179 m32rbf_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
 180 {
 181   switch (cr)
 182     {
 183     case H_CR_PSW : /* psw */
 184       {
 185         int old_sm = (CPU (h_psw) & 0x80) != 0;
 186         int new_sm = (newval & 0x80) != 0;
 187         CPU (h_bpsw) = (newval >> 8) & 0xff;
 188         CPU (h_psw) = newval & 0xff;
 189         SET_H_COND (newval & 1);
 190         /* When switching stack modes, update the registers.  */
 191         if (old_sm != new_sm)
 192           {
 193             if (old_sm)
 194               {
 195                 /* Switching user -> system.  */
 196                 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
 197                 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
 198               }
 199             else
 200               {
 201                 /* Switching system -> user.  */
 202                 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
 203                 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
 204               }
 205           }
 206         break;
 207       }
 208     case H_CR_BBPSW : /* backup backup psw */
 209       CPU (h_bbpsw) = newval & 0xff;
 210       break;
 211     case H_CR_CBR : /* condition bit */
 212       SET_H_COND (newval & 1);
 213       break;
 214     case H_CR_SPI : /* interrupt stack pointer */
 215       if (! GET_H_SM ())
 216         CPU (h_gr[H_GR_SP]) = newval;
 217       else
 218         CPU (h_cr[H_CR_SPI]) = newval;
 219       break;
 220     case H_CR_SPU : /* user stack pointer */
 221       if (GET_H_SM ())
 222         CPU (h_gr[H_GR_SP]) = newval;
 223       else
 224         CPU (h_cr[H_CR_SPU]) = newval;
 225       break;
 226     case H_CR_BPC : /* backup pc */
 227       CPU (h_cr[H_CR_BPC]) = newval;
 228       break;
 229     case H_CR_BBPC : /* backup backup pc */
 230       CPU (h_cr[H_CR_BBPC]) = newval;
 231       break;
 232     case 4 : /* ??? unspecified, but apparently available */
 233     case 5 : /* ??? unspecified, but apparently available */
 234       CPU (h_cr[cr]) = newval;
 235       break;
 236     default :
 237       /* ignore */
 238       break;
 239     }
 240 }
 241
 242 /* Cover fns to access h-psw.  */
 243
 244 UQI
 245 m32rbf_h_psw_get_handler (SIM_CPU *current_cpu)
 246 {
 247   return (CPU (h_psw) & 0xfe) | (CPU (h_cond) & 1);
 248 }
 249
 250 void
 251 m32rbf_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
 252 {
 253   CPU (h_psw) = newval;
 254   CPU (h_cond) = newval & 1;
 255 }
 256
 257 /* Cover fns to access h-accum.  */
 258
 259 DI
 260 m32rbf_h_accum_get_handler (SIM_CPU *current_cpu)
 261 {
 262   /* Sign extend the top 8 bits.  */
 263   DI r;
 264 #if 1
 265   r = ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff));
 266   r = XORDI (r, MAKEDI (0x800000, 0));
 267   r = SUBDI (r, MAKEDI (0x800000, 0));
 268 #else
 269   SI hi,lo;
 270   r = CPU (h_accum);
 271   hi = GETHIDI (r);
 272   lo = GETLODI (r);
 273   hi = ((hi & 0xffffff) ^ 0x800000) - 0x800000;
 274   r = MAKEDI (hi, lo);
 275 #endif
 276   return r;
 277 }
 278
 279 void
 280 m32rbf_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
 281 {
 282   CPU (h_accum) = newval;
 283 }
 284 \f
 285 #if WITH_PROFILE_MODEL_P
 286
 287 /* FIXME: Some of these should be inline or macros.  Later.  */
 288
 289 /* Initialize cycle counting for an insn.
 290    FIRST_P is non-zero if this is the first insn in a set of parallel
 291    insns.  */
 292
 293 void
 294 m32rbf_model_insn_before (SIM_CPU *cpu, int first_p)
 295 {
 296   M32R_MISC_PROFILE *mp = CPU_M32R_MISC_PROFILE (cpu);
 297   mp->cti_stall = 0;
 298   mp->load_stall = 0;
 299   if (first_p)
 300     {
 301       mp->load_regs_pending = 0;
 302       mp->biggest_cycles = 0;
 303     }
 304 }
 305
 306 /* Record the cycles computed for an insn.
 307    LAST_P is non-zero if this is the last insn in a set of parallel insns,
 308    and we update the total cycle count.
 309    CYCLES is the cycle count of the insn.  */
 310
 311 void
 312 m32rbf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
 313 {
 314   PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
 315   M32R_MISC_PROFILE *mp = CPU_M32R_MISC_PROFILE (cpu);
 316   unsigned long total = cycles + mp->cti_stall + mp->load_stall;
 317
 318   if (last_p)
 319     {
 320       unsigned long biggest = total > mp->biggest_cycles ? total : mp->biggest_cycles;
 321       PROFILE_MODEL_TOTAL_CYCLES (p) += biggest;
 322       PROFILE_MODEL_CUR_INSN_CYCLES (p) = total;
 323     }
 324   else
 325     {
 326       /* Here we take advantage of the fact that !last_p -> first_p.  */
 327       mp->biggest_cycles = total;
 328       PROFILE_MODEL_CUR_INSN_CYCLES (p) = total;
 329     }
 330
 331   /* Branch and load stall counts are recorded independently of the
 332      total cycle count.  */
 333   PROFILE_MODEL_CTI_STALL_CYCLES (p) += mp->cti_stall;
 334   PROFILE_MODEL_LOAD_STALL_CYCLES (p) += mp->load_stall;
 335
 336   mp->load_regs = mp->load_regs_pending;
 337 }
 338
 339 static INLINE void
 340 check_load_stall (SIM_CPU *cpu, int regno)
 341 {
 342   UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
 343
 344   if (regno != -1
 345       && (h_gr & (1 << regno)) != 0)
 346     {
 347       CPU_M32R_MISC_PROFILE (cpu)->load_stall += 2;
 348       if (TRACE_INSN_P (cpu))
 349         cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
 350     }
 351 }
 352
 353 int
 354 m32rbf_model_m32r_d_u_exec (SIM_CPU *cpu, const IDESC *idesc,
 355                             int unit_num, int referenced,
 356                             INT sr, INT sr2, INT dr)
 357 {
 358   check_load_stall (cpu, sr);
 359   check_load_stall (cpu, sr2);
 360   return idesc->timing->units[unit_num].done;
 361 }
 362
 363 int
 364 m32rbf_model_m32r_d_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
 365                            int unit_num, int referenced,
 366                            INT src1, INT src2)
 367 {
 368   check_load_stall (cpu, src1);
 369   check_load_stall (cpu, src2);
 370   return idesc->timing->units[unit_num].done;
 371 }
 372
 373 int
 374 m32rbf_model_m32r_d_u_mac (SIM_CPU *cpu, const IDESC *idesc,
 375                            int unit_num, int referenced,
 376                            INT src1, INT src2)
 377 {
 378   check_load_stall (cpu, src1);
 379   check_load_stall (cpu, src2);
 380   return idesc->timing->units[unit_num].done;
 381 }
 382
 383 int
 384 m32rbf_model_m32r_d_u_cti (SIM_CPU *cpu, const IDESC *idesc,
 385                            int unit_num, int referenced,
 386                            INT sr)
 387 {
 388   PROFILE_DATA *profile = CPU_PROFILE_DATA (cpu);
 389   int taken_p = (referenced & (1 << 1)) != 0;
 390
 391   check_load_stall (cpu, sr);
 392   if (taken_p)
 393     {
 394       CPU_M32R_MISC_PROFILE (cpu)->cti_stall += 2;
 395       PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
 396     }
 397   else
 398     PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
 399   return idesc->timing->units[unit_num].done;
 400 }
 401
 402 int
 403 m32rbf_model_m32r_d_u_load (SIM_CPU *cpu, const IDESC *idesc,
 404                             int unit_num, int referenced,
 405                             INT sr, INT dr)
 406 {
 407   CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending |= (1 << dr);
 408   check_load_stall (cpu, sr);
 409   return idesc->timing->units[unit_num].done;
 410 }
 411
 412 int
 413 m32rbf_model_m32r_d_u_store (SIM_CPU *cpu, const IDESC *idesc,
 414                              int unit_num, int referenced,
 415                              INT src1, INT src2)
 416 {
 417   check_load_stall (cpu, src1);
 418   check_load_stall (cpu, src2);
 419   return idesc->timing->units[unit_num].done;
 420 }
 421
 422 int
 423 m32rbf_model_test_u_exec (SIM_CPU *cpu, const IDESC *idesc,
 424                           int unit_num, int referenced)
 425 {
 426   return idesc->timing->units[unit_num].done;
 427 }
 428
 429 #endif /* WITH_PROFILE_MODEL_P */